2 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Gardner Buchanan.
16 * 4. The name of Gardner Buchanan may not be used to endorse or promote
17 * products derived from this software without specific prior written
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 * This is a driver for SMC's 9000 series of Ethernet adapters.
38 * This FreeBSD driver is derived from the smc9194 Linux driver by
39 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
40 * This driver also shamelessly borrows from the FreeBSD ep driver
41 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca>
42 * All rights reserved.
44 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded
45 * PC. It is adapted from Erik Stahlman's Linux driver which worked
46 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook,
47 * it will work for the entire SMC 9xxx series. (Ha Ha)
49 * "Features" of the SMC chip:
50 * 4608 byte packet memory. (for the 91C92. Others have more)
51 * EEPROM for configuration
55 * Erik Stahlman erik@vt.edu
56 * Herb Peyerl hpeyerl@novatel.ca
57 * Andres Vega Garcia avega@sophia.inria.fr
58 * Serge Babkin babkin@hq.icb.chel.su
59 * Gardner Buchanan gbuchanan@shl.com
63 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)"
64 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp"
67 * o Setting of the hardware address isn't supported.
68 * o Hardware padding isn't used.
72 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT)
74 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org>
75 * BSD-nomads, Tokyo, Japan.
78 * Multicast support by Kei TANAKA <kei@pal.xerox.com>
79 * Special thanks to itojun@itojun.org
82 #include <sys/param.h>
83 #include <sys/systm.h>
84 #include <sys/errno.h>
85 #include <sys/kernel.h>
86 #include <sys/sockio.h>
88 #include <sys/socket.h>
89 #include <sys/syslog.h>
91 #include <sys/module.h>
94 #include <machine/bus.h>
95 #include <machine/resource.h>
98 #include <net/ethernet.h>
100 #include <net/if_var.h>
101 #include <net/if_arp.h>
102 #include <net/if_dl.h>
103 #include <net/if_types.h>
104 #include <net/if_mib.h>
107 #include <netinet/in.h>
108 #include <netinet/in_systm.h>
109 #include <netinet/in_var.h>
110 #include <netinet/ip.h>
114 #include <net/bpfdesc.h>
116 #include <dev/sn/if_snreg.h>
117 #include <dev/sn/if_snvar.h>
119 /* Exported variables */
120 devclass_t sn_devclass;
122 static int snioctl(struct ifnet * ifp, u_long, caddr_t);
124 static void snresume(struct ifnet *);
126 static void snintr_locked(struct sn_softc *);
127 static void sninit_locked(void *);
128 static void snstart_locked(struct ifnet *);
130 static void sninit(void *);
131 static void snread(struct ifnet *);
132 static void snstart(struct ifnet *);
133 static void snstop(struct sn_softc *);
134 static void snwatchdog(void *);
136 static void sn_setmcast(struct sn_softc *);
137 static int sn_getmcf(struct ifnet *ifp, u_char *mcf);
139 /* I (GB) have been unlucky getting the hardware padding
144 static const char *chip_ids[15] = {
146 /* 3 */ "SMC91C90/91C92",
147 /* 4 */ "SMC91C94/91C96",
151 /* 8 */ "SMC91C100FD",
158 sn_attach(device_t dev)
160 struct sn_softc *sc = device_get_softc(dev);
169 ifp = sc->ifp = if_alloc(IFT_ETHER);
171 device_printf(dev, "can not if_alloc()\n");
176 callout_init_mtx(&sc->watchdog, &sc->sc_mtx, 0);
178 sc->pages_wanted = -1;
180 if (bootverbose || 1) {
181 SMC_SELECT_BANK(sc, 3);
182 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf;
184 device_printf(dev, " %s ", chip_ids[rev]);
186 device_printf(dev, " unsupported chip: rev %d ", rev);
187 SMC_SELECT_BANK(sc, 1);
188 i = CSR_READ_2(sc, CONFIG_REG_W);
189 printf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP");
193 * Read the station address from the chip. The MAC address is bank 1,
196 SMC_SELECT_BANK(sc, 1);
197 p = (uint8_t *) eaddr;
198 for (i = 0; i < 6; i += 2) {
199 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i);
200 p[i + 1] = address >> 8;
201 p[i] = address & 0xFF;
204 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
205 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
206 ifp->if_start = snstart;
207 ifp->if_ioctl = snioctl;
208 ifp->if_init = sninit;
209 ifp->if_baudrate = 10000000;
210 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
211 ifp->if_snd.ifq_maxlen = ifqmaxlen;
212 IFQ_SET_READY(&ifp->if_snd);
214 ether_ifattach(ifp, eaddr);
217 * Activate the interrupt so we can get card interrupts. This
218 * needs to be done last so that we don't have/hold the lock
219 * during startup to avoid LORs in the network layer.
221 if ((err = bus_setup_intr(dev, sc->irq_res,
222 INTR_TYPE_NET | INTR_MPSAFE, NULL, sn_intr, sc,
223 &sc->intrhand)) != 0) {
232 sn_detach(device_t dev)
234 struct sn_softc *sc = device_get_softc(dev);
235 struct ifnet *ifp = sc->ifp;
241 callout_drain(&sc->watchdog);
251 struct sn_softc *sc = xsc;
258 * Reset and initialize the chip
261 sninit_locked(void *xsc)
263 struct sn_softc *sc = xsc;
264 struct ifnet *ifp = sc->ifp;
268 SN_ASSERT_LOCKED(sc);
271 * This resets the registers mostly to defaults, but doesn't affect
272 * EEPROM. After the reset cycle, we pause briefly for the chip to
275 SMC_SELECT_BANK(sc, 0);
276 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
278 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
282 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
285 * Set the control register to automatically release succesfully
286 * transmitted packets (making the best use out of our limited
287 * memory) and to enable the EPH interrupt on certain TX errors.
289 SMC_SELECT_BANK(sc, 1);
290 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
291 CTR_CR_ENABLE | CTR_LE_ENABLE));
293 /* Set squelch level to 240mV (default 480mV) */
294 flags = CSR_READ_2(sc, CONFIG_REG_W);
295 flags |= CR_SET_SQLCH;
296 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
299 * Reset the MMU and wait for it to be un-busy.
301 SMC_SELECT_BANK(sc, 2);
302 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
303 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
307 * Disable all interrupts
309 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
314 * Set the transmitter control. We want it enabled.
320 * I (GB) have been unlucky getting this to work.
322 flags |= TCR_PAD_ENABLE;
325 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
329 * Now, enable interrupts
331 SMC_SELECT_BANK(sc, 2);
338 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
339 sc->intr_mask = mask;
340 sc->pages_wanted = -1;
344 * Mark the interface running but not active.
346 ifp->if_drv_flags |= IFF_DRV_RUNNING;
347 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
348 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
351 * Attempt to push out any waiting packets.
357 snstart(struct ifnet *ifp)
359 struct sn_softc *sc = ifp->if_softc;
367 snstart_locked(struct ifnet *ifp)
369 struct sn_softc *sc = ifp->if_softc;
381 SN_ASSERT_LOCKED(sc);
383 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
385 if (sc->pages_wanted != -1) {
386 if_printf(ifp, "snstart() while memory allocation pending\n");
392 * Sneak a peek at the next packet
394 m = ifp->if_snd.ifq_head;
398 * Compute the frame length and set pad to give an overall even
399 * number of bytes. Below we assume that the packet length is even.
401 for (len = 0, top = m; m; m = m->m_next)
407 * We drop packets that are too large. Perhaps we should truncate
410 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
411 if_printf(ifp, "large packet discarded (A)\n");
412 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
413 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
420 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
422 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
423 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
430 * The MMU wants the number of pages to be the number of 256 byte
431 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
432 * include space for the status word, byte count and control bytes in
433 * the allocation request.
435 numPages = (length + 6) >> 8;
439 * Now, try to allocate the memory
441 SMC_SELECT_BANK(sc, 2);
442 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
445 * Wait a short amount of time to see if the allocation request
446 * completes. Otherwise, I enable the interrupt and wait for
447 * completion asynchronously.
450 time_out = MEMORY_WAIT_TIME;
452 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT)
454 } while (--time_out);
456 if (!time_out || junk > 10) {
459 * No memory now. Oh well, wait until the chip finds memory
460 * later. Remember how many pages we were asking for and
461 * enable the allocation completion interrupt. Also set a
462 * watchdog in case we miss the interrupt. We mark the
463 * interface active since there is no point in attempting an
464 * snstart() until after the memory is available.
466 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT;
467 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
468 sc->intr_mask = mask;
471 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
472 sc->pages_wanted = numPages;
476 * The memory allocation completed. Check the results.
478 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
479 if (packet_no & ARR_FAILED) {
481 if_printf(ifp, "Memory allocation failed\n");
485 * We have a packet number, so tell the card to use it.
487 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
490 * Point to the beginning of the packet
492 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
495 * Send the packet length (+6 for status, length and control byte)
496 * and the status word (set to zeros)
498 CSR_WRITE_2(sc, DATA_REG_W, 0);
499 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
500 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
503 * Get the packet from the kernel. This will include the Ethernet
504 * frame header, MAC Addresses etc.
506 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
509 * Push out the data to the card.
511 for (top = m; m != 0; m = m->m_next) {
516 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
520 * Push out remaining byte.
523 CSR_WRITE_1(sc, DATA_REG_B,
524 *(mtod(m, caddr_t) + m->m_len - 1));
531 CSR_WRITE_2(sc, DATA_REG_W, 0);
535 CSR_WRITE_1(sc, DATA_REG_B, 0);
538 * Push out control byte and unused packet byte The control byte is 0
539 * meaning the packet is even lengthed and no special CRC handling is
542 CSR_WRITE_2(sc, DATA_REG_W, 0);
545 * Enable the interrupts and let the chipset deal with it Also set a
546 * watchdog in case we miss the interrupt.
548 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
549 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
550 sc->intr_mask = mask;
552 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
554 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
559 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
566 * Is another packet coming in? We don't want to overflow the tiny
567 * RX FIFO. If nothing has arrived then attempt to queue another
570 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY)
577 /* Resume a packet transmit operation after a memory allocation
580 * This is basically a hacked up copy of snstart() which handles
581 * a completed memory allocation the same way snstart() does.
582 * It then passes control to snstart to handle any other queued
586 snresume(struct ifnet *ifp)
588 struct sn_softc *sc = ifp->if_softc;
596 uint16_t pages_wanted;
599 if (sc->pages_wanted < 0)
602 pages_wanted = sc->pages_wanted;
603 sc->pages_wanted = -1;
606 * Sneak a peek at the next packet
608 m = ifp->if_snd.ifq_head;
610 if_printf(ifp, "snresume() with nothing to send\n");
614 * Compute the frame length and set pad to give an overall even
615 * number of bytes. Below we assume that the packet length is even.
617 for (len = 0, top = m; m; m = m->m_next)
623 * We drop packets that are too large. Perhaps we should truncate
626 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
627 if_printf(ifp, "large packet discarded (B)\n");
628 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
629 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
636 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
638 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
639 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
647 * The MMU wants the number of pages to be the number of 256 byte
648 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
649 * include space for the status word, byte count and control bytes in
650 * the allocation request.
652 numPages = (length + 6) >> 8;
655 SMC_SELECT_BANK(sc, 2);
658 * The memory allocation completed. Check the results. If it failed,
659 * we simply set a watchdog timer and hope for the best.
661 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
662 if (packet_no & ARR_FAILED) {
663 if_printf(ifp, "Memory allocation failed. Weird.\n");
668 * We have a packet number, so tell the card to use it.
670 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
673 * Now, numPages should match the pages_wanted recorded when the
674 * memory allocation was initiated.
676 if (pages_wanted != numPages) {
677 if_printf(ifp, "memory allocation wrong size. Weird.\n");
679 * If the allocation was the wrong size we simply release the
680 * memory once it is granted. Wait for the MMU to be un-busy.
682 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
684 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
689 * Point to the beginning of the packet
691 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
694 * Send the packet length (+6 for status, length and control byte)
695 * and the status word (set to zeros)
697 CSR_WRITE_2(sc, DATA_REG_W, 0);
698 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
699 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
702 * Get the packet from the kernel. This will include the Ethernet
703 * frame header, MAC Addresses etc.
705 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
708 * Push out the data to the card.
710 for (top = m; m != 0; m = m->m_next) {
715 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
718 * Push out remaining byte.
721 CSR_WRITE_1(sc, DATA_REG_B,
722 *(mtod(m, caddr_t) + m->m_len - 1));
729 CSR_WRITE_2(sc, DATA_REG_W, 0);
733 CSR_WRITE_1(sc, DATA_REG_B, 0);
736 * Push out control byte and unused packet byte The control byte is 0
737 * meaning the packet is even lengthed and no special CRC handling is
740 CSR_WRITE_2(sc, DATA_REG_W, 0);
743 * Enable the interrupts and let the chipset deal with it Also set a
744 * watchdog in case we miss the interrupt.
746 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
747 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
748 sc->intr_mask = mask;
749 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
753 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
759 * Now pass control to snstart() to queue any additional packets
761 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
765 * We've sent something, so we're active. Set a watchdog in case the
766 * TX_EMPTY interrupt is lost.
768 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
777 struct sn_softc *sc = (struct sn_softc *) arg;
785 snintr_locked(struct sn_softc *sc)
787 int status, interrupts;
788 struct ifnet *ifp = sc->ifp;
791 * Chip state registers
799 * Clear the watchdog.
803 SMC_SELECT_BANK(sc, 2);
806 * Obtain the current interrupt mask and clear the hardware mask
807 * while servicing interrupts.
809 mask = CSR_READ_1(sc, INTR_MASK_REG_B);
810 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
813 * Get the set of interrupts which occurred and eliminate any which
816 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B);
817 status = interrupts & mask;
820 * Now, process each of the interrupt types.
826 if (status & IM_RX_OVRN_INT) {
828 * Acknowlege Interrupt
830 SMC_SELECT_BANK(sc, 2);
831 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT);
833 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
838 if (status & IM_RCV_INT) {
841 SMC_SELECT_BANK(sc, 2);
842 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
844 if (packet_number & FIFO_REMPTY) {
846 * we got called , but nothing was on the FIFO
848 printf("sn: Receive interrupt with nothing on FIFO\n");
854 * An on-card memory allocation came through.
856 if (status & IM_ALLOC_INT) {
858 * Disable this interrupt.
860 mask &= ~IM_ALLOC_INT;
861 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
865 * TX Completion. Handle a transmit error message. This will only be
866 * called when there is an error, because of the AUTO_RELEASE mode.
868 if (status & IM_TX_INT) {
870 * Acknowlege Interrupt
872 SMC_SELECT_BANK(sc, 2);
873 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT);
875 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W);
876 packet_no &= FIFO_TX_MASK;
879 * select this as the packet to read from
881 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
884 * Position the pointer to the first word from this packet
886 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
889 * Fetch the TX status word. The value found here will be a
890 * copy of the EPH_STATUS_REG_W at the time the transmit
893 tx_status = CSR_READ_2(sc, DATA_REG_W);
895 if (tx_status & EPHSR_TX_SUC) {
896 device_printf(sc->dev,
897 "Successful packet caused interrupt\n");
899 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
902 if (tx_status & EPHSR_LATCOL)
903 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
906 * Some of these errors will have disabled transmit.
907 * Re-enable transmit now.
909 SMC_SELECT_BANK(sc, 0);
912 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE);
914 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
918 * kill the failed packet. Wait for the MMU to be un-busy.
920 SMC_SELECT_BANK(sc, 2);
921 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
923 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
926 * Attempt to queue more transmits.
928 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
932 * Transmit underrun. We use this opportunity to update transmit
933 * statistics from the card.
935 if (status & IM_TX_EMPTY_INT) {
938 * Acknowlege Interrupt
940 SMC_SELECT_BANK(sc, 2);
941 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
944 * Disable this interrupt.
946 mask &= ~IM_TX_EMPTY_INT;
948 SMC_SELECT_BANK(sc, 0);
949 card_stats = CSR_READ_2(sc, COUNTER_REG_W);
954 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, card_stats & ECR_COLN_MASK);
957 * Multiple collisions
959 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (card_stats & ECR_MCOLN_MASK) >> 4);
961 SMC_SELECT_BANK(sc, 2);
964 * Attempt to enqueue some more stuff.
966 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
970 * Some other error. Try to fix it by resetting the adapter.
972 if (status & IM_EPH_INT) {
979 * Handled all interrupt sources.
982 SMC_SELECT_BANK(sc, 2);
985 * Reestablish interrupts from mask which have not been deselected
986 * during this interrupt. Note that the hardware mask, which was set
987 * to 0x00 at the start of this service routine, may have been
988 * updated by one or more of the interrupt handers and we must let
989 * those new interrupts stay enabled here.
991 mask |= CSR_READ_1(sc, INTR_MASK_REG_B);
992 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
993 sc->intr_mask = mask;
997 snread(struct ifnet *ifp)
999 struct sn_softc *sc = ifp->if_softc;
1000 struct ether_header *eh;
1004 uint16_t packet_length;
1007 SMC_SELECT_BANK(sc, 2);
1009 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1011 if (packet_number & FIFO_REMPTY) {
1014 * we got called , but nothing was on the FIFO
1016 printf("sn: Receive interrupt with nothing on FIFO\n");
1023 * Start reading from the start of the packet. Since PTR_RCV is set,
1024 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK.
1026 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
1029 * First two words are status and packet_length
1031 status = CSR_READ_2(sc, DATA_REG_W);
1032 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK;
1035 * The packet length contains 3 extra words: status, length, and a
1036 * extra word with the control byte.
1041 * Account for receive errors and discard.
1043 if (status & RS_ERRORS) {
1044 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1048 * A packet is received.
1052 * Adjust for odd-length packet.
1054 if (status & RS_ODDFRAME)
1058 * Allocate a header mbuf from the kernel.
1060 MGETHDR(m, M_NOWAIT, MT_DATA);
1064 m->m_pkthdr.rcvif = ifp;
1065 m->m_pkthdr.len = m->m_len = packet_length;
1068 * Attach an mbuf cluster.
1070 if (!(MCLGET(m, M_NOWAIT))) {
1072 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1073 printf("sn: snread() kernel memory allocation problem\n");
1076 eh = mtod(m, struct ether_header *);
1079 * Get packet, including link layer address, from interface.
1081 data = (uint8_t *) eh;
1082 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1);
1083 if (packet_length & 1) {
1084 data += packet_length & ~1;
1085 *data = CSR_READ_1(sc, DATA_REG_B);
1087 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1090 * Remove link layer addresses and whatnot.
1092 m->m_pkthdr.len = m->m_len = packet_length;
1095 * Drop locks before calling if_input() since it may re-enter
1096 * snstart() in the netisr case. This would result in a
1097 * lock reversal. Better performance might be obtained by
1098 * chaining all packets received, dropping the lock, and then
1099 * calling if_input() on each one.
1102 (*ifp->if_input)(ifp, m);
1108 * Error or good, tell the card to get rid of this packet Wait for
1109 * the MMU to be un-busy.
1111 SMC_SELECT_BANK(sc, 2);
1112 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
1114 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE);
1117 * Check whether another packet is ready
1119 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1120 if (packet_number & FIFO_REMPTY) {
1128 * Handle IOCTLS. This function is completely stolen from if_ep.c
1129 * As with its progenitor, it does not handle hardware address
1133 snioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1135 struct sn_softc *sc = ifp->if_softc;
1141 if ((ifp->if_flags & IFF_UP) == 0 &&
1142 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1145 /* reinitialize card on any parameter change */
1153 /* update multicast filter list. */
1160 error = ether_ioctl(ifp, cmd, data);
1167 snwatchdog(void *arg)
1169 struct sn_softc *sc;
1172 SN_ASSERT_LOCKED(sc);
1173 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
1174 if (sc->timer == 0 || --sc->timer > 0)
1180 /* 1. zero the interrupt mask
1181 * 2. clear the enable receive flag
1182 * 3. clear the enable xmit flags
1185 snstop(struct sn_softc *sc)
1188 struct ifnet *ifp = sc->ifp;
1191 * Clear interrupt mask; disable all interrupts.
1193 SMC_SELECT_BANK(sc, 2);
1194 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
1197 * Disable transmitter and Receiver
1199 SMC_SELECT_BANK(sc, 0);
1200 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
1201 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
1207 callout_stop(&sc->watchdog);
1208 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1213 sn_activate(device_t dev)
1215 struct sn_softc *sc = device_get_softc(dev);
1218 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid,
1219 0, ~0, SMC_IO_EXTENT, RF_ACTIVE);
1220 if (!sc->port_res) {
1222 device_printf(dev, "Cannot allocate ioport\n");
1227 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
1231 device_printf(dev, "Cannot allocate irq\n");
1239 sn_deactivate(device_t dev)
1241 struct sn_softc *sc = device_get_softc(dev);
1244 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1247 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
1251 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid,
1255 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
1262 * Function: sn_probe(device_t dev)
1265 * Tests to see if a given ioaddr points to an SMC9xxx chip.
1266 * Tries to cause as little damage as possible if it's not a SMC chip.
1267 * Returns a 0 on success
1270 * (1) see if the high byte of BANK_SELECT is 0x33
1271 * (2) compare the ioaddr with the base register's address
1272 * (3) see if I recognize the chip ID in the appropriate register
1277 sn_probe(device_t dev)
1279 struct sn_softc *sc = device_get_softc(dev);
1281 uint16_t revision_register;
1282 uint16_t base_address_register;
1285 if ((err = sn_activate(dev)) != 0)
1289 * First, see if the high byte is 0x33
1291 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1292 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1294 device_printf(dev, "test1 failed\n");
1299 * The above MIGHT indicate a device, but I need to write to further
1300 * test this. Go to bank 0, then test that the register still
1301 * reports the high byte is 0x33.
1303 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000);
1304 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1305 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1307 device_printf(dev, "test2 failed\n");
1312 * well, we've already written once, so hopefully another time won't
1313 * hurt. This time, I need to switch the bank register to bank 1, so
1314 * I can access the base address register. The contents of the
1315 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected
1316 * to match the I/O port address where the adapter is being probed.
1318 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001);
1319 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0;
1321 if (rman_get_start(sc->port_res) != base_address_register) {
1324 * Well, the base address register didn't match. Must not
1325 * have been a SMC chip after all.
1328 device_printf(dev, "test3 failed ioaddr = 0x%x, "
1329 "base_address_register = 0x%x\n",
1330 rman_get_start(sc->port_res), base_address_register);
1336 * Check if the revision register is something that I recognize.
1337 * These might need to be added to later, as future revisions could
1340 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3);
1341 revision_register = CSR_READ_2(sc, REVISION_REG_W);
1342 if (!chip_ids[(revision_register >> 4) & 0xF]) {
1345 * I don't regonize this chip, so...
1348 device_printf(dev, "test4 failed\n");
1354 * at this point I'll assume that the chip is an SMC9xxx. It might be
1355 * prudent to check a listing of MAC addresses against the hardware
1356 * address, or do some other tests.
1368 sn_setmcast(struct sn_softc *sc)
1370 struct ifnet *ifp = sc->ifp;
1374 SN_ASSERT_LOCKED(sc);
1377 * Set the receiver filter. We want receive enabled and auto strip
1378 * of CRC from received packet. If we are promiscuous then set that
1381 flags = RCR_ENABLE | RCR_STRIP_CRC;
1383 if (ifp->if_flags & IFF_PROMISC) {
1384 flags |= RCR_PROMISC | RCR_ALMUL;
1385 } else if (ifp->if_flags & IFF_ALLMULTI) {
1388 if (sn_getmcf(ifp, mcf)) {
1390 SMC_SELECT_BANK(sc, 3);
1391 CSR_WRITE_2(sc, MULTICAST1_REG_W,
1392 ((uint16_t)mcf[1] << 8) | mcf[0]);
1393 CSR_WRITE_2(sc, MULTICAST2_REG_W,
1394 ((uint16_t)mcf[3] << 8) | mcf[2]);
1395 CSR_WRITE_2(sc, MULTICAST3_REG_W,
1396 ((uint16_t)mcf[5] << 8) | mcf[4]);
1397 CSR_WRITE_2(sc, MULTICAST4_REG_W,
1398 ((uint16_t)mcf[7] << 8) | mcf[6]);
1403 SMC_SELECT_BANK(sc, 0);
1404 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags);
1408 sn_getmcf(struct ifnet *ifp, uint8_t *mcf)
1411 uint32_t index, index2;
1413 struct ifmultiaddr *ifma;
1417 if_maddr_rlock(ifp);
1418 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1419 if (ifma->ifma_addr->sa_family != AF_LINK) {
1420 if_maddr_runlock(ifp);
1423 index = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1424 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f;
1426 for (i = 0; i < 6; i++) {
1428 index2 |= (index & 0x01);
1431 af[index2 >> 3] |= 1 << (index2 & 7);
1433 if_maddr_runlock(ifp);
1434 return 1; /* use multicast filter */