2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Gardner Buchanan.
18 * 4. The name of Gardner Buchanan may not be used to endorse or promote
19 * products derived from this software without specific prior written
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * This is a driver for SMC's 9000 series of Ethernet adapters.
40 * This FreeBSD driver is derived from the smc9194 Linux driver by
41 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
42 * This driver also shamelessly borrows from the FreeBSD ep driver
43 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca>
44 * All rights reserved.
46 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded
47 * PC. It is adapted from Erik Stahlman's Linux driver which worked
48 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook,
49 * it will work for the entire SMC 9xxx series. (Ha Ha)
51 * "Features" of the SMC chip:
52 * 4608 byte packet memory. (for the 91C92. Others have more)
53 * EEPROM for configuration
57 * Erik Stahlman erik@vt.edu
58 * Herb Peyerl hpeyerl@novatel.ca
59 * Andres Vega Garcia avega@sophia.inria.fr
60 * Serge Babkin babkin@hq.icb.chel.su
61 * Gardner Buchanan gbuchanan@shl.com
65 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)"
66 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp"
69 * o Setting of the hardware address isn't supported.
70 * o Hardware padding isn't used.
74 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT)
76 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org>
77 * BSD-nomads, Tokyo, Japan.
80 * Multicast support by Kei TANAKA <kei@pal.xerox.com>
81 * Special thanks to itojun@itojun.org
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/errno.h>
87 #include <sys/kernel.h>
88 #include <sys/sockio.h>
89 #include <sys/malloc.h>
91 #include <sys/socket.h>
92 #include <sys/syslog.h>
94 #include <sys/module.h>
97 #include <machine/bus.h>
98 #include <machine/resource.h>
101 #include <net/ethernet.h>
103 #include <net/if_var.h>
104 #include <net/if_arp.h>
105 #include <net/if_dl.h>
106 #include <net/if_types.h>
107 #include <net/if_mib.h>
110 #include <netinet/in.h>
111 #include <netinet/in_systm.h>
112 #include <netinet/in_var.h>
113 #include <netinet/ip.h>
117 #include <net/bpfdesc.h>
119 #include <dev/sn/if_snreg.h>
120 #include <dev/sn/if_snvar.h>
122 /* Exported variables */
123 devclass_t sn_devclass;
125 static int snioctl(struct ifnet * ifp, u_long, caddr_t);
127 static void snresume(struct ifnet *);
129 static void snintr_locked(struct sn_softc *);
130 static void sninit_locked(void *);
131 static void snstart_locked(struct ifnet *);
133 static void sninit(void *);
134 static void snread(struct ifnet *);
135 static void snstart(struct ifnet *);
136 static void snstop(struct sn_softc *);
137 static void snwatchdog(void *);
139 static void sn_setmcast(struct sn_softc *);
140 static int sn_getmcf(struct ifnet *ifp, u_char *mcf);
142 /* I (GB) have been unlucky getting the hardware padding
147 static const char *chip_ids[15] = {
149 /* 3 */ "SMC91C90/91C92",
150 /* 4 */ "SMC91C94/91C96",
154 /* 8 */ "SMC91C100FD",
161 sn_attach(device_t dev)
163 struct sn_softc *sc = device_get_softc(dev);
172 ifp = sc->ifp = if_alloc(IFT_ETHER);
174 device_printf(dev, "can not if_alloc()\n");
179 callout_init_mtx(&sc->watchdog, &sc->sc_mtx, 0);
181 sc->pages_wanted = -1;
183 if (bootverbose || 1) {
184 SMC_SELECT_BANK(sc, 3);
185 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf;
187 device_printf(dev, " %s ", chip_ids[rev]);
189 device_printf(dev, " unsupported chip: rev %d ", rev);
190 SMC_SELECT_BANK(sc, 1);
191 i = CSR_READ_2(sc, CONFIG_REG_W);
192 printf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP");
196 * Read the station address from the chip. The MAC address is bank 1,
199 SMC_SELECT_BANK(sc, 1);
200 p = (uint8_t *) eaddr;
201 for (i = 0; i < 6; i += 2) {
202 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i);
203 p[i + 1] = address >> 8;
204 p[i] = address & 0xFF;
207 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
208 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
209 ifp->if_start = snstart;
210 ifp->if_ioctl = snioctl;
211 ifp->if_init = sninit;
212 ifp->if_baudrate = 10000000;
213 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
214 ifp->if_snd.ifq_maxlen = ifqmaxlen;
215 IFQ_SET_READY(&ifp->if_snd);
217 ether_ifattach(ifp, eaddr);
220 * Activate the interrupt so we can get card interrupts. This
221 * needs to be done last so that we don't have/hold the lock
222 * during startup to avoid LORs in the network layer.
224 if ((err = bus_setup_intr(dev, sc->irq_res,
225 INTR_TYPE_NET | INTR_MPSAFE, NULL, sn_intr, sc,
226 &sc->intrhand)) != 0) {
235 sn_detach(device_t dev)
237 struct sn_softc *sc = device_get_softc(dev);
238 struct ifnet *ifp = sc->ifp;
244 callout_drain(&sc->watchdog);
254 struct sn_softc *sc = xsc;
261 * Reset and initialize the chip
264 sninit_locked(void *xsc)
266 struct sn_softc *sc = xsc;
267 struct ifnet *ifp = sc->ifp;
271 SN_ASSERT_LOCKED(sc);
274 * This resets the registers mostly to defaults, but doesn't affect
275 * EEPROM. After the reset cycle, we pause briefly for the chip to
278 SMC_SELECT_BANK(sc, 0);
279 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
281 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
285 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
288 * Set the control register to automatically release successfully
289 * transmitted packets (making the best use out of our limited
290 * memory) and to enable the EPH interrupt on certain TX errors.
292 SMC_SELECT_BANK(sc, 1);
293 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
294 CTR_CR_ENABLE | CTR_LE_ENABLE));
296 /* Set squelch level to 240mV (default 480mV) */
297 flags = CSR_READ_2(sc, CONFIG_REG_W);
298 flags |= CR_SET_SQLCH;
299 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
302 * Reset the MMU and wait for it to be un-busy.
304 SMC_SELECT_BANK(sc, 2);
305 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
306 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
310 * Disable all interrupts
312 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
317 * Set the transmitter control. We want it enabled.
323 * I (GB) have been unlucky getting this to work.
325 flags |= TCR_PAD_ENABLE;
328 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
332 * Now, enable interrupts
334 SMC_SELECT_BANK(sc, 2);
341 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
342 sc->intr_mask = mask;
343 sc->pages_wanted = -1;
347 * Mark the interface running but not active.
349 ifp->if_drv_flags |= IFF_DRV_RUNNING;
350 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
351 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
354 * Attempt to push out any waiting packets.
360 snstart(struct ifnet *ifp)
362 struct sn_softc *sc = ifp->if_softc;
370 snstart_locked(struct ifnet *ifp)
372 struct sn_softc *sc = ifp->if_softc;
384 SN_ASSERT_LOCKED(sc);
386 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
388 if (sc->pages_wanted != -1) {
389 if_printf(ifp, "snstart() while memory allocation pending\n");
395 * Sneak a peek at the next packet
397 m = ifp->if_snd.ifq_head;
401 * Compute the frame length and set pad to give an overall even
402 * number of bytes. Below we assume that the packet length is even.
404 for (len = 0, top = m; m; m = m->m_next)
410 * We drop packets that are too large. Perhaps we should truncate
413 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
414 if_printf(ifp, "large packet discarded (A)\n");
415 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
416 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
423 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
425 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
426 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
433 * The MMU wants the number of pages to be the number of 256 byte
434 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
435 * include space for the status word, byte count and control bytes in
436 * the allocation request.
438 numPages = (length + 6) >> 8;
442 * Now, try to allocate the memory
444 SMC_SELECT_BANK(sc, 2);
445 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
448 * Wait a short amount of time to see if the allocation request
449 * completes. Otherwise, I enable the interrupt and wait for
450 * completion asynchronously.
453 time_out = MEMORY_WAIT_TIME;
455 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT)
457 } while (--time_out);
459 if (!time_out || junk > 10) {
462 * No memory now. Oh well, wait until the chip finds memory
463 * later. Remember how many pages we were asking for and
464 * enable the allocation completion interrupt. Also set a
465 * watchdog in case we miss the interrupt. We mark the
466 * interface active since there is no point in attempting an
467 * snstart() until after the memory is available.
469 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT;
470 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
471 sc->intr_mask = mask;
474 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
475 sc->pages_wanted = numPages;
479 * The memory allocation completed. Check the results.
481 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
482 if (packet_no & ARR_FAILED) {
484 if_printf(ifp, "Memory allocation failed\n");
488 * We have a packet number, so tell the card to use it.
490 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
493 * Point to the beginning of the packet
495 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
498 * Send the packet length (+6 for status, length and control byte)
499 * and the status word (set to zeros)
501 CSR_WRITE_2(sc, DATA_REG_W, 0);
502 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
503 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
506 * Get the packet from the kernel. This will include the Ethernet
507 * frame header, MAC Addresses etc.
509 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
512 * Push out the data to the card.
514 for (top = m; m != NULL; m = m->m_next) {
519 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
523 * Push out remaining byte.
526 CSR_WRITE_1(sc, DATA_REG_B,
527 *(mtod(m, caddr_t) + m->m_len - 1));
534 CSR_WRITE_2(sc, DATA_REG_W, 0);
538 CSR_WRITE_1(sc, DATA_REG_B, 0);
541 * Push out control byte and unused packet byte The control byte is 0
542 * meaning the packet is even lengthed and no special CRC handling is
545 CSR_WRITE_2(sc, DATA_REG_W, 0);
548 * Enable the interrupts and let the chipset deal with it Also set a
549 * watchdog in case we miss the interrupt.
551 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
552 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
553 sc->intr_mask = mask;
555 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
557 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
562 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
569 * Is another packet coming in? We don't want to overflow the tiny
570 * RX FIFO. If nothing has arrived then attempt to queue another
573 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY)
580 /* Resume a packet transmit operation after a memory allocation
583 * This is basically a hacked up copy of snstart() which handles
584 * a completed memory allocation the same way snstart() does.
585 * It then passes control to snstart to handle any other queued
589 snresume(struct ifnet *ifp)
591 struct sn_softc *sc = ifp->if_softc;
599 uint16_t pages_wanted;
602 if (sc->pages_wanted < 0)
605 pages_wanted = sc->pages_wanted;
606 sc->pages_wanted = -1;
609 * Sneak a peek at the next packet
611 m = ifp->if_snd.ifq_head;
613 if_printf(ifp, "snresume() with nothing to send\n");
617 * Compute the frame length and set pad to give an overall even
618 * number of bytes. Below we assume that the packet length is even.
620 for (len = 0, top = m; m; m = m->m_next)
626 * We drop packets that are too large. Perhaps we should truncate
629 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
630 if_printf(ifp, "large packet discarded (B)\n");
631 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
632 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
639 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
641 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
642 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
650 * The MMU wants the number of pages to be the number of 256 byte
651 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
652 * include space for the status word, byte count and control bytes in
653 * the allocation request.
655 numPages = (length + 6) >> 8;
658 SMC_SELECT_BANK(sc, 2);
661 * The memory allocation completed. Check the results. If it failed,
662 * we simply set a watchdog timer and hope for the best.
664 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
665 if (packet_no & ARR_FAILED) {
666 if_printf(ifp, "Memory allocation failed. Weird.\n");
671 * We have a packet number, so tell the card to use it.
673 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
676 * Now, numPages should match the pages_wanted recorded when the
677 * memory allocation was initiated.
679 if (pages_wanted != numPages) {
680 if_printf(ifp, "memory allocation wrong size. Weird.\n");
682 * If the allocation was the wrong size we simply release the
683 * memory once it is granted. Wait for the MMU to be un-busy.
685 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
687 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
692 * Point to the beginning of the packet
694 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
697 * Send the packet length (+6 for status, length and control byte)
698 * and the status word (set to zeros)
700 CSR_WRITE_2(sc, DATA_REG_W, 0);
701 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
702 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
705 * Get the packet from the kernel. This will include the Ethernet
706 * frame header, MAC Addresses etc.
708 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
711 * Push out the data to the card.
713 for (top = m; m != NULL; m = m->m_next) {
718 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
721 * Push out remaining byte.
724 CSR_WRITE_1(sc, DATA_REG_B,
725 *(mtod(m, caddr_t) + m->m_len - 1));
732 CSR_WRITE_2(sc, DATA_REG_W, 0);
736 CSR_WRITE_1(sc, DATA_REG_B, 0);
739 * Push out control byte and unused packet byte The control byte is 0
740 * meaning the packet is even lengthed and no special CRC handling is
743 CSR_WRITE_2(sc, DATA_REG_W, 0);
746 * Enable the interrupts and let the chipset deal with it Also set a
747 * watchdog in case we miss the interrupt.
749 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
750 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
751 sc->intr_mask = mask;
752 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
756 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
762 * Now pass control to snstart() to queue any additional packets
764 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
768 * We've sent something, so we're active. Set a watchdog in case the
769 * TX_EMPTY interrupt is lost.
771 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
780 struct sn_softc *sc = (struct sn_softc *) arg;
788 snintr_locked(struct sn_softc *sc)
790 int status, interrupts;
791 struct ifnet *ifp = sc->ifp;
794 * Chip state registers
802 * Clear the watchdog.
806 SMC_SELECT_BANK(sc, 2);
809 * Obtain the current interrupt mask and clear the hardware mask
810 * while servicing interrupts.
812 mask = CSR_READ_1(sc, INTR_MASK_REG_B);
813 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
816 * Get the set of interrupts which occurred and eliminate any which
819 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B);
820 status = interrupts & mask;
823 * Now, process each of the interrupt types.
829 if (status & IM_RX_OVRN_INT) {
831 * Acknowlege Interrupt
833 SMC_SELECT_BANK(sc, 2);
834 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT);
836 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
841 if (status & IM_RCV_INT) {
844 SMC_SELECT_BANK(sc, 2);
845 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
847 if (packet_number & FIFO_REMPTY) {
849 * we got called , but nothing was on the FIFO
851 printf("sn: Receive interrupt with nothing on FIFO\n");
857 * An on-card memory allocation came through.
859 if (status & IM_ALLOC_INT) {
861 * Disable this interrupt.
863 mask &= ~IM_ALLOC_INT;
864 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
868 * TX Completion. Handle a transmit error message. This will only be
869 * called when there is an error, because of the AUTO_RELEASE mode.
871 if (status & IM_TX_INT) {
873 * Acknowlege Interrupt
875 SMC_SELECT_BANK(sc, 2);
876 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT);
878 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W);
879 packet_no &= FIFO_TX_MASK;
882 * select this as the packet to read from
884 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
887 * Position the pointer to the first word from this packet
889 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
892 * Fetch the TX status word. The value found here will be a
893 * copy of the EPH_STATUS_REG_W at the time the transmit
896 tx_status = CSR_READ_2(sc, DATA_REG_W);
898 if (tx_status & EPHSR_TX_SUC) {
899 device_printf(sc->dev,
900 "Successful packet caused interrupt\n");
902 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
905 if (tx_status & EPHSR_LATCOL)
906 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
909 * Some of these errors will have disabled transmit.
910 * Re-enable transmit now.
912 SMC_SELECT_BANK(sc, 0);
915 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE);
917 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
921 * kill the failed packet. Wait for the MMU to be un-busy.
923 SMC_SELECT_BANK(sc, 2);
924 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
926 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
929 * Attempt to queue more transmits.
931 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
935 * Transmit underrun. We use this opportunity to update transmit
936 * statistics from the card.
938 if (status & IM_TX_EMPTY_INT) {
941 * Acknowlege Interrupt
943 SMC_SELECT_BANK(sc, 2);
944 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
947 * Disable this interrupt.
949 mask &= ~IM_TX_EMPTY_INT;
951 SMC_SELECT_BANK(sc, 0);
952 card_stats = CSR_READ_2(sc, COUNTER_REG_W);
957 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, card_stats & ECR_COLN_MASK);
960 * Multiple collisions
962 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (card_stats & ECR_MCOLN_MASK) >> 4);
964 SMC_SELECT_BANK(sc, 2);
967 * Attempt to enqueue some more stuff.
969 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
973 * Some other error. Try to fix it by resetting the adapter.
975 if (status & IM_EPH_INT) {
982 * Handled all interrupt sources.
985 SMC_SELECT_BANK(sc, 2);
988 * Reestablish interrupts from mask which have not been deselected
989 * during this interrupt. Note that the hardware mask, which was set
990 * to 0x00 at the start of this service routine, may have been
991 * updated by one or more of the interrupt handers and we must let
992 * those new interrupts stay enabled here.
994 mask |= CSR_READ_1(sc, INTR_MASK_REG_B);
995 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
996 sc->intr_mask = mask;
1000 snread(struct ifnet *ifp)
1002 struct sn_softc *sc = ifp->if_softc;
1003 struct ether_header *eh;
1007 uint16_t packet_length;
1010 SMC_SELECT_BANK(sc, 2);
1012 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1014 if (packet_number & FIFO_REMPTY) {
1017 * we got called , but nothing was on the FIFO
1019 printf("sn: Receive interrupt with nothing on FIFO\n");
1026 * Start reading from the start of the packet. Since PTR_RCV is set,
1027 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK.
1029 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
1032 * First two words are status and packet_length
1034 status = CSR_READ_2(sc, DATA_REG_W);
1035 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK;
1038 * The packet length contains 3 extra words: status, length, and a
1039 * extra word with the control byte.
1044 * Account for receive errors and discard.
1046 if (status & RS_ERRORS) {
1047 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1051 * A packet is received.
1055 * Adjust for odd-length packet.
1057 if (status & RS_ODDFRAME)
1061 * Allocate a header mbuf from the kernel.
1063 MGETHDR(m, M_NOWAIT, MT_DATA);
1067 m->m_pkthdr.rcvif = ifp;
1068 m->m_pkthdr.len = m->m_len = packet_length;
1071 * Attach an mbuf cluster.
1073 if (!(MCLGET(m, M_NOWAIT))) {
1075 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1076 printf("sn: snread() kernel memory allocation problem\n");
1079 eh = mtod(m, struct ether_header *);
1082 * Get packet, including link layer address, from interface.
1084 data = (uint8_t *) eh;
1085 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1);
1086 if (packet_length & 1) {
1087 data += packet_length & ~1;
1088 *data = CSR_READ_1(sc, DATA_REG_B);
1090 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1093 * Remove link layer addresses and whatnot.
1095 m->m_pkthdr.len = m->m_len = packet_length;
1098 * Drop locks before calling if_input() since it may re-enter
1099 * snstart() in the netisr case. This would result in a
1100 * lock reversal. Better performance might be obtained by
1101 * chaining all packets received, dropping the lock, and then
1102 * calling if_input() on each one.
1105 (*ifp->if_input)(ifp, m);
1111 * Error or good, tell the card to get rid of this packet Wait for
1112 * the MMU to be un-busy.
1114 SMC_SELECT_BANK(sc, 2);
1115 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
1117 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE);
1120 * Check whether another packet is ready
1122 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1123 if (packet_number & FIFO_REMPTY) {
1131 * Handle IOCTLS. This function is completely stolen from if_ep.c
1132 * As with its progenitor, it does not handle hardware address
1136 snioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1138 struct sn_softc *sc = ifp->if_softc;
1144 if ((ifp->if_flags & IFF_UP) == 0 &&
1145 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1148 /* reinitialize card on any parameter change */
1156 /* update multicast filter list. */
1163 error = ether_ioctl(ifp, cmd, data);
1170 snwatchdog(void *arg)
1172 struct sn_softc *sc;
1175 SN_ASSERT_LOCKED(sc);
1176 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
1177 if (sc->timer == 0 || --sc->timer > 0)
1183 /* 1. zero the interrupt mask
1184 * 2. clear the enable receive flag
1185 * 3. clear the enable xmit flags
1188 snstop(struct sn_softc *sc)
1191 struct ifnet *ifp = sc->ifp;
1194 * Clear interrupt mask; disable all interrupts.
1196 SMC_SELECT_BANK(sc, 2);
1197 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
1200 * Disable transmitter and Receiver
1202 SMC_SELECT_BANK(sc, 0);
1203 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
1204 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
1210 callout_stop(&sc->watchdog);
1211 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1216 sn_activate(device_t dev)
1218 struct sn_softc *sc = device_get_softc(dev);
1221 sc->port_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
1222 &sc->port_rid, SMC_IO_EXTENT, RF_ACTIVE);
1223 if (!sc->port_res) {
1225 device_printf(dev, "Cannot allocate ioport\n");
1230 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
1234 device_printf(dev, "Cannot allocate irq\n");
1242 sn_deactivate(device_t dev)
1244 struct sn_softc *sc = device_get_softc(dev);
1247 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1250 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
1254 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid,
1258 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
1265 * Function: sn_probe(device_t dev)
1268 * Tests to see if a given ioaddr points to an SMC9xxx chip.
1269 * Tries to cause as little damage as possible if it's not a SMC chip.
1270 * Returns a 0 on success
1273 * (1) see if the high byte of BANK_SELECT is 0x33
1274 * (2) compare the ioaddr with the base register's address
1275 * (3) see if I recognize the chip ID in the appropriate register
1280 sn_probe(device_t dev)
1282 struct sn_softc *sc = device_get_softc(dev);
1284 uint16_t revision_register;
1285 uint16_t base_address_register;
1288 if ((err = sn_activate(dev)) != 0)
1292 * First, see if the high byte is 0x33
1294 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1295 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1297 device_printf(dev, "test1 failed\n");
1302 * The above MIGHT indicate a device, but I need to write to further
1303 * test this. Go to bank 0, then test that the register still
1304 * reports the high byte is 0x33.
1306 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000);
1307 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1308 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1310 device_printf(dev, "test2 failed\n");
1315 * well, we've already written once, so hopefully another time won't
1316 * hurt. This time, I need to switch the bank register to bank 1, so
1317 * I can access the base address register. The contents of the
1318 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected
1319 * to match the I/O port address where the adapter is being probed.
1321 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001);
1322 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0;
1324 if (rman_get_start(sc->port_res) != base_address_register) {
1327 * Well, the base address register didn't match. Must not
1328 * have been a SMC chip after all.
1331 device_printf(dev, "test3 failed ioaddr = 0x%x, "
1332 "base_address_register = 0x%x\n",
1333 rman_get_start(sc->port_res), base_address_register);
1339 * Check if the revision register is something that I recognize.
1340 * These might need to be added to later, as future revisions could
1343 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3);
1344 revision_register = CSR_READ_2(sc, REVISION_REG_W);
1345 if (!chip_ids[(revision_register >> 4) & 0xF]) {
1348 * I don't regonize this chip, so...
1351 device_printf(dev, "test4 failed\n");
1357 * at this point I'll assume that the chip is an SMC9xxx. It might be
1358 * prudent to check a listing of MAC addresses against the hardware
1359 * address, or do some other tests.
1371 sn_setmcast(struct sn_softc *sc)
1373 struct ifnet *ifp = sc->ifp;
1377 SN_ASSERT_LOCKED(sc);
1380 * Set the receiver filter. We want receive enabled and auto strip
1381 * of CRC from received packet. If we are promiscuous then set that
1384 flags = RCR_ENABLE | RCR_STRIP_CRC;
1386 if (ifp->if_flags & IFF_PROMISC) {
1387 flags |= RCR_PROMISC | RCR_ALMUL;
1388 } else if (ifp->if_flags & IFF_ALLMULTI) {
1391 if (sn_getmcf(ifp, mcf)) {
1393 SMC_SELECT_BANK(sc, 3);
1394 CSR_WRITE_2(sc, MULTICAST1_REG_W,
1395 ((uint16_t)mcf[1] << 8) | mcf[0]);
1396 CSR_WRITE_2(sc, MULTICAST2_REG_W,
1397 ((uint16_t)mcf[3] << 8) | mcf[2]);
1398 CSR_WRITE_2(sc, MULTICAST3_REG_W,
1399 ((uint16_t)mcf[5] << 8) | mcf[4]);
1400 CSR_WRITE_2(sc, MULTICAST4_REG_W,
1401 ((uint16_t)mcf[7] << 8) | mcf[6]);
1406 SMC_SELECT_BANK(sc, 0);
1407 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags);
1411 sn_getmcf(struct ifnet *ifp, uint8_t *mcf)
1414 uint32_t index, index2;
1416 struct ifmultiaddr *ifma;
1420 if_maddr_rlock(ifp);
1421 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1422 if (ifma->ifma_addr->sa_family != AF_LINK) {
1423 if_maddr_runlock(ifp);
1426 index = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1427 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f;
1429 for (i = 0; i < 6; i++) {
1431 index2 |= (index & 0x01);
1434 af[index2 >> 3] |= 1 << (index2 & 7);
1436 if_maddr_runlock(ifp);
1437 return 1; /* use multicast filter */