2 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Gardner Buchanan.
16 * 4. The name of Gardner Buchanan may not be used to endorse or promote
17 * products derived from this software without specific prior written
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 * This is a driver for SMC's 9000 series of Ethernet adapters.
38 * This FreeBSD driver is derived from the smc9194 Linux driver by
39 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
40 * This driver also shamelessly borrows from the FreeBSD ep driver
41 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca>
42 * All rights reserved.
44 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded
45 * PC. It is adapted from Erik Stahlman's Linux driver which worked
46 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook,
47 * it will work for the entire SMC 9xxx series. (Ha Ha)
49 * "Features" of the SMC chip:
50 * 4608 byte packet memory. (for the 91C92. Others have more)
51 * EEPROM for configuration
55 * Erik Stahlman erik@vt.edu
56 * Herb Peyerl hpeyerl@novatel.ca
57 * Andres Vega Garcia avega@sophia.inria.fr
58 * Serge Babkin babkin@hq.icb.chel.su
59 * Gardner Buchanan gbuchanan@shl.com
63 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)"
64 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp"
67 * o Setting of the hardware address isn't supported.
68 * o Hardware padding isn't used.
72 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT)
74 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org>
75 * BSD-nomads, Tokyo, Japan.
78 * Multicast support by Kei TANAKA <kei@pal.xerox.com>
79 * Special thanks to itojun@itojun.org
82 #include <sys/param.h>
83 #include <sys/systm.h>
84 #include <sys/errno.h>
85 #include <sys/sockio.h>
87 #include <sys/socket.h>
88 #include <sys/syslog.h>
90 #include <sys/module.h>
93 #include <machine/bus.h>
94 #include <machine/resource.h>
97 #include <net/ethernet.h>
99 #include <net/if_arp.h>
100 #include <net/if_dl.h>
101 #include <net/if_types.h>
102 #include <net/if_mib.h>
105 #include <netinet/in.h>
106 #include <netinet/in_systm.h>
107 #include <netinet/in_var.h>
108 #include <netinet/ip.h>
112 #include <net/bpfdesc.h>
114 #include <dev/sn/if_snreg.h>
115 #include <dev/sn/if_snvar.h>
117 /* Exported variables */
118 devclass_t sn_devclass;
120 static int snioctl(struct ifnet * ifp, u_long, caddr_t);
122 static void snresume(struct ifnet *);
124 static void sninit_locked(void *);
125 static void snstart_locked(struct ifnet *);
127 static void sninit(void *);
128 static void snread(struct ifnet *);
129 static void snstart(struct ifnet *);
130 static void snstop(struct sn_softc *);
131 static void snwatchdog(struct ifnet *);
133 static void sn_setmcast(struct sn_softc *);
134 static int sn_getmcf(struct ifnet *ifp, u_char *mcf);
136 /* I (GB) have been unlucky getting the hardware padding
141 static const char *chip_ids[15] = {
143 /* 3 */ "SMC91C90/91C92",
144 /* 4 */ "SMC91C94/91C96",
148 /* 8 */ "SMC91C100FD",
155 sn_attach(device_t dev)
157 struct sn_softc *sc = device_get_softc(dev);
166 ifp = sc->ifp = if_alloc(IFT_ETHER);
168 device_printf(dev, "can not if_alloc()\n");
174 sc->pages_wanted = -1;
176 if (bootverbose || 1) {
177 SMC_SELECT_BANK(sc, 3);
178 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf;
180 device_printf(dev, " %s ", chip_ids[rev]);
182 device_printf(dev, " unsupported chip: rev %d ", rev);
183 SMC_SELECT_BANK(sc, 1);
184 i = CSR_READ_2(sc, CONFIG_REG_W);
185 printf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP");
189 * Read the station address from the chip. The MAC address is bank 1,
192 SMC_SELECT_BANK(sc, 1);
193 p = (uint8_t *) eaddr;
194 for (i = 0; i < 6; i += 2) {
195 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i);
196 p[i + 1] = address >> 8;
197 p[i] = address & 0xFF;
200 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
201 ifp->if_mtu = ETHERMTU;
202 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
203 ifp->if_start = snstart;
204 ifp->if_ioctl = snioctl;
205 ifp->if_watchdog = snwatchdog;
206 ifp->if_init = sninit;
207 ifp->if_baudrate = 10000000;
208 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
209 ifp->if_snd.ifq_maxlen = ifqmaxlen;
210 IFQ_SET_READY(&ifp->if_snd);
213 ether_ifattach(ifp, eaddr);
216 * Activate the interrupt so we can get card interrupts. This
217 * needs to be done last so that we don't have/hold the lock
218 * during startup to avoid LORs in the network layer.
220 if ((err = bus_setup_intr(dev, sc->irq_res,
221 INTR_TYPE_NET | INTR_MPSAFE, NULL, sn_intr, sc,
222 &sc->intrhand)) != 0) {
231 sn_detach(device_t dev)
233 struct sn_softc *sc = device_get_softc(dev);
234 struct ifnet *ifp = sc->ifp;
237 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
248 struct sn_softc *sc = xsc;
255 * Reset and initialize the chip
258 sninit_locked(void *xsc)
260 struct sn_softc *sc = xsc;
261 struct ifnet *ifp = sc->ifp;
265 SN_ASSERT_LOCKED(sc);
268 * This resets the registers mostly to defaults, but doesn't affect
269 * EEPROM. After the reset cycle, we pause briefly for the chip to
272 SMC_SELECT_BANK(sc, 0);
273 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
275 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
279 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
282 * Set the control register to automatically release succesfully
283 * transmitted packets (making the best use out of our limited
284 * memory) and to enable the EPH interrupt on certain TX errors.
286 SMC_SELECT_BANK(sc, 1);
287 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
288 CTR_CR_ENABLE | CTR_LE_ENABLE));
290 /* Set squelch level to 240mV (default 480mV) */
291 flags = CSR_READ_2(sc, CONFIG_REG_W);
292 flags |= CR_SET_SQLCH;
293 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
296 * Reset the MMU and wait for it to be un-busy.
298 SMC_SELECT_BANK(sc, 2);
299 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
300 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
304 * Disable all interrupts
306 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
311 * Set the transmitter control. We want it enabled.
317 * I (GB) have been unlucky getting this to work.
319 flags |= TCR_PAD_ENABLE;
322 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
326 * Now, enable interrupts
328 SMC_SELECT_BANK(sc, 2);
335 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
336 sc->intr_mask = mask;
337 sc->pages_wanted = -1;
341 * Mark the interface running but not active.
343 ifp->if_drv_flags |= IFF_DRV_RUNNING;
344 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
347 * Attempt to push out any waiting packets.
353 snstart(struct ifnet *ifp)
355 struct sn_softc *sc = ifp->if_softc;
363 snstart_locked(struct ifnet *ifp)
365 struct sn_softc *sc = ifp->if_softc;
377 SN_ASSERT_LOCKED(sc);
379 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
381 if (sc->pages_wanted != -1) {
382 if_printf(ifp, "snstart() while memory allocation pending\n");
388 * Sneak a peek at the next packet
390 m = ifp->if_snd.ifq_head;
394 * Compute the frame length and set pad to give an overall even
395 * number of bytes. Below we assume that the packet length is even.
397 for (len = 0, top = m; m; m = m->m_next)
403 * We drop packets that are too large. Perhaps we should truncate
406 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
407 if_printf(ifp, "large packet discarded (A)\n");
409 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
416 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
418 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
419 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
426 * The MMU wants the number of pages to be the number of 256 byte
427 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
428 * include space for the status word, byte count and control bytes in
429 * the allocation request.
431 numPages = (length + 6) >> 8;
435 * Now, try to allocate the memory
437 SMC_SELECT_BANK(sc, 2);
438 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
441 * Wait a short amount of time to see if the allocation request
442 * completes. Otherwise, I enable the interrupt and wait for
443 * completion asyncronously.
446 time_out = MEMORY_WAIT_TIME;
448 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT)
450 } while (--time_out);
452 if (!time_out || junk > 10) {
455 * No memory now. Oh well, wait until the chip finds memory
456 * later. Remember how many pages we were asking for and
457 * enable the allocation completion interrupt. Also set a
458 * watchdog in case we miss the interrupt. We mark the
459 * interface active since there is no point in attempting an
460 * snstart() until after the memory is available.
462 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT;
463 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
464 sc->intr_mask = mask;
467 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
468 sc->pages_wanted = numPages;
472 * The memory allocation completed. Check the results.
474 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
475 if (packet_no & ARR_FAILED) {
477 if_printf(ifp, "Memory allocation failed\n");
481 * We have a packet number, so tell the card to use it.
483 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
486 * Point to the beginning of the packet
488 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
491 * Send the packet length (+6 for status, length and control byte)
492 * and the status word (set to zeros)
494 CSR_WRITE_2(sc, DATA_REG_W, 0);
495 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
496 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
499 * Get the packet from the kernel. This will include the Ethernet
500 * frame header, MAC Addresses etc.
502 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
505 * Push out the data to the card.
507 for (top = m; m != 0; m = m->m_next) {
512 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
516 * Push out remaining byte.
519 CSR_WRITE_1(sc, DATA_REG_B,
520 *(mtod(m, caddr_t) + m->m_len - 1));
527 CSR_WRITE_2(sc, DATA_REG_W, 0);
531 CSR_WRITE_1(sc, DATA_REG_B, 0);
534 * Push out control byte and unused packet byte The control byte is 0
535 * meaning the packet is even lengthed and no special CRC handling is
538 CSR_WRITE_2(sc, DATA_REG_W, 0);
541 * Enable the interrupts and let the chipset deal with it Also set a
542 * watchdog in case we miss the interrupt.
544 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
545 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
546 sc->intr_mask = mask;
548 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
550 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
562 * Is another packet coming in? We don't want to overflow the tiny
563 * RX FIFO. If nothing has arrived then attempt to queue another
566 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY)
573 /* Resume a packet transmit operation after a memory allocation
576 * This is basically a hacked up copy of snstart() which handles
577 * a completed memory allocation the same way snstart() does.
578 * It then passes control to snstart to handle any other queued
582 snresume(struct ifnet *ifp)
584 struct sn_softc *sc = ifp->if_softc;
592 uint16_t pages_wanted;
595 if (sc->pages_wanted < 0)
598 pages_wanted = sc->pages_wanted;
599 sc->pages_wanted = -1;
602 * Sneak a peek at the next packet
604 m = ifp->if_snd.ifq_head;
606 if_printf(ifp, "snresume() with nothing to send\n");
610 * Compute the frame length and set pad to give an overall even
611 * number of bytes. Below we assume that the packet length is even.
613 for (len = 0, top = m; m; m = m->m_next)
619 * We drop packets that are too large. Perhaps we should truncate
622 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
623 if_printf(ifp, "large packet discarded (B)\n");
625 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
632 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
634 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
635 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
643 * The MMU wants the number of pages to be the number of 256 byte
644 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
645 * include space for the status word, byte count and control bytes in
646 * the allocation request.
648 numPages = (length + 6) >> 8;
651 SMC_SELECT_BANK(sc, 2);
654 * The memory allocation completed. Check the results. If it failed,
655 * we simply set a watchdog timer and hope for the best.
657 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
658 if (packet_no & ARR_FAILED) {
659 if_printf(ifp, "Memory allocation failed. Weird.\n");
664 * We have a packet number, so tell the card to use it.
666 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
669 * Now, numPages should match the pages_wanted recorded when the
670 * memory allocation was initiated.
672 if (pages_wanted != numPages) {
673 if_printf(ifp, "memory allocation wrong size. Weird.\n");
675 * If the allocation was the wrong size we simply release the
676 * memory once it is granted. Wait for the MMU to be un-busy.
678 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
680 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
685 * Point to the beginning of the packet
687 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
690 * Send the packet length (+6 for status, length and control byte)
691 * and the status word (set to zeros)
693 CSR_WRITE_2(sc, DATA_REG_W, 0);
694 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
695 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
698 * Get the packet from the kernel. This will include the Ethernet
699 * frame header, MAC Addresses etc.
701 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
704 * Push out the data to the card.
706 for (top = m; m != 0; m = m->m_next) {
711 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
714 * Push out remaining byte.
717 CSR_WRITE_1(sc, DATA_REG_B,
718 *(mtod(m, caddr_t) + m->m_len - 1));
725 CSR_WRITE_2(sc, DATA_REG_W, 0);
729 CSR_WRITE_1(sc, DATA_REG_B, 0);
732 * Push out control byte and unused packet byte The control byte is 0
733 * meaning the packet is even lengthed and no special CRC handling is
736 CSR_WRITE_2(sc, DATA_REG_W, 0);
739 * Enable the interrupts and let the chipset deal with it Also set a
740 * watchdog in case we miss the interrupt.
742 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
743 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
744 sc->intr_mask = mask;
745 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
755 * Now pass control to snstart() to queue any additional packets
757 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
761 * We've sent something, so we're active. Set a watchdog in case the
762 * TX_EMPTY interrupt is lost.
764 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
774 int status, interrupts;
775 struct sn_softc *sc = (struct sn_softc *) arg;
776 struct ifnet *ifp = sc->ifp;
779 * Chip state registers
789 * Clear the watchdog.
793 SMC_SELECT_BANK(sc, 2);
796 * Obtain the current interrupt mask and clear the hardware mask
797 * while servicing interrupts.
799 mask = CSR_READ_1(sc, INTR_MASK_REG_B);
800 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
803 * Get the set of interrupts which occurred and eliminate any which
806 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B);
807 status = interrupts & mask;
810 * Now, process each of the interrupt types.
816 if (status & IM_RX_OVRN_INT) {
818 * Acknowlege Interrupt
820 SMC_SELECT_BANK(sc, 2);
821 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT);
828 if (status & IM_RCV_INT) {
831 SMC_SELECT_BANK(sc, 2);
832 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
834 if (packet_number & FIFO_REMPTY) {
836 * we got called , but nothing was on the FIFO
838 printf("sn: Receive interrupt with nothing on FIFO\n");
844 * An on-card memory allocation came through.
846 if (status & IM_ALLOC_INT) {
848 * Disable this interrupt.
850 mask &= ~IM_ALLOC_INT;
851 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
855 * TX Completion. Handle a transmit error message. This will only be
856 * called when there is an error, because of the AUTO_RELEASE mode.
858 if (status & IM_TX_INT) {
860 * Acknowlege Interrupt
862 SMC_SELECT_BANK(sc, 2);
863 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT);
865 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W);
866 packet_no &= FIFO_TX_MASK;
869 * select this as the packet to read from
871 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
874 * Position the pointer to the first word from this packet
876 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
879 * Fetch the TX status word. The value found here will be a
880 * copy of the EPH_STATUS_REG_W at the time the transmit
883 tx_status = CSR_READ_2(sc, DATA_REG_W);
885 if (tx_status & EPHSR_TX_SUC) {
886 device_printf(sc->dev,
887 "Successful packet caused interrupt\n");
892 if (tx_status & EPHSR_LATCOL)
893 ++ifp->if_collisions;
896 * Some of these errors will have disabled transmit.
897 * Re-enable transmit now.
899 SMC_SELECT_BANK(sc, 0);
902 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE);
904 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
908 * kill the failed packet. Wait for the MMU to be un-busy.
910 SMC_SELECT_BANK(sc, 2);
911 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
913 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
916 * Attempt to queue more transmits.
918 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
922 * Transmit underrun. We use this opportunity to update transmit
923 * statistics from the card.
925 if (status & IM_TX_EMPTY_INT) {
928 * Acknowlege Interrupt
930 SMC_SELECT_BANK(sc, 2);
931 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
934 * Disable this interrupt.
936 mask &= ~IM_TX_EMPTY_INT;
938 SMC_SELECT_BANK(sc, 0);
939 card_stats = CSR_READ_2(sc, COUNTER_REG_W);
944 ifp->if_collisions += card_stats & ECR_COLN_MASK;
947 * Multiple collisions
949 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4;
951 SMC_SELECT_BANK(sc, 2);
954 * Attempt to enqueue some more stuff.
956 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
960 * Some other error. Try to fix it by resetting the adapter.
962 if (status & IM_EPH_INT) {
969 * Handled all interrupt sources.
972 SMC_SELECT_BANK(sc, 2);
975 * Reestablish interrupts from mask which have not been deselected
976 * during this interrupt. Note that the hardware mask, which was set
977 * to 0x00 at the start of this service routine, may have been
978 * updated by one or more of the interrupt handers and we must let
979 * those new interrupts stay enabled here.
981 mask |= CSR_READ_1(sc, INTR_MASK_REG_B);
982 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
983 sc->intr_mask = mask;
988 snread(struct ifnet *ifp)
990 struct sn_softc *sc = ifp->if_softc;
991 struct ether_header *eh;
995 uint16_t packet_length;
998 SMC_SELECT_BANK(sc, 2);
1000 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1002 if (packet_number & FIFO_REMPTY) {
1005 * we got called , but nothing was on the FIFO
1007 printf("sn: Receive interrupt with nothing on FIFO\n");
1014 * Start reading from the start of the packet. Since PTR_RCV is set,
1015 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK.
1017 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
1020 * First two words are status and packet_length
1022 status = CSR_READ_2(sc, DATA_REG_W);
1023 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK;
1026 * The packet length contains 3 extra words: status, length, and a
1027 * extra word with the control byte.
1032 * Account for receive errors and discard.
1034 if (status & RS_ERRORS) {
1039 * A packet is received.
1043 * Adjust for odd-length packet.
1045 if (status & RS_ODDFRAME)
1049 * Allocate a header mbuf from the kernel.
1051 MGETHDR(m, M_DONTWAIT, MT_DATA);
1055 m->m_pkthdr.rcvif = ifp;
1056 m->m_pkthdr.len = m->m_len = packet_length;
1059 * Attach an mbuf cluster
1061 MCLGET(m, M_DONTWAIT);
1064 * Insist on getting a cluster
1066 if ((m->m_flags & M_EXT) == 0) {
1069 printf("sn: snread() kernel memory allocation problem\n");
1072 eh = mtod(m, struct ether_header *);
1075 * Get packet, including link layer address, from interface.
1077 data = (uint8_t *) eh;
1078 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1);
1079 if (packet_length & 1) {
1080 data += packet_length & ~1;
1081 *data = CSR_READ_1(sc, DATA_REG_B);
1086 * Remove link layer addresses and whatnot.
1088 m->m_pkthdr.len = m->m_len = packet_length;
1091 * Drop locks before calling if_input() since it may re-enter
1092 * snstart() in the netisr case. This would result in a
1093 * lock reversal. Better performance might be obtained by
1094 * chaining all packets received, dropping the lock, and then
1095 * calling if_input() on each one.
1098 (*ifp->if_input)(ifp, m);
1104 * Error or good, tell the card to get rid of this packet Wait for
1105 * the MMU to be un-busy.
1107 SMC_SELECT_BANK(sc, 2);
1108 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
1110 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE);
1113 * Check whether another packet is ready
1115 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1116 if (packet_number & FIFO_REMPTY) {
1124 * Handle IOCTLS. This function is completely stolen from if_ep.c
1125 * As with its progenitor, it does not handle hardware address
1129 snioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1131 struct sn_softc *sc = ifp->if_softc;
1137 if ((ifp->if_flags & IFF_UP) == 0 &&
1138 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1139 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1142 /* reinitialize card on any parameter change */
1150 /* update multicast filter list. */
1157 error = ether_ioctl(ifp, cmd, data);
1164 snwatchdog(struct ifnet *ifp)
1166 sn_intr(ifp->if_softc);
1170 /* 1. zero the interrupt mask
1171 * 2. clear the enable receive flag
1172 * 3. clear the enable xmit flags
1175 snstop(struct sn_softc *sc)
1178 struct ifnet *ifp = sc->ifp;
1181 * Clear interrupt mask; disable all interrupts.
1183 SMC_SELECT_BANK(sc, 2);
1184 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
1187 * Disable transmitter and Receiver
1189 SMC_SELECT_BANK(sc, 0);
1190 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
1191 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
1201 sn_activate(device_t dev)
1203 struct sn_softc *sc = device_get_softc(dev);
1206 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid,
1207 0, ~0, SMC_IO_EXTENT, RF_ACTIVE);
1208 if (!sc->port_res) {
1210 device_printf(dev, "Cannot allocate ioport\n");
1215 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
1219 device_printf(dev, "Cannot allocate irq\n");
1223 sc->bst = rman_get_bustag(sc->port_res);
1224 sc->bsh = rman_get_bushandle(sc->port_res);
1229 sn_deactivate(device_t dev)
1231 struct sn_softc *sc = device_get_softc(dev);
1234 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1237 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
1241 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid,
1245 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
1252 * Function: sn_probe(device_t dev)
1255 * Tests to see if a given ioaddr points to an SMC9xxx chip.
1256 * Tries to cause as little damage as possible if it's not a SMC chip.
1257 * Returns a 0 on success
1260 * (1) see if the high byte of BANK_SELECT is 0x33
1261 * (2) compare the ioaddr with the base register's address
1262 * (3) see if I recognize the chip ID in the appropriate register
1267 sn_probe(device_t dev)
1269 struct sn_softc *sc = device_get_softc(dev);
1271 uint16_t revision_register;
1272 uint16_t base_address_register;
1275 if ((err = sn_activate(dev)) != 0)
1279 * First, see if the high byte is 0x33
1281 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1282 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1284 device_printf(dev, "test1 failed\n");
1289 * The above MIGHT indicate a device, but I need to write to further
1290 * test this. Go to bank 0, then test that the register still
1291 * reports the high byte is 0x33.
1293 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000);
1294 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1295 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1297 device_printf(dev, "test2 failed\n");
1302 * well, we've already written once, so hopefully another time won't
1303 * hurt. This time, I need to switch the bank register to bank 1, so
1304 * I can access the base address register. The contents of the
1305 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected
1306 * to match the I/O port address where the adapter is being probed.
1308 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001);
1309 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0;
1311 if (rman_get_start(sc->port_res) != base_address_register) {
1314 * Well, the base address register didn't match. Must not
1315 * have been a SMC chip after all.
1318 device_printf(dev, "test3 failed ioaddr = 0x%x, "
1319 "base_address_register = 0x%x\n",
1320 rman_get_start(sc->port_res), base_address_register);
1326 * Check if the revision register is something that I recognize.
1327 * These might need to be added to later, as future revisions could
1330 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3);
1331 revision_register = CSR_READ_2(sc, REVISION_REG_W);
1332 if (!chip_ids[(revision_register >> 4) & 0xF]) {
1335 * I don't regonize this chip, so...
1338 device_printf(dev, "test4 failed\n");
1344 * at this point I'll assume that the chip is an SMC9xxx. It might be
1345 * prudent to check a listing of MAC addresses against the hardware
1346 * address, or do some other tests.
1358 sn_setmcast(struct sn_softc *sc)
1360 struct ifnet *ifp = sc->ifp;
1364 SN_ASSERT_LOCKED(sc);
1367 * Set the receiver filter. We want receive enabled and auto strip
1368 * of CRC from received packet. If we are promiscuous then set that
1371 flags = RCR_ENABLE | RCR_STRIP_CRC;
1373 if (ifp->if_flags & IFF_PROMISC) {
1374 flags |= RCR_PROMISC | RCR_ALMUL;
1375 } else if (ifp->if_flags & IFF_ALLMULTI) {
1378 if (sn_getmcf(ifp, mcf)) {
1380 SMC_SELECT_BANK(sc, 3);
1381 CSR_WRITE_2(sc, MULTICAST1_REG_W,
1382 ((uint16_t)mcf[1] << 8) | mcf[0]);
1383 CSR_WRITE_2(sc, MULTICAST2_REG_W,
1384 ((uint16_t)mcf[3] << 8) | mcf[2]);
1385 CSR_WRITE_2(sc, MULTICAST3_REG_W,
1386 ((uint16_t)mcf[5] << 8) | mcf[4]);
1387 CSR_WRITE_2(sc, MULTICAST4_REG_W,
1388 ((uint16_t)mcf[7] << 8) | mcf[6]);
1393 SMC_SELECT_BANK(sc, 0);
1394 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags);
1398 sn_getmcf(struct ifnet *ifp, uint8_t *mcf)
1401 uint32_t index, index2;
1403 struct ifmultiaddr *ifma;
1407 if_maddr_rlock(ifp);
1408 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1409 if (ifma->ifma_addr->sa_family != AF_LINK) {
1410 if_maddr_runlock(ifp);
1413 index = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1414 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f;
1416 for (i = 0; i < 6; i++) {
1418 index2 |= (index & 0x01);
1421 af[index2 >> 3] |= 1 << (index2 & 7);
1423 if_maddr_runlock(ifp);
1424 return 1; /* use multicast filter */