2 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Gardner Buchanan.
16 * 4. The name of Gardner Buchanan may not be used to endorse or promote
17 * products derived from this software without specific prior written
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 * This file contains register information and access macros for
36 * the SMC91xxx chipset.
38 * Information contained in this file was obtained from the SMC91C92
39 * and SMC91C94 manuals from SMC. You will need one of these in order
40 * to make any meaningful changes to this driver. Information about
41 * obtaining one can be found at http://www.smc.com in the components
44 * This FreeBSD driver is derived in part from the smc9194 Linux driver
45 * by Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
46 * It is also derived in part from the FreeBSD ep (3C509) driver which
47 * is Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights
55 * Wait time for memory to be free. This probably shouldn't be
56 * tuned that much, as waiting for this means nothing else happens
59 #define MEMORY_WAIT_TIME 1000
62 /* The SMC91xxx uses 16 I/O ports
64 #define SMC_IO_EXTENT 16
68 * A description of the SMC registers is probably in order here,
69 * although for details, the SMC datasheet is invaluable.
70 * The data sheet I (GB) am using is "SMC91C92 Single Chip Ethernet
71 * Controller With RAM", Rev. 12/0/94. Constant definitions I give
72 * here are loosely based on the mnemonic names given to them in the
73 * data sheet, but there are many exceptions.
75 * Basically, the chip has 4 banks of registers (0 to 3), which
76 * are accessed by writing a number into the BANK_SELECT register
77 * (I also use a SMC_SELECT_BANK macro for this). Registers are
78 * either Byte or Word sized. My constant definitions end in _B
79 * or _W as appropriate.
81 * The banks are arranged so that for most purposes, bank 2 is all
82 * that is needed for normal run time tasks.
86 * Bank Select Register. This also doubles as
87 * a chip identification register. This register
88 * is mapped at the same position in all banks.
90 #define BANK_SELECT_REG_W 0x0e
91 #define BSR_DETECT_MASK 0xff00
92 #define BSR_DETECT_VALUE 0x3300
98 /* Transmit Control Register controls some aspects of the transmit
99 * behavior of the Ethernet Protocol Handler.
101 #define TXMIT_CONTROL_REG_W 0x00
103 #define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */
104 #define TCR_LOOP 0x0002 /* Enable internal analogue loopback */
105 #define TCR_FORCOL 0x0004 /* Force Collision on next TX */
106 #define TCR_PAD_ENABLE 0x0080 /* Pad short packets to 64 bytes */
107 #define TCR_NOCRC 0x0100 /* Do not append CRC */
108 #define TCR_MON_CSN 0x0400 /* monitors the carrier status */
109 #define TCR_FDUPLX 0x0800 /* receive packets sent out */
110 #define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */
111 #define TCR_EPH_LOOP 0x2000 /* Enable internal digital loopback */
114 /* Status of the last transmitted frame and instantaneous status of
115 * the Ethernet Protocol Handler jumbled together. In auto-release
116 * mode this information is simply discarded after each TX. This info
117 * is copied to the status word of in-memory packets after transmit
118 * where relevent statuses can be checked.
120 #define EPH_STATUS_REG_W 0x02
122 #define EPHSR_TX_SUC 0x0001 /* Transmit was successful */
123 #define EPHSR_SNGLCOL 0x0002 /* Single collision occurred */
124 #define EPHSR_MULCOL 0x0004 /* Multiple Collisions occurred */
125 #define EPHSR_LTX_MULT 0x0008 /* Transmit was a multicast */
126 #define EPHSR_16COL 0x0010 /* 16 Collisions occurred, TX disabled */
127 #define EPHSR_SQET 0x0020 /* SQE Test failed, TX disabled */
128 #define EPHSR_LTX_BRD 0x0040 /* Transmit was a broadcast */
129 #define EPHSR_DEFR 0x0080 /* TX deferred due to carrier det. */
130 #define EPHSR_LATCOL 0x0200 /* Late collision detected, TX disabled */
131 #define EPHSR_LOST_CAR 0x0400 /* Lost carrier sense, TX disabled */
132 #define EPHSR_EXC_DEF 0x0800 /* Excessive deferrals in TX >2 MAXETHER
134 #define EPHSR_CTR_ROL 0x1000 /* Some ECR Counter(s) rolled over */
135 #define EPHSR_RX_OVRN 0x2000 /* Receiver overrun, packets dropped */
136 #define EPHSR_LINK_OK 0x4000 /* Link integrity is OK */
137 #define EPHSR_TXUNRN 0x8000 /* Transmit underrun */
140 /* Receiver Control Register controls some aspects of the receive
141 * behavior of the Ethernet Protocol Handler.
143 #define RECV_CONTROL_REG_W 0x04
145 #define RCR_RX_ABORT 0x0001 /* Received huge packet */
146 #define RCR_PROMISC 0x0002 /* enable promiscuous mode */
147 #define RCR_ALMUL 0x0004 /* receive all multicast packets */
148 #define RCR_ENABLE 0x0100 /* IFF this is set, we can recieve packets */
149 #define RCR_STRIP_CRC 0x0200 /* strips CRC */
150 #define RCR_GAIN_BITS 0x0c00 /* PLL Gain control (for testing) */
151 #define RCR_FILT_CAR 0x4000 /* Enable 12 bit carrier filter */
152 #define RCR_SOFTRESET 0x8000 /* Resets the EPH logic */
155 /* TX Statistics counters
157 #define COUNTER_REG_W 0x06
159 #define ECR_COLN_MASK 0x000f /* Vanilla collisions */
160 #define ECR_MCOLN_MASK 0x00f0 /* Multiple collisions */
161 #define ECR_DTX_MASK 0x0f00 /* Deferred transmits */
162 #define ECR_EXDTX_MASK 0xf000 /* Excessively deferred transmits */
164 /* Memory Information
166 #define MEM_INFO_REG_W 0x08
168 #define MIR_FREE_MASK 0xff00 /* Free memory pages available */
169 #define MIR_TOTAL_MASK 0x00ff /* Total memory pages available */
171 /* Memory Configuration
173 #define MEM_CFG_REG_W 0x0a
175 #define MCR_TXRSV_MASK 0x001f /* Count of pages reserved for transmit */
178 /* Bank 0, Register 0x0c is unised in the SMC91C92
185 /* Adapter configuration
187 #define CONFIG_REG_W 0x00
189 #define CR_INT_SEL0 0x0002 /* Interrupt selector */
190 #define CR_INT_SEL1 0x0004 /* Interrupt selector */
191 #define CR_DIS_LINK 0x0040 /* Disable 10BaseT Link Test */
192 #define CR_16BIT 0x0080 /* Bus width */
193 #define CR_AUI_SELECT 0x0100 /* Use external (AUI) Transceiver */
194 #define CR_SET_SQLCH 0x0200 /* Squelch level */
195 #define CR_FULL_STEP 0x0400 /* AUI signalling mode */
196 #define CR_NOW_WAIT_ST 0x1000 /* Disable bus wait states */
198 /* The contents of this port are used by the adapter
199 * to decode its I/O address. We use it as a varification
200 * that the adapter is detected properly when probing.
202 #define BASE_ADDR_REG_W 0x02 /* The select IO Base addr. */
204 /* These registers hold the Ethernet MAC address.
206 #define IAR_ADDR0_REG_W 0x04 /* My Ethernet address */
207 #define IAR_ADDR1_REG_W 0x06 /* My Ethernet address */
208 #define IAR_ADDR2_REG_W 0x08 /* My Ethernet address */
210 /* General purpose register used for talking to the EEPROM.
212 #define GENERAL_REG_W 0x0a
214 /* Control register used for talking to the EEPROM and
215 * setting some EPH functions.
217 #define CONTROL_REG_W 0x0c
218 #define CTR_STORE 0x0001 /* Store something to EEPROM */
219 #define CTR_RELOAD 0x0002 /* Read EEPROM into registers */
220 #define CTR_EEPROM_SEL 0x0004 /* Select registers for Reload/Store */
221 #define CTR_TE_ENABLE 0x0020 /* Enable TX Error detection via EPH_INT */
222 #define CTR_CR_ENABLE 0x0040 /* Enable Counter Rollover via EPH_INT */
223 #define CTR_LE_ENABLE 0x0080 /* Enable Link Error detection via EPH_INT */
224 #define CTR_AUTO_RELEASE 0x0800 /* Enable auto release mode for TX */
225 #define CTR_POWERDOWN 0x2000 /* Enter powerdown mode */
226 #define CTR_RCV_BAD 0x4000 /* Enable receipt of frames with bad CRC */
232 /* Memory Management Unit Control Register
233 * Controls allocation of memory to receive and
234 * transmit functions.
236 #define MMU_CMD_REG_W 0x00
237 #define MMUCR_BUSY 0x0001 /* MMU busy performing a release */
241 #define MMUCR_NOP 0x0000 /* Do nothing */
242 #define MMUCR_ALLOC 0x0020 /* Or with number of 256 byte packets - 1 */
243 #define MMUCR_RESET 0x0040 /* Reset MMU State */
244 #define MMUCR_REMOVE 0x0060 /* Dequeue (but not free) current RX packet */
245 #define MMUCR_RELEASE 0x0080 /* Dequeue and free the current RX packet */
246 #define MMUCR_FREEPKT 0x00a0 /* Release packet in PNR register */
247 #define MMUCR_ENQUEUE 0x00c0 /* Enqueue the packet for transmit */
248 #define MMUCR_RESETTX 0x00e0 /* Reset transmit queues */
250 /* Packet Number at TX Area
252 #define PACKET_NUM_REG_B 0x02
254 /* Packet number resulting from MMUCR_ALLOC
256 #define ALLOC_RESULT_REG_B 0x03
257 #define ARR_FAILED 0x80
259 /* Transmit and receive queue heads
261 #define FIFO_PORTS_REG_W 0x04
262 #define FIFO_REMPTY 0x8000
263 #define FIFO_TEMPTY 0x0080
264 #define FIFO_RX_MASK 0x7f00
265 #define FIFO_TX_MASK 0x007f
267 /* The address within the packet for reading/writing. The
268 * PTR_RCV bit is tricky. When PTR_RCV==1, the packet number
269 * to be read is found in the FIFO_PORTS_REG_W, FIFO_RX_MASK.
270 * When PTR_RCV==0, the packet number to be written is found
271 * in the PACKET_NUM_REG_B.
273 #define POINTER_REG_W 0x06
274 #define PTR_READ 0x2000 /* Intended access mode */
275 #define PTR_AUTOINC 0x4000 /* Do auto inc after read/write */
276 #define PTR_RCV 0x8000 /* FIFO_RX is packet, otherwise PNR is packet */
278 /* Data I/O register to be used in conjunction with
279 * The pointer register to read and write data from the
280 * card. The same register can be used for byte and word
283 #define DATA_REG_W 0x08
284 #define DATA_REG_B 0x08
285 #define DATA_1_REG_B 0x08
286 #define DATA_2_REG_B 0x0a
288 /* Sense interrupt status (READ)
290 #define INTR_STAT_REG_B 0x0c
292 /* Acknowledge interrupt sources (WRITE)
294 #define INTR_ACK_REG_B 0x0c
296 /* Interrupt mask. Bit set indicates interrupt allowed.
298 #define INTR_MASK_REG_B 0x0d
302 #define IM_RCV_INT 0x01 /* A packet has been received */
303 #define IM_TX_INT 0x02 /* Packet TX complete */
304 #define IM_TX_EMPTY_INT 0x04 /* No packets left to TX */
305 #define IM_ALLOC_INT 0x08 /* Memory allocation completed */
306 #define IM_RX_OVRN_INT 0x10 /* Receiver was overrun */
307 #define IM_EPH_INT 0x20 /* Misc. EPH conditions (see CONTROL_REG_W) */
308 #define IM_ERCV_INT 0x40 /* not on SMC9192 */
313 /* Multicast subscriptions.
314 * The multicast handling in the SMC90Cxx is quite complicated. A table
315 * of multicast address subscriptions is provided and a clever way of
316 * speeding the search of that table by hashing is implemented in the
317 * hardware. I have ignored this and simply subscribed to all multicasts
318 * and let the kernel deal with the results.
320 #define MULTICAST1_REG_W 0x00
321 #define MULTICAST2_REG_W 0x02
322 #define MULTICAST3_REG_W 0x04
323 #define MULTICAST4_REG_W 0x06
325 /* These registers do not exist on SMC9192, or at least
326 * are not documented in the SMC91C92 data sheet.
327 * The REVISION_REG_W register does however seem to work.
329 #define MGMT_REG_W 0x08
330 #define REVISION_REG_W 0x0a /* (hi: chip id low: rev #) */
331 #define ERCV_REG_W 0x0c
333 /* These are constants expected to be found in the
340 #define CHIP_91100FD 8
342 /* When packets are stuffed into the card or sucked out of the card
343 * they are set up more or less as follows:
346 * 00 SSSSSSSS SSSSSSSS - STATUS-WORD 16 bit TX or RX status
347 * 02 RRRRR - RESERVED (unused)
348 * 02 CCC CCCCCCCC - BYTE COUNT (RX: always even, TX: bit 0 ignored)
349 * 04 DDDDDDDD DDDDDDDD - DESTINATION ADDRESS
350 * 06 DDDDDDDD DDDDDDDD (48 bit Ethernet MAC Address)
351 * 08 DDDDDDDD DDDDDDDD
352 * 0A SSSSSSSS SSSSSSSS - SOURCE ADDRESS
353 * 0C SSSSSSSS SSSSSSSS (48 bit Ethernet MAC Address)
354 * 0E SSSSSSSS SSSSSSSS
355 * 10 PPPPPPPP PPPPPPPP
356 * .. PPPPPPPP PPPPPPPP
357 * C-2 CCCCCCCC - CONTROL BYTE
358 * C-2 PPPPPPPP - Last data byte (If odd length)
360 * The STATUS_WORD is derived from the EPH_STATUS_REG_W register
361 * during transmit and is composed of another set of bits described
362 * below during receive.
366 /* Receive status bits. These values are found in the status word
367 * field of a received packet. For receive packets I use the RS_ODDFRAME
368 * to detect whether a frame has an extra byte on it. The CTLB_ODD
369 * bit of the control byte tells the same thing.
371 #define RS_MULTICAST 0x0001 /* Packet is multicast */
372 #define RS_HASH_MASK 0x007e /* Mask of multicast hash value */
373 #define RS_TOOSHORT 0x0400 /* Frame was a runt, <64 bytes */
374 #define RS_TOOLONG 0x0800 /* Frame was giant, >1518 */
375 #define RS_ODDFRAME 0x1000 /* Frame is odd lengthed */
376 #define RS_BADCRC 0x2000 /* Frame had CRC error */
377 #define RS_ALGNERR 0x8000 /* Frame had alignment error */
378 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
380 #define RLEN_MASK 0x07ff /* Significant length bits in RX length */
382 /* The control byte has the following significant bits.
383 * For transmit, the CTLB_ODD bit specifies whether an extra byte
384 * is present in the frame. Bit 0 of the byte count field is
385 * ignored. I just pad every frame to even length and forget about
388 #define CTLB_CRC 0x10 /* Add CRC for this packet (TX only) */
389 #define CTLB_ODD 0x20 /* The packet length is ODD */
393 * I define some macros to make it easier to do somewhat common
394 * or slightly complicated, repeated tasks.
397 /* Select a register bank, 0 to 3
399 #define SMC_SELECT_BANK(sc, x) { CSR_WRITE_2(sc, BANK_SELECT_REG_W, (x)); }
401 /* Define a small delay for the reset
403 #define SMC_DELAY(sc) { CSR_READ_2(sc, RECV_CONTROL_REG_W); \
404 CSR_READ_2(sc, RECV_CONTROL_REG_W); \
405 CSR_READ_2(sc, RECV_CONTROL_REG_W); }
407 #endif /* _IF_SNREG_H_ */