2 * Copyright (c) 2001 George Reid <greid@ukug.uk.freebsd.org>
3 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
4 * Copyright (c) 1997,1998 Luigi Rizzo
5 * Copyright (c) 1994,1995 Hannu Savolainen
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <dev/sound/pcm/sound.h>
32 SND_DECLARE_FILE("$FreeBSD$");
34 /* board-specific include files */
35 #include <dev/sound/isa/mss.h>
36 #include <dev/sound/isa/sb.h>
37 #include <dev/sound/chip.h>
39 #include <isa/isavar.h>
43 #define MSS_DEFAULT_BUFSZ (4096)
44 #define MSS_INDEXED_REGS 0x20
45 #define OPL_INDEXED_REGS 0x19
50 struct mss_info *parent;
51 struct pcm_channel *channel;
52 struct snd_dbuf *buffer;
58 struct resource *io_base; /* primary I/O address for the board */
60 struct resource *conf_base; /* and the opti931 also has a config space */
64 struct resource *drq1; /* play */
66 struct resource *drq2; /* rec */
69 bus_dma_tag_t parent_dmat;
72 char mss_indexed_regs[MSS_INDEXED_REGS];
73 char opl_indexed_regs[OPL_INDEXED_REGS];
74 int bd_id; /* used to hold board-id info, eg. sb version,
75 * mss codec type, etc. etc.
77 int opti_offset; /* offset from config_base for opti931 */
78 u_long bd_flags; /* board-specific flags */
79 int optibase; /* base address for OPTi9xx config */
80 struct resource *indir; /* Indirect register index address */
82 int password; /* password for opti9xx cards */
83 int passwdreg; /* password register */
85 struct mss_chinfo pch, rch;
88 static int mss_probe(device_t dev);
89 static int mss_attach(device_t dev);
91 static driver_intr_t mss_intr;
93 /* prototypes for local functions */
94 static int mss_detect(device_t dev, struct mss_info *mss);
96 static int opti_detect(device_t dev, struct mss_info *mss);
98 static char *ymf_test(device_t dev, struct mss_info *mss);
99 static void ad_unmute(struct mss_info *mss);
101 /* mixer set funcs */
102 static int mss_mixer_set(struct mss_info *mss, int dev, int left, int right);
103 static int mss_set_recsrc(struct mss_info *mss, int mask);
106 static int ad_wait_init(struct mss_info *mss, int x);
107 static int ad_read(struct mss_info *mss, int reg);
108 static void ad_write(struct mss_info *mss, int reg, u_char data);
109 static void ad_write_cnt(struct mss_info *mss, int reg, u_short data);
110 static void ad_enter_MCE(struct mss_info *mss);
111 static void ad_leave_MCE(struct mss_info *mss);
113 /* OPTi-specific functions */
114 static void opti_write(struct mss_info *mss, u_char reg,
117 static u_char opti_read(struct mss_info *mss, u_char reg);
119 static int opti_init(device_t dev, struct mss_info *mss);
122 static void conf_wr(struct mss_info *mss, u_char reg, u_char data);
123 static u_char conf_rd(struct mss_info *mss, u_char reg);
125 static int pnpmss_probe(device_t dev);
126 static int pnpmss_attach(device_t dev);
128 static driver_intr_t opti931_intr;
130 static u_int32_t mss_fmt[] = {
132 AFMT_STEREO | AFMT_U8,
134 AFMT_STEREO | AFMT_S16_LE,
136 AFMT_STEREO | AFMT_MU_LAW,
138 AFMT_STEREO | AFMT_A_LAW,
141 static struct pcmchan_caps mss_caps = {4000, 48000, mss_fmt, 0};
143 static u_int32_t guspnp_fmt[] = {
145 AFMT_STEREO | AFMT_U8,
147 AFMT_STEREO | AFMT_S16_LE,
149 AFMT_STEREO | AFMT_A_LAW,
152 static struct pcmchan_caps guspnp_caps = {4000, 48000, guspnp_fmt, 0};
154 static u_int32_t opti931_fmt[] = {
156 AFMT_STEREO | AFMT_U8,
158 AFMT_STEREO | AFMT_S16_LE,
161 static struct pcmchan_caps opti931_caps = {4000, 48000, opti931_fmt, 0};
163 #define MD_AD1848 0x91
164 #define MD_AD1845 0x92
165 #define MD_CS42XX 0xA1
166 #define MD_CS423X 0xA2
167 #define MD_OPTI930 0xB0
168 #define MD_OPTI931 0xB1
169 #define MD_OPTI925 0xB2
170 #define MD_OPTI924 0xB3
171 #define MD_GUSPNP 0xB8
172 #define MD_GUSMAX 0xB9
173 #define MD_YM0020 0xC1
176 #define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */
178 #define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX)
181 mss_lock(struct mss_info *mss)
183 snd_mtxlock(mss->lock);
187 mss_unlock(struct mss_info *mss)
189 snd_mtxunlock(mss->lock);
193 port_rd(struct resource *port, int off)
196 return bus_space_read_1(rman_get_bustag(port),
197 rman_get_bushandle(port),
204 port_wr(struct resource *port, int off, u_int8_t data)
207 bus_space_write_1(rman_get_bustag(port),
208 rman_get_bushandle(port),
213 io_rd(struct mss_info *mss, int reg)
215 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
216 return port_rd(mss->io_base, reg);
220 io_wr(struct mss_info *mss, int reg, u_int8_t data)
222 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
223 port_wr(mss->io_base, reg, data);
227 conf_wr(struct mss_info *mss, u_char reg, u_char value)
229 port_wr(mss->conf_base, 0, reg);
230 port_wr(mss->conf_base, 1, value);
234 conf_rd(struct mss_info *mss, u_char reg)
236 port_wr(mss->conf_base, 0, reg);
237 return port_rd(mss->conf_base, 1);
241 opti_wr(struct mss_info *mss, u_char reg, u_char value)
243 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
244 port_wr(mss->conf_base, mss->opti_offset + 1, value);
248 opti_rd(struct mss_info *mss, u_char reg)
250 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
251 return port_rd(mss->conf_base, mss->opti_offset + 1);
255 gus_wr(struct mss_info *mss, u_char reg, u_char value)
257 port_wr(mss->conf_base, 3, reg);
258 port_wr(mss->conf_base, 5, value);
262 gus_rd(struct mss_info *mss, u_char reg)
264 port_wr(mss->conf_base, 3, reg);
265 return port_rd(mss->conf_base, 5);
269 mss_release_resources(struct mss_info *mss, device_t dev)
273 bus_teardown_intr(dev, mss->irq, mss->ih);
274 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid,
279 if (mss->drq2 != mss->drq1) {
280 isa_dma_release(rman_get_start(mss->drq2));
281 bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid,
287 isa_dma_release(rman_get_start(mss->drq1));
288 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid,
293 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid,
297 if (mss->conf_base) {
298 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
303 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid,
307 if (mss->parent_dmat) {
308 bus_dma_tag_destroy(mss->parent_dmat);
309 mss->parent_dmat = 0;
311 if (mss->lock) snd_mtxfree(mss->lock);
317 mss_alloc_resources(struct mss_info *mss, device_t dev)
319 int pdma, rdma, ok = 1;
321 mss->io_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
322 &mss->io_rid, RF_ACTIVE);
324 mss->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
325 &mss->irq_rid, RF_ACTIVE);
327 mss->drq1 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
330 if (mss->conf_rid >= 0 && !mss->conf_base)
331 mss->conf_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
334 if (mss->drq2_rid >= 0 && !mss->drq2)
335 mss->drq2 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
339 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0;
340 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0;
341 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0;
344 pdma = rman_get_start(mss->drq1);
345 isa_dma_acquire(pdma);
346 isa_dmainit(pdma, mss->bufsize);
347 mss->bd_flags &= ~BD_F_DUPLEX;
349 rdma = rman_get_start(mss->drq2);
350 isa_dma_acquire(rdma);
351 isa_dmainit(rdma, mss->bufsize);
352 mss->bd_flags |= BD_F_DUPLEX;
353 } else mss->drq2 = mss->drq1;
359 * The various mixers use a variety of bitmasks etc. The Voxware
360 * driver had a very nice technique to describe a mixer and interface
361 * to it. A table defines, for each channel, which register, bits,
362 * offset, polarity to use. This procedure creates the new value
363 * using the table and the old value.
367 change_bits(mixer_tab *t, u_char *regval, int dev, int chn, int newval)
372 DEB(printf("ch_bits dev %d ch %d val %d old 0x%02x "
373 "r %d p %d bit %d off %d\n",
374 dev, chn, newval, *regval,
375 (*t)[dev][chn].regno, (*t)[dev][chn].polarity,
376 (*t)[dev][chn].nbits, (*t)[dev][chn].bitoffs ) );
378 if ( (*t)[dev][chn].polarity == 1) /* reverse */
379 newval = 100 - newval ;
381 mask = (1 << (*t)[dev][chn].nbits) - 1;
382 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
383 shift = (*t)[dev][chn].bitoffs /*- (*t)[dev][LEFT_CHN].nbits + 1*/;
385 *regval &= ~(mask << shift); /* Filter out the previous value */
386 *regval |= (newval & mask) << shift; /* Set the new value */
389 /* -------------------------------------------------------------------- */
390 /* only one source can be set... */
392 mss_set_recsrc(struct mss_info *mss, int mask)
397 case SOUND_MASK_LINE:
398 case SOUND_MASK_LINE3:
403 case SOUND_MASK_LINE1:
407 case SOUND_MASK_IMIX:
413 mask = SOUND_MASK_MIC;
416 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev);
417 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev);
421 /* there are differences in the mixer depending on the actual sound card. */
423 mss_mixer_set(struct mss_info *mss, int dev, int left, int right)
429 switch (mss->bd_id) {
431 mix_d = &opti931_devices;
434 mix_d = &opti930_devices;
437 mix_d = &mix_devices;
440 if ((*mix_d)[dev][LEFT_CHN].nbits == 0) {
441 DEB(printf("nbits = 0 for dev %d\n", dev));
445 if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */
447 /* Set the left channel */
449 regoffs = (*mix_d)[dev][LEFT_CHN].regno;
450 old = val = ad_read(mss, regoffs);
451 /* if volume is 0, mute chan. Otherwise, unmute. */
452 if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f;
453 change_bits(mix_d, &val, dev, LEFT_CHN, left);
454 ad_write(mss, regoffs, val);
456 DEB(printf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n",
457 dev, regoffs, old, val));
459 if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */
460 /* Set the right channel */
461 regoffs = (*mix_d)[dev][RIGHT_CHN].regno;
462 old = val = ad_read(mss, regoffs);
463 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f;
464 change_bits(mix_d, &val, dev, RIGHT_CHN, right);
465 ad_write(mss, regoffs, val);
467 DEB(printf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n",
468 dev, regoffs, old, val));
470 return 0; /* success */
473 /* -------------------------------------------------------------------- */
476 mssmix_init(struct snd_mixer *m)
478 struct mss_info *mss = mix_getdevinfo(m);
480 mix_setdevs(m, MODE2_MIXER_DEVICES);
481 mix_setrecdevs(m, MSS_REC_DEVICES);
484 mix_setdevs(m, OPTI930_MIXER_DEVICES);
488 mix_setdevs(m, OPTI931_MIXER_DEVICES);
490 ad_write(mss, 20, 0x88);
491 ad_write(mss, 21, 0x88);
496 mix_setdevs(m, MODE1_MIXER_DEVICES);
501 /* this is only necessary in mode 3 ... */
503 ad_write(mss, 22, 0x88);
504 ad_write(mss, 23, 0x88);
512 mssmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
514 struct mss_info *mss = mix_getdevinfo(m);
517 mss_mixer_set(mss, dev, left, right);
520 return left | (right << 8);
524 mssmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
526 struct mss_info *mss = mix_getdevinfo(m);
529 src = mss_set_recsrc(mss, src);
534 static kobj_method_t mssmix_mixer_methods[] = {
535 KOBJMETHOD(mixer_init, mssmix_init),
536 KOBJMETHOD(mixer_set, mssmix_set),
537 KOBJMETHOD(mixer_setrecsrc, mssmix_setrecsrc),
540 MIXER_DECLARE(mssmix_mixer);
542 /* -------------------------------------------------------------------- */
545 ymmix_init(struct snd_mixer *m)
547 struct mss_info *mss = mix_getdevinfo(m);
550 mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC
551 | SOUND_MASK_BASS | SOUND_MASK_TREBLE);
552 /* Set master volume */
554 conf_wr(mss, OPL3SAx_VOLUMEL, 7);
555 conf_wr(mss, OPL3SAx_VOLUMER, 7);
562 ymmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
564 struct mss_info *mss = mix_getdevinfo(m);
569 case SOUND_MIXER_VOLUME:
570 if (left) t = 15 - (left * 15) / 100;
571 else t = 0x80; /* mute */
572 conf_wr(mss, OPL3SAx_VOLUMEL, t);
573 if (right) t = 15 - (right * 15) / 100;
574 else t = 0x80; /* mute */
575 conf_wr(mss, OPL3SAx_VOLUMER, t);
578 case SOUND_MIXER_MIC:
580 if (left) t = 31 - (left * 31) / 100;
581 else t = 0x80; /* mute */
582 conf_wr(mss, OPL3SAx_MIC, t);
585 case SOUND_MIXER_BASS:
586 l = (left * 7) / 100;
587 r = (right * 7) / 100;
589 conf_wr(mss, OPL3SAx_BASS, t);
592 case SOUND_MIXER_TREBLE:
593 l = (left * 7) / 100;
594 r = (right * 7) / 100;
596 conf_wr(mss, OPL3SAx_TREBLE, t);
600 mss_mixer_set(mss, dev, left, right);
604 return left | (right << 8);
608 ymmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
610 struct mss_info *mss = mix_getdevinfo(m);
612 src = mss_set_recsrc(mss, src);
617 static kobj_method_t ymmix_mixer_methods[] = {
618 KOBJMETHOD(mixer_init, ymmix_init),
619 KOBJMETHOD(mixer_set, ymmix_set),
620 KOBJMETHOD(mixer_setrecsrc, ymmix_setrecsrc),
623 MIXER_DECLARE(ymmix_mixer);
625 /* -------------------------------------------------------------------- */
627 * XXX This might be better off in the gusc driver.
630 gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt)
632 static const unsigned char irq_bits[16] = {
633 0, 0, 0, 3, 0, 2, 0, 4, 0, 1, 0, 5, 6, 0, 0, 7
635 static const unsigned char dma_bits[8] = {
636 0, 1, 0, 2, 0, 3, 4, 5
638 device_t parent = device_get_parent(dev);
639 unsigned char irqctl, dmactl;
644 port_wr(alt, 0x0f, 0x05);
645 port_wr(alt, 0x00, 0x0c);
646 port_wr(alt, 0x0b, 0x00);
648 port_wr(alt, 0x0f, 0x00);
650 irqctl = irq_bits[isa_get_irq(parent)];
651 /* Share the IRQ with the MIDI driver. */
653 dmactl = dma_bits[isa_get_drq(parent)];
654 if (device_get_flags(parent) & DV_F_DUAL_DMA)
655 dmactl |= dma_bits[device_get_flags(parent) & DV_F_DRQ_MASK]
659 * Set the DMA and IRQ control latches.
661 port_wr(alt, 0x00, 0x0c);
662 port_wr(alt, 0x0b, dmactl | 0x80);
663 port_wr(alt, 0x00, 0x4c);
664 port_wr(alt, 0x0b, irqctl);
666 port_wr(alt, 0x00, 0x0c);
667 port_wr(alt, 0x0b, dmactl);
668 port_wr(alt, 0x00, 0x4c);
669 port_wr(alt, 0x0b, irqctl);
671 port_wr(mss->conf_base, 2, 0);
672 port_wr(alt, 0x00, 0x0c);
673 port_wr(mss->conf_base, 2, 0);
679 mss_init(struct mss_info *mss, device_t dev)
682 struct resource *alt;
685 mss->bd_flags |= BD_F_MCE_BIT;
689 * The MED3931 v.1.0 allocates 3 bytes for the config
690 * space, whereas v.2.0 allocates 4 bytes. What I know
691 * for sure is that the upper two ports must be used,
692 * and they should end on a boundary of 4 bytes. So I
693 * need the following trick.
696 (rman_get_start(mss->conf_base) & ~3) + 2
697 - rman_get_start(mss->conf_base);
698 BVDDB(printf("mss_init: opti_offset=%d\n", mss->opti_offset));
699 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */
700 ad_write(mss, 10, 2); /* enable interrupts */
701 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */
702 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */
707 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */
709 /* release reset and enable DAC */
710 gus_wr(mss, 0x4c /* _URSTI */, 3);
715 alt = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
718 printf("XXX couldn't init GUS PnP/MAX\n");
721 port_wr(alt, 0, 0xC); /* enable int and dma */
722 if (mss->bd_id == MD_GUSMAX)
723 gusmax_setup(mss, dev, alt);
724 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt);
727 * unmute left & right line. Need to go in mode3, unmute,
730 tmp = ad_read(mss, 0x0c);
731 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */
732 ad_write(mss, 0x19, 0); /* unmute left */
733 ad_write(mss, 0x1b, 0); /* unmute right */
734 ad_write(mss, 0x0c, tmp); /* restore old mode */
736 /* send codec interrupts on irq1 and only use that one */
737 gus_wr(mss, 0x5a, 0x4f);
739 /* enable access to hidden regs */
740 tmp = gus_rd(mss, 0x5b /* IVERI */);
741 gus_wr(mss, 0x5b, tmp | 1);
742 BVDDB(printf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4)));
746 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */
747 r6 = conf_rd(mss, OPL3SAx_DMACONF);
748 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */
749 BVDDB(printf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);)
750 /* yamaha - set volume to max */
751 conf_wr(mss, OPL3SAx_VOLUMEL, 0);
752 conf_wr(mss, OPL3SAx_VOLUMER, 0);
753 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b);
756 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931)
757 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */
759 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4);
761 ad_write(mss, 10, 2); /* int enable */
762 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
763 /* the following seem required on the CS4232 */
770 * main irq handler for the CS423x. The OPTi931 code is
772 * The correct way to operate for a device with multiple internal
773 * interrupt sources is to loop on the status register and ack
774 * interrupts until all interrupts are served and none are reported. At
775 * this point the IRQ line to the ISA IRQ controller should go low
776 * and be raised at the next interrupt.
778 * Since the ISA IRQ controller is sent EOI _before_ passing control
779 * to the isr, it might happen that we serve an interrupt early, in
780 * which case the status register at the next interrupt should just
781 * say that there are no more interrupts...
787 struct mss_info *mss = arg;
788 u_char c = 0, served = 0;
791 DEB(printf("mss_intr\n"));
793 ad_read(mss, 11); /* fake read of status bits */
795 /* loop until there are interrupts, but no more than 10 times. */
796 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) {
797 /* get exact reason for full-duplex boards */
798 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30;
800 if (sndbuf_runsz(mss->pch.buffer) && (c & 0x10)) {
803 chn_intr(mss->pch.channel);
806 if (sndbuf_runsz(mss->rch.buffer) && (c & 0x20)) {
809 chn_intr(mss->rch.channel);
812 /* now ack the interrupt */
813 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */
814 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
817 BVDDB(printf("mss_intr: irq, but not from mss\n"));
818 } else if (served == 0) {
819 BVDDB(printf("mss_intr: unexpected irq with reason %x\n", c));
821 * this should not happen... I have no idea what to do now.
822 * maybe should do a sanity check and restart dmas ?
824 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
830 * AD_WAIT_INIT waits if we are initializing the board and
831 * we cannot modify its settings
834 ad_wait_init(struct mss_info *mss, int x)
836 int arg = x, n = 0; /* to shut up the compiler... */
838 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10);
840 printf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n);
845 ad_read(struct mss_info *mss, int reg)
849 ad_wait_init(mss, 201000);
850 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
851 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
852 x = io_rd(mss, MSS_IDATA);
853 /* printf("ad_read %d, %x\n", reg, x); */
858 ad_write(struct mss_info *mss, int reg, u_char data)
862 /* printf("ad_write %d, %x\n", reg, data); */
863 ad_wait_init(mss, 1002000);
864 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
865 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
866 io_wr(mss, MSS_IDATA, data);
870 ad_write_cnt(struct mss_info *mss, int reg, u_short cnt)
872 ad_write(mss, reg+1, cnt & 0xff);
873 ad_write(mss, reg, cnt >> 8); /* upper base must be last */
877 wait_for_calibration(struct mss_info *mss)
882 * Wait until the auto calibration process has finished.
884 * 1) Wait until the chip becomes ready (reads don't return 0x80).
885 * 2) Wait until the ACI bit of I11 gets on
886 * 3) Wait until the ACI bit of I11 gets off
889 t = ad_wait_init(mss, 1000000);
890 if (t & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n");
893 * The calibration mode for chips that support it is set so that
894 * we never see ACI go on.
896 if (mss->bd_id == MD_GUSMAX || mss->bd_id == MD_GUSPNP) {
897 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--);
900 * XXX This should only be enabled for cards that *really*
901 * need it. Are there any?
903 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100);
905 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100);
909 ad_unmute(struct mss_info *mss)
911 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE);
912 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE);
916 ad_enter_MCE(struct mss_info *mss)
920 mss->bd_flags |= BD_F_MCE_BIT;
921 ad_wait_init(mss, 203000);
922 prev = io_rd(mss, MSS_INDEX);
924 io_wr(mss, MSS_INDEX, prev | MSS_MCE);
928 ad_leave_MCE(struct mss_info *mss)
932 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) {
933 DEB(printf("--- hey, leave_MCE: MCE bit was not set!\n"));
937 ad_wait_init(mss, 1000000);
939 mss->bd_flags &= ~BD_F_MCE_BIT;
941 prev = io_rd(mss, MSS_INDEX);
943 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */
944 wait_for_calibration(mss);
948 mss_speed(struct mss_chinfo *ch, int speed)
950 struct mss_info *mss = ch->parent;
952 * In the CS4231, the low 4 bits of I8 are used to hold the
953 * sample rate. Only a fixed number of values is allowed. This
954 * table lists them. The speed-setting routines scans the table
955 * looking for the closest match. This is the only supported method.
957 * In the CS4236, there is an alternate metod (which we do not
958 * support yet) which provides almost arbitrary frequency setting.
959 * In the AD1845, it looks like the sample rate can be
960 * almost arbitrary, and written directly to a register.
961 * In the OPTi931, there is a SB command which provides for
962 * almost arbitrary frequency setting.
966 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */
967 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */
968 ad_write(mss, 23, speed & 0xff); /* Speed LSB */
969 /* XXX must also do something in I27 for the ad1845 */
971 int i, sel = 0; /* assume entry 0 does not contain -1 */
972 static int speeds[] =
973 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050,
974 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615};
976 for (i = 1; i < 16; i++)
978 abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i;
980 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel);
981 ad_wait_init(mss, 10000);
989 * mss_format checks that the format is supported (or defaults to AFMT_U8)
990 * and returns the bit setting for the 1848 register corresponding to
991 * the desired format.
997 mss_format(struct mss_chinfo *ch, u_int32_t format)
999 struct mss_info *mss = ch->parent;
1000 int i, arg = format & ~AFMT_STEREO;
1003 * The data format uses 3 bits (just 2 on the 1848). For each
1004 * bit setting, the following array returns the corresponding format.
1005 * The code scans the array looking for a suitable format. In
1006 * case it is not found, default to AFMT_U8 (not such a good
1007 * choice, but let's do it for compatibility...).
1011 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW,
1012 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1};
1015 for (i = 0; i < 8; i++) if (arg == fmts[i]) break;
1017 if (format & AFMT_STEREO) arg |= 1;
1020 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg);
1021 ad_wait_init(mss, 10000);
1022 if (ad_read(mss, 12) & 0x40) { /* mode2? */
1023 ad_write(mss, 28, arg); /* capture mode */
1024 ad_wait_init(mss, 10000);
1031 mss_trigger(struct mss_chinfo *ch, int go)
1033 struct mss_info *mss = ch->parent;
1035 int retry, wr, cnt, ss;
1038 ss <<= (ch->fmt & AFMT_STEREO)? 1 : 0;
1039 ss <<= (ch->fmt & AFMT_16BIT)? 1 : 0;
1041 wr = (ch->dir == PCMDIR_PLAY)? 1 : 0;
1042 m = ad_read(mss, 9);
1045 cnt = (ch->blksz / ss) - 1;
1047 DEB(if (m & 4) printf("OUCH! reg 9 0x%02x\n", m););
1048 m |= wr? I9_PEN : I9_CEN; /* enable DMA */
1049 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt);
1053 case PCMTRIG_ABORT: /* XXX check this... */
1054 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */
1057 * try to disable DMA by clearing count registers. Not sure it
1058 * is needed, and it might cause false interrupts when the
1059 * DMA is re-enabled later.
1061 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0);
1064 /* on the OPTi931 the enable bit seems hard to set... */
1065 for (retry = 10; retry > 0; retry--) {
1066 ad_write(mss, 9, m);
1067 if (ad_read(mss, 9) == m) break;
1069 if (retry == 0) BVDDB(printf("stop dma, failed to set bit 0x%02x 0x%02x\n", \
1070 m, ad_read(mss, 9)));
1076 * the opti931 seems to miss interrupts when working in full
1077 * duplex, so we try some heuristics to catch them.
1080 opti931_intr(void *arg)
1082 struct mss_info *mss = (struct mss_info *)arg;
1083 u_char masked = 0, i11, mc11, c = 0;
1084 u_char reason; /* b0 = playback, b1 = capture, b2 = timer */
1088 reason = io_rd(mss, MSS_STATUS);
1089 if (!(reason & 1)) {/* no int, maybe a shared line ? */
1090 DEB(printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11)));
1095 i11 = ad_read(mss, 11); /* XXX what's for ? */
1098 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc;
1101 DEB(printf("Warning: CD interrupt\n");)
1105 DEB(printf("Warning: MPU interrupt\n");)
1108 if (mc11 & masked) BVDDB(printf("irq reset failed, mc11 0x%02x, 0x%02x\n",\
1112 * the nice OPTi931 sets the IRQ line before setting the bits in
1113 * mc11. So, on some occasions I have to retry (max 10 times).
1115 if (mc11 == 0) { /* perhaps can return ... */
1116 reason = io_rd(mss, MSS_STATUS);
1118 DEB(printf("one more try...\n");)
1119 if (--loops) goto again;
1120 else BVDDB(printf("intr, but mc11 not set\n");)
1122 if (loops == 0) BVDDB(printf("intr, nothing in mcir11 0x%02x\n", mc11));
1127 if (sndbuf_runsz(mss->rch.buffer) && (mc11 & 8)) {
1129 chn_intr(mss->rch.channel);
1132 if (sndbuf_runsz(mss->pch.buffer) && (mc11 & 4)) {
1134 chn_intr(mss->pch.channel);
1137 opti_wr(mss, 11, ~mc11); /* ack */
1138 if (--loops) goto again;
1140 DEB(printf("xxx too many loops\n");)
1143 /* -------------------------------------------------------------------- */
1144 /* channel interface */
1146 msschan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
1148 struct mss_info *mss = devinfo;
1149 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch;
1155 if (sndbuf_alloc(ch->buffer, mss->parent_dmat, 0, mss->bufsize) != 0)
1157 sndbuf_dmasetup(ch->buffer, (dir == PCMDIR_PLAY)? mss->drq1 : mss->drq2);
1162 msschan_setformat(kobj_t obj, void *data, u_int32_t format)
1164 struct mss_chinfo *ch = data;
1165 struct mss_info *mss = ch->parent;
1168 mss_format(ch, format);
1174 msschan_setspeed(kobj_t obj, void *data, u_int32_t speed)
1176 struct mss_chinfo *ch = data;
1177 struct mss_info *mss = ch->parent;
1181 r = mss_speed(ch, speed);
1188 msschan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1190 struct mss_chinfo *ch = data;
1192 ch->blksz = blocksize;
1193 sndbuf_resize(ch->buffer, 2, ch->blksz);
1199 msschan_trigger(kobj_t obj, void *data, int go)
1201 struct mss_chinfo *ch = data;
1202 struct mss_info *mss = ch->parent;
1204 if (!PCMTRIG_COMMON(go))
1207 sndbuf_dma(ch->buffer, go);
1209 mss_trigger(ch, go);
1215 msschan_getptr(kobj_t obj, void *data)
1217 struct mss_chinfo *ch = data;
1218 return sndbuf_dmaptr(ch->buffer);
1221 static struct pcmchan_caps *
1222 msschan_getcaps(kobj_t obj, void *data)
1224 struct mss_chinfo *ch = data;
1226 switch(ch->parent->bd_id) {
1228 return &opti931_caps;
1233 return &guspnp_caps;
1242 static kobj_method_t msschan_methods[] = {
1243 KOBJMETHOD(channel_init, msschan_init),
1244 KOBJMETHOD(channel_setformat, msschan_setformat),
1245 KOBJMETHOD(channel_setspeed, msschan_setspeed),
1246 KOBJMETHOD(channel_setblocksize, msschan_setblocksize),
1247 KOBJMETHOD(channel_trigger, msschan_trigger),
1248 KOBJMETHOD(channel_getptr, msschan_getptr),
1249 KOBJMETHOD(channel_getcaps, msschan_getcaps),
1252 CHANNEL_DECLARE(msschan);
1254 /* -------------------------------------------------------------------- */
1257 * mss_probe() is the probe routine. Note, it is not necessary to
1258 * go through this for PnP devices, since they are already
1259 * indentified precisely using their PnP id.
1261 * The base address supplied in the device refers to the old MSS
1262 * specs where the four 4 registers in io space contain configuration
1263 * information. Some boards (as an example, early MSS boards)
1264 * has such a block of registers, whereas others (generally CS42xx)
1265 * do not. In order to distinguish between the two and do not have
1266 * to supply two separate probe routines, the flags entry in isa_device
1267 * has a bit to mark this.
1272 mss_probe(device_t dev)
1275 int flags, irq, drq, result = ENXIO, setres = 0;
1276 struct mss_info *mss;
1278 if (isa_get_logicalid(dev)) return ENXIO; /* not yet */
1280 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
1281 if (!mss) return ENXIO;
1288 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1289 0, ~0, 8, RF_ACTIVE);
1290 if (!mss->io_base) {
1291 BVDDB(printf("mss_probe: no address given, try 0x%x\n", 0x530));
1293 /* XXX verify this */
1295 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid,
1297 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1298 0, ~0, 8, RF_ACTIVE);
1300 if (!mss->io_base) goto no;
1302 /* got irq/dma regs? */
1303 flags = device_get_flags(dev);
1304 irq = isa_get_irq(dev);
1305 drq = isa_get_drq(dev);
1307 if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end;
1310 * Check if the IO port returns valid signature. The original MS
1311 * Sound system returns 0x04 while some cards
1312 * (AudioTriX Pro for example) return 0x00 or 0x0f.
1315 device_set_desc(dev, "MSS");
1316 tmpx = tmp = io_rd(mss, 3);
1317 if (tmp == 0xff) { /* Bus float */
1318 BVDDB(printf("I/O addr inactive (%x), try pseudo_mss\n", tmp));
1319 device_set_flags(dev, flags & ~DV_F_TRUE_MSS);
1323 if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00 || tmp == 0x05)) {
1324 BVDDB(printf("No MSS signature detected on port 0x%lx (0x%x)\n",
1325 rman_get_start(mss->io_base), tmpx));
1333 printf("MSS: Bad IRQ %d\n", irq);
1336 if (!(drq == 0 || drq == 1 || drq == 3)) {
1337 printf("MSS: Bad DMA %d\n", drq);
1341 /* 8-bit board: only drq1/3 and irq7/9 */
1343 printf("MSS: Can't use DMA0 with a 8 bit card/slot\n");
1346 if (!(irq == 7 || irq == 9)) {
1347 printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n",
1353 result = mss_detect(dev, mss);
1355 mss_release_resources(mss, dev);
1357 if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev,
1358 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */
1364 mss_detect(device_t dev, struct mss_info *mss)
1367 u_char tmp = 0, tmp1, tmp2;
1368 char *name, *yamaha;
1370 if (mss->bd_id != 0) {
1371 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id,
1372 device_get_desc(dev));
1377 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */
1380 if (opti_detect(dev, mss)) {
1381 switch (mss->bd_id) {
1389 printf("Found OPTi device %s\n", name);
1390 if (opti_init(dev, mss) == 0) goto gotit;
1395 * Check that the I/O address is in use.
1397 * bit 7 of the base I/O port is known to be 0 after the chip has
1398 * performed its power on initialization. Just assume this has
1399 * happened before the OS is starting.
1401 * If the I/O address is unused, it typically returns 0xff.
1404 for (i = 0; i < 10; i++)
1405 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000);
1408 if (i >= 10) { /* Not an AD1848 */
1409 BVDDB(printf("mss_detect, busy still set (0x%02x)\n", tmp));
1413 * Test if it's possible to change contents of the indirect
1414 * registers. Registers 0 and 1 are ADC volume registers. The bit
1415 * 0x10 is read only so try to avoid using it.
1418 ad_write(mss, 0, 0xaa);
1419 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */
1420 tmp1 = ad_read(mss, 0);
1421 tmp2 = ad_read(mss, 1);
1422 if (tmp1 != 0xaa || tmp2 != 0x45) {
1423 BVDDB(printf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2));
1427 ad_write(mss, 0, 0x45);
1428 ad_write(mss, 1, 0xaa);
1429 tmp1 = ad_read(mss, 0);
1430 tmp2 = ad_read(mss, 1);
1431 if (tmp1 != 0x45 || tmp2 != 0xaa) {
1432 BVDDB(printf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2));
1437 * The indirect register I12 has some read only bits. Lets try to
1441 tmp = ad_read(mss, 12);
1442 ad_write(mss, 12, (~tmp) & 0x0f);
1443 tmp1 = ad_read(mss, 12);
1445 if ((tmp & 0x0f) != (tmp1 & 0x0f)) {
1446 BVDDB(printf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp));
1451 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1453 * 0x0A=RevC. also CS4231/CS4231A and OPTi931
1456 BVDDB(printf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);)
1459 * The original AD1848/CS4248 has just 16 indirect registers. This
1460 * means that I0 and I16 should return the same value (etc.). Ensure
1461 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1465 ad_write(mss, 12, 0); /* Mode2=disabled */
1467 for (i = 0; i < 16; i++) {
1468 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) {
1469 BVDDB(printf("mss_detect warning - I%d: 0x%02x/0x%02x\n",
1472 * note - this seems to fail on the 4232 on I11. So we just break
1473 * rather than fail. (which makes this test pointless - cg)
1475 break; /* return 0; */
1480 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit
1481 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231.
1483 * On the OPTi931, however, I12 is readonly and only contains the
1484 * chip revision ID (as in the CS4231A). The upper bits return 0.
1487 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */
1489 tmp1 = ad_read(mss, 12);
1490 if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */
1491 if ((tmp1 & 0xf0) == 0x00) {
1492 BVDDB(printf("this should be an OPTi931\n");)
1493 } else if ((tmp1 & 0xc0) != 0xC0) goto gotit;
1495 * The 4231 has bit7=1 always, and bit6 we just set to 1.
1496 * We want to check that this is really a CS4231
1497 * Verify that setting I0 doesn't change I16.
1499 ad_write(mss, 16, 0); /* Set I16 to known value */
1500 ad_write(mss, 0, 0x45);
1501 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit;
1503 ad_write(mss, 0, 0xaa);
1504 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */
1505 BVDDB(printf("mss_detect error - step H(%x)\n", tmp1));
1508 /* Verify that some bits of I25 are read only. */
1509 tmp1 = ad_read(mss, 25); /* Original bits */
1510 ad_write(mss, 25, ~tmp1); /* Invert all bits */
1511 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) {
1514 /* It's at least CS4231 */
1516 mss->bd_id = MD_CS42XX;
1519 * It could be an AD1845 or CS4231A as well.
1520 * CS4231 and AD1845 report the same revision info in I25
1521 * while the CS4231A reports different.
1524 id = ad_read(mss, 25) & 0xe7;
1526 * b7-b5 = version number;
1536 mss->bd_id = MD_CS42XX;
1541 mss->bd_id = MD_CS42XX;
1545 /* strange: the 4231 data sheet says b4-b3 are XX
1546 * so this should be the same as 0xa2
1549 mss->bd_id = MD_CS42XX;
1554 * It must be a CS4231 or AD1845. The register I23
1555 * of CS4231 is undefined and it appears to be read
1556 * only. AD1845 uses I23 for setting sample rate.
1557 * Assume the chip is AD1845 if I23 is changeable.
1560 tmp = ad_read(mss, 23);
1562 ad_write(mss, 23, ~tmp);
1563 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */
1565 mss->bd_id = MD_AD1845;
1567 ad_write(mss, 23, tmp); /* Restore */
1569 yamaha = ymf_test(dev, mss);
1571 mss->bd_id = MD_YM0020;
1576 case 0x83: /* CS4236 */
1577 case 0x03: /* CS4236 on Intel PR440FX motherboard XXX */
1579 mss->bd_id = MD_CS42XX;
1582 default: /* Assume CS4231 */
1583 BVDDB(printf("unknown id 0x%02x, assuming CS4231\n", id);)
1584 mss->bd_id = MD_CS42XX;
1587 ad_write(mss, 25, tmp1); /* Restore bits */
1589 BVDDB(printf("mss_detect() - Detected %s\n", name));
1590 device_set_desc(dev, name);
1591 device_set_flags(dev,
1592 ((device_get_flags(dev) & ~DV_F_DEV_MASK) |
1593 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK)));
1601 opti_detect(device_t dev, struct mss_info *mss)
1604 static const struct opticard {
1611 { MD_OPTI930, 0, 0xe4, 0xf8f, 0xe0e }, /* 930 */
1612 { MD_OPTI924, 3, 0xe5, 0xf8c, 0, }, /* 924 */
1617 for (c = 0; cards[c].base; c++) {
1618 mss->optibase = cards[c].base;
1619 mss->password = cards[c].password;
1620 mss->passwdreg = cards[c].passwdreg;
1621 mss->bd_id = cards[c].boardid;
1623 if (cards[c].indir_reg)
1624 mss->indir = bus_alloc_resource(dev, SYS_RES_IOPORT,
1625 &mss->indir_rid, cards[c].indir_reg,
1626 cards[c].indir_reg+1, 1, RF_ACTIVE);
1628 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
1629 &mss->conf_rid, mss->optibase, mss->optibase+9,
1632 if (opti_read(mss, 1) != 0xff) {
1636 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, mss->indir);
1639 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, mss->conf_base);
1640 mss->conf_base = NULL;
1648 ymf_test(device_t dev, struct mss_info *mss)
1650 static int ports[] = {0x370, 0x310, 0x538};
1651 int p, i, j, version;
1652 static char *chipset[] = {
1654 "OPL3-SA2 (YMF711)", /* 1 */
1655 "OPL3-SA3 (YMF715)", /* 2 */
1656 "OPL3-SA3 (YMF715)", /* 3 */
1657 "OPL3-SAx (YMF719)", /* 4 */
1658 "OPL3-SAx (YMF719)", /* 5 */
1659 "OPL3-SAx (YMF719)", /* 6 */
1660 "OPL3-SAx (YMF719)", /* 7 */
1663 for (p = 0; p < 3; p++) {
1665 mss->conf_base = bus_alloc_resource(dev,
1668 ports[p], ports[p] + 1, 2,
1670 if (!mss->conf_base) return 0;
1672 /* Test the index port of the config registers */
1673 i = port_rd(mss->conf_base, 0);
1674 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF);
1675 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0;
1676 port_wr(mss->conf_base, 0, i);
1678 bus_release_resource(dev, SYS_RES_IOPORT,
1679 mss->conf_rid, mss->conf_base);
1681 /* PC98 need this. I don't know reason why. */
1682 bus_delete_resource(dev, SYS_RES_IOPORT, mss->conf_rid);
1687 version = conf_rd(mss, OPL3SAx_MISC) & 0x07;
1688 return chipset[version];
1694 mss_doattach(device_t dev, struct mss_info *mss)
1696 int pdma, rdma, flags = device_get_flags(dev);
1697 char status[SND_STATUSLEN], status2[SND_STATUSLEN];
1699 mss->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_mss softc");
1700 mss->bufsize = pcm_getbuffersize(dev, 4096, MSS_DEFAULT_BUFSZ, 65536);
1701 if (!mss_alloc_resources(mss, dev)) goto no;
1703 pdma = rman_get_start(mss->drq1);
1704 rdma = rman_get_start(mss->drq2);
1705 if (flags & DV_F_TRUE_MSS) {
1706 /* has IRQ/DMA registers, set IRQ and DMA addr */
1707 #ifdef PC98 /* CS423[12] in PC98 can use IRQ3,5,10,12 */
1708 static char interrupt_bits[13] =
1709 {-1, -1, -1, 0x08, -1, 0x10, -1, -1, -1, -1, 0x18, -1, 0x20};
1711 static char interrupt_bits[12] =
1712 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20};
1714 static char pdma_bits[4] = {1, 2, -1, 3};
1715 static char valid_rdma[4] = {1, 0, -1, 0};
1718 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1)
1720 #ifndef PC98 /* CS423[12] in PC98 don't support this. */
1721 io_wr(mss, 0, bits | 0x40); /* config port */
1722 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n");
1724 /* Write IRQ+DMA setup */
1725 if (pdma_bits[pdma] == -1) goto no;
1726 bits |= pdma_bits[pdma];
1728 if (rdma == valid_rdma[pdma]) bits |= 4;
1730 printf("invalid dual dma config %d:%d\n", pdma, rdma);
1734 io_wr(mss, 0, bits);
1735 printf("drq/irq conf %x\n", io_rd(mss, 0));
1737 mixer_init(dev, (mss->bd_id == MD_YM0020)? &ymmix_mixer_class : &mssmix_mixer_class, mss);
1738 switch (mss->bd_id) {
1740 snd_setup_intr(dev, mss->irq, 0, opti931_intr, mss, &mss->ih);
1743 snd_setup_intr(dev, mss->irq, 0, mss_intr, mss, &mss->ih);
1746 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX);
1747 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
1749 /*lowaddr*/BUS_SPACE_MAXADDR_24BIT,
1750 /*highaddr*/BUS_SPACE_MAXADDR,
1751 /*filter*/NULL, /*filterarg*/NULL,
1752 /*maxsize*/mss->bufsize, /*nsegments*/1,
1753 /*maxsegz*/0x3ffff, /*flags*/0,
1754 /*lockfunc*/busdma_lock_mutex, /*lockarg*/&Giant,
1755 &mss->parent_dmat) != 0) {
1756 device_printf(dev, "unable to create dma tag\n");
1761 snprintf(status2, SND_STATUSLEN, ":%d", rdma);
1765 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld drq %d%s bufsz %u",
1766 rman_get_start(mss->io_base), rman_get_start(mss->irq), pdma, status2, mss->bufsize);
1768 if (pcm_register(dev, mss, 1, 1)) goto no;
1769 pcm_addchan(dev, PCMDIR_REC, &msschan_class, mss);
1770 pcm_addchan(dev, PCMDIR_PLAY, &msschan_class, mss);
1771 pcm_setstatus(dev, status);
1775 mss_release_resources(mss, dev);
1780 mss_detach(device_t dev)
1783 struct mss_info *mss;
1785 r = pcm_unregister(dev);
1789 mss = pcm_getdevinfo(dev);
1790 mss_release_resources(mss, dev);
1796 mss_attach(device_t dev)
1798 struct mss_info *mss;
1799 int flags = device_get_flags(dev);
1801 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
1802 if (!mss) return ENXIO;
1809 if (flags & DV_F_DUAL_DMA) {
1810 bus_set_resource(dev, SYS_RES_DRQ, 1,
1811 flags & DV_F_DRQ_MASK, 1);
1814 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT;
1815 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss);
1816 return mss_doattach(dev, mss);
1820 * mss_resume() is the code to allow a laptop to resume using the sound
1823 * This routine re-sets the state of the board to the state before going
1824 * to sleep. According to the yamaha docs this is the right thing to do,
1825 * but getting DMA restarted appears to be a bit of a trick, so the device
1826 * has to be closed and re-opened to be re-used, but there is no skipping
1827 * problem, and volume, bass/treble and most other things are restored
1833 mss_resume(device_t dev)
1836 * Restore the state taken below.
1838 struct mss_info *mss;
1841 mss = pcm_getdevinfo(dev);
1843 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X) {
1844 /* This works on a Toshiba Libretto 100CT. */
1845 for (i = 0; i < MSS_INDEXED_REGS; i++)
1846 ad_write(mss, i, mss->mss_indexed_regs[i]);
1847 for (i = 0; i < OPL_INDEXED_REGS; i++)
1848 conf_wr(mss, i, mss->opl_indexed_regs[i]);
1852 if (mss->bd_id == MD_CS423X) {
1853 /* Needed on IBM Thinkpad 600E */
1855 mss_format(&mss->pch, mss->pch.channel->format);
1856 mss_speed(&mss->pch, mss->pch.channel->speed);
1865 * mss_suspend() is the code that gets called right before a laptop
1868 * This code saves the state of the sound card right before shutdown
1869 * so it can be restored above.
1874 mss_suspend(device_t dev)
1877 struct mss_info *mss;
1879 mss = pcm_getdevinfo(dev);
1881 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X)
1883 /* this stops playback. */
1884 conf_wr(mss, 0x12, 0x0c);
1885 for(i = 0; i < MSS_INDEXED_REGS; i++)
1886 mss->mss_indexed_regs[i] = ad_read(mss, i);
1887 for(i = 0; i < OPL_INDEXED_REGS; i++)
1888 mss->opl_indexed_regs[i] = conf_rd(mss, i);
1889 mss->opl_indexed_regs[0x12] = 0x0;
1894 static device_method_t mss_methods[] = {
1895 /* Device interface */
1896 DEVMETHOD(device_probe, mss_probe),
1897 DEVMETHOD(device_attach, mss_attach),
1898 DEVMETHOD(device_detach, mss_detach),
1899 DEVMETHOD(device_suspend, mss_suspend),
1900 DEVMETHOD(device_resume, mss_resume),
1905 static driver_t mss_driver = {
1911 DRIVER_MODULE(snd_mss, isa, mss_driver, pcm_devclass, 0, 0);
1912 MODULE_DEPEND(snd_mss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1913 MODULE_VERSION(snd_mss, 1);
1916 azt2320_mss_mode(struct mss_info *mss, device_t dev)
1918 struct resource *sbport;
1923 sbport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1925 for (i = 0; i < 1000; i++) {
1926 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1927 DELAY((i > 100) ? 1000 : 10);
1929 port_wr(sbport, SBDSP_CMD, 0x09);
1933 for (i = 0; i < 1000; i++) {
1934 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1935 DELAY((i > 100) ? 1000 : 10);
1937 port_wr(sbport, SBDSP_CMD, 0x00);
1943 bus_release_resource(dev, SYS_RES_IOPORT, rid, sbport);
1948 static struct isa_pnp_id pnpmss_ids[] = {
1949 {0x0000630e, "CS423x"}, /* CSC0000 */
1950 {0x0001630e, "CS423x-PCI"}, /* CSC0100 */
1951 {0x01000000, "CMI8330"}, /* @@@0001 */
1952 {0x2100a865, "Yamaha OPL-SAx"}, /* YMH0021 */
1953 {0x1110d315, "ENSONIQ SoundscapeVIVO"}, /* ENS1011 */
1954 {0x1093143e, "OPTi931"}, /* OPT9310 */
1955 {0x5092143e, "OPTi925"}, /* OPT9250 XXX guess */
1956 {0x0000143e, "OPTi924"}, /* OPT0924 */
1957 {0x1022b839, "Neomagic 256AV (non-ac97)"}, /* NMX2210 */
1958 {0x01005407, "Aztech 2320"}, /* AZT0001 */
1960 {0x0000561e, "GusPnP"}, /* GRV0000 */
1966 pnpmss_probe(device_t dev)
1970 lid = isa_get_logicalid(dev);
1971 vid = isa_get_vendorid(dev);
1972 if (lid == 0x01000000 && vid != 0x0100a90d) /* CMI0001 */
1974 return ISA_PNP_PROBE(device_get_parent(dev), dev, pnpmss_ids);
1978 pnpmss_attach(device_t dev)
1980 struct mss_info *mss;
1982 mss = malloc(sizeof(*mss), M_DEVBUF, M_WAITOK | M_ZERO);
1988 mss->bd_id = MD_CS42XX;
1990 switch (isa_get_logicalid(dev)) {
1991 case 0x0000630e: /* CSC0000 */
1992 case 0x0001630e: /* CSC0100 */
1993 mss->bd_flags |= BD_F_MSS_OFFSET;
1994 mss->bd_id = MD_CS423X;
1997 case 0x2100a865: /* YHM0021 */
2000 mss->bd_id = MD_YM0020;
2003 case 0x1110d315: /* ENS1011 */
2005 mss->bd_id = MD_VIVO;
2008 case 0x1093143e: /* OPT9310 */
2009 mss->bd_flags |= BD_F_MSS_OFFSET;
2011 mss->bd_id = MD_OPTI931;
2014 case 0x5092143e: /* OPT9250 XXX guess */
2017 mss->bd_id = MD_OPTI925;
2020 case 0x0000143e: /* OPT0924 */
2021 mss->password = 0xe5;
2023 mss->optibase = 0xf0c;
2026 mss->bd_id = MD_OPTI924;
2027 mss->bd_flags |= BD_F_924PNP;
2028 if(opti_init(dev, mss) != 0) {
2029 free(mss, M_DEVBUF);
2034 case 0x1022b839: /* NMX2210 */
2038 case 0x01005407: /* AZT0001 */
2039 /* put into MSS mode first (snatched from NetBSD) */
2040 if (azt2320_mss_mode(mss, dev) == -1) {
2041 free(mss, M_DEVBUF);
2045 mss->bd_flags |= BD_F_MSS_OFFSET;
2050 case 0x0000561e: /* GRV0000 */
2051 mss->bd_flags |= BD_F_MSS_OFFSET;
2056 mss->bd_id = MD_GUSPNP;
2059 case 0x01000000: /* @@@0001 */
2063 /* Unknown MSS default. We could let the CSC0000 stuff match too */
2065 mss->bd_flags |= BD_F_MSS_OFFSET;
2068 return mss_doattach(dev, mss);
2072 opti_init(device_t dev, struct mss_info *mss)
2074 int flags = device_get_flags(dev);
2077 if (!mss->conf_base) {
2078 bus_set_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
2079 mss->optibase, 0x9);
2081 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2082 &mss->conf_rid, mss->optibase, mss->optibase+0x9,
2086 if (!mss->conf_base)
2090 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2091 &mss->io_rid, 0, ~0, 8, RF_ACTIVE);
2093 if (!mss->io_base) /* No hint specified, use 0x530 */
2094 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2095 &mss->io_rid, 0x530, 0x537, 8, RF_ACTIVE);
2100 switch (rman_get_start(mss->io_base)) {
2114 printf("opti_init: invalid MSS base address!\n");
2119 switch (mss->bd_id) {
2121 opti_write(mss, 1, 0x80 | basebits); /* MSS mode */
2122 opti_write(mss, 2, 0x00); /* Disable CD */
2123 opti_write(mss, 3, 0xf0); /* Disable SB IRQ */
2124 opti_write(mss, 4, 0xf0);
2125 opti_write(mss, 5, 0x00);
2126 opti_write(mss, 6, 0x02); /* MPU stuff */
2130 opti_write(mss, 1, 0x00 | basebits);
2131 opti_write(mss, 3, 0x00); /* Disable SB IRQ/DMA */
2132 opti_write(mss, 4, 0x52); /* Empty FIFO */
2133 opti_write(mss, 5, 0x3c); /* Mode 2 */
2134 opti_write(mss, 6, 0x02); /* Enable MSS */
2138 if (mss->bd_flags & BD_F_924PNP) {
2139 u_int32_t irq = isa_get_irq(dev);
2140 u_int32_t drq = isa_get_drq(dev);
2141 bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1);
2142 bus_set_resource(dev, SYS_RES_DRQ, mss->drq1_rid, drq, 1);
2143 if (flags & DV_F_DUAL_DMA) {
2144 bus_set_resource(dev, SYS_RES_DRQ, 1,
2145 flags & DV_F_DRQ_MASK, 1);
2150 /* OPTixxx has I/DRQ registers */
2152 device_set_flags(dev, device_get_flags(dev) | DV_F_TRUE_MSS);
2158 opti_write(struct mss_info *mss, u_char reg, u_char val)
2160 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2162 switch(mss->bd_id) {
2164 if (reg > 7) { /* Indirect register */
2165 port_wr(mss->conf_base, mss->passwdreg, reg);
2166 port_wr(mss->conf_base, mss->passwdreg,
2168 port_wr(mss->conf_base, 9, val);
2171 port_wr(mss->conf_base, reg, val);
2175 port_wr(mss->indir, 0, reg);
2176 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2177 port_wr(mss->indir, 1, val);
2184 opti_read(struct mss_info *mss, u_char reg)
2186 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2188 switch(mss->bd_id) {
2190 if (reg > 7) { /* Indirect register */
2191 port_wr(mss->conf_base, mss->passwdreg, reg);
2192 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2193 return(port_rd(mss->conf_base, 9));
2195 return(port_rd(mss->conf_base, reg));
2199 port_wr(mss->indir, 0, reg);
2200 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2201 return port_rd(mss->indir, 1);
2208 static device_method_t pnpmss_methods[] = {
2209 /* Device interface */
2210 DEVMETHOD(device_probe, pnpmss_probe),
2211 DEVMETHOD(device_attach, pnpmss_attach),
2212 DEVMETHOD(device_detach, mss_detach),
2213 DEVMETHOD(device_suspend, mss_suspend),
2214 DEVMETHOD(device_resume, mss_resume),
2219 static driver_t pnpmss_driver = {
2225 DRIVER_MODULE(snd_pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0);
2226 DRIVER_MODULE(snd_pnpmss, acpi, pnpmss_driver, pcm_devclass, 0, 0);
2227 MODULE_DEPEND(snd_pnpmss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2228 MODULE_VERSION(snd_pnpmss, 1);
2231 guspcm_probe(device_t dev)
2233 struct sndcard_func *func;
2235 func = device_get_ivars(dev);
2236 if (func == NULL || func->func != SCF_PCM)
2239 device_set_desc(dev, "GUS CS4231");
2244 guspcm_attach(device_t dev)
2246 device_t parent = device_get_parent(dev);
2247 struct mss_info *mss;
2251 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
2255 mss->bd_flags = BD_F_MSS_OFFSET;
2262 if (isa_get_logicalid(parent) == 0)
2263 mss->bd_id = MD_GUSMAX;
2265 mss->bd_id = MD_GUSPNP;
2270 flags = device_get_flags(parent);
2271 if (flags & DV_F_DUAL_DMA)
2274 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid,
2275 0, ~0, 8, RF_ACTIVE);
2277 if (mss->conf_base == NULL) {
2278 mss_release_resources(mss, dev);
2282 base = isa_get_port(parent);
2284 ctl = 0x40; /* CS4231 enable */
2285 if (isa_get_drq(dev) > 3)
2286 ctl |= 0x10; /* 16-bit dma channel 1 */
2287 if ((flags & DV_F_DUAL_DMA) != 0 && (flags & DV_F_DRQ_MASK) > 3)
2288 ctl |= 0x20; /* 16-bit dma channel 2 */
2289 ctl |= (base >> 4) & 0x0f; /* 2X0 -> 3XC */
2290 port_wr(mss->conf_base, 6, ctl);
2293 return mss_doattach(dev, mss);
2296 static device_method_t guspcm_methods[] = {
2297 DEVMETHOD(device_probe, guspcm_probe),
2298 DEVMETHOD(device_attach, guspcm_attach),
2299 DEVMETHOD(device_detach, mss_detach),
2304 static driver_t guspcm_driver = {
2310 DRIVER_MODULE(snd_guspcm, gusc, guspcm_driver, pcm_devclass, 0, 0);
2311 MODULE_DEPEND(snd_guspcm, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2312 MODULE_VERSION(snd_guspcm, 1);