3 * Copyright (c) 1996-2008, 4Front Technologies
4 * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com)
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 /*---------------------------------------------------------------------------
31 * Copyright (C) 1997-1999, ESS Technology, Inc.
32 * This source code, its compiled object code, and its associated data sets
33 * are copyright (C) 1997-1999 ESS Technology, Inc.
34 *---------------------------------------------------------------------------
35 * This header contains data structures and registers taken from the
36 * 4Front OSS Allegro BSD licensed driver (in the Attic/ directory).
37 * Files used for this header include:
39 * kernel.h and hckernel.h
41 *---------------------------------------------------------------------------
44 #ifndef _DEV_SOUND_PCI_ALLEGRO_REG_H
45 #define _DEV_SOUND_PCI_ALLEGRO_REG_H
47 /* Allegro PCI configuration registers */
48 #define PCI_LEGACY_AUDIO_CTRL 0x40
49 #define SOUND_BLASTER_ENABLE 0x00000001
50 #define FM_SYNTHESIS_ENABLE 0x00000002
51 #define GAME_PORT_ENABLE 0x00000004
52 #define MPU401_IO_ENABLE 0x00000008
53 #define MPU401_IRQ_ENABLE 0x00000010
54 #define ALIAS_10BIT_IO 0x00000020
55 #define SB_DMA_MASK 0x000000C0
56 #define SB_DMA_0 0x00000040
57 #define SB_DMA_1 0x00000040
58 #define SB_DMA_R 0x00000080
59 #define SB_DMA_3 0x000000C0
60 #define SB_IRQ_MASK 0x00000700
61 #define SB_IRQ_5 0x00000000
62 #define SB_IRQ_7 0x00000100
63 #define SB_IRQ_9 0x00000200
64 #define SB_IRQ_10 0x00000300
65 #define MIDI_IRQ_MASK 0x00003800
66 #define SERIAL_IRQ_ENABLE 0x00004000
67 #define DISABLE_LEGACY 0x00008000
69 #define PCI_ALLEGRO_CONFIG 0x50
70 #define SB_ADDR_240 0x00000004
71 #define MPU_ADDR_MASK 0x00000018
72 #define MPU_ADDR_330 0x00000000
73 #define MPU_ADDR_300 0x00000008
74 #define MPU_ADDR_320 0x00000010
75 #define MPU_ADDR_340 0x00000018
76 #define USE_PCI_TIMING 0x00000040
77 #define POSTED_WRITE_ENABLE 0x00000080
78 #define DMA_POLICY_MASK 0x00000700
79 #define DMA_DDMA 0x00000000
80 #define DMA_TDMA 0x00000100
81 #define DMA_PCPCI 0x00000200
82 #define DMA_WBDMA16 0x00000400
83 #define DMA_WBDMA4 0x00000500
84 #define DMA_WBDMA2 0x00000600
85 #define DMA_WBDMA1 0x00000700
86 #define DMA_SAFE_GUARD 0x00000800
87 #define HI_PERF_GP_ENABLE 0x00001000
88 #define PIC_SNOOP_MODE_0 0x00002000
89 #define PIC_SNOOP_MODE_1 0x00004000
90 #define SOUNDBLASTER_IRQ_MASK 0x00008000
91 #define RING_IN_ENABLE 0x00010000
92 #define SPDIF_TEST_MODE 0x00020000
93 #define CLK_MULT_MODE_SELECT_2 0x00040000
94 #define EEPROM_WRITE_ENABLE 0x00080000
95 #define CODEC_DIR_IN 0x00100000
96 #define HV_BUTTON_FROM_GD 0x00200000
97 #define REDUCED_DEBOUNCE 0x00400000
98 #define HV_CTRL_ENABLE 0x00800000
99 #define SPDIF_ENABLE 0x01000000
100 #define CLK_DIV_SELECT 0x06000000
101 #define CLK_DIV_BY_48 0x00000000
102 #define CLK_DIV_BY_49 0x02000000
103 #define CLK_DIV_BY_50 0x04000000
104 #define CLK_DIV_RESERVED 0x06000000
105 #define PM_CTRL_ENABLE 0x08000000
106 #define CLK_MULT_MODE_SELECT 0x30000000
107 #define CLK_MULT_MODE_SHIFT 28
108 #define CLK_MULT_MODE_0 0x00000000
109 #define CLK_MULT_MODE_1 0x10000000
110 #define CLK_MULT_MODE_2 0x20000000
111 #define CLK_MULT_MODE_3 0x30000000
112 #define INT_CLK_SELECT 0x40000000
113 #define INT_CLK_MULT_RESET 0x80000000
116 #define INT_CLK_SRC_NOT_PCI 0x00100000
117 #define INT_CLK_MULT_ENABLE 0x80000000
119 #define PCI_ACPI_CONTROL 0x54
120 #define PCI_ACPI_D0 0x00000000
121 #define PCI_ACPI_D1 0xB4F70000
122 #define PCI_ACPI_D2 0xB4F7B4F7
124 #define PCI_USER_CONFIG 0x58
125 #define EXT_PCI_MASTER_ENABLE 0x00000001
126 #define SPDIF_OUT_SELECT 0x00000002
127 #define TEST_PIN_DIR_CTRL 0x00000004
128 #define AC97_CODEC_TEST 0x00000020
129 #define TRI_STATE_BUFFER 0x00000080
130 #define IN_CLK_12MHZ_SELECT 0x00000100
131 #define MULTI_FUNC_DISABLE 0x00000200
132 #define EXT_MASTER_PAIR_SEL 0x00000400
133 #define PCI_MASTER_SUPPORT 0x00000800
134 #define STOP_CLOCK_ENABLE 0x00001000
135 #define EAPD_DRIVE_ENABLE 0x00002000
136 #define REQ_TRI_STATE_ENABLE 0x00004000
137 #define REQ_LOW_ENABLE 0x00008000
138 #define MIDI_1_ENABLE 0x00010000
139 #define MIDI_2_ENABLE 0x00020000
140 #define SB_AUDIO_SYNC 0x00040000
141 #define HV_CTRL_TEST 0x00100000
142 #define SOUNDBLASTER_TEST 0x00400000
144 #define PCI_USER_CONFIG_C 0x5C
146 #define PCI_DDMA_CTRL 0x60
147 #define DDMA_ENABLE 0x00000001
150 /* Allegro registers */
151 #define HOST_INT_CTRL 0x18
152 #define SB_INT_ENABLE 0x0001
153 #define MPU401_INT_ENABLE 0x0002
154 #define ASSP_INT_ENABLE 0x0010
155 #define RING_INT_ENABLE 0x0020
156 #define HV_INT_ENABLE 0x0040
157 #define CLKRUN_GEN_ENABLE 0x0100
158 #define HV_CTRL_TO_PME 0x0400
159 #define SOFTWARE_RESET_ENABLE 0x8000
161 #define HOST_INT_STATUS 0x1A
162 #define SB_INT_PENDING 0x01
163 #define MPU401_INT_PENDING 0x02
164 #define ASSP_INT_PENDING 0x10
165 #define RING_INT_PENDING 0x20
166 #define HV_INT_PENDING 0x40
168 #define HARDWARE_VOL_CTRL 0x1B
169 #define SHADOW_MIX_REG_VOICE 0x1C
170 #define HW_VOL_COUNTER_VOICE 0x1D
171 #define SHADOW_MIX_REG_MASTER 0x1E
172 #define HW_VOL_COUNTER_MASTER 0x1F
174 #define CODEC_COMMAND 0x30
175 #define CODEC_READ_B 0x80
177 #define CODEC_STATUS 0x30
178 #define CODEC_BUSY_B 0x01
180 #define CODEC_DATA 0x32
184 #define AC97_RESET 0x00
187 #define AC97_VOL_MUTE_B 0x8000
188 #define AC97_VOL_M 0x1F
189 #define AC97_LEFT_VOL_S 8
191 #define AC97_MASTER_VOL 0x02
192 #define AC97_LINE_LEVEL_VOL 0x04
193 #define AC97_MASTER_MONO_VOL 0x06
194 #define AC97_PC_BEEP_VOL 0x0A
195 #define AC97_PC_BEEP_VOL_M 0x0F
196 #define AC97_SROUND_MASTER_VOL 0x38
197 #define AC97_PC_BEEP_VOL_S 1
200 #define AC97_PHONE_VOL 0x0C
201 #define AC97_MIC_VOL 0x0E
203 #define AC97_MIC_20DB_ENABLE 0x40
206 #define AC97_LINEIN_VOL 0x10
207 #define AC97_CD_VOL 0x12
208 #define AC97_VIDEO_VOL 0x14
209 #define AC97_AUX_VOL 0x16
211 #define AC97_PCM_OUT_VOL 0x18
213 #define AC97_RECORD_SELECT 0x1A
215 #define AC97_RECORD_MIC 0x00
216 #define AC97_RECORD_CD 0x01
217 #define AC97_RECORD_VIDEO 0x02
218 #define AC97_RECORD_AUX 0x03
219 #define AC97_RECORD_MONO_MUX 0x02
220 #define AC97_RECORD_DIGITAL 0x03
221 #define AC97_RECORD_LINE 0x04
222 #define AC97_RECORD_STEREO 0x05
223 #define AC97_RECORD_MONO 0x06
224 #define AC97_RECORD_PHONE 0x07
227 #define AC97_RECORD_GAIN 0x1C
229 #define AC97_RECORD_VOL_M 0x0F
232 #define AC97_GENERAL_PURPOSE 0x20
234 #define AC97_POWER_DOWN_CTRL 0x26
235 #define AC97_ADC_READY 0x0001
236 #define AC97_DAC_READY 0x0002
237 #define AC97_ANALOG_READY 0x0004
238 #define AC97_VREF_ON 0x0008
239 #define AC97_PR0 0x0100
240 #define AC97_PR1 0x0200
241 #define AC97_PR2 0x0400
242 #define AC97_PR3 0x0800
243 #define AC97_PR4 0x1000
245 #define AC97_RESERVED1 0x28
247 #define AC97_VENDOR_TEST 0x5A
249 #define AC97_CLOCK_DELAY 0x5C
250 #define AC97_LINEOUT_MUX_SEL 0x0001
251 #define AC97_MONO_MUX_SEL 0x0002
252 #define AC97_CLOCK_DELAY_SEL 0x1F
253 #define AC97_DAC_CDS_SHIFT 6
254 #define AC97_ADC_CDS_SHIFT 11
256 #define AC97_MULTI_CHANNEL_SEL 0x74
259 #define AC97_VENDOR_ID1 0x7C
260 #define AC97_VENDOR_ID2 0x7E
263 #define RING_BUS_CTRL_A 0x36
264 #define RAC_PME_ENABLE 0x0100
265 #define RAC_SDFS_ENABLE 0x0200
266 #define LAC_PME_ENABLE 0x0400
267 #define LAC_SDFS_ENABLE 0x0800
268 #define SERIAL_AC_LINK_ENABLE 0x1000
269 #define IO_SRAM_ENABLE 0x2000
270 #define IIS_INPUT_ENABLE 0x8000
272 #define RING_BUS_CTRL_B 0x38
273 #define SECOND_CODEC_ID_MASK 0x0003
274 #define SPDIF_FUNC_ENABLE 0x0010
275 #define SECOND_AC_ENABLE 0x0020
276 #define SB_MODULE_INTF_ENABLE 0x0040
277 #define SSPE_ENABLE 0x0040
278 #define M3I_DOCK_ENABLE 0x0080
280 #define SDO_OUT_DEST_CTRL 0x3A
281 #define COMMAND_ADDR_OUT 0x0003
282 #define PCM_LR_OUT_LOCAL 0x0000
283 #define PCM_LR_OUT_REMOTE 0x0004
284 #define PCM_LR_OUT_MUTE 0x0008
285 #define PCM_LR_OUT_BOTH 0x000C
286 #define LINE1_DAC_OUT_LOCAL 0x0000
287 #define LINE1_DAC_OUT_REMOTE 0x0010
288 #define LINE1_DAC_OUT_MUTE 0x0020
289 #define LINE1_DAC_OUT_BOTH 0x0030
290 #define PCM_CLS_OUT_LOCAL 0x0000
291 #define PCM_CLS_OUT_REMOTE 0x0040
292 #define PCM_CLS_OUT_MUTE 0x0080
293 #define PCM_CLS_OUT_BOTH 0x00C0
294 #define PCM_RLF_OUT_LOCAL 0x0000
295 #define PCM_RLF_OUT_REMOTE 0x0100
296 #define PCM_RLF_OUT_MUTE 0x0200
297 #define PCM_RLF_OUT_BOTH 0x0300
298 #define LINE2_DAC_OUT_LOCAL 0x0000
299 #define LINE2_DAC_OUT_REMOTE 0x0400
300 #define LINE2_DAC_OUT_MUTE 0x0800
301 #define LINE2_DAC_OUT_BOTH 0x0C00
302 #define HANDSET_OUT_LOCAL 0x0000
303 #define HANDSET_OUT_REMOTE 0x1000
304 #define HANDSET_OUT_MUTE 0x2000
305 #define HANDSET_OUT_BOTH 0x3000
306 #define IO_CTRL_OUT_LOCAL 0x0000
307 #define IO_CTRL_OUT_REMOTE 0x4000
308 #define IO_CTRL_OUT_MUTE 0x8000
309 #define IO_CTRL_OUT_BOTH 0xC000
311 #define SDO_IN_DEST_CTRL 0x3C
312 #define STATUS_ADDR_IN 0x0003
313 #define PCM_LR_IN_LOCAL 0x0000
314 #define PCM_LR_IN_REMOTE 0x0004
315 #define PCM_LR_RESERVED 0x0008
316 #define PCM_LR_IN_BOTH 0x000C
317 #define LINE1_ADC_IN_LOCAL 0x0000
318 #define LINE1_ADC_IN_REMOTE 0x0010
319 #define LINE1_ADC_IN_MUTE 0x0020
320 #define MIC_ADC_IN_LOCAL 0x0000
321 #define MIC_ADC_IN_REMOTE 0x0040
322 #define MIC_ADC_IN_MUTE 0x0080
323 #define LINE2_DAC_IN_LOCAL 0x0000
324 #define LINE2_DAC_IN_REMOTE 0x0400
325 #define LINE2_DAC_IN_MUTE 0x0800
326 #define HANDSET_IN_LOCAL 0x0000
327 #define HANDSET_IN_REMOTE 0x1000
328 #define HANDSET_IN_MUTE 0x2000
329 #define IO_STATUS_IN_LOCAL 0x0000
330 #define IO_STATUS_IN_REMOTE 0x4000
332 #define SPDIF_IN_CTRL 0x3E
333 #define SPDIF_IN_ENABLE 0x0001
335 #define GPIO_DATA 0x60
336 #define GPIO_DATA_MASK 0x0FFF
337 #define GPIO_HV_STATUS 0x3000
338 #define GPIO_PME_STATUS 0x4000
340 #define GPIO_MASK 0x64
341 #define GPIO_DIRECTION 0x68
342 #define GPO_PRIMARY_AC97 0x0001
343 #define GPI_LINEOUT_SENSE 0x0004
344 #define GPO_SECONDARY_AC97 0x0008
345 #define GPI_VOL_DOWN 0x0010
346 #define GPI_VOL_UP 0x0020
347 #define GPI_IIS_CLK 0x0040
348 #define GPI_IIS_LRCLK 0x0080
349 #define GPI_IIS_DATA 0x0100
350 #define GPI_DOCKING_STATUS 0x0100
351 #define GPI_HEADPHONE_SENSE 0x0200
352 #define GPO_EXT_AMP_SHUTDOWN 0x1000
355 #define GPO_M3_EXT_AMP_SHUTDN 0x0002
357 #define ASSP_INDEX_PORT 0x80
358 #define ASSP_MEMORY_PORT 0x82
359 #define ASSP_DATA_PORT 0x84
361 #define MPU401_DATA_PORT 0x98
362 #define MPU401_STATUS_PORT 0x99
364 #define CLK_MULT_DATA_PORT 0x9C
366 #define ASSP_CONTROL_A 0xA2
367 #define ASSP_0_WS_ENABLE 0x01
368 #define ASSP_CTRL_A_RESERVED1 0x02
369 #define ASSP_CTRL_A_RESERVED2 0x04
370 #define ASSP_CLK_49MHZ_SELECT 0x08
371 #define FAST_PLU_ENABLE 0x10
372 #define ASSP_CTRL_A_RESERVED3 0x20
373 #define DSP_CLK_36MHZ_SELECT 0x40
375 #define ASSP_CONTROL_B 0xA4
376 #define RESET_ASSP 0x00
377 #define RUN_ASSP 0x01
378 #define ENABLE_ASSP_CLOCK 0x00
379 #define STOP_ASSP_CLOCK 0x10
380 #define RESET_TOGGLE 0x40
382 #define ASSP_CONTROL_C 0xA6
383 #define ASSP_HOST_INT_ENABLE 0x01
384 #define FM_ADDR_REMAP_DISABLE 0x02
385 #define HOST_WRITE_PORT_ENABLE 0x08
387 #define ASSP_HOST_INT_STATUS 0xAC
388 #define DSP2HOST_REQ_PIORECORD 0x01
389 #define DSP2HOST_REQ_I2SRATE 0x02
390 #define DSP2HOST_REQ_TIMER 0x04
396 #define REV_A_CODE_MEMORY_BEGIN 0x0000
397 #define REV_A_CODE_MEMORY_END 0x0FFF
398 #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
399 #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
401 #define REV_B_CODE_MEMORY_BEGIN 0x0000
402 #define REV_B_CODE_MEMORY_END 0x0BFF
403 #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
404 #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
406 #if (REV_A_CODE_MEMORY_LENGTH % REV_A_CODE_MEMORY_UNIT_LENGTH)
407 #error Assumption about code memory unit length failed.
409 #if (REV_B_CODE_MEMORY_LENGTH % REV_B_CODE_MEMORY_UNIT_LENGTH)
410 #error Assumption about code memory unit length failed.
413 #define REV_A_DATA_MEMORY_BEGIN 0x1000
414 #define REV_A_DATA_MEMORY_END 0x2FFF
415 #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
416 #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
418 #define REV_B_DATA_MEMORY_BEGIN 0x1000
419 /*#define REV_B_DATA_MEMORY_END 0x23FF */
420 #define REV_B_DATA_MEMORY_END 0x2BFF
421 #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
422 #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
424 #if (REV_A_DATA_MEMORY_LENGTH % REV_A_DATA_MEMORY_UNIT_LENGTH)
425 #error Assumption about data memory unit length failed.
427 #if (REV_B_DATA_MEMORY_LENGTH % REV_B_DATA_MEMORY_UNIT_LENGTH)
428 #error Assumption about data memory unit length failed.
431 #define CODE_MEMORY_MAP_LENGTH (64 + 1)
432 #define DATA_MEMORY_MAP_LENGTH (64 + 1)
434 #if (CODE_MEMORY_MAP_LENGTH < ((REV_A_CODE_MEMORY_LENGTH / REV_A_CODE_MEMORY_UNIT_LENGTH) + 1))
435 #error Code memory map length too short.
437 #if (DATA_MEMORY_MAP_LENGTH < ((REV_A_DATA_MEMORY_LENGTH / REV_A_DATA_MEMORY_UNIT_LENGTH) + 1))
438 #error Data memory map length too short.
440 #if (CODE_MEMORY_MAP_LENGTH < ((REV_B_CODE_MEMORY_LENGTH / REV_B_CODE_MEMORY_UNIT_LENGTH) + 1))
441 #error Code memory map length too short.
443 #if (DATA_MEMORY_MAP_LENGTH < ((REV_B_DATA_MEMORY_LENGTH / REV_B_DATA_MEMORY_UNIT_LENGTH) + 1))
444 #error Data memory map length too short.
449 * Kernel code memory definition
452 #define KCODE_VECTORS_BEGIN 0x0000
453 #define KCODE_VECTORS_END 0x002F
454 #define KCODE_VECTORS_UNIT_LENGTH 0x0002
455 #define KCODE_VECTORS_LENGTH (KCODE_VECTORS_END - KCODE_VECTORS_BEGIN + 1)
459 * Kernel data memory definition
462 #define KDATA_BASE_ADDR 0x1000
463 #define KDATA_BASE_ADDR2 0x1080
465 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
466 #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
467 #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
468 #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
469 #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
470 #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
471 #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
472 #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
473 #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
475 #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
476 #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
478 #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
479 #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
480 #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
481 #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
482 #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
483 #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
484 #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
485 #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
486 #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
487 #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
489 #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
490 #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
492 #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
493 #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
495 #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
496 #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
498 #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
499 #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
500 #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
502 #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
503 #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
504 #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
505 #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
506 #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
508 #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
509 #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
510 #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
512 #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
513 #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
514 #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
516 #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
517 #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
518 #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
519 #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
520 #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
521 #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
522 #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
523 #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
524 #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
525 #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
527 #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
528 #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
529 #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
531 #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
532 #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
534 #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
535 #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
536 #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
538 #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
539 #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
540 #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
541 #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
542 #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
543 #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
545 #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
546 #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
547 #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
548 #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
549 #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
550 #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
552 #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
553 #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
554 #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
555 #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
556 #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
557 #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
559 #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
560 #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
561 #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
562 #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
564 #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
565 #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
567 #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
568 #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
570 #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
571 #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
572 #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
573 #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
574 #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
576 #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
577 #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
580 #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
581 #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
582 #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
584 #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
585 #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
587 #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
589 #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
590 #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
591 #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
592 #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
593 #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
594 #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
595 #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
596 #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
597 #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
598 #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
599 #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
600 #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
602 #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
603 #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
604 #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
605 #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
607 #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
608 #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
610 #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
611 #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
612 #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
613 #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
615 #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
616 #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
617 #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
618 #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
619 #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
625 /* smart mixer buffer */
627 #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
628 #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
629 #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
630 #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
631 #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
632 #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
633 #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
634 #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
635 #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
636 #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
637 #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
638 #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
639 #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
640 #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
641 #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
642 #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
644 #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
645 #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
646 #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
647 #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
648 #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
649 #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
650 #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
651 #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
652 #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
653 #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
654 #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
656 #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
657 #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
658 #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
659 #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
660 #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
661 #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
664 * Client data memory definition
667 #define CDATA_INSTANCE_READY 0x00
669 #define CDATA_HOST_SRC_ADDRL 0x01
670 #define CDATA_HOST_SRC_ADDRH 0x02
671 #define CDATA_HOST_SRC_END_PLUS_1L 0x03
672 #define CDATA_HOST_SRC_END_PLUS_1H 0x04
673 #define CDATA_HOST_SRC_CURRENTL 0x05
674 #define CDATA_HOST_SRC_CURRENTH 0x06
676 #define CDATA_IN_BUF_CONNECT 0x07
677 #define CDATA_OUT_BUF_CONNECT 0x08
679 #define CDATA_IN_BUF_BEGIN 0x09
680 #define CDATA_IN_BUF_END_PLUS_1 0x0A
681 #define CDATA_IN_BUF_HEAD 0x0B
682 #define CDATA_IN_BUF_TAIL 0x0C
684 #define CDATA_OUT_BUF_BEGIN 0x0D
685 #define CDATA_OUT_BUF_END_PLUS_1 0x0E
686 #define CDATA_OUT_BUF_HEAD 0x0F
687 #define CDATA_OUT_BUF_TAIL 0x10
689 #define CDATA_DMA_CONTROL 0x11
690 #define CDATA_RESERVED 0x12
692 #define CDATA_FREQUENCY 0x13
693 #define CDATA_LEFT_VOLUME 0x14
694 #define CDATA_RIGHT_VOLUME 0x15
695 #define CDATA_LEFT_SUR_VOL 0x16
696 #define CDATA_RIGHT_SUR_VOL 0x17
698 /* These are from Allegro hckernel.h */
699 #define CDATA_HEADER_LEN 0x18
700 #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
701 #define SRC3_MODE_OFFSET CDATA_HEADER_LEN + 1
702 #define SRC3_WORD_LENGTH_OFFSET CDATA_HEADER_LEN + 2
703 #define SRC3_PARAMETER_OFFSET CDATA_HEADER_LEN + 3
704 #define SRC3_COEFF_ADDR_OFFSET CDATA_HEADER_LEN + 8
705 #define SRC3_FILTAP_ADDR_OFFSET CDATA_HEADER_LEN + 10
706 #define SRC3_TEMP_INBUF_ADDR_OFFSET CDATA_HEADER_LEN + 16
707 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET CDATA_HEADER_LEN + 17
708 #define FOR_FUTURE_USE 10 /* for storing temporary variable in future */
711 * DMA control definition
714 #define DMACONTROL_BLOCK_MASK 0x000F
715 #define DMAC_BLOCK0_SELECTOR 0x0000
716 #define DMAC_BLOCK1_SELECTOR 0x0001
717 #define DMAC_BLOCK2_SELECTOR 0x0002
718 #define DMAC_BLOCK3_SELECTOR 0x0003
719 #define DMAC_BLOCK4_SELECTOR 0x0004
720 #define DMAC_BLOCK5_SELECTOR 0x0005
721 #define DMAC_BLOCK6_SELECTOR 0x0006
722 #define DMAC_BLOCK7_SELECTOR 0x0007
723 #define DMAC_BLOCK8_SELECTOR 0x0008
724 #define DMAC_BLOCK9_SELECTOR 0x0009
725 #define DMAC_BLOCKA_SELECTOR 0x000A
726 #define DMAC_BLOCKB_SELECTOR 0x000B
727 #define DMAC_BLOCKC_SELECTOR 0x000C
728 #define DMAC_BLOCKD_SELECTOR 0x000D
729 #define DMAC_BLOCKE_SELECTOR 0x000E
730 #define DMAC_BLOCKF_SELECTOR 0x000F
731 #define DMACONTROL_PAGE_MASK 0x00F0
732 #define DMAC_PAGE0_SELECTOR 0x0030
733 #define DMAC_PAGE1_SELECTOR 0x0020
734 #define DMAC_PAGE2_SELECTOR 0x0010
735 #define DMAC_PAGE3_SELECTOR 0x0000
736 #define DMACONTROL_AUTOREPEAT 0x1000
737 #define DMACONTROL_STOPPED 0x2000
738 #define DMACONTROL_DIRECTION 0x0100
741 * Kernel/client memory allocation
744 #define NUM_UNITS_KERNEL_CODE 16
745 #define NUM_UNITS_KERNEL_DATA 2
747 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
749 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
751 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 4
754 #define NUM_UNITS( BYTES, UNITLEN ) ((((BYTES+1)>>1) + (UNITLEN-1)) / UNITLEN)
760 #define DSP_PORT_TIMER_COUNT 0x06
761 #define DSP_PORT_MEMORY_INDEX 0x80
762 #define DSP_PORT_MEMORY_TYPE 0x82
763 #define DSP_PORT_MEMORY_DATA 0x84
764 #define DSP_PORT_CONTROL_REG_A 0xA2
765 #define DSP_PORT_CONTROL_REG_B 0xA4
766 #define DSP_PORT_CONTROL_REG_C 0xA6
768 #define MEMTYPE_INTERNAL_CODE 0x0002
769 #define MEMTYPE_INTERNAL_DATA 0x0003
770 #define MEMTYPE_MASK 0x0003
772 #define REGB_ENABLE_RESET 0x01
773 #define REGB_STOP_CLOCK 0x10
775 #define REGC_DISABLE_FM_MAPPING 0x02
777 #define DP_SHIFT_COUNT 7
779 #define DMA_BLOCK_LENGTH 32
781 /* These are from Allegro srcmgr.h */
782 #define MINISRC_BIQUAD_STAGE 2
783 #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
784 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
785 #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
786 #define MINISRC_BIQUAD_STAGE 2
787 /* M. SRC LPF coefficient could be changed in the DSP code */
788 #define MINISRC_COEF_LOC 0X175
790 #endif /* !_DEV_SOUND_PCI_ALLEGRO_REG_H */