2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
28 * This driver exists largely as a result of other people's efforts.
29 * Much of register handling is based on NetBSD CMI8x38 audio driver
30 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien
31 * <cltien@cmedia.com.tw> clarified points regarding the DMA related
32 * registers and the 8738 mixer devices. His Linux driver was also a
33 * useful reference point.
37 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>.
39 * This card/code does not always manage to sample at 44100 - actual
40 * rate drifts slightly between recordings (usually 0-3%). No
41 * differences visible in register dumps between times that work and
45 #ifdef HAVE_KERNEL_OPTION_HEADERS
49 #include <dev/sound/pcm/sound.h>
50 #include <dev/sound/pci/cmireg.h>
51 #include <dev/sound/isa/sb.h>
53 #include <dev/pci/pcireg.h>
54 #include <dev/pci/pcivar.h>
56 #include <sys/sysctl.h>
57 #include <dev/sound/midi/mpu401.h>
60 #include "mpufoi_if.h"
62 SND_DECLARE_FILE("$FreeBSD$");
64 /* Supported chip ID's */
65 #define CMI8338A_PCI_ID 0x010013f6
66 #define CMI8338B_PCI_ID 0x010113f6
67 #define CMI8738_PCI_ID 0x011113f6
68 #define CMI8738B_PCI_ID 0x011213f6
69 #define CMI120_USB_ID 0x01030d8c
71 /* Buffer size max is 64k for permitted DMA boundaries */
72 #define CMI_DEFAULT_BUFSZ 16384
74 /* Interrupts per length of buffer */
75 #define CMI_INTR_PER_BUFFER 2
77 /* Clarify meaning of named defines in cmireg.h */
78 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES
79 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES
80 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES
81 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES
83 /* Our indication of custom mixer control */
84 #define CMPCI_NON_SB16_CONTROL 0xff
86 /* Debugging macro's */
89 #define DEB(x) /* x */
93 #define DEBMIX(x) /* x */
96 /* ------------------------------------------------------------------------- */
102 struct sc_info *parent;
103 struct pcm_channel *channel;
104 struct snd_dbuf *buffer;
105 u_int32_t fmt, spd, phys_buf, bps;
106 u_int32_t dma_active:1, dma_was_active:1;
114 bus_space_handle_t sh;
115 bus_dma_tag_t parent_dmat;
116 struct resource *reg, *irq;
123 struct sc_chinfo pch, rch;
126 mpu401_intr_t *mpu_intr;
127 struct resource *mpu_reg;
129 bus_space_tag_t mpu_bt;
130 bus_space_handle_t mpu_bh;
135 static u_int32_t cmi_fmt[] = {
136 SND_FORMAT(AFMT_U8, 1, 0),
137 SND_FORMAT(AFMT_U8, 2, 0),
138 SND_FORMAT(AFMT_S16_LE, 1, 0),
139 SND_FORMAT(AFMT_S16_LE, 2, 0),
143 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0};
145 /* ------------------------------------------------------------------------- */
146 /* Register Utilities */
149 cmi_rd(struct sc_info *sc, int regno, int size)
153 return bus_space_read_1(sc->st, sc->sh, regno);
155 return bus_space_read_2(sc->st, sc->sh, regno);
157 return bus_space_read_4(sc->st, sc->sh, regno);
159 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size));
165 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
169 bus_space_write_1(sc->st, sc->sh, regno, data);
172 bus_space_write_2(sc->st, sc->sh, regno, data);
175 bus_space_write_4(sc->st, sc->sh, regno, data);
181 cmi_partial_wr4(struct sc_info *sc,
182 int reg, int shift, u_int32_t mask, u_int32_t val)
186 r = cmi_rd(sc, reg, 4);
187 r &= ~(mask << shift);
189 cmi_wr(sc, reg, r, 4);
193 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask)
197 r = cmi_rd(sc, reg, 4);
199 cmi_wr(sc, reg, r, 4);
203 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask)
207 r = cmi_rd(sc, reg, 4);
209 cmi_wr(sc, reg, r, 4);
212 /* ------------------------------------------------------------------------- */
215 static int cmi_rates[] = {5512, 8000, 11025, 16000,
216 22050, 32000, 44100, 48000};
217 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0]))
219 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1
220 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */
223 cmpci_rate_to_regvalue(int rate)
227 for(i = 0; i < NUM_CMI_RATES - 1; i++) {
228 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) {
233 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i]));
235 r = ((i >> 1) | (i << 2)) & 0x07;
240 cmpci_regvalue_to_rate(u_int32_t r)
244 i = ((r << 1) | (r >> 2)) & 0x07;
245 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i));
249 /* ------------------------------------------------------------------------- */
250 /* ADC/DAC control - there are 2 dma channels on 8738, either can be
251 * playback or capture. We use ch0 for playback and ch1 for capture. */
254 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base)
258 ch->phys_buf = sndbuf_getbufaddr(ch->buffer);
260 cmi_wr(sc, base, ch->phys_buf, 4);
261 sz = (u_int32_t)sndbuf_getsize(ch->buffer);
263 s = sz / ch->bps - 1;
264 cmi_wr(sc, base + 4, s, 2);
266 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1;
267 cmi_wr(sc, base + 6, i, 2);
272 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch)
274 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
276 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
277 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
278 CMPCI_REG_CH0_INTR_ENABLE);
284 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch)
286 u_int32_t r = ch->dma_active;
288 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
289 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
290 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
291 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
297 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch)
299 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
300 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
301 /* Enable Interrupts */
302 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
303 CMPCI_REG_CH1_INTR_ENABLE);
304 DEB(printf("cmi_ch1_start: dma prog\n"));
309 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch)
311 u_int32_t r = ch->dma_active;
313 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
314 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
315 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
316 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
322 cmi_spdif_speed(struct sc_info *sc, int speed) {
323 u_int32_t fcr1, lcr, mcr;
325 if (speed >= 44100) {
326 fcr1 = CMPCI_REG_SPDIF0_ENABLE;
327 lcr = CMPCI_REG_XSPDIF_ENABLE;
328 mcr = (speed == 48000) ?
329 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0;
331 fcr1 = mcr = lcr = 0;
334 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0,
335 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr);
336 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0,
337 CMPCI_REG_SPDIF0_ENABLE, fcr1);
338 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0,
339 CMPCI_REG_XSPDIF_ENABLE, lcr);
342 /* ------------------------------------------------------------------------- */
343 /* Channel Interface implementation */
346 cmichan_init(kobj_t obj, void *devinfo,
347 struct snd_dbuf *b, struct pcm_channel *c, int dir)
349 struct sc_info *sc = devinfo;
350 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
355 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
356 ch->spd = DSP_DEFAULT_SPEED;
359 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
360 DEB(printf("cmichan_init failed\n"));
365 snd_mtxlock(sc->lock);
366 if (ch->dir == PCMDIR_PLAY) {
367 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
369 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
371 snd_mtxunlock(sc->lock);
377 cmichan_setformat(kobj_t obj, void *data, u_int32_t format)
379 struct sc_chinfo *ch = data;
380 struct sc_info *sc = ch->parent;
383 if (format & AFMT_S16_LE) {
384 f = CMPCI_REG_FORMAT_16BIT;
387 f = CMPCI_REG_FORMAT_8BIT;
391 if (AFMT_CHANNEL(format) > 1) {
392 f |= CMPCI_REG_FORMAT_STEREO;
395 f |= CMPCI_REG_FORMAT_MONO;
398 snd_mtxlock(sc->lock);
399 if (ch->dir == PCMDIR_PLAY) {
400 cmi_partial_wr4(ch->parent,
401 CMPCI_REG_CHANNEL_FORMAT,
402 CMPCI_REG_CH0_FORMAT_SHIFT,
403 CMPCI_REG_CH0_FORMAT_MASK,
406 cmi_partial_wr4(ch->parent,
407 CMPCI_REG_CHANNEL_FORMAT,
408 CMPCI_REG_CH1_FORMAT_SHIFT,
409 CMPCI_REG_CH1_FORMAT_MASK,
412 snd_mtxunlock(sc->lock);
419 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed)
421 struct sc_chinfo *ch = data;
422 struct sc_info *sc = ch->parent;
425 r = cmpci_rate_to_regvalue(speed);
426 snd_mtxlock(sc->lock);
427 if (ch->dir == PCMDIR_PLAY) {
429 /* disable if req before rate change */
430 cmi_spdif_speed(ch->parent, speed);
432 cmi_partial_wr4(ch->parent,
434 CMPCI_REG_DAC_FS_SHIFT,
435 CMPCI_REG_DAC_FS_MASK,
437 if (speed >= 44100 && ch->parent->spdif_enabled) {
438 /* enable if req after rate change */
439 cmi_spdif_speed(ch->parent, speed);
441 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
442 rsp >>= CMPCI_REG_DAC_FS_SHIFT;
443 rsp &= CMPCI_REG_DAC_FS_MASK;
445 cmi_partial_wr4(ch->parent,
447 CMPCI_REG_ADC_FS_SHIFT,
448 CMPCI_REG_ADC_FS_MASK,
450 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
451 rsp >>= CMPCI_REG_ADC_FS_SHIFT;
452 rsp &= CMPCI_REG_ADC_FS_MASK;
454 snd_mtxunlock(sc->lock);
455 ch->spd = cmpci_regvalue_to_rate(r);
457 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n",
458 (ch->dir == PCMDIR_PLAY) ? "play" : "rec",
459 speed, ch->spd, cmpci_regvalue_to_rate(rsp)));
465 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
467 struct sc_chinfo *ch = data;
468 struct sc_info *sc = ch->parent;
470 /* user has requested interrupts every blocksize bytes */
471 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) {
472 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER;
474 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize);
480 cmichan_trigger(kobj_t obj, void *data, int go)
482 struct sc_chinfo *ch = data;
483 struct sc_info *sc = ch->parent;
485 if (!PCMTRIG_COMMON(go))
488 snd_mtxlock(sc->lock);
489 if (ch->dir == PCMDIR_PLAY) {
492 cmi_ch0_start(sc, ch);
496 cmi_ch0_stop(sc, ch);
502 cmi_ch1_start(sc, ch);
506 cmi_ch1_stop(sc, ch);
510 snd_mtxunlock(sc->lock);
515 cmichan_getptr(kobj_t obj, void *data)
517 struct sc_chinfo *ch = data;
518 struct sc_info *sc = ch->parent;
519 u_int32_t physptr, bufptr, sz;
521 snd_mtxlock(sc->lock);
522 if (ch->dir == PCMDIR_PLAY) {
523 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4);
525 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4);
527 snd_mtxunlock(sc->lock);
529 sz = sndbuf_getsize(ch->buffer);
530 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz;
538 struct sc_info *sc = data;
542 snd_mtxlock(sc->lock);
543 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4);
544 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) {
547 if (intrstat & CMPCI_REG_CH0_INTR) {
548 toclear |= CMPCI_REG_CH0_INTR_ENABLE;
549 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
552 if (intrstat & CMPCI_REG_CH1_INTR) {
553 toclear |= CMPCI_REG_CH1_INTR_ENABLE;
554 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
558 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear);
559 snd_mtxunlock(sc->lock);
561 /* Signal interrupts to channel */
562 if (intrstat & CMPCI_REG_CH0_INTR) {
563 chn_intr(sc->pch.channel);
566 if (intrstat & CMPCI_REG_CH1_INTR) {
567 chn_intr(sc->rch.channel);
570 snd_mtxlock(sc->lock);
571 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear);
576 (sc->mpu_intr)(sc->mpu);
578 snd_mtxunlock(sc->lock);
582 static struct pcmchan_caps *
583 cmichan_getcaps(kobj_t obj, void *data)
588 static kobj_method_t cmichan_methods[] = {
589 KOBJMETHOD(channel_init, cmichan_init),
590 KOBJMETHOD(channel_setformat, cmichan_setformat),
591 KOBJMETHOD(channel_setspeed, cmichan_setspeed),
592 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize),
593 KOBJMETHOD(channel_trigger, cmichan_trigger),
594 KOBJMETHOD(channel_getptr, cmichan_getptr),
595 KOBJMETHOD(channel_getcaps, cmichan_getcaps),
598 CHANNEL_DECLARE(cmichan);
600 /* ------------------------------------------------------------------------- */
601 /* Mixer - sb16 with kinks */
604 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val)
606 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
607 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1);
611 cmimix_rd(struct sc_info *sc, u_int8_t port)
613 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
614 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1);
618 u_int8_t rreg; /* right reg chan register */
619 u_int8_t stereo:1; /* (no explanation needed, honest) */
620 u_int8_t rec:1; /* recording source */
621 u_int8_t bits:3; /* num bits to represent maximum gain rep */
622 u_int8_t oselect; /* output select mask */
623 u_int8_t iselect; /* right input select mask */
624 } static const cmt[SOUND_MIXER_NRDEVICES] = {
625 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5,
626 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R},
627 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5,
628 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R},
629 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5,
630 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R},
631 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5,
632 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC},
633 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0},
634 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0},
635 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0},
636 /* These controls are not implemented in CMI8738, but maybe at a
637 future date. They are not documented in C-Media documentation,
638 though appear in other drivers for future h/w (ALSA, Linux, NetBSD).
640 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0},
641 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0},
642 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0},
643 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0},
644 /* The mic pre-amp is implemented with non-SB16 compatible
646 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0},
649 #define MIXER_GAIN_REG_RTOL(r) (r - 1)
652 cmimix_init(struct snd_mixer *m)
654 struct sc_info *sc = mix_getdevinfo(m);
657 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
658 if (cmt[i].bits) v |= 1 << i;
662 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
663 if (cmt[i].rec) v |= 1 << i;
665 mix_setrecdevs(m, v);
667 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0);
668 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
669 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
670 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX,
671 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
676 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
678 struct sc_info *sc = mix_getdevinfo(m);
682 max = (1 << cmt[dev].bits) - 1;
684 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) {
685 /* For time being this can only be one thing (mic in
687 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0;
688 l = left * max / 100;
689 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */
690 v |= ((l << 1) | (~l >> 3)) & 0x0f;
691 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1);
695 l = (left * max / 100) << (8 - cmt[dev].bits);
696 if (cmt[dev].stereo) {
697 r = (right * max / 100) << (8 - cmt[dev].bits);
698 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l);
699 cmimix_wr(sc, cmt[dev].rreg, r);
700 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\
701 "value 0x%02x:0x%02x\n",
702 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r));
705 cmimix_wr(sc, cmt[dev].rreg, l);
706 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \
707 "value 0x%02x:0x%02x\n",
708 dev, cmt[dev].rreg, l, l));
711 /* Zero gain does not mute channel from output, but this does... */
712 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX);
713 if (l == 0 && r == 0) {
714 v &= ~cmt[dev].oselect;
716 v |= cmt[dev].oselect;
718 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v);
724 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src)
726 struct sc_info *sc = mix_getdevinfo(m);
730 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
733 sl |= cmt[i].iselect;
735 ml |= cmt[i].iselect;
739 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml);
740 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
741 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml));
742 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml);
743 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml);
744 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
745 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml));
750 /* Optional SPDIF support. */
753 cmi_initsys(struct sc_info* sc)
755 /* XXX: an user should be able to set this with a control tool,
756 if not done before 7.0-RELEASE, this needs to be converted
757 to a device specific sysctl "dev.pcm.X.yyy" via
758 device_get_sysctl_*() as discussed on multimedia@ in msg-id
759 <861wujij2q.fsf@xps.des.no> */
760 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev),
761 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
762 OID_AUTO, "spdif_enabled", CTLFLAG_RW,
763 &sc->spdif_enabled, 0,
764 "enable SPDIF output at 44.1 kHz and above");
769 /* ------------------------------------------------------------------------- */
770 static kobj_method_t cmi_mixer_methods[] = {
771 KOBJMETHOD(mixer_init, cmimix_init),
772 KOBJMETHOD(mixer_set, cmimix_set),
773 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc),
776 MIXER_DECLARE(cmi_mixer);
783 cmi_mread(struct mpu401 *arg, void *sc, int reg)
787 d = bus_space_read_1(0,0, 0x330 + reg);
788 /* printf("cmi_mread: reg %x %x\n",reg, d);
794 cmi_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b)
797 bus_space_write_1(0,0,0x330 + reg , b);
801 cmi_muninit(struct mpu401 *arg, void *cookie)
803 struct sc_info *sc = cookie;
805 snd_mtxlock(sc->lock);
808 snd_mtxunlock(sc->lock);
813 static kobj_method_t cmi_mpu_methods[] = {
814 KOBJMETHOD(mpufoi_read, cmi_mread),
815 KOBJMETHOD(mpufoi_write, cmi_mwrite),
816 KOBJMETHOD(mpufoi_uninit, cmi_muninit),
820 static DEFINE_CLASS(cmi_mpu, cmi_mpu_methods, 0);
823 cmi_midiattach(struct sc_info *sc) {
833 Notes, CMPCI_REG_VMPUSEL sets the io port for the mpu. Does
834 anyone know how to bus_space tag?
836 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
837 cmi_clr4(sc, CMPCI_REG_LEGACY_CTRL,
838 CMPCI_REG_VMPUSEL_MASK << CMPCI_REG_VMPUSEL_SHIFT);
839 cmi_set4(sc, CMPCI_REG_LEGACY_CTRL,
840 0 << CMPCI_REG_VMPUSEL_SHIFT );
841 cmi_set4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
842 sc->mpu = mpu401_init(&cmi_mpu_class, sc, cmi_intr, &sc->mpu_intr);
847 /* ------------------------------------------------------------------------- */
848 /* Power and reset */
851 cmi_power(struct sc_info *sc, int state)
854 case 0: /* full power */
855 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
859 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
865 cmi_init(struct sc_info *sc)
868 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
870 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
872 /* Disable interrupts and channels */
873 cmi_clr4(sc, CMPCI_REG_FUNC_0,
874 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
875 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
876 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE);
878 /* Configure DMA channels, ch0 = play, ch1 = capture */
879 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR);
880 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR);
882 /* Attempt to enable 4 Channel output */
883 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D);
885 /* Disable SPDIF1 - not compatible with config */
886 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE);
887 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
893 cmi_uninit(struct sc_info *sc)
895 /* Disable interrupts and channels */
896 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
897 CMPCI_REG_CH0_INTR_ENABLE |
898 CMPCI_REG_CH1_INTR_ENABLE |
899 CMPCI_REG_TDMA_INTR_ENABLE);
900 cmi_clr4(sc, CMPCI_REG_FUNC_0,
901 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
902 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
908 /* ------------------------------------------------------------------------- */
909 /* Bus and device registration */
911 cmi_probe(device_t dev)
913 switch(pci_get_devid(dev)) {
914 case CMI8338A_PCI_ID:
915 device_set_desc(dev, "CMedia CMI8338A");
916 return BUS_PROBE_DEFAULT;
917 case CMI8338B_PCI_ID:
918 device_set_desc(dev, "CMedia CMI8338B");
919 return BUS_PROBE_DEFAULT;
921 device_set_desc(dev, "CMedia CMI8738");
922 return BUS_PROBE_DEFAULT;
923 case CMI8738B_PCI_ID:
924 device_set_desc(dev, "CMedia CMI8738B");
925 return BUS_PROBE_DEFAULT;
927 device_set_desc(dev, "CMedia CMI120");
928 return BUS_PROBE_DEFAULT;
935 cmi_attach(device_t dev)
938 char status[SND_STATUSLEN];
940 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
941 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_cmi softc");
942 pci_enable_busmaster(dev);
945 sc->regid = PCIR_BAR(0);
946 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid,
949 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n");
952 sc->st = rman_get_bustag(sc->reg);
953 sc->sh = rman_get_bushandle(sc->reg);
959 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
960 RF_ACTIVE | RF_SHAREABLE);
962 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) {
963 device_printf(dev, "cmi_attach: Unable to map interrupt\n");
967 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536);
969 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
971 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
972 /*highaddr*/BUS_SPACE_MAXADDR,
973 /*filter*/NULL, /*filterarg*/NULL,
974 /*maxsize*/sc->bufsz, /*nsegments*/1,
975 /*maxsegz*/0x3ffff, /*flags*/0,
978 &sc->parent_dmat) != 0) {
979 device_printf(dev, "cmi_attach: Unable to create dma tag\n");
987 if (mixer_init(dev, &cmi_mixer_class, sc))
990 if (pcm_register(dev, sc, 1, 1))
995 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc);
996 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc);
998 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s",
999 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi));
1000 pcm_setstatus(dev, status);
1002 DEB(printf("cmi_attach: succeeded\n"));
1006 if (sc->parent_dmat)
1007 bus_dma_tag_destroy(sc->parent_dmat);
1009 bus_teardown_intr(dev, sc->irq, sc->ih);
1011 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1013 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
1015 snd_mtxfree(sc->lock);
1023 cmi_detach(device_t dev)
1028 r = pcm_unregister(dev);
1031 sc = pcm_getdevinfo(dev);
1035 bus_dma_tag_destroy(sc->parent_dmat);
1036 bus_teardown_intr(dev, sc->irq, sc->ih);
1037 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1039 mpu401_uninit(sc->mpu);
1040 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
1042 bus_release_resource(dev, SYS_RES_IOPORT, sc->mpu_regid, sc->mpu_reg);
1044 snd_mtxfree(sc->lock);
1051 cmi_suspend(device_t dev)
1053 struct sc_info *sc = pcm_getdevinfo(dev);
1055 snd_mtxlock(sc->lock);
1056 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch);
1057 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch);
1059 snd_mtxunlock(sc->lock);
1064 cmi_resume(device_t dev)
1066 struct sc_info *sc = pcm_getdevinfo(dev);
1068 snd_mtxlock(sc->lock);
1070 if (cmi_init(sc) != 0) {
1071 device_printf(dev, "unable to reinitialize the card\n");
1072 snd_mtxunlock(sc->lock);
1076 if (mixer_reinit(dev) == -1) {
1077 device_printf(dev, "unable to reinitialize the mixer\n");
1078 snd_mtxunlock(sc->lock);
1082 if (sc->pch.dma_was_active) {
1083 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd);
1084 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt);
1085 cmi_ch0_start(sc, &sc->pch);
1088 if (sc->rch.dma_was_active) {
1089 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd);
1090 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt);
1091 cmi_ch1_start(sc, &sc->rch);
1093 snd_mtxunlock(sc->lock);
1097 static device_method_t cmi_methods[] = {
1098 DEVMETHOD(device_probe, cmi_probe),
1099 DEVMETHOD(device_attach, cmi_attach),
1100 DEVMETHOD(device_detach, cmi_detach),
1101 DEVMETHOD(device_resume, cmi_resume),
1102 DEVMETHOD(device_suspend, cmi_suspend),
1106 static driver_t cmi_driver = {
1112 DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, 0, 0);
1113 MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1114 MODULE_DEPEND(snd_cmi, midi, 1,1,1);
1115 MODULE_VERSION(snd_cmi, 1);