2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
26 * This driver exists largely as a result of other people's efforts.
27 * Much of register handling is based on NetBSD CMI8x38 audio driver
28 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien
29 * <cltien@cmedia.com.tw> clarified points regarding the DMA related
30 * registers and the 8738 mixer devices. His Linux driver was also a
31 * useful reference point.
35 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>.
37 * This card/code does not always manage to sample at 44100 - actual
38 * rate drifts slightly between recordings (usually 0-3%). No
39 * differences visible in register dumps between times that work and
43 #include <dev/sound/pcm/sound.h>
44 #include <dev/sound/pci/cmireg.h>
45 #include <dev/sound/isa/sb.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
50 #include <sys/sysctl.h>
51 #include <dev/sound/midi/mpu401.h>
54 #include "mpufoi_if.h"
56 SND_DECLARE_FILE("$FreeBSD$");
58 /* Supported chip ID's */
59 #define CMI8338A_PCI_ID 0x010013f6
60 #define CMI8338B_PCI_ID 0x010113f6
61 #define CMI8738_PCI_ID 0x011113f6
62 #define CMI8738B_PCI_ID 0x011213f6
64 /* Buffer size max is 64k for permitted DMA boundaries */
65 #define CMI_DEFAULT_BUFSZ 16384
67 /* Interrupts per length of buffer */
68 #define CMI_INTR_PER_BUFFER 2
70 /* Clarify meaning of named defines in cmireg.h */
71 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES
72 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES
73 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES
74 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES
76 /* Our indication of custom mixer control */
77 #define CMPCI_NON_SB16_CONTROL 0xff
79 /* Debugging macro's */
82 #define DEB(x) /* x */
86 #define DEBMIX(x) /* x */
89 /* ------------------------------------------------------------------------- */
95 struct sc_info *parent;
96 struct pcm_channel *channel;
97 struct snd_dbuf *buffer;
98 u_int32_t fmt, spd, phys_buf, bps;
99 u_int32_t dma_active:1, dma_was_active:1;
107 bus_space_handle_t sh;
108 bus_dma_tag_t parent_dmat;
109 struct resource *reg, *irq;
116 struct sc_chinfo pch, rch;
119 mpu401_intr_t *mpu_intr;
120 struct resource *mpu_reg;
122 bus_space_tag_t mpu_bt;
123 bus_space_handle_t mpu_bh;
128 static u_int32_t cmi_fmt[] = {
130 AFMT_STEREO | AFMT_U8,
132 AFMT_STEREO | AFMT_S16_LE,
136 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0};
138 /* ------------------------------------------------------------------------- */
139 /* Register Utilities */
142 cmi_rd(struct sc_info *sc, int regno, int size)
146 return bus_space_read_1(sc->st, sc->sh, regno);
148 return bus_space_read_2(sc->st, sc->sh, regno);
150 return bus_space_read_4(sc->st, sc->sh, regno);
152 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size));
158 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
162 bus_space_write_1(sc->st, sc->sh, regno, data);
165 bus_space_write_2(sc->st, sc->sh, regno, data);
168 bus_space_write_4(sc->st, sc->sh, regno, data);
174 cmi_partial_wr4(struct sc_info *sc,
175 int reg, int shift, u_int32_t mask, u_int32_t val)
179 r = cmi_rd(sc, reg, 4);
180 r &= ~(mask << shift);
182 cmi_wr(sc, reg, r, 4);
186 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask)
190 r = cmi_rd(sc, reg, 4);
192 cmi_wr(sc, reg, r, 4);
196 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask)
200 r = cmi_rd(sc, reg, 4);
202 cmi_wr(sc, reg, r, 4);
205 /* ------------------------------------------------------------------------- */
208 static int cmi_rates[] = {5512, 8000, 11025, 16000,
209 22050, 32000, 44100, 48000};
210 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0]))
212 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1
213 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */
216 cmpci_rate_to_regvalue(int rate)
220 for(i = 0; i < NUM_CMI_RATES - 1; i++) {
221 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) {
226 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i]));
228 r = ((i >> 1) | (i << 2)) & 0x07;
233 cmpci_regvalue_to_rate(u_int32_t r)
237 i = ((r << 1) | (r >> 2)) & 0x07;
238 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i));
242 /* ------------------------------------------------------------------------- */
243 /* ADC/DAC control - there are 2 dma channels on 8738, either can be
244 * playback or capture. We use ch0 for playback and ch1 for capture. */
247 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base)
251 ch->phys_buf = sndbuf_getbufaddr(ch->buffer);
253 cmi_wr(sc, base, ch->phys_buf, 4);
254 sz = (u_int32_t)sndbuf_getsize(ch->buffer);
256 s = sz / ch->bps - 1;
257 cmi_wr(sc, base + 4, s, 2);
259 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1;
260 cmi_wr(sc, base + 6, i, 2);
265 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch)
267 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
269 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
270 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
271 CMPCI_REG_CH0_INTR_ENABLE);
277 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch)
279 u_int32_t r = ch->dma_active;
281 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
282 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
283 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
284 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
290 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch)
292 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
293 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
294 /* Enable Interrupts */
295 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
296 CMPCI_REG_CH1_INTR_ENABLE);
297 DEB(printf("cmi_ch1_start: dma prog\n"));
302 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch)
304 u_int32_t r = ch->dma_active;
306 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
307 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
308 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
309 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
315 cmi_spdif_speed(struct sc_info *sc, int speed) {
316 u_int32_t fcr1, lcr, mcr;
318 if (speed >= 44100) {
319 fcr1 = CMPCI_REG_SPDIF0_ENABLE;
320 lcr = CMPCI_REG_XSPDIF_ENABLE;
321 mcr = (speed == 48000) ?
322 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0;
324 fcr1 = mcr = lcr = 0;
327 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0,
328 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr);
329 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0,
330 CMPCI_REG_SPDIF0_ENABLE, fcr1);
331 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0,
332 CMPCI_REG_XSPDIF_ENABLE, lcr);
335 /* ------------------------------------------------------------------------- */
336 /* Channel Interface implementation */
339 cmichan_init(kobj_t obj, void *devinfo,
340 struct snd_dbuf *b, struct pcm_channel *c, int dir)
342 struct sc_info *sc = devinfo;
343 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
349 ch->spd = DSP_DEFAULT_SPEED;
352 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
353 DEB(printf("cmichan_init failed\n"));
358 snd_mtxlock(sc->lock);
359 if (ch->dir == PCMDIR_PLAY) {
360 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
362 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
364 snd_mtxunlock(sc->lock);
370 cmichan_setformat(kobj_t obj, void *data, u_int32_t format)
372 struct sc_chinfo *ch = data;
373 struct sc_info *sc = ch->parent;
376 if (format & AFMT_S16_LE) {
377 f = CMPCI_REG_FORMAT_16BIT;
380 f = CMPCI_REG_FORMAT_8BIT;
384 if (format & AFMT_STEREO) {
385 f |= CMPCI_REG_FORMAT_STEREO;
388 f |= CMPCI_REG_FORMAT_MONO;
391 snd_mtxlock(sc->lock);
392 if (ch->dir == PCMDIR_PLAY) {
393 cmi_partial_wr4(ch->parent,
394 CMPCI_REG_CHANNEL_FORMAT,
395 CMPCI_REG_CH0_FORMAT_SHIFT,
396 CMPCI_REG_CH0_FORMAT_MASK,
399 cmi_partial_wr4(ch->parent,
400 CMPCI_REG_CHANNEL_FORMAT,
401 CMPCI_REG_CH1_FORMAT_SHIFT,
402 CMPCI_REG_CH1_FORMAT_MASK,
405 snd_mtxunlock(sc->lock);
412 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed)
414 struct sc_chinfo *ch = data;
415 struct sc_info *sc = ch->parent;
418 r = cmpci_rate_to_regvalue(speed);
419 snd_mtxlock(sc->lock);
420 if (ch->dir == PCMDIR_PLAY) {
422 /* disable if req before rate change */
423 cmi_spdif_speed(ch->parent, speed);
425 cmi_partial_wr4(ch->parent,
427 CMPCI_REG_DAC_FS_SHIFT,
428 CMPCI_REG_DAC_FS_MASK,
430 if (speed >= 44100 && ch->parent->spdif_enabled) {
431 /* enable if req after rate change */
432 cmi_spdif_speed(ch->parent, speed);
434 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
435 rsp >>= CMPCI_REG_DAC_FS_SHIFT;
436 rsp &= CMPCI_REG_DAC_FS_MASK;
438 cmi_partial_wr4(ch->parent,
440 CMPCI_REG_ADC_FS_SHIFT,
441 CMPCI_REG_ADC_FS_MASK,
443 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
444 rsp >>= CMPCI_REG_ADC_FS_SHIFT;
445 rsp &= CMPCI_REG_ADC_FS_MASK;
447 snd_mtxunlock(sc->lock);
448 ch->spd = cmpci_regvalue_to_rate(r);
450 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n",
451 (ch->dir == PCMDIR_PLAY) ? "play" : "rec",
452 speed, ch->spd, cmpci_regvalue_to_rate(rsp)));
458 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
460 struct sc_chinfo *ch = data;
461 struct sc_info *sc = ch->parent;
463 /* user has requested interrupts every blocksize bytes */
464 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) {
465 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER;
467 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize);
473 cmichan_trigger(kobj_t obj, void *data, int go)
475 struct sc_chinfo *ch = data;
476 struct sc_info *sc = ch->parent;
478 if (!PCMTRIG_COMMON(go))
481 snd_mtxlock(sc->lock);
482 if (ch->dir == PCMDIR_PLAY) {
485 cmi_ch0_start(sc, ch);
489 cmi_ch0_stop(sc, ch);
495 cmi_ch1_start(sc, ch);
499 cmi_ch1_stop(sc, ch);
503 snd_mtxunlock(sc->lock);
508 cmichan_getptr(kobj_t obj, void *data)
510 struct sc_chinfo *ch = data;
511 struct sc_info *sc = ch->parent;
512 u_int32_t physptr, bufptr, sz;
514 snd_mtxlock(sc->lock);
515 if (ch->dir == PCMDIR_PLAY) {
516 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4);
518 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4);
520 snd_mtxunlock(sc->lock);
522 sz = sndbuf_getsize(ch->buffer);
523 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz;
531 struct sc_info *sc = data;
535 snd_mtxlock(sc->lock);
536 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4);
537 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) {
540 if (intrstat & CMPCI_REG_CH0_INTR) {
541 toclear |= CMPCI_REG_CH0_INTR_ENABLE;
542 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
545 if (intrstat & CMPCI_REG_CH1_INTR) {
546 toclear |= CMPCI_REG_CH1_INTR_ENABLE;
547 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
551 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear);
552 snd_mtxunlock(sc->lock);
554 /* Signal interrupts to channel */
555 if (intrstat & CMPCI_REG_CH0_INTR) {
556 chn_intr(sc->pch.channel);
559 if (intrstat & CMPCI_REG_CH1_INTR) {
560 chn_intr(sc->rch.channel);
563 snd_mtxlock(sc->lock);
564 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear);
569 (sc->mpu_intr)(sc->mpu);
571 snd_mtxunlock(sc->lock);
575 static struct pcmchan_caps *
576 cmichan_getcaps(kobj_t obj, void *data)
581 static kobj_method_t cmichan_methods[] = {
582 KOBJMETHOD(channel_init, cmichan_init),
583 KOBJMETHOD(channel_setformat, cmichan_setformat),
584 KOBJMETHOD(channel_setspeed, cmichan_setspeed),
585 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize),
586 KOBJMETHOD(channel_trigger, cmichan_trigger),
587 KOBJMETHOD(channel_getptr, cmichan_getptr),
588 KOBJMETHOD(channel_getcaps, cmichan_getcaps),
591 CHANNEL_DECLARE(cmichan);
593 /* ------------------------------------------------------------------------- */
594 /* Mixer - sb16 with kinks */
597 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val)
599 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
600 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1);
604 cmimix_rd(struct sc_info *sc, u_int8_t port)
606 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
607 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1);
611 u_int8_t rreg; /* right reg chan register */
612 u_int8_t stereo:1; /* (no explanation needed, honest) */
613 u_int8_t rec:1; /* recording source */
614 u_int8_t bits:3; /* num bits to represent maximum gain rep */
615 u_int8_t oselect; /* output select mask */
616 u_int8_t iselect; /* right input select mask */
617 } static const cmt[SOUND_MIXER_NRDEVICES] = {
618 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5,
619 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R},
620 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5,
621 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R},
622 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5,
623 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R},
624 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5,
625 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC},
626 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0},
627 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0},
628 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0},
629 /* These controls are not implemented in CMI8738, but maybe at a
630 future date. They are not documented in C-Media documentation,
631 though appear in other drivers for future h/w (ALSA, Linux, NetBSD).
633 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0},
634 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0},
635 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0},
636 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0},
637 /* The mic pre-amp is implemented with non-SB16 compatible
639 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0},
642 #define MIXER_GAIN_REG_RTOL(r) (r - 1)
645 cmimix_init(struct snd_mixer *m)
647 struct sc_info *sc = mix_getdevinfo(m);
650 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
651 if (cmt[i].bits) v |= 1 << i;
655 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
656 if (cmt[i].rec) v |= 1 << i;
658 mix_setrecdevs(m, v);
660 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0);
661 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
662 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
663 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX,
664 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
669 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
671 struct sc_info *sc = mix_getdevinfo(m);
675 max = (1 << cmt[dev].bits) - 1;
677 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) {
678 /* For time being this can only be one thing (mic in
680 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0;
681 l = left * max / 100;
682 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */
683 v |= ((l << 1) | (~l >> 3)) & 0x0f;
684 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1);
688 l = (left * max / 100) << (8 - cmt[dev].bits);
689 if (cmt[dev].stereo) {
690 r = (right * max / 100) << (8 - cmt[dev].bits);
691 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l);
692 cmimix_wr(sc, cmt[dev].rreg, r);
693 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\
694 "value 0x%02x:0x%02x\n",
695 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r));
698 cmimix_wr(sc, cmt[dev].rreg, l);
699 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \
700 "value 0x%02x:0x%02x\n",
701 dev, cmt[dev].rreg, l, l));
704 /* Zero gain does not mute channel from output, but this does... */
705 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX);
706 if (l == 0 && r == 0) {
707 v &= ~cmt[dev].oselect;
709 v |= cmt[dev].oselect;
711 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v);
717 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src)
719 struct sc_info *sc = mix_getdevinfo(m);
723 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
726 sl |= cmt[i].iselect;
728 ml |= cmt[i].iselect;
732 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml);
733 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
734 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml));
735 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml);
736 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml);
737 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
738 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml));
743 /* Optional SPDIF support. */
746 cmi_initsys(struct sc_info* sc)
749 /* XXX: an user should be able to set this with a control tool,
750 if not done before 7.0-RELEASE, this needs to be converted
751 to a device specific sysctl "dev.pcm.X.yyy" via
752 device_get_sysctl_*() as discussed on multimedia@ in msg-id
753 <861wujij2q.fsf@xps.des.no> */
754 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev),
755 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
756 OID_AUTO, "spdif_enabled", CTLFLAG_RW,
757 &sc->spdif_enabled, 0,
758 "enable SPDIF output at 44.1 kHz and above");
759 #endif /* SND_DYNSYSCTL */
763 /* ------------------------------------------------------------------------- */
764 static kobj_method_t cmi_mixer_methods[] = {
765 KOBJMETHOD(mixer_init, cmimix_init),
766 KOBJMETHOD(mixer_set, cmimix_set),
767 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc),
770 MIXER_DECLARE(cmi_mixer);
777 cmi_mread(void *arg, struct sc_info *sc, int reg)
781 d = bus_space_read_1(0,0, 0x330 + reg);
782 /* printf("cmi_mread: reg %x %x\n",reg, d);
788 cmi_mwrite(void *arg, struct sc_info *sc, int reg, unsigned char b)
791 bus_space_write_1(0,0,0x330 + reg , b);
795 cmi_muninit(void *arg, struct sc_info *sc)
798 snd_mtxlock(sc->lock);
801 snd_mtxunlock(sc->lock);
806 static kobj_method_t cmi_mpu_methods[] = {
807 KOBJMETHOD(mpufoi_read, cmi_mread),
808 KOBJMETHOD(mpufoi_write, cmi_mwrite),
809 KOBJMETHOD(mpufoi_uninit, cmi_muninit),
813 static DEFINE_CLASS(cmi_mpu, cmi_mpu_methods, 0);
816 cmi_midiattach(struct sc_info *sc) {
826 Notes, CMPCI_REG_VMPUSEL sets the io port for the mpu. Does
827 anyone know how to bus_space tag?
829 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
830 cmi_clr4(sc, CMPCI_REG_LEGACY_CTRL,
831 CMPCI_REG_VMPUSEL_MASK << CMPCI_REG_VMPUSEL_SHIFT);
832 cmi_set4(sc, CMPCI_REG_LEGACY_CTRL,
833 0 << CMPCI_REG_VMPUSEL_SHIFT );
834 cmi_set4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
835 sc->mpu = mpu401_init(&cmi_mpu_class, sc, cmi_intr, &sc->mpu_intr);
840 /* ------------------------------------------------------------------------- */
841 /* Power and reset */
844 cmi_power(struct sc_info *sc, int state)
847 case 0: /* full power */
848 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
852 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
858 cmi_init(struct sc_info *sc)
861 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
863 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
865 /* Disable interrupts and channels */
866 cmi_clr4(sc, CMPCI_REG_FUNC_0,
867 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
868 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
869 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE);
871 /* Configure DMA channels, ch0 = play, ch1 = capture */
872 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR);
873 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR);
875 /* Attempt to enable 4 Channel output */
876 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D);
878 /* Disable SPDIF1 - not compatible with config */
879 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE);
880 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
886 cmi_uninit(struct sc_info *sc)
888 /* Disable interrupts and channels */
889 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
890 CMPCI_REG_CH0_INTR_ENABLE |
891 CMPCI_REG_CH1_INTR_ENABLE |
892 CMPCI_REG_TDMA_INTR_ENABLE);
893 cmi_clr4(sc, CMPCI_REG_FUNC_0,
894 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
895 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
901 /* ------------------------------------------------------------------------- */
902 /* Bus and device registration */
904 cmi_probe(device_t dev)
906 switch(pci_get_devid(dev)) {
907 case CMI8338A_PCI_ID:
908 device_set_desc(dev, "CMedia CMI8338A");
909 return BUS_PROBE_DEFAULT;
910 case CMI8338B_PCI_ID:
911 device_set_desc(dev, "CMedia CMI8338B");
912 return BUS_PROBE_DEFAULT;
914 device_set_desc(dev, "CMedia CMI8738");
915 return BUS_PROBE_DEFAULT;
916 case CMI8738B_PCI_ID:
917 device_set_desc(dev, "CMedia CMI8738B");
918 return BUS_PROBE_DEFAULT;
925 cmi_attach(device_t dev)
929 char status[SND_STATUSLEN];
931 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
932 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_cmi softc");
933 data = pci_read_config(dev, PCIR_COMMAND, 2);
934 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN);
935 pci_write_config(dev, PCIR_COMMAND, data, 2);
936 data = pci_read_config(dev, PCIR_COMMAND, 2);
939 sc->regid = PCIR_BAR(0);
940 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid,
943 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n");
946 sc->st = rman_get_bustag(sc->reg);
947 sc->sh = rman_get_bushandle(sc->reg);
953 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
954 RF_ACTIVE | RF_SHAREABLE);
956 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) {
957 device_printf(dev, "cmi_attach: Unable to map interrupt\n");
961 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536);
963 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
965 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
966 /*highaddr*/BUS_SPACE_MAXADDR,
967 /*filter*/NULL, /*filterarg*/NULL,
968 /*maxsize*/sc->bufsz, /*nsegments*/1,
969 /*maxsegz*/0x3ffff, /*flags*/0,
972 &sc->parent_dmat) != 0) {
973 device_printf(dev, "cmi_attach: Unable to create dma tag\n");
981 if (mixer_init(dev, &cmi_mixer_class, sc))
984 if (pcm_register(dev, sc, 1, 1))
989 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc);
990 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc);
992 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s",
993 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi));
994 pcm_setstatus(dev, status);
996 DEB(printf("cmi_attach: succeeded\n"));
1000 if (sc->parent_dmat)
1001 bus_dma_tag_destroy(sc->parent_dmat);
1003 bus_teardown_intr(dev, sc->irq, sc->ih);
1005 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1007 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
1009 snd_mtxfree(sc->lock);
1017 cmi_detach(device_t dev)
1022 r = pcm_unregister(dev);
1025 sc = pcm_getdevinfo(dev);
1029 bus_dma_tag_destroy(sc->parent_dmat);
1030 bus_teardown_intr(dev, sc->irq, sc->ih);
1031 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1033 mpu401_uninit(sc->mpu);
1034 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
1036 bus_release_resource(dev, SYS_RES_IOPORT, sc->mpu_regid, sc->mpu_reg);
1038 snd_mtxfree(sc->lock);
1045 cmi_suspend(device_t dev)
1047 struct sc_info *sc = pcm_getdevinfo(dev);
1049 snd_mtxlock(sc->lock);
1050 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch);
1051 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch);
1053 snd_mtxunlock(sc->lock);
1058 cmi_resume(device_t dev)
1060 struct sc_info *sc = pcm_getdevinfo(dev);
1062 snd_mtxlock(sc->lock);
1064 if (cmi_init(sc) != 0) {
1065 device_printf(dev, "unable to reinitialize the card\n");
1066 snd_mtxunlock(sc->lock);
1070 if (mixer_reinit(dev) == -1) {
1071 device_printf(dev, "unable to reinitialize the mixer\n");
1072 snd_mtxunlock(sc->lock);
1076 if (sc->pch.dma_was_active) {
1077 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd);
1078 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt);
1079 cmi_ch0_start(sc, &sc->pch);
1082 if (sc->rch.dma_was_active) {
1083 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd);
1084 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt);
1085 cmi_ch1_start(sc, &sc->rch);
1087 snd_mtxunlock(sc->lock);
1091 static device_method_t cmi_methods[] = {
1092 DEVMETHOD(device_probe, cmi_probe),
1093 DEVMETHOD(device_attach, cmi_attach),
1094 DEVMETHOD(device_detach, cmi_detach),
1095 DEVMETHOD(device_resume, cmi_resume),
1096 DEVMETHOD(device_suspend, cmi_suspend),
1100 static driver_t cmi_driver = {
1106 DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, 0, 0);
1107 MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1108 MODULE_DEPEND(snd_cmi, midi, 1,1,1);
1109 MODULE_VERSION(snd_cmi, 1);