2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
30 * This driver exists largely as a result of other people's efforts.
31 * Much of register handling is based on NetBSD CMI8x38 audio driver
32 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien
33 * <cltien@cmedia.com.tw> clarified points regarding the DMA related
34 * registers and the 8738 mixer devices. His Linux driver was also a
35 * useful reference point.
39 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>.
41 * This card/code does not always manage to sample at 44100 - actual
42 * rate drifts slightly between recordings (usually 0-3%). No
43 * differences visible in register dumps between times that work and
47 #ifdef HAVE_KERNEL_OPTION_HEADERS
51 #include <dev/sound/pcm/sound.h>
52 #include <dev/sound/pci/cmireg.h>
53 #include <dev/sound/isa/sb.h>
55 #include <dev/pci/pcireg.h>
56 #include <dev/pci/pcivar.h>
58 #include <sys/sysctl.h>
59 #include <dev/sound/midi/mpu401.h>
62 #include "mpufoi_if.h"
64 SND_DECLARE_FILE("$FreeBSD$");
66 /* Supported chip ID's */
67 #define CMI8338A_PCI_ID 0x010013f6
68 #define CMI8338B_PCI_ID 0x010113f6
69 #define CMI8738_PCI_ID 0x011113f6
70 #define CMI8738B_PCI_ID 0x011213f6
71 #define CMI120_USB_ID 0x01030d8c
73 /* Buffer size max is 64k for permitted DMA boundaries */
74 #define CMI_DEFAULT_BUFSZ 16384
76 /* Interrupts per length of buffer */
77 #define CMI_INTR_PER_BUFFER 2
79 /* Clarify meaning of named defines in cmireg.h */
80 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES
81 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES
82 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES
83 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES
85 /* Our indication of custom mixer control */
86 #define CMPCI_NON_SB16_CONTROL 0xff
88 /* Debugging macro's */
91 #define DEB(x) /* x */
95 #define DEBMIX(x) /* x */
98 /* ------------------------------------------------------------------------- */
104 struct sc_info *parent;
105 struct pcm_channel *channel;
106 struct snd_dbuf *buffer;
107 u_int32_t fmt, spd, phys_buf, bps;
108 u_int32_t dma_active:1, dma_was_active:1;
116 bus_space_handle_t sh;
117 bus_dma_tag_t parent_dmat;
118 struct resource *reg, *irq;
125 struct sc_chinfo pch, rch;
128 mpu401_intr_t *mpu_intr;
129 struct resource *mpu_reg;
131 bus_space_tag_t mpu_bt;
132 bus_space_handle_t mpu_bh;
137 static u_int32_t cmi_fmt[] = {
138 SND_FORMAT(AFMT_U8, 1, 0),
139 SND_FORMAT(AFMT_U8, 2, 0),
140 SND_FORMAT(AFMT_S16_LE, 1, 0),
141 SND_FORMAT(AFMT_S16_LE, 2, 0),
145 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0};
147 /* ------------------------------------------------------------------------- */
148 /* Register Utilities */
151 cmi_rd(struct sc_info *sc, int regno, int size)
155 return bus_space_read_1(sc->st, sc->sh, regno);
157 return bus_space_read_2(sc->st, sc->sh, regno);
159 return bus_space_read_4(sc->st, sc->sh, regno);
161 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size));
167 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
171 bus_space_write_1(sc->st, sc->sh, regno, data);
174 bus_space_write_2(sc->st, sc->sh, regno, data);
177 bus_space_write_4(sc->st, sc->sh, regno, data);
183 cmi_partial_wr4(struct sc_info *sc,
184 int reg, int shift, u_int32_t mask, u_int32_t val)
188 r = cmi_rd(sc, reg, 4);
189 r &= ~(mask << shift);
191 cmi_wr(sc, reg, r, 4);
195 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask)
199 r = cmi_rd(sc, reg, 4);
201 cmi_wr(sc, reg, r, 4);
205 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask)
209 r = cmi_rd(sc, reg, 4);
211 cmi_wr(sc, reg, r, 4);
214 /* ------------------------------------------------------------------------- */
217 static int cmi_rates[] = {5512, 8000, 11025, 16000,
218 22050, 32000, 44100, 48000};
219 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0]))
221 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1
222 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */
225 cmpci_rate_to_regvalue(int rate)
229 for(i = 0; i < NUM_CMI_RATES - 1; i++) {
230 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) {
235 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i]));
237 r = ((i >> 1) | (i << 2)) & 0x07;
242 cmpci_regvalue_to_rate(u_int32_t r)
246 i = ((r << 1) | (r >> 2)) & 0x07;
247 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i));
251 /* ------------------------------------------------------------------------- */
252 /* ADC/DAC control - there are 2 dma channels on 8738, either can be
253 * playback or capture. We use ch0 for playback and ch1 for capture. */
256 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base)
260 ch->phys_buf = sndbuf_getbufaddr(ch->buffer);
262 cmi_wr(sc, base, ch->phys_buf, 4);
263 sz = (u_int32_t)sndbuf_getsize(ch->buffer);
265 s = sz / ch->bps - 1;
266 cmi_wr(sc, base + 4, s, 2);
268 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1;
269 cmi_wr(sc, base + 6, i, 2);
274 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch)
276 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
278 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
279 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
280 CMPCI_REG_CH0_INTR_ENABLE);
286 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch)
288 u_int32_t r = ch->dma_active;
290 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
291 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
292 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
293 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
299 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch)
301 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
302 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
303 /* Enable Interrupts */
304 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
305 CMPCI_REG_CH1_INTR_ENABLE);
306 DEB(printf("cmi_ch1_start: dma prog\n"));
311 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch)
313 u_int32_t r = ch->dma_active;
315 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
316 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
317 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
318 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
324 cmi_spdif_speed(struct sc_info *sc, int speed) {
325 u_int32_t fcr1, lcr, mcr;
327 if (speed >= 44100) {
328 fcr1 = CMPCI_REG_SPDIF0_ENABLE;
329 lcr = CMPCI_REG_XSPDIF_ENABLE;
330 mcr = (speed == 48000) ?
331 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0;
333 fcr1 = mcr = lcr = 0;
336 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0,
337 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr);
338 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0,
339 CMPCI_REG_SPDIF0_ENABLE, fcr1);
340 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0,
341 CMPCI_REG_XSPDIF_ENABLE, lcr);
344 /* ------------------------------------------------------------------------- */
345 /* Channel Interface implementation */
348 cmichan_init(kobj_t obj, void *devinfo,
349 struct snd_dbuf *b, struct pcm_channel *c, int dir)
351 struct sc_info *sc = devinfo;
352 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
357 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
358 ch->spd = DSP_DEFAULT_SPEED;
361 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
362 DEB(printf("cmichan_init failed\n"));
367 snd_mtxlock(sc->lock);
368 if (ch->dir == PCMDIR_PLAY) {
369 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
371 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
373 snd_mtxunlock(sc->lock);
379 cmichan_setformat(kobj_t obj, void *data, u_int32_t format)
381 struct sc_chinfo *ch = data;
382 struct sc_info *sc = ch->parent;
385 if (format & AFMT_S16_LE) {
386 f = CMPCI_REG_FORMAT_16BIT;
389 f = CMPCI_REG_FORMAT_8BIT;
393 if (AFMT_CHANNEL(format) > 1) {
394 f |= CMPCI_REG_FORMAT_STEREO;
397 f |= CMPCI_REG_FORMAT_MONO;
400 snd_mtxlock(sc->lock);
401 if (ch->dir == PCMDIR_PLAY) {
402 cmi_partial_wr4(ch->parent,
403 CMPCI_REG_CHANNEL_FORMAT,
404 CMPCI_REG_CH0_FORMAT_SHIFT,
405 CMPCI_REG_CH0_FORMAT_MASK,
408 cmi_partial_wr4(ch->parent,
409 CMPCI_REG_CHANNEL_FORMAT,
410 CMPCI_REG_CH1_FORMAT_SHIFT,
411 CMPCI_REG_CH1_FORMAT_MASK,
414 snd_mtxunlock(sc->lock);
421 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed)
423 struct sc_chinfo *ch = data;
424 struct sc_info *sc = ch->parent;
427 r = cmpci_rate_to_regvalue(speed);
428 snd_mtxlock(sc->lock);
429 if (ch->dir == PCMDIR_PLAY) {
431 /* disable if req before rate change */
432 cmi_spdif_speed(ch->parent, speed);
434 cmi_partial_wr4(ch->parent,
436 CMPCI_REG_DAC_FS_SHIFT,
437 CMPCI_REG_DAC_FS_MASK,
439 if (speed >= 44100 && ch->parent->spdif_enabled) {
440 /* enable if req after rate change */
441 cmi_spdif_speed(ch->parent, speed);
443 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
444 rsp >>= CMPCI_REG_DAC_FS_SHIFT;
445 rsp &= CMPCI_REG_DAC_FS_MASK;
447 cmi_partial_wr4(ch->parent,
449 CMPCI_REG_ADC_FS_SHIFT,
450 CMPCI_REG_ADC_FS_MASK,
452 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
453 rsp >>= CMPCI_REG_ADC_FS_SHIFT;
454 rsp &= CMPCI_REG_ADC_FS_MASK;
456 snd_mtxunlock(sc->lock);
457 ch->spd = cmpci_regvalue_to_rate(r);
459 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n",
460 (ch->dir == PCMDIR_PLAY) ? "play" : "rec",
461 speed, ch->spd, cmpci_regvalue_to_rate(rsp)));
467 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
469 struct sc_chinfo *ch = data;
470 struct sc_info *sc = ch->parent;
472 /* user has requested interrupts every blocksize bytes */
473 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) {
474 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER;
476 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize);
482 cmichan_trigger(kobj_t obj, void *data, int go)
484 struct sc_chinfo *ch = data;
485 struct sc_info *sc = ch->parent;
487 if (!PCMTRIG_COMMON(go))
490 snd_mtxlock(sc->lock);
491 if (ch->dir == PCMDIR_PLAY) {
494 cmi_ch0_start(sc, ch);
498 cmi_ch0_stop(sc, ch);
504 cmi_ch1_start(sc, ch);
508 cmi_ch1_stop(sc, ch);
512 snd_mtxunlock(sc->lock);
517 cmichan_getptr(kobj_t obj, void *data)
519 struct sc_chinfo *ch = data;
520 struct sc_info *sc = ch->parent;
521 u_int32_t physptr, bufptr, sz;
523 snd_mtxlock(sc->lock);
524 if (ch->dir == PCMDIR_PLAY) {
525 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4);
527 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4);
529 snd_mtxunlock(sc->lock);
531 sz = sndbuf_getsize(ch->buffer);
532 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz;
540 struct sc_info *sc = data;
544 snd_mtxlock(sc->lock);
545 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4);
546 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) {
549 if (intrstat & CMPCI_REG_CH0_INTR) {
550 toclear |= CMPCI_REG_CH0_INTR_ENABLE;
551 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
554 if (intrstat & CMPCI_REG_CH1_INTR) {
555 toclear |= CMPCI_REG_CH1_INTR_ENABLE;
556 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
560 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear);
561 snd_mtxunlock(sc->lock);
563 /* Signal interrupts to channel */
564 if (intrstat & CMPCI_REG_CH0_INTR) {
565 chn_intr(sc->pch.channel);
568 if (intrstat & CMPCI_REG_CH1_INTR) {
569 chn_intr(sc->rch.channel);
572 snd_mtxlock(sc->lock);
573 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear);
578 (sc->mpu_intr)(sc->mpu);
580 snd_mtxunlock(sc->lock);
584 static struct pcmchan_caps *
585 cmichan_getcaps(kobj_t obj, void *data)
590 static kobj_method_t cmichan_methods[] = {
591 KOBJMETHOD(channel_init, cmichan_init),
592 KOBJMETHOD(channel_setformat, cmichan_setformat),
593 KOBJMETHOD(channel_setspeed, cmichan_setspeed),
594 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize),
595 KOBJMETHOD(channel_trigger, cmichan_trigger),
596 KOBJMETHOD(channel_getptr, cmichan_getptr),
597 KOBJMETHOD(channel_getcaps, cmichan_getcaps),
600 CHANNEL_DECLARE(cmichan);
602 /* ------------------------------------------------------------------------- */
603 /* Mixer - sb16 with kinks */
606 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val)
608 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
609 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1);
613 cmimix_rd(struct sc_info *sc, u_int8_t port)
615 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
616 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1);
620 u_int8_t rreg; /* right reg chan register */
621 u_int8_t stereo:1; /* (no explanation needed, honest) */
622 u_int8_t rec:1; /* recording source */
623 u_int8_t bits:3; /* num bits to represent maximum gain rep */
624 u_int8_t oselect; /* output select mask */
625 u_int8_t iselect; /* right input select mask */
626 } static const cmt[SOUND_MIXER_NRDEVICES] = {
627 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5,
628 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R},
629 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5,
630 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R},
631 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5,
632 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R},
633 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5,
634 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC},
635 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0},
636 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0},
637 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0},
638 /* These controls are not implemented in CMI8738, but maybe at a
639 future date. They are not documented in C-Media documentation,
640 though appear in other drivers for future h/w (ALSA, Linux, NetBSD).
642 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0},
643 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0},
644 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0},
645 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0},
646 /* The mic pre-amp is implemented with non-SB16 compatible
648 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0},
651 #define MIXER_GAIN_REG_RTOL(r) (r - 1)
654 cmimix_init(struct snd_mixer *m)
656 struct sc_info *sc = mix_getdevinfo(m);
659 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
660 if (cmt[i].bits) v |= 1 << i;
664 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
665 if (cmt[i].rec) v |= 1 << i;
667 mix_setrecdevs(m, v);
669 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0);
670 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
671 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
672 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX,
673 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
678 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
680 struct sc_info *sc = mix_getdevinfo(m);
684 max = (1 << cmt[dev].bits) - 1;
686 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) {
687 /* For time being this can only be one thing (mic in
689 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0;
690 l = left * max / 100;
691 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */
692 v |= ((l << 1) | (~l >> 3)) & 0x0f;
693 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1);
697 l = (left * max / 100) << (8 - cmt[dev].bits);
698 if (cmt[dev].stereo) {
699 r = (right * max / 100) << (8 - cmt[dev].bits);
700 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l);
701 cmimix_wr(sc, cmt[dev].rreg, r);
702 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\
703 "value 0x%02x:0x%02x\n",
704 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r));
707 cmimix_wr(sc, cmt[dev].rreg, l);
708 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \
709 "value 0x%02x:0x%02x\n",
710 dev, cmt[dev].rreg, l, l));
713 /* Zero gain does not mute channel from output, but this does... */
714 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX);
715 if (l == 0 && r == 0) {
716 v &= ~cmt[dev].oselect;
718 v |= cmt[dev].oselect;
720 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v);
726 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src)
728 struct sc_info *sc = mix_getdevinfo(m);
732 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
735 sl |= cmt[i].iselect;
737 ml |= cmt[i].iselect;
741 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml);
742 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
743 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml));
744 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml);
745 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml);
746 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
747 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml));
752 /* Optional SPDIF support. */
755 cmi_initsys(struct sc_info* sc)
757 /* XXX: an user should be able to set this with a control tool,
758 if not done before 7.0-RELEASE, this needs to be converted
759 to a device specific sysctl "dev.pcm.X.yyy" via
760 device_get_sysctl_*() as discussed on multimedia@ in msg-id
761 <861wujij2q.fsf@xps.des.no> */
762 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev),
763 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
764 OID_AUTO, "spdif_enabled", CTLFLAG_RW,
765 &sc->spdif_enabled, 0,
766 "enable SPDIF output at 44.1 kHz and above");
771 /* ------------------------------------------------------------------------- */
772 static kobj_method_t cmi_mixer_methods[] = {
773 KOBJMETHOD(mixer_init, cmimix_init),
774 KOBJMETHOD(mixer_set, cmimix_set),
775 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc),
778 MIXER_DECLARE(cmi_mixer);
785 cmi_mread(struct mpu401 *arg, void *sc, int reg)
789 d = bus_space_read_1(0,0, 0x330 + reg);
790 /* printf("cmi_mread: reg %x %x\n",reg, d);
796 cmi_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b)
799 bus_space_write_1(0,0,0x330 + reg , b);
803 cmi_muninit(struct mpu401 *arg, void *cookie)
805 struct sc_info *sc = cookie;
807 snd_mtxlock(sc->lock);
810 snd_mtxunlock(sc->lock);
815 static kobj_method_t cmi_mpu_methods[] = {
816 KOBJMETHOD(mpufoi_read, cmi_mread),
817 KOBJMETHOD(mpufoi_write, cmi_mwrite),
818 KOBJMETHOD(mpufoi_uninit, cmi_muninit),
822 static DEFINE_CLASS(cmi_mpu, cmi_mpu_methods, 0);
825 cmi_midiattach(struct sc_info *sc) {
835 Notes, CMPCI_REG_VMPUSEL sets the io port for the mpu. Does
836 anyone know how to bus_space tag?
838 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
839 cmi_clr4(sc, CMPCI_REG_LEGACY_CTRL,
840 CMPCI_REG_VMPUSEL_MASK << CMPCI_REG_VMPUSEL_SHIFT);
841 cmi_set4(sc, CMPCI_REG_LEGACY_CTRL,
842 0 << CMPCI_REG_VMPUSEL_SHIFT );
843 cmi_set4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
844 sc->mpu = mpu401_init(&cmi_mpu_class, sc, cmi_intr, &sc->mpu_intr);
849 /* ------------------------------------------------------------------------- */
850 /* Power and reset */
853 cmi_power(struct sc_info *sc, int state)
856 case 0: /* full power */
857 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
861 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
867 cmi_init(struct sc_info *sc)
870 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
872 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
874 /* Disable interrupts and channels */
875 cmi_clr4(sc, CMPCI_REG_FUNC_0,
876 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
877 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
878 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE);
880 /* Configure DMA channels, ch0 = play, ch1 = capture */
881 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR);
882 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR);
884 /* Attempt to enable 4 Channel output */
885 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D);
887 /* Disable SPDIF1 - not compatible with config */
888 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE);
889 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
895 cmi_uninit(struct sc_info *sc)
897 /* Disable interrupts and channels */
898 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
899 CMPCI_REG_CH0_INTR_ENABLE |
900 CMPCI_REG_CH1_INTR_ENABLE |
901 CMPCI_REG_TDMA_INTR_ENABLE);
902 cmi_clr4(sc, CMPCI_REG_FUNC_0,
903 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
904 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
910 /* ------------------------------------------------------------------------- */
911 /* Bus and device registration */
913 cmi_probe(device_t dev)
915 switch(pci_get_devid(dev)) {
916 case CMI8338A_PCI_ID:
917 device_set_desc(dev, "CMedia CMI8338A");
918 return BUS_PROBE_DEFAULT;
919 case CMI8338B_PCI_ID:
920 device_set_desc(dev, "CMedia CMI8338B");
921 return BUS_PROBE_DEFAULT;
923 device_set_desc(dev, "CMedia CMI8738");
924 return BUS_PROBE_DEFAULT;
925 case CMI8738B_PCI_ID:
926 device_set_desc(dev, "CMedia CMI8738B");
927 return BUS_PROBE_DEFAULT;
929 device_set_desc(dev, "CMedia CMI120");
930 return BUS_PROBE_DEFAULT;
937 cmi_attach(device_t dev)
940 char status[SND_STATUSLEN];
942 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
943 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_cmi softc");
944 pci_enable_busmaster(dev);
947 sc->regid = PCIR_BAR(0);
948 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid,
951 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n");
954 sc->st = rman_get_bustag(sc->reg);
955 sc->sh = rman_get_bushandle(sc->reg);
961 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
962 RF_ACTIVE | RF_SHAREABLE);
964 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) {
965 device_printf(dev, "cmi_attach: Unable to map interrupt\n");
969 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536);
971 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
973 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
974 /*highaddr*/BUS_SPACE_MAXADDR,
975 /*filter*/NULL, /*filterarg*/NULL,
976 /*maxsize*/sc->bufsz, /*nsegments*/1,
977 /*maxsegz*/0x3ffff, /*flags*/0,
980 &sc->parent_dmat) != 0) {
981 device_printf(dev, "cmi_attach: Unable to create dma tag\n");
989 if (mixer_init(dev, &cmi_mixer_class, sc))
992 if (pcm_register(dev, sc, 1, 1))
997 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc);
998 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc);
1000 snprintf(status, SND_STATUSLEN, "at io 0x%jx irq %jd %s",
1001 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi));
1002 pcm_setstatus(dev, status);
1004 DEB(printf("cmi_attach: succeeded\n"));
1008 if (sc->parent_dmat)
1009 bus_dma_tag_destroy(sc->parent_dmat);
1011 bus_teardown_intr(dev, sc->irq, sc->ih);
1013 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1015 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
1017 snd_mtxfree(sc->lock);
1025 cmi_detach(device_t dev)
1030 r = pcm_unregister(dev);
1033 sc = pcm_getdevinfo(dev);
1037 bus_dma_tag_destroy(sc->parent_dmat);
1038 bus_teardown_intr(dev, sc->irq, sc->ih);
1039 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1041 mpu401_uninit(sc->mpu);
1042 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
1044 bus_release_resource(dev, SYS_RES_IOPORT, sc->mpu_regid, sc->mpu_reg);
1046 snd_mtxfree(sc->lock);
1053 cmi_suspend(device_t dev)
1055 struct sc_info *sc = pcm_getdevinfo(dev);
1057 snd_mtxlock(sc->lock);
1058 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch);
1059 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch);
1061 snd_mtxunlock(sc->lock);
1066 cmi_resume(device_t dev)
1068 struct sc_info *sc = pcm_getdevinfo(dev);
1070 snd_mtxlock(sc->lock);
1072 if (cmi_init(sc) != 0) {
1073 device_printf(dev, "unable to reinitialize the card\n");
1074 snd_mtxunlock(sc->lock);
1078 if (mixer_reinit(dev) == -1) {
1079 device_printf(dev, "unable to reinitialize the mixer\n");
1080 snd_mtxunlock(sc->lock);
1084 if (sc->pch.dma_was_active) {
1085 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd);
1086 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt);
1087 cmi_ch0_start(sc, &sc->pch);
1090 if (sc->rch.dma_was_active) {
1091 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd);
1092 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt);
1093 cmi_ch1_start(sc, &sc->rch);
1095 snd_mtxunlock(sc->lock);
1099 static device_method_t cmi_methods[] = {
1100 DEVMETHOD(device_probe, cmi_probe),
1101 DEVMETHOD(device_attach, cmi_attach),
1102 DEVMETHOD(device_detach, cmi_detach),
1103 DEVMETHOD(device_resume, cmi_resume),
1104 DEVMETHOD(device_suspend, cmi_suspend),
1108 static driver_t cmi_driver = {
1114 DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, 0, 0);
1115 MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1116 MODULE_DEPEND(snd_cmi, midi, 1,1,1);
1117 MODULE_VERSION(snd_cmi, 1);