2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
30 * This driver exists largely as a result of other people's efforts.
31 * Much of register handling is based on NetBSD CMI8x38 audio driver
32 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien
33 * <cltien@cmedia.com.tw> clarified points regarding the DMA related
34 * registers and the 8738 mixer devices. His Linux driver was also a
35 * useful reference point.
39 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>.
41 * This card/code does not always manage to sample at 44100 - actual
42 * rate drifts slightly between recordings (usually 0-3%). No
43 * differences visible in register dumps between times that work and
47 #ifdef HAVE_KERNEL_OPTION_HEADERS
51 #include <dev/sound/pcm/sound.h>
52 #include <dev/sound/pci/cmireg.h>
53 #include <dev/sound/isa/sb.h>
55 #include <dev/pci/pcireg.h>
56 #include <dev/pci/pcivar.h>
58 #include <sys/sysctl.h>
59 #include <dev/sound/midi/mpu401.h>
62 #include "mpufoi_if.h"
64 SND_DECLARE_FILE("$FreeBSD$");
66 /* Supported chip ID's */
67 #define CMI8338A_PCI_ID 0x010013f6
68 #define CMI8338B_PCI_ID 0x010113f6
69 #define CMI8738_PCI_ID 0x011113f6
70 #define CMI8738B_PCI_ID 0x011213f6
71 #define CMI120_USB_ID 0x01030d8c
73 /* Buffer size max is 64k for permitted DMA boundaries */
74 #define CMI_DEFAULT_BUFSZ 16384
76 /* Interrupts per length of buffer */
77 #define CMI_INTR_PER_BUFFER 2
79 /* Clarify meaning of named defines in cmireg.h */
80 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES
81 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES
82 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES
83 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES
85 /* Our indication of custom mixer control */
86 #define CMPCI_NON_SB16_CONTROL 0xff
88 /* Debugging macro's */
91 #define DEB(x) /* x */
95 #define DEBMIX(x) /* x */
98 /* ------------------------------------------------------------------------- */
104 struct sc_info *parent;
105 struct pcm_channel *channel;
106 struct snd_dbuf *buffer;
107 u_int32_t fmt, spd, phys_buf, bps;
108 u_int32_t dma_active:1, dma_was_active:1;
116 bus_space_handle_t sh;
117 bus_dma_tag_t parent_dmat;
118 struct resource *reg, *irq;
125 struct sc_chinfo pch, rch;
128 mpu401_intr_t *mpu_intr;
129 struct resource *mpu_reg;
131 bus_space_tag_t mpu_bt;
132 bus_space_handle_t mpu_bh;
137 static u_int32_t cmi_fmt[] = {
138 SND_FORMAT(AFMT_U8, 1, 0),
139 SND_FORMAT(AFMT_U8, 2, 0),
140 SND_FORMAT(AFMT_S16_LE, 1, 0),
141 SND_FORMAT(AFMT_S16_LE, 2, 0),
145 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0};
147 /* ------------------------------------------------------------------------- */
148 /* Register Utilities */
151 cmi_rd(struct sc_info *sc, int regno, int size)
155 return bus_space_read_1(sc->st, sc->sh, regno);
157 return bus_space_read_2(sc->st, sc->sh, regno);
159 return bus_space_read_4(sc->st, sc->sh, regno);
161 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size));
167 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
171 bus_space_write_1(sc->st, sc->sh, regno, data);
174 bus_space_write_2(sc->st, sc->sh, regno, data);
177 bus_space_write_4(sc->st, sc->sh, regno, data);
183 cmi_partial_wr4(struct sc_info *sc,
184 int reg, int shift, u_int32_t mask, u_int32_t val)
188 r = cmi_rd(sc, reg, 4);
189 r &= ~(mask << shift);
191 cmi_wr(sc, reg, r, 4);
195 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask)
199 r = cmi_rd(sc, reg, 4);
201 cmi_wr(sc, reg, r, 4);
205 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask)
209 r = cmi_rd(sc, reg, 4);
211 cmi_wr(sc, reg, r, 4);
214 /* ------------------------------------------------------------------------- */
217 static int cmi_rates[] = {5512, 8000, 11025, 16000,
218 22050, 32000, 44100, 48000};
219 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0]))
221 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1
222 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */
225 cmpci_rate_to_regvalue(int rate)
229 for(i = 0; i < NUM_CMI_RATES - 1; i++) {
230 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) {
235 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i]));
237 r = ((i >> 1) | (i << 2)) & 0x07;
242 cmpci_regvalue_to_rate(u_int32_t r)
246 i = ((r << 1) | (r >> 2)) & 0x07;
247 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i));
251 /* ------------------------------------------------------------------------- */
252 /* ADC/DAC control - there are 2 dma channels on 8738, either can be
253 * playback or capture. We use ch0 for playback and ch1 for capture. */
256 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base)
260 ch->phys_buf = sndbuf_getbufaddr(ch->buffer);
262 cmi_wr(sc, base, ch->phys_buf, 4);
263 sz = (u_int32_t)sndbuf_getsize(ch->buffer);
265 s = sz / ch->bps - 1;
266 cmi_wr(sc, base + 4, s, 2);
268 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1;
269 cmi_wr(sc, base + 6, i, 2);
273 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch)
275 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
277 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
278 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
279 CMPCI_REG_CH0_INTR_ENABLE);
285 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch)
287 u_int32_t r = ch->dma_active;
289 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
290 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
291 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
292 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
298 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch)
300 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
301 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
302 /* Enable Interrupts */
303 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
304 CMPCI_REG_CH1_INTR_ENABLE);
305 DEB(printf("cmi_ch1_start: dma prog\n"));
310 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch)
312 u_int32_t r = ch->dma_active;
314 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
315 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
316 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
317 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
323 cmi_spdif_speed(struct sc_info *sc, int speed) {
324 u_int32_t fcr1, lcr, mcr;
326 if (speed >= 44100) {
327 fcr1 = CMPCI_REG_SPDIF0_ENABLE;
328 lcr = CMPCI_REG_XSPDIF_ENABLE;
329 mcr = (speed == 48000) ?
330 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0;
332 fcr1 = mcr = lcr = 0;
335 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0,
336 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr);
337 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0,
338 CMPCI_REG_SPDIF0_ENABLE, fcr1);
339 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0,
340 CMPCI_REG_XSPDIF_ENABLE, lcr);
343 /* ------------------------------------------------------------------------- */
344 /* Channel Interface implementation */
347 cmichan_init(kobj_t obj, void *devinfo,
348 struct snd_dbuf *b, struct pcm_channel *c, int dir)
350 struct sc_info *sc = devinfo;
351 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
356 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
357 ch->spd = DSP_DEFAULT_SPEED;
360 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
361 DEB(printf("cmichan_init failed\n"));
366 snd_mtxlock(sc->lock);
367 if (ch->dir == PCMDIR_PLAY) {
368 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
370 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
372 snd_mtxunlock(sc->lock);
378 cmichan_setformat(kobj_t obj, void *data, u_int32_t format)
380 struct sc_chinfo *ch = data;
381 struct sc_info *sc = ch->parent;
384 if (format & AFMT_S16_LE) {
385 f = CMPCI_REG_FORMAT_16BIT;
388 f = CMPCI_REG_FORMAT_8BIT;
392 if (AFMT_CHANNEL(format) > 1) {
393 f |= CMPCI_REG_FORMAT_STEREO;
396 f |= CMPCI_REG_FORMAT_MONO;
399 snd_mtxlock(sc->lock);
400 if (ch->dir == PCMDIR_PLAY) {
401 cmi_partial_wr4(ch->parent,
402 CMPCI_REG_CHANNEL_FORMAT,
403 CMPCI_REG_CH0_FORMAT_SHIFT,
404 CMPCI_REG_CH0_FORMAT_MASK,
407 cmi_partial_wr4(ch->parent,
408 CMPCI_REG_CHANNEL_FORMAT,
409 CMPCI_REG_CH1_FORMAT_SHIFT,
410 CMPCI_REG_CH1_FORMAT_MASK,
413 snd_mtxunlock(sc->lock);
420 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed)
422 struct sc_chinfo *ch = data;
423 struct sc_info *sc = ch->parent;
426 r = cmpci_rate_to_regvalue(speed);
427 snd_mtxlock(sc->lock);
428 if (ch->dir == PCMDIR_PLAY) {
430 /* disable if req before rate change */
431 cmi_spdif_speed(ch->parent, speed);
433 cmi_partial_wr4(ch->parent,
435 CMPCI_REG_DAC_FS_SHIFT,
436 CMPCI_REG_DAC_FS_MASK,
438 if (speed >= 44100 && ch->parent->spdif_enabled) {
439 /* enable if req after rate change */
440 cmi_spdif_speed(ch->parent, speed);
442 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
443 rsp >>= CMPCI_REG_DAC_FS_SHIFT;
444 rsp &= CMPCI_REG_DAC_FS_MASK;
446 cmi_partial_wr4(ch->parent,
448 CMPCI_REG_ADC_FS_SHIFT,
449 CMPCI_REG_ADC_FS_MASK,
451 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
452 rsp >>= CMPCI_REG_ADC_FS_SHIFT;
453 rsp &= CMPCI_REG_ADC_FS_MASK;
455 snd_mtxunlock(sc->lock);
456 ch->spd = cmpci_regvalue_to_rate(r);
458 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n",
459 (ch->dir == PCMDIR_PLAY) ? "play" : "rec",
460 speed, ch->spd, cmpci_regvalue_to_rate(rsp)));
466 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
468 struct sc_chinfo *ch = data;
469 struct sc_info *sc = ch->parent;
471 /* user has requested interrupts every blocksize bytes */
472 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) {
473 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER;
475 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize);
481 cmichan_trigger(kobj_t obj, void *data, int go)
483 struct sc_chinfo *ch = data;
484 struct sc_info *sc = ch->parent;
486 if (!PCMTRIG_COMMON(go))
489 snd_mtxlock(sc->lock);
490 if (ch->dir == PCMDIR_PLAY) {
493 cmi_ch0_start(sc, ch);
497 cmi_ch0_stop(sc, ch);
503 cmi_ch1_start(sc, ch);
507 cmi_ch1_stop(sc, ch);
511 snd_mtxunlock(sc->lock);
516 cmichan_getptr(kobj_t obj, void *data)
518 struct sc_chinfo *ch = data;
519 struct sc_info *sc = ch->parent;
520 u_int32_t physptr, bufptr, sz;
522 snd_mtxlock(sc->lock);
523 if (ch->dir == PCMDIR_PLAY) {
524 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4);
526 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4);
528 snd_mtxunlock(sc->lock);
530 sz = sndbuf_getsize(ch->buffer);
531 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz;
539 struct sc_info *sc = data;
543 snd_mtxlock(sc->lock);
544 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4);
545 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) {
547 if (intrstat & CMPCI_REG_CH0_INTR) {
548 toclear |= CMPCI_REG_CH0_INTR_ENABLE;
549 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
552 if (intrstat & CMPCI_REG_CH1_INTR) {
553 toclear |= CMPCI_REG_CH1_INTR_ENABLE;
554 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
558 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear);
559 snd_mtxunlock(sc->lock);
561 /* Signal interrupts to channel */
562 if (intrstat & CMPCI_REG_CH0_INTR) {
563 chn_intr(sc->pch.channel);
566 if (intrstat & CMPCI_REG_CH1_INTR) {
567 chn_intr(sc->rch.channel);
570 snd_mtxlock(sc->lock);
571 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear);
575 (sc->mpu_intr)(sc->mpu);
577 snd_mtxunlock(sc->lock);
581 static struct pcmchan_caps *
582 cmichan_getcaps(kobj_t obj, void *data)
587 static kobj_method_t cmichan_methods[] = {
588 KOBJMETHOD(channel_init, cmichan_init),
589 KOBJMETHOD(channel_setformat, cmichan_setformat),
590 KOBJMETHOD(channel_setspeed, cmichan_setspeed),
591 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize),
592 KOBJMETHOD(channel_trigger, cmichan_trigger),
593 KOBJMETHOD(channel_getptr, cmichan_getptr),
594 KOBJMETHOD(channel_getcaps, cmichan_getcaps),
597 CHANNEL_DECLARE(cmichan);
599 /* ------------------------------------------------------------------------- */
600 /* Mixer - sb16 with kinks */
603 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val)
605 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
606 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1);
610 cmimix_rd(struct sc_info *sc, u_int8_t port)
612 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
613 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1);
617 u_int8_t rreg; /* right reg chan register */
618 u_int8_t stereo:1; /* (no explanation needed, honest) */
619 u_int8_t rec:1; /* recording source */
620 u_int8_t bits:3; /* num bits to represent maximum gain rep */
621 u_int8_t oselect; /* output select mask */
622 u_int8_t iselect; /* right input select mask */
623 } static const cmt[SOUND_MIXER_NRDEVICES] = {
624 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5,
625 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R},
626 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5,
627 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R},
628 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5,
629 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R},
630 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5,
631 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC},
632 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0},
633 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0},
634 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0},
635 /* These controls are not implemented in CMI8738, but maybe at a
636 future date. They are not documented in C-Media documentation,
637 though appear in other drivers for future h/w (ALSA, Linux, NetBSD).
639 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0},
640 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0},
641 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0},
642 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0},
643 /* The mic pre-amp is implemented with non-SB16 compatible
645 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0},
648 #define MIXER_GAIN_REG_RTOL(r) (r - 1)
651 cmimix_init(struct snd_mixer *m)
653 struct sc_info *sc = mix_getdevinfo(m);
656 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
657 if (cmt[i].bits) v |= 1 << i;
661 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
662 if (cmt[i].rec) v |= 1 << i;
664 mix_setrecdevs(m, v);
666 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0);
667 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
668 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
669 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX,
670 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
675 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
677 struct sc_info *sc = mix_getdevinfo(m);
681 max = (1 << cmt[dev].bits) - 1;
683 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) {
684 /* For time being this can only be one thing (mic in
686 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0;
687 l = left * max / 100;
688 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */
689 v |= ((l << 1) | (~l >> 3)) & 0x0f;
690 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1);
694 l = (left * max / 100) << (8 - cmt[dev].bits);
695 if (cmt[dev].stereo) {
696 r = (right * max / 100) << (8 - cmt[dev].bits);
697 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l);
698 cmimix_wr(sc, cmt[dev].rreg, r);
699 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\
700 "value 0x%02x:0x%02x\n",
701 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r));
704 cmimix_wr(sc, cmt[dev].rreg, l);
705 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \
706 "value 0x%02x:0x%02x\n",
707 dev, cmt[dev].rreg, l, l));
710 /* Zero gain does not mute channel from output, but this does... */
711 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX);
712 if (l == 0 && r == 0) {
713 v &= ~cmt[dev].oselect;
715 v |= cmt[dev].oselect;
717 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v);
723 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src)
725 struct sc_info *sc = mix_getdevinfo(m);
729 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
732 sl |= cmt[i].iselect;
734 ml |= cmt[i].iselect;
738 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml);
739 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
740 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml));
741 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml);
742 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml);
743 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
744 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml));
749 /* Optional SPDIF support. */
752 cmi_initsys(struct sc_info* sc)
754 /* XXX: an user should be able to set this with a control tool,
755 if not done before 7.0-RELEASE, this needs to be converted
756 to a device specific sysctl "dev.pcm.X.yyy" via
757 device_get_sysctl_*() as discussed on multimedia@ in msg-id
758 <861wujij2q.fsf@xps.des.no> */
759 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev),
760 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
761 OID_AUTO, "spdif_enabled", CTLFLAG_RW,
762 &sc->spdif_enabled, 0,
763 "enable SPDIF output at 44.1 kHz and above");
768 /* ------------------------------------------------------------------------- */
769 static kobj_method_t cmi_mixer_methods[] = {
770 KOBJMETHOD(mixer_init, cmimix_init),
771 KOBJMETHOD(mixer_set, cmimix_set),
772 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc),
775 MIXER_DECLARE(cmi_mixer);
782 cmi_mread(struct mpu401 *arg, void *sc, int reg)
786 d = bus_space_read_1(0,0, 0x330 + reg);
787 /* printf("cmi_mread: reg %x %x\n",reg, d);
793 cmi_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b)
796 bus_space_write_1(0,0,0x330 + reg , b);
800 cmi_muninit(struct mpu401 *arg, void *cookie)
802 struct sc_info *sc = cookie;
804 snd_mtxlock(sc->lock);
807 snd_mtxunlock(sc->lock);
812 static kobj_method_t cmi_mpu_methods[] = {
813 KOBJMETHOD(mpufoi_read, cmi_mread),
814 KOBJMETHOD(mpufoi_write, cmi_mwrite),
815 KOBJMETHOD(mpufoi_uninit, cmi_muninit),
819 static DEFINE_CLASS(cmi_mpu, cmi_mpu_methods, 0);
822 cmi_midiattach(struct sc_info *sc) {
832 Notes, CMPCI_REG_VMPUSEL sets the io port for the mpu. Does
833 anyone know how to bus_space tag?
835 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
836 cmi_clr4(sc, CMPCI_REG_LEGACY_CTRL,
837 CMPCI_REG_VMPUSEL_MASK << CMPCI_REG_VMPUSEL_SHIFT);
838 cmi_set4(sc, CMPCI_REG_LEGACY_CTRL,
839 0 << CMPCI_REG_VMPUSEL_SHIFT );
840 cmi_set4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
841 sc->mpu = mpu401_init(&cmi_mpu_class, sc, cmi_intr, &sc->mpu_intr);
844 /* ------------------------------------------------------------------------- */
845 /* Power and reset */
848 cmi_power(struct sc_info *sc, int state)
851 case 0: /* full power */
852 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
856 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
862 cmi_init(struct sc_info *sc)
865 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
867 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
869 /* Disable interrupts and channels */
870 cmi_clr4(sc, CMPCI_REG_FUNC_0,
871 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
872 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
873 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE);
875 /* Configure DMA channels, ch0 = play, ch1 = capture */
876 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR);
877 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR);
879 /* Attempt to enable 4 Channel output */
880 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D);
882 /* Disable SPDIF1 - not compatible with config */
883 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE);
884 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
890 cmi_uninit(struct sc_info *sc)
892 /* Disable interrupts and channels */
893 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
894 CMPCI_REG_CH0_INTR_ENABLE |
895 CMPCI_REG_CH1_INTR_ENABLE |
896 CMPCI_REG_TDMA_INTR_ENABLE);
897 cmi_clr4(sc, CMPCI_REG_FUNC_0,
898 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
899 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
905 /* ------------------------------------------------------------------------- */
906 /* Bus and device registration */
908 cmi_probe(device_t dev)
910 switch(pci_get_devid(dev)) {
911 case CMI8338A_PCI_ID:
912 device_set_desc(dev, "CMedia CMI8338A");
913 return BUS_PROBE_DEFAULT;
914 case CMI8338B_PCI_ID:
915 device_set_desc(dev, "CMedia CMI8338B");
916 return BUS_PROBE_DEFAULT;
918 device_set_desc(dev, "CMedia CMI8738");
919 return BUS_PROBE_DEFAULT;
920 case CMI8738B_PCI_ID:
921 device_set_desc(dev, "CMedia CMI8738B");
922 return BUS_PROBE_DEFAULT;
924 device_set_desc(dev, "CMedia CMI120");
925 return BUS_PROBE_DEFAULT;
932 cmi_attach(device_t dev)
935 char status[SND_STATUSLEN];
937 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
938 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_cmi softc");
939 pci_enable_busmaster(dev);
942 sc->regid = PCIR_BAR(0);
943 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid,
946 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n");
949 sc->st = rman_get_bustag(sc->reg);
950 sc->sh = rman_get_bushandle(sc->reg);
956 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
957 RF_ACTIVE | RF_SHAREABLE);
959 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) {
960 device_printf(dev, "cmi_attach: Unable to map interrupt\n");
964 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536);
966 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
968 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
969 /*highaddr*/BUS_SPACE_MAXADDR,
970 /*filter*/NULL, /*filterarg*/NULL,
971 /*maxsize*/sc->bufsz, /*nsegments*/1,
972 /*maxsegz*/0x3ffff, /*flags*/0,
975 &sc->parent_dmat) != 0) {
976 device_printf(dev, "cmi_attach: Unable to create dma tag\n");
984 if (mixer_init(dev, &cmi_mixer_class, sc))
987 if (pcm_register(dev, sc, 1, 1))
992 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc);
993 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc);
995 snprintf(status, SND_STATUSLEN, "at io 0x%jx irq %jd %s",
996 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi));
997 pcm_setstatus(dev, status);
999 DEB(printf("cmi_attach: succeeded\n"));
1003 if (sc->parent_dmat)
1004 bus_dma_tag_destroy(sc->parent_dmat);
1006 bus_teardown_intr(dev, sc->irq, sc->ih);
1008 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1010 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
1012 snd_mtxfree(sc->lock);
1020 cmi_detach(device_t dev)
1025 r = pcm_unregister(dev);
1028 sc = pcm_getdevinfo(dev);
1032 bus_dma_tag_destroy(sc->parent_dmat);
1033 bus_teardown_intr(dev, sc->irq, sc->ih);
1034 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1036 mpu401_uninit(sc->mpu);
1037 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
1039 bus_release_resource(dev, SYS_RES_IOPORT, sc->mpu_regid, sc->mpu_reg);
1041 snd_mtxfree(sc->lock);
1048 cmi_suspend(device_t dev)
1050 struct sc_info *sc = pcm_getdevinfo(dev);
1052 snd_mtxlock(sc->lock);
1053 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch);
1054 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch);
1056 snd_mtxunlock(sc->lock);
1061 cmi_resume(device_t dev)
1063 struct sc_info *sc = pcm_getdevinfo(dev);
1065 snd_mtxlock(sc->lock);
1067 if (cmi_init(sc) != 0) {
1068 device_printf(dev, "unable to reinitialize the card\n");
1069 snd_mtxunlock(sc->lock);
1073 if (mixer_reinit(dev) == -1) {
1074 device_printf(dev, "unable to reinitialize the mixer\n");
1075 snd_mtxunlock(sc->lock);
1079 if (sc->pch.dma_was_active) {
1080 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd);
1081 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt);
1082 cmi_ch0_start(sc, &sc->pch);
1085 if (sc->rch.dma_was_active) {
1086 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd);
1087 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt);
1088 cmi_ch1_start(sc, &sc->rch);
1090 snd_mtxunlock(sc->lock);
1094 static device_method_t cmi_methods[] = {
1095 DEVMETHOD(device_probe, cmi_probe),
1096 DEVMETHOD(device_attach, cmi_attach),
1097 DEVMETHOD(device_detach, cmi_detach),
1098 DEVMETHOD(device_resume, cmi_resume),
1099 DEVMETHOD(device_suspend, cmi_suspend),
1103 static driver_t cmi_driver = {
1109 DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, 0, 0);
1110 MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1111 MODULE_DEPEND(snd_cmi, midi, 1,1,1);
1112 MODULE_VERSION(snd_cmi, 1);