2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1999 Seigo Tanimura
7 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in
8 * cwcealdr1.zip, the sample sources by Crystal Semiconductor.
9 * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <machine/resource.h>
40 #include <machine/bus.h>
43 #ifdef HAVE_KERNEL_OPTION_HEADERS
47 #include <dev/sound/pcm/sound.h>
48 #include <dev/sound/chip.h>
49 #include <dev/sound/pci/csareg.h>
50 #include <dev/sound/pci/csavar.h>
52 #include <dev/pci/pcireg.h>
53 #include <dev/pci/pcivar.h>
55 #include <dev/sound/pci/cs461x_dsp.h>
57 SND_DECLARE_FILE("$FreeBSD$");
59 /* This is the pci device id. */
60 #define CS4610_PCI_ID 0x60011013
61 #define CS4614_PCI_ID 0x60031013
62 #define CS4615_PCI_ID 0x60041013
64 /* Here is the parameter structure per a device. */
66 device_t dev; /* device */
67 csa_res res; /* resources */
69 device_t pcm; /* pcm device */
70 driver_intr_t* pcmintr; /* pcm intr */
71 void *pcmintr_arg; /* pcm intr arg */
72 device_t midi; /* midi device */
73 driver_intr_t* midiintr; /* midi intr */
74 void *midiintr_arg; /* midi intr arg */
75 void *ih; /* cookie */
77 struct csa_card *card;
78 struct csa_bridgeinfo binfo; /* The state of this bridge. */
81 typedef struct csa_softc *sc_p;
83 static int csa_probe(device_t dev);
84 static int csa_attach(device_t dev);
85 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
86 rman_res_t start, rman_res_t end,
87 rman_res_t count, u_int flags);
88 static int csa_release_resource(device_t bus, device_t child, int type, int rid,
90 static int csa_setup_intr(device_t bus, device_t child,
91 struct resource *irq, int flags,
92 driver_filter_t *filter,
93 driver_intr_t *intr, void *arg, void **cookiep);
94 static int csa_teardown_intr(device_t bus, device_t child,
95 struct resource *irq, void *cookie);
96 static driver_intr_t csa_intr;
97 static int csa_initialize(sc_p scp);
98 static int csa_downloadimage(csa_res *resp);
99 static int csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len);
101 static devclass_t csa_devclass;
117 devclass_t pci_devclass;
118 device_t *pci_devices, *pci_children, *busp, *childp;
119 int pci_count = 0, pci_childcount = 0;
122 bus_space_tag_t btag;
124 if ((pci_devclass = devclass_find("pci")) == NULL) {
128 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
130 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
132 if (device_get_children(*busp, &pci_children, &pci_childcount))
134 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) {
135 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) {
136 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10;
138 btag = X86_BUS_SPACE_IO;
140 control = bus_space_read_2(btag, 0x0, port);
142 control |= run? 0 : 0x2000;
143 bus_space_write_2(btag, 0x0, port, control);
144 free(pci_devices, M_TEMP);
145 free(pci_children, M_TEMP);
149 free(pci_children, M_TEMP);
152 free(pci_devices, M_TEMP);
159 static struct csa_card cards_4610[] = {
160 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0},
163 static struct csa_card cards_4614[] = {
164 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0},
165 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1},
166 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0},
167 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
168 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
169 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0},
170 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0},
171 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0},
172 {0x153b, 0x1136, "Terratec SiXPack 5.1+", NULL, NULL, NULL, 0},
173 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0},
176 static struct csa_card cards_4615[] = {
177 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0},
180 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0};
185 struct csa_card *cards;
188 static struct card_type cards[] = {
189 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610},
190 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614},
191 {CS4615_PCI_ID, "CS4615", cards_4615},
195 static struct card_type *
196 csa_findcard(device_t dev)
201 while (cards[i].devid != 0) {
202 if (pci_get_devid(dev) == cards[i].devid)
210 csa_findsubcard(device_t dev)
213 struct card_type *card;
214 struct csa_card *subcard;
216 card = csa_findcard(dev);
219 subcard = card->cards;
221 while (subcard[i].subvendor != 0) {
222 if (pci_get_subvendor(dev) == subcard[i].subvendor
223 && pci_get_subdevice(dev) == subcard[i].subdevice) {
232 csa_probe(device_t dev)
234 struct card_type *card;
236 card = csa_findcard(dev);
238 device_set_desc(dev, card->name);
239 return BUS_PROBE_DEFAULT;
245 csa_attach(device_t dev)
249 struct sndcard_func *func;
252 scp = device_get_softc(dev);
254 /* Fill in the softc. */
255 bzero(scp, sizeof(*scp));
258 pci_enable_busmaster(dev);
260 /* Allocate the resources. */
262 scp->card = csa_findsubcard(dev);
263 scp->binfo.card = scp->card;
264 printf("csa: card is %s\n", scp->card->name);
265 resp->io_rid = PCIR_BAR(0);
266 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
267 &resp->io_rid, RF_ACTIVE);
268 if (resp->io == NULL)
270 resp->mem_rid = PCIR_BAR(1);
271 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
272 &resp->mem_rid, RF_ACTIVE);
273 if (resp->mem == NULL)
276 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
277 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE);
278 if (resp->irq == NULL)
281 /* Enable interrupt. */
282 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih))
285 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
286 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
289 /* Initialize the chip. */
290 if (csa_initialize(scp))
293 /* Reset the Processor. */
296 /* Download the Processor Image to the processor. */
297 if (csa_downloadimage(resp))
300 /* Attach the children. */
303 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
308 func->varinfo = &scp->binfo;
309 func->func = SCF_PCM;
310 scp->pcm = device_add_child(dev, "pcm", -1);
311 device_set_ivars(scp->pcm, func);
314 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
319 func->varinfo = &scp->binfo;
320 func->func = SCF_MIDI;
321 scp->midi = device_add_child(dev, "midi", -1);
322 device_set_ivars(scp->midi, func);
324 bus_generic_attach(dev);
329 bus_teardown_intr(dev, resp->irq, scp->ih);
331 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
333 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
335 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
340 csa_detach(device_t dev)
344 struct sndcard_func *func;
347 scp = device_get_softc(dev);
350 if (scp->midi != NULL) {
351 func = device_get_ivars(scp->midi);
352 err = device_delete_child(dev, scp->midi);
356 free(func, M_DEVBUF);
360 if (scp->pcm != NULL) {
361 func = device_get_ivars(scp->pcm);
362 err = device_delete_child(dev, scp->pcm);
366 free(func, M_DEVBUF);
370 bus_teardown_intr(dev, resp->irq, scp->ih);
371 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
372 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
373 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
375 return bus_generic_detach(dev);
379 csa_resume(device_t dev)
384 scp = device_get_softc(dev);
387 /* Initialize the chip. */
388 if (csa_initialize(scp))
391 /* Reset the Processor. */
394 /* Download the Processor Image to the processor. */
395 if (csa_downloadimage(resp))
398 return (bus_generic_resume(dev));
401 static struct resource *
402 csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
403 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
407 struct resource *res;
409 scp = device_get_softc(bus);
437 csa_release_resource(device_t bus, device_t child, int type, int rid,
444 * The following three functions deal with interrupt handling.
445 * An interrupt is primarily handled by the bridge driver.
446 * The bridge driver then determines the child devices to pass
447 * the interrupt. Certain information of the device can be read
448 * only once(eg the value of HISR). The bridge driver is responsible
449 * to pass such the information to the children.
453 csa_setup_intr(device_t bus, device_t child,
454 struct resource *irq, int flags,
455 driver_filter_t *filter,
456 driver_intr_t *intr, void *arg, void **cookiep)
460 struct sndcard_func *func;
462 if (filter != NULL) {
463 printf("ata-csa.c: we cannot use a filter here\n");
466 scp = device_get_softc(bus);
470 * Look at the function code of the child to determine
471 * the appropriate hander for it.
473 func = device_get_ivars(child);
474 if (func == NULL || irq != resp->irq)
477 switch (func->func) {
480 scp->pcmintr_arg = arg;
484 scp->midiintr = intr;
485 scp->midiintr_arg = arg;
492 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
493 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
499 csa_teardown_intr(device_t bus, device_t child,
500 struct resource *irq, void *cookie)
504 struct sndcard_func *func;
506 scp = device_get_softc(bus);
510 * Look at the function code of the child to determine
511 * the appropriate hander for it.
513 func = device_get_ivars(child);
514 if (func == NULL || irq != resp->irq || cookie != scp)
517 switch (func->func) {
520 scp->pcmintr_arg = NULL;
524 scp->midiintr = NULL;
525 scp->midiintr_arg = NULL;
535 /* The interrupt handler */
545 /* Is this interrupt for us? */
546 hisr = csa_readio(resp, BA0_HISR);
547 if ((hisr & 0x7fffffff) == 0) {
549 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
554 * Pass the value of HISR via struct csa_bridgeinfo.
555 * The children get access through their ivars.
557 scp->binfo.hisr = hisr;
559 /* Invoke the handlers of the children. */
560 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) {
561 scp->pcmintr(scp->pcmintr_arg);
562 hisr &= ~(HISR_VC0 | HISR_VC1);
564 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) {
565 scp->midiintr(scp->midiintr_arg);
570 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
574 csa_initialize(sc_p scp)
577 u_int32_t acsts, acisv;
583 * First, blast the clock control register to zero so that the PLL starts
584 * out in a known state, and blast the master serial port control register
585 * to zero so that the serial ports also start out in a known state.
587 csa_writeio(resp, BA0_CLKCR1, 0);
588 csa_writeio(resp, BA0_SERMC1, 0);
591 * If we are in AC97 mode, then we must set the part to a host controlled
592 * AC-link. Otherwise, we won't be able to bring up the link.
595 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */
597 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */
601 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
602 * spec) and then drive it high. This is done for non AC97 modes since
603 * there might be logic external to the CS461x that uses the ARST# line
606 csa_writeio(resp, BA0_ACCTL, 1);
608 csa_writeio(resp, BA0_ACCTL, 0);
610 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
613 * The first thing we do here is to enable sync generation. As soon
614 * as we start receiving bit clock, we'll start producing the SYNC
617 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
620 * Now wait for a short while to allow the AC97 part to start
621 * generating bit clock (so we don't try to start the PLL without an
627 * Set the serial port timing configuration, so that
628 * the clock control circuit gets its clock from the correct place.
630 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97);
634 * Write the selected clock control setup to the hardware. Do not turn on
635 * SWCE yet (if requested), so that the devices clocked by the output of
636 * PLL are not clocked until the PLL is stable.
638 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
639 csa_writeio(resp, BA0_PLLM, 0x3a);
640 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8);
645 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP);
648 * Wait until the PLL has stabilized.
653 * Turn on clocking of the core so that we can setup the serial ports.
655 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE);
658 * Fill the serial port FIFOs with silence.
660 csa_clearserialfifos(resp);
663 * Set the serial port FIFO pointer to the first sample in the FIFO.
666 csa_writeio(resp, BA0_SERBSP, 0);
670 * Write the serial port configuration to the part. The master
671 * enable bit is not set until all other values have been written.
673 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
674 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
675 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
678 * Wait for the codec ready signal from the AC97 codec.
681 for (i = 0 ; i < 1000 ; i++) {
683 * First, lets wait a short while to let things settle out a bit,
684 * and to prevent retrying the read too quickly.
689 * Read the AC97 status register to see if we've seen a CODEC READY
690 * signal from the AC97 codec.
692 acsts = csa_readio(resp, BA0_ACSTS);
693 if ((acsts & ACSTS_CRDY) != 0)
698 * Make sure we sampled CODEC READY.
700 if ((acsts & ACSTS_CRDY) == 0)
704 * Assert the vaid frame signal so that we can start sending commands
707 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
710 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
711 * the codec is pumping ADC data across the AC-link.
714 for (i = 0 ; i < 2000 ; i++) {
716 * First, lets wait a short while to let things settle out a bit,
717 * and to prevent retrying the read too quickly.
720 DELAY(10000000L); /* clw */
725 * Read the input slot valid register and see if input slots 3 and
728 acisv = csa_readio(resp, BA0_ACISV);
729 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
733 * Make sure we sampled valid input slots 3 and 4. If not, then return
736 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
740 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
741 * commense the transfer of digital audio data to the AC97 codec.
743 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
746 * Power down the DAC and ADC. We will power them up (if) when we need
750 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300);
754 * Turn off the Processor by turning off the software clock enable flag in
755 * the clock control register.
758 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE;
759 csa_writeio(resp, BA0_CLKCR1, clkcr1);
763 * Enable interrupts on the part.
766 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
773 csa_clearserialfifos(csa_res *resp)
776 u_int8_t clkcr1, serbst;
779 * See if the devices are powered down. If so, we must power them up first
780 * or they will not respond.
783 clkcr1 = csa_readio(resp, BA0_CLKCR1);
784 if ((clkcr1 & CLKCR1_SWCE) == 0) {
785 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE);
790 * We want to clear out the serial port FIFOs so we don't end up playing
791 * whatever random garbage happens to be in them. We fill the sample FIFOs
792 * with zero (silence).
794 csa_writeio(resp, BA0_SERBWP, 0);
796 /* Fill all 256 sample FIFO locations. */
798 for (i = 0 ; i < 256 ; i++) {
799 /* Make sure the previous FIFO write operation has completed. */
800 for (j = 0 ; j < 5 ; j++) {
802 serbst = csa_readio(resp, BA0_SERBST);
803 if ((serbst & SERBST_WBSY) == 0)
806 if ((serbst & SERBST_WBSY) != 0) {
808 csa_writeio(resp, BA0_CLKCR1, clkcr1);
810 /* Write the serial port FIFO index. */
811 csa_writeio(resp, BA0_SERBAD, i);
812 /* Tell the serial port to load the new value into the FIFO location. */
813 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC);
816 * Now, if we powered up the devices, then power them back down again.
817 * This is kinda ugly, but should never happen.
820 csa_writeio(resp, BA0_CLKCR1, clkcr1);
824 csa_resetdsp(csa_res *resp)
829 * Write the reset bit of the SP control register.
831 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP);
834 * Write the control register.
836 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN);
839 * Clear the trap registers.
841 for (i = 0 ; i < 8 ; i++) {
842 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i);
843 csa_writemem(resp, BA1_TWPR, 0xffff);
845 csa_writemem(resp, BA1_DREG, 0);
848 * Set the frame timer to reflect the number of cycles per frame.
850 csa_writemem(resp, BA1_FRMT, 0xadf);
854 csa_downloadimage(csa_res *resp)
859 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) {
861 * DMA this block from host memory to the appropriate
862 * memory on the CSDevice.
864 ret = csa_transferimage(resp,
865 cs461x_firmware.BA1Array + offset,
866 cs461x_firmware.MemoryStat[ul].ulDestAddr,
867 cs461x_firmware.MemoryStat[ul].ulSourceSize);
870 offset += cs461x_firmware.MemoryStat[ul].ulSourceSize >> 2;
876 csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len)
881 * We do not allow DMAs from host memory to host memory (although the DMA
882 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes
883 * in size (because that DMA can not do that). Return an error if either
884 * of these conditions exist.
886 if ((len & 0x3) != 0)
889 /* Check the destination address that it is a multiple of 4 */
890 if ((dest & 0x3) != 0)
893 /* Write the buffer out. */
894 for (ul = 0 ; ul < len ; ul += 4)
895 csa_writemem(resp, dest + ul, src[ul >> 2]);
900 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data)
903 u_int32_t acctl, acsts;
906 * Make sure that there is not data sitting around from a previous
907 * uncompleted access. ACSDA = Status Data Register = 47Ch
909 csa_readio(resp, BA0_ACSDA);
912 * Setup the AC97 control registers on the CS461x to send the
913 * appropriate command to the AC97 to perform the read.
914 * ACCAD = Command Address Register = 46Ch
915 * ACCDA = Command Data Register = 470h
916 * ACCTL = Control Register = 460h
917 * set DCV - will clear when process completed
918 * set CRW - Read command
919 * set VFRM - valid frame enabled
920 * set ESYN - ASYNC generation enabled
921 * set RSTN - ARST# inactive, AC97 codec not reset
925 * Get the actual AC97 register from the offset
927 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
928 csa_writeio(resp, BA0_ACCDA, 0);
929 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
932 * Wait for the read to occur.
935 for (i = 0 ; i < 10 ; i++) {
937 * First, we want to wait for a short time.
942 * Now, check to see if the read has completed.
943 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
945 acctl = csa_readio(resp, BA0_ACCTL);
946 if ((acctl & ACCTL_DCV) == 0)
951 * Make sure the read completed.
953 if ((acctl & ACCTL_DCV) != 0)
957 * Wait for the valid status bit to go active.
960 for (i = 0 ; i < 10 ; i++) {
962 * Read the AC97 status register.
963 * ACSTS = Status Register = 464h
965 acsts = csa_readio(resp, BA0_ACSTS);
967 * See if we have valid status.
968 * VSTS - Valid Status
970 if ((acsts & ACSTS_VSTS) != 0)
973 * Wait for a short while.
979 * Make sure we got valid status.
981 if ((acsts & ACSTS_VSTS) == 0)
985 * Read the data returned from the AC97 register.
986 * ACSDA = Status Data Register = 474h
988 *data = csa_readio(resp, BA0_ACSDA);
994 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data)
1000 * Setup the AC97 control registers on the CS461x to send the
1001 * appropriate command to the AC97 to perform the write.
1002 * ACCAD = Command Address Register = 46Ch
1003 * ACCDA = Command Data Register = 470h
1004 * ACCTL = Control Register = 460h
1005 * set DCV - will clear when process completed
1006 * set VFRM - valid frame enabled
1007 * set ESYN - ASYNC generation enabled
1008 * set RSTN - ARST# inactive, AC97 codec not reset
1012 * Get the actual AC97 register from the offset
1014 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
1015 csa_writeio(resp, BA0_ACCDA, data);
1016 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
1019 * Wait for the write to occur.
1022 for (i = 0 ; i < 10 ; i++) {
1024 * First, we want to wait for a short time.
1029 * Now, check to see if the read has completed.
1030 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
1032 acctl = csa_readio(resp, BA0_ACCTL);
1033 if ((acctl & ACCTL_DCV) == 0)
1038 * Make sure the write completed.
1040 if ((acctl & ACCTL_DCV) != 0)
1047 csa_readio(csa_res *resp, u_long offset)
1051 if (offset < BA0_AC97_RESET)
1052 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff;
1054 if (csa_readcodec(resp, offset, &ul))
1061 csa_writeio(csa_res *resp, u_long offset, u_int32_t data)
1063 if (offset < BA0_AC97_RESET)
1064 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data);
1066 csa_writecodec(resp, offset, data);
1070 csa_readmem(csa_res *resp, u_long offset)
1072 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset);
1076 csa_writemem(csa_res *resp, u_long offset, u_int32_t data)
1078 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data);
1081 static device_method_t csa_methods[] = {
1082 /* Device interface */
1083 DEVMETHOD(device_probe, csa_probe),
1084 DEVMETHOD(device_attach, csa_attach),
1085 DEVMETHOD(device_detach, csa_detach),
1086 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1087 DEVMETHOD(device_suspend, bus_generic_suspend),
1088 DEVMETHOD(device_resume, csa_resume),
1091 DEVMETHOD(bus_alloc_resource, csa_alloc_resource),
1092 DEVMETHOD(bus_release_resource, csa_release_resource),
1093 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1094 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1095 DEVMETHOD(bus_setup_intr, csa_setup_intr),
1096 DEVMETHOD(bus_teardown_intr, csa_teardown_intr),
1101 static driver_t csa_driver = {
1104 sizeof(struct csa_softc),
1108 * csa can be attached to a pci bus.
1110 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0);
1111 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1112 MODULE_VERSION(snd_csa, 1);