2 * Copyright (c) 1999 Seigo Tanimura
5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in
6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor.
7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <machine/resource.h>
38 #include <machine/bus.h>
41 #ifdef HAVE_KERNEL_OPTION_HEADERS
45 #include <dev/sound/pcm/sound.h>
46 #include <dev/sound/chip.h>
47 #include <dev/sound/pci/csareg.h>
48 #include <dev/sound/pci/csavar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
53 #include <dev/sound/pci/cs461x_dsp.h>
55 SND_DECLARE_FILE("$FreeBSD$");
57 /* This is the pci device id. */
58 #define CS4610_PCI_ID 0x60011013
59 #define CS4614_PCI_ID 0x60031013
60 #define CS4615_PCI_ID 0x60041013
62 /* Here is the parameter structure per a device. */
64 device_t dev; /* device */
65 csa_res res; /* resources */
67 device_t pcm; /* pcm device */
68 driver_intr_t* pcmintr; /* pcm intr */
69 void *pcmintr_arg; /* pcm intr arg */
70 device_t midi; /* midi device */
71 driver_intr_t* midiintr; /* midi intr */
72 void *midiintr_arg; /* midi intr arg */
73 void *ih; /* cookie */
75 struct csa_card *card;
76 struct csa_bridgeinfo binfo; /* The state of this bridge. */
79 typedef struct csa_softc *sc_p;
81 static int csa_probe(device_t dev);
82 static int csa_attach(device_t dev);
83 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
84 rman_res_t start, rman_res_t end,
85 rman_res_t count, u_int flags);
86 static int csa_release_resource(device_t bus, device_t child, int type, int rid,
88 static int csa_setup_intr(device_t bus, device_t child,
89 struct resource *irq, int flags,
90 driver_filter_t *filter,
91 driver_intr_t *intr, void *arg, void **cookiep);
92 static int csa_teardown_intr(device_t bus, device_t child,
93 struct resource *irq, void *cookie);
94 static driver_intr_t csa_intr;
95 static int csa_initialize(sc_p scp);
96 static int csa_downloadimage(csa_res *resp);
97 static int csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len);
99 static devclass_t csa_devclass;
115 devclass_t pci_devclass;
116 device_t *pci_devices, *pci_children, *busp, *childp;
117 int pci_count = 0, pci_childcount = 0;
120 bus_space_tag_t btag;
122 if ((pci_devclass = devclass_find("pci")) == NULL) {
126 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
128 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
130 if (device_get_children(*busp, &pci_children, &pci_childcount))
132 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) {
133 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) {
134 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10;
136 btag = X86_BUS_SPACE_IO;
138 control = bus_space_read_2(btag, 0x0, port);
140 control |= run? 0 : 0x2000;
141 bus_space_write_2(btag, 0x0, port, control);
142 free(pci_devices, M_TEMP);
143 free(pci_children, M_TEMP);
147 free(pci_children, M_TEMP);
150 free(pci_devices, M_TEMP);
157 static struct csa_card cards_4610[] = {
158 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0},
161 static struct csa_card cards_4614[] = {
162 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0},
163 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1},
164 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0},
165 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
166 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
167 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0},
168 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0},
169 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0},
170 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0},
173 static struct csa_card cards_4615[] = {
174 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0},
177 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0};
182 struct csa_card *cards;
185 static struct card_type cards[] = {
186 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610},
187 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614},
188 {CS4615_PCI_ID, "CS4615", cards_4615},
192 static struct card_type *
193 csa_findcard(device_t dev)
198 while (cards[i].devid != 0) {
199 if (pci_get_devid(dev) == cards[i].devid)
207 csa_findsubcard(device_t dev)
210 struct card_type *card;
211 struct csa_card *subcard;
213 card = csa_findcard(dev);
216 subcard = card->cards;
218 while (subcard[i].subvendor != 0) {
219 if (pci_get_subvendor(dev) == subcard[i].subvendor
220 && pci_get_subdevice(dev) == subcard[i].subdevice) {
229 csa_probe(device_t dev)
231 struct card_type *card;
233 card = csa_findcard(dev);
235 device_set_desc(dev, card->name);
236 return BUS_PROBE_DEFAULT;
242 csa_attach(device_t dev)
246 struct sndcard_func *func;
249 scp = device_get_softc(dev);
251 /* Fill in the softc. */
252 bzero(scp, sizeof(*scp));
255 pci_enable_busmaster(dev);
257 /* Allocate the resources. */
259 scp->card = csa_findsubcard(dev);
260 scp->binfo.card = scp->card;
261 printf("csa: card is %s\n", scp->card->name);
262 resp->io_rid = PCIR_BAR(0);
263 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
264 &resp->io_rid, RF_ACTIVE);
265 if (resp->io == NULL)
267 resp->mem_rid = PCIR_BAR(1);
268 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
269 &resp->mem_rid, RF_ACTIVE);
270 if (resp->mem == NULL)
273 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
274 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE);
275 if (resp->irq == NULL)
278 /* Enable interrupt. */
279 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih))
282 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
283 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
286 /* Initialize the chip. */
287 if (csa_initialize(scp))
290 /* Reset the Processor. */
293 /* Download the Processor Image to the processor. */
294 if (csa_downloadimage(resp))
297 /* Attach the children. */
300 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
305 func->varinfo = &scp->binfo;
306 func->func = SCF_PCM;
307 scp->pcm = device_add_child(dev, "pcm", -1);
308 device_set_ivars(scp->pcm, func);
311 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
316 func->varinfo = &scp->binfo;
317 func->func = SCF_MIDI;
318 scp->midi = device_add_child(dev, "midi", -1);
319 device_set_ivars(scp->midi, func);
321 bus_generic_attach(dev);
326 bus_teardown_intr(dev, resp->irq, scp->ih);
328 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
330 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
332 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
337 csa_detach(device_t dev)
341 struct sndcard_func *func;
344 scp = device_get_softc(dev);
347 if (scp->midi != NULL) {
348 func = device_get_ivars(scp->midi);
349 err = device_delete_child(dev, scp->midi);
353 free(func, M_DEVBUF);
357 if (scp->pcm != NULL) {
358 func = device_get_ivars(scp->pcm);
359 err = device_delete_child(dev, scp->pcm);
363 free(func, M_DEVBUF);
367 bus_teardown_intr(dev, resp->irq, scp->ih);
368 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
369 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
370 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
372 return bus_generic_detach(dev);
376 csa_resume(device_t dev)
381 scp = device_get_softc(dev);
384 /* Initialize the chip. */
385 if (csa_initialize(scp))
388 /* Reset the Processor. */
391 /* Download the Processor Image to the processor. */
392 if (csa_downloadimage(resp))
395 return (bus_generic_resume(dev));
398 static struct resource *
399 csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
400 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
404 struct resource *res;
406 scp = device_get_softc(bus);
434 csa_release_resource(device_t bus, device_t child, int type, int rid,
441 * The following three functions deal with interrupt handling.
442 * An interrupt is primarily handled by the bridge driver.
443 * The bridge driver then determines the child devices to pass
444 * the interrupt. Certain information of the device can be read
445 * only once(eg the value of HISR). The bridge driver is responsible
446 * to pass such the information to the children.
450 csa_setup_intr(device_t bus, device_t child,
451 struct resource *irq, int flags,
452 driver_filter_t *filter,
453 driver_intr_t *intr, void *arg, void **cookiep)
457 struct sndcard_func *func;
459 if (filter != NULL) {
460 printf("ata-csa.c: we cannot use a filter here\n");
463 scp = device_get_softc(bus);
467 * Look at the function code of the child to determine
468 * the appropriate hander for it.
470 func = device_get_ivars(child);
471 if (func == NULL || irq != resp->irq)
474 switch (func->func) {
477 scp->pcmintr_arg = arg;
481 scp->midiintr = intr;
482 scp->midiintr_arg = arg;
489 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
490 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
496 csa_teardown_intr(device_t bus, device_t child,
497 struct resource *irq, void *cookie)
501 struct sndcard_func *func;
503 scp = device_get_softc(bus);
507 * Look at the function code of the child to determine
508 * the appropriate hander for it.
510 func = device_get_ivars(child);
511 if (func == NULL || irq != resp->irq || cookie != scp)
514 switch (func->func) {
517 scp->pcmintr_arg = NULL;
521 scp->midiintr = NULL;
522 scp->midiintr_arg = NULL;
532 /* The interrupt handler */
542 /* Is this interrupt for us? */
543 hisr = csa_readio(resp, BA0_HISR);
544 if ((hisr & 0x7fffffff) == 0) {
546 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
551 * Pass the value of HISR via struct csa_bridgeinfo.
552 * The children get access through their ivars.
554 scp->binfo.hisr = hisr;
556 /* Invoke the handlers of the children. */
557 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) {
558 scp->pcmintr(scp->pcmintr_arg);
559 hisr &= ~(HISR_VC0 | HISR_VC1);
561 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) {
562 scp->midiintr(scp->midiintr_arg);
567 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
571 csa_initialize(sc_p scp)
574 u_int32_t acsts, acisv;
580 * First, blast the clock control register to zero so that the PLL starts
581 * out in a known state, and blast the master serial port control register
582 * to zero so that the serial ports also start out in a known state.
584 csa_writeio(resp, BA0_CLKCR1, 0);
585 csa_writeio(resp, BA0_SERMC1, 0);
588 * If we are in AC97 mode, then we must set the part to a host controlled
589 * AC-link. Otherwise, we won't be able to bring up the link.
592 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */
594 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */
598 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
599 * spec) and then drive it high. This is done for non AC97 modes since
600 * there might be logic external to the CS461x that uses the ARST# line
603 csa_writeio(resp, BA0_ACCTL, 1);
605 csa_writeio(resp, BA0_ACCTL, 0);
607 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
610 * The first thing we do here is to enable sync generation. As soon
611 * as we start receiving bit clock, we'll start producing the SYNC
614 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
617 * Now wait for a short while to allow the AC97 part to start
618 * generating bit clock (so we don't try to start the PLL without an
624 * Set the serial port timing configuration, so that
625 * the clock control circuit gets its clock from the correct place.
627 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97);
631 * Write the selected clock control setup to the hardware. Do not turn on
632 * SWCE yet (if requested), so that the devices clocked by the output of
633 * PLL are not clocked until the PLL is stable.
635 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
636 csa_writeio(resp, BA0_PLLM, 0x3a);
637 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8);
642 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP);
645 * Wait until the PLL has stabilized.
650 * Turn on clocking of the core so that we can setup the serial ports.
652 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE);
655 * Fill the serial port FIFOs with silence.
657 csa_clearserialfifos(resp);
660 * Set the serial port FIFO pointer to the first sample in the FIFO.
663 csa_writeio(resp, BA0_SERBSP, 0);
667 * Write the serial port configuration to the part. The master
668 * enable bit is not set until all other values have been written.
670 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
671 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
672 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
675 * Wait for the codec ready signal from the AC97 codec.
678 for (i = 0 ; i < 1000 ; i++) {
680 * First, lets wait a short while to let things settle out a bit,
681 * and to prevent retrying the read too quickly.
686 * Read the AC97 status register to see if we've seen a CODEC READY
687 * signal from the AC97 codec.
689 acsts = csa_readio(resp, BA0_ACSTS);
690 if ((acsts & ACSTS_CRDY) != 0)
695 * Make sure we sampled CODEC READY.
697 if ((acsts & ACSTS_CRDY) == 0)
701 * Assert the vaid frame signal so that we can start sending commands
704 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
707 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
708 * the codec is pumping ADC data across the AC-link.
711 for (i = 0 ; i < 1000 ; i++) {
713 * First, lets wait a short while to let things settle out a bit,
714 * and to prevent retrying the read too quickly.
717 DELAY(10000000L); /* clw */
722 * Read the input slot valid register and see if input slots 3 and
725 acisv = csa_readio(resp, BA0_ACISV);
726 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
730 * Make sure we sampled valid input slots 3 and 4. If not, then return
733 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
737 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
738 * commense the transfer of digital audio data to the AC97 codec.
740 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
743 * Power down the DAC and ADC. We will power them up (if) when we need
747 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300);
751 * Turn off the Processor by turning off the software clock enable flag in
752 * the clock control register.
755 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE;
756 csa_writeio(resp, BA0_CLKCR1, clkcr1);
760 * Enable interrupts on the part.
763 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
770 csa_clearserialfifos(csa_res *resp)
773 u_int8_t clkcr1, serbst;
776 * See if the devices are powered down. If so, we must power them up first
777 * or they will not respond.
780 clkcr1 = csa_readio(resp, BA0_CLKCR1);
781 if ((clkcr1 & CLKCR1_SWCE) == 0) {
782 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE);
787 * We want to clear out the serial port FIFOs so we don't end up playing
788 * whatever random garbage happens to be in them. We fill the sample FIFOs
789 * with zero (silence).
791 csa_writeio(resp, BA0_SERBWP, 0);
793 /* Fill all 256 sample FIFO locations. */
795 for (i = 0 ; i < 256 ; i++) {
796 /* Make sure the previous FIFO write operation has completed. */
797 for (j = 0 ; j < 5 ; j++) {
799 serbst = csa_readio(resp, BA0_SERBST);
800 if ((serbst & SERBST_WBSY) == 0)
803 if ((serbst & SERBST_WBSY) != 0) {
805 csa_writeio(resp, BA0_CLKCR1, clkcr1);
807 /* Write the serial port FIFO index. */
808 csa_writeio(resp, BA0_SERBAD, i);
809 /* Tell the serial port to load the new value into the FIFO location. */
810 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC);
813 * Now, if we powered up the devices, then power them back down again.
814 * This is kinda ugly, but should never happen.
817 csa_writeio(resp, BA0_CLKCR1, clkcr1);
821 csa_resetdsp(csa_res *resp)
826 * Write the reset bit of the SP control register.
828 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP);
831 * Write the control register.
833 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN);
836 * Clear the trap registers.
838 for (i = 0 ; i < 8 ; i++) {
839 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i);
840 csa_writemem(resp, BA1_TWPR, 0xffff);
842 csa_writemem(resp, BA1_DREG, 0);
845 * Set the frame timer to reflect the number of cycles per frame.
847 csa_writemem(resp, BA1_FRMT, 0xadf);
851 csa_downloadimage(csa_res *resp)
856 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) {
858 * DMA this block from host memory to the appropriate
859 * memory on the CSDevice.
861 ret = csa_transferimage(resp,
862 cs461x_firmware.BA1Array + offset,
863 cs461x_firmware.MemoryStat[ul].ulDestAddr,
864 cs461x_firmware.MemoryStat[ul].ulSourceSize);
867 offset += cs461x_firmware.MemoryStat[ul].ulSourceSize >> 2;
873 csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len)
878 * We do not allow DMAs from host memory to host memory (although the DMA
879 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes
880 * in size (because that DMA can not do that). Return an error if either
881 * of these conditions exist.
883 if ((len & 0x3) != 0)
886 /* Check the destination address that it is a multiple of 4 */
887 if ((dest & 0x3) != 0)
890 /* Write the buffer out. */
891 for (ul = 0 ; ul < len ; ul += 4)
892 csa_writemem(resp, dest + ul, src[ul >> 2]);
897 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data)
900 u_int32_t acctl, acsts;
903 * Make sure that there is not data sitting around from a previous
904 * uncompleted access. ACSDA = Status Data Register = 47Ch
906 csa_readio(resp, BA0_ACSDA);
909 * Setup the AC97 control registers on the CS461x to send the
910 * appropriate command to the AC97 to perform the read.
911 * ACCAD = Command Address Register = 46Ch
912 * ACCDA = Command Data Register = 470h
913 * ACCTL = Control Register = 460h
914 * set DCV - will clear when process completed
915 * set CRW - Read command
916 * set VFRM - valid frame enabled
917 * set ESYN - ASYNC generation enabled
918 * set RSTN - ARST# inactive, AC97 codec not reset
922 * Get the actual AC97 register from the offset
924 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
925 csa_writeio(resp, BA0_ACCDA, 0);
926 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
929 * Wait for the read to occur.
932 for (i = 0 ; i < 10 ; i++) {
934 * First, we want to wait for a short time.
939 * Now, check to see if the read has completed.
940 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
942 acctl = csa_readio(resp, BA0_ACCTL);
943 if ((acctl & ACCTL_DCV) == 0)
948 * Make sure the read completed.
950 if ((acctl & ACCTL_DCV) != 0)
954 * Wait for the valid status bit to go active.
957 for (i = 0 ; i < 10 ; i++) {
959 * Read the AC97 status register.
960 * ACSTS = Status Register = 464h
962 acsts = csa_readio(resp, BA0_ACSTS);
964 * See if we have valid status.
965 * VSTS - Valid Status
967 if ((acsts & ACSTS_VSTS) != 0)
970 * Wait for a short while.
976 * Make sure we got valid status.
978 if ((acsts & ACSTS_VSTS) == 0)
982 * Read the data returned from the AC97 register.
983 * ACSDA = Status Data Register = 474h
985 *data = csa_readio(resp, BA0_ACSDA);
991 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data)
997 * Setup the AC97 control registers on the CS461x to send the
998 * appropriate command to the AC97 to perform the write.
999 * ACCAD = Command Address Register = 46Ch
1000 * ACCDA = Command Data Register = 470h
1001 * ACCTL = Control Register = 460h
1002 * set DCV - will clear when process completed
1003 * set VFRM - valid frame enabled
1004 * set ESYN - ASYNC generation enabled
1005 * set RSTN - ARST# inactive, AC97 codec not reset
1009 * Get the actual AC97 register from the offset
1011 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
1012 csa_writeio(resp, BA0_ACCDA, data);
1013 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
1016 * Wait for the write to occur.
1019 for (i = 0 ; i < 10 ; i++) {
1021 * First, we want to wait for a short time.
1026 * Now, check to see if the read has completed.
1027 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
1029 acctl = csa_readio(resp, BA0_ACCTL);
1030 if ((acctl & ACCTL_DCV) == 0)
1035 * Make sure the write completed.
1037 if ((acctl & ACCTL_DCV) != 0)
1044 csa_readio(csa_res *resp, u_long offset)
1048 if (offset < BA0_AC97_RESET)
1049 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff;
1051 if (csa_readcodec(resp, offset, &ul))
1058 csa_writeio(csa_res *resp, u_long offset, u_int32_t data)
1060 if (offset < BA0_AC97_RESET)
1061 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data);
1063 csa_writecodec(resp, offset, data);
1067 csa_readmem(csa_res *resp, u_long offset)
1069 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset);
1073 csa_writemem(csa_res *resp, u_long offset, u_int32_t data)
1075 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data);
1078 static device_method_t csa_methods[] = {
1079 /* Device interface */
1080 DEVMETHOD(device_probe, csa_probe),
1081 DEVMETHOD(device_attach, csa_attach),
1082 DEVMETHOD(device_detach, csa_detach),
1083 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1084 DEVMETHOD(device_suspend, bus_generic_suspend),
1085 DEVMETHOD(device_resume, csa_resume),
1088 DEVMETHOD(bus_alloc_resource, csa_alloc_resource),
1089 DEVMETHOD(bus_release_resource, csa_release_resource),
1090 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1091 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1092 DEVMETHOD(bus_setup_intr, csa_setup_intr),
1093 DEVMETHOD(bus_teardown_intr, csa_teardown_intr),
1098 static driver_t csa_driver = {
1101 sizeof(struct csa_softc),
1105 * csa can be attached to a pci bus.
1107 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0);
1108 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1109 MODULE_VERSION(snd_csa, 1);