2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2000 Cameron Grant <cg@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
29 #ifdef HAVE_KERNEL_OPTION_HEADERS
33 #include <dev/sound/pcm/sound.h>
34 #include <dev/sound/pcm/ac97.h>
36 #include <dev/pci/pcireg.h>
37 #include <dev/pci/pcivar.h>
39 #include <dev/sound/pci/ds1.h>
40 #include <dev/sound/pci/ds1-fw.h>
42 SND_DECLARE_FILE("$FreeBSD$");
44 /* -------------------------------------------------------------------- */
47 #define DS1_RECPRIMARY 0
48 #define DS1_IRQHZ ((48000 << 8) / 256)
49 #define DS1_BUFFSIZE 4096
52 volatile u_int32_t Format;
53 volatile u_int32_t LoopDefault;
54 volatile u_int32_t PgBase;
55 volatile u_int32_t PgLoop;
56 volatile u_int32_t PgLoopEnd;
57 volatile u_int32_t PgLoopFrac;
58 volatile u_int32_t PgDeltaEnd;
59 volatile u_int32_t LpfKEnd;
60 volatile u_int32_t EgGainEnd;
61 volatile u_int32_t LchGainEnd;
62 volatile u_int32_t RchGainEnd;
63 volatile u_int32_t Effect1GainEnd;
64 volatile u_int32_t Effect2GainEnd;
65 volatile u_int32_t Effect3GainEnd;
66 volatile u_int32_t LpfQ;
67 volatile u_int32_t Status;
68 volatile u_int32_t NumOfFrames;
69 volatile u_int32_t LoopCount;
70 volatile u_int32_t PgStart;
71 volatile u_int32_t PgStartFrac;
72 volatile u_int32_t PgDelta;
73 volatile u_int32_t LpfK;
74 volatile u_int32_t EgGain;
75 volatile u_int32_t LchGain;
76 volatile u_int32_t RchGain;
77 volatile u_int32_t Effect1Gain;
78 volatile u_int32_t Effect2Gain;
79 volatile u_int32_t Effect3Gain;
80 volatile u_int32_t LpfD1;
81 volatile u_int32_t LpfD2;
85 volatile u_int32_t PgBase;
86 volatile u_int32_t PgLoopEnd;
87 volatile u_int32_t PgStart;
88 volatile u_int32_t NumOfLoops;
93 /* channel registers */
95 int run, spd, dir, fmt;
96 struct snd_dbuf *buffer;
97 struct pcm_channel *channel;
98 volatile struct pbank *lslot, *rslot;
100 struct sc_info *parent;
104 int run, spd, dir, fmt, num;
105 struct snd_dbuf *buffer;
106 struct pcm_channel *channel;
107 volatile struct rbank *slot;
108 struct sc_info *parent;
111 /* device private data */
115 u_int32_t cd2id, ctrlbase;
118 bus_space_handle_t sh;
119 bus_dma_tag_t buffer_dmat, control_dmat;
122 struct resource *reg, *irq;
128 u_int32_t *pbase, pbankbase, pbanksize;
129 volatile struct pbank *pbank[2 * 64];
130 volatile struct rbank *rbank;
131 int pslotfree, currbank, pchn, rchn;
134 struct sc_pchinfo pch[DS1_CHANS];
135 struct sc_rchinfo rch[2];
139 u_int32_t dev, subdev;
143 {0x00041073, 0, "Yamaha DS-1 (YMF724)", CntrlInst},
144 {0x000d1073, 0, "Yamaha DS-1E (YMF724F)", CntrlInst1E},
145 {0x00051073, 0, "Yamaha DS-1? (YMF734)", CntrlInst},
146 {0x00081073, 0, "Yamaha DS-1? (YMF737)", CntrlInst},
147 {0x00201073, 0, "Yamaha DS-1? (YMF738)", CntrlInst},
148 {0x00061073, 0, "Yamaha DS-1? (YMF738_TEG)", CntrlInst},
149 {0x000a1073, 0x00041073, "Yamaha DS-1 (YMF740)", CntrlInst},
150 {0x000a1073, 0x000a1073, "Yamaha DS-1 (YMF740B)", CntrlInst},
151 {0x000a1073, 0x53328086, "Yamaha DS-1 (YMF740I)", CntrlInst},
152 {0x000a1073, 0, "Yamaha DS-1 (YMF740?)", CntrlInst},
153 {0x000c1073, 0, "Yamaha DS-1E (YMF740C)", CntrlInst1E},
154 {0x00101073, 0, "Yamaha DS-1E (YMF744)", CntrlInst1E},
155 {0x00121073, 0, "Yamaha DS-1E (YMF754)", CntrlInst1E},
159 /* -------------------------------------------------------------------- */
166 static int ds_init(struct sc_info *);
167 static void ds_intr(void *);
169 /* talk to the card */
170 static u_int32_t ds_rd(struct sc_info *, int, int);
171 static void ds_wr(struct sc_info *, int, u_int32_t, int);
173 /* -------------------------------------------------------------------- */
175 static u_int32_t ds_recfmt[] = {
176 SND_FORMAT(AFMT_U8, 1, 0),
177 SND_FORMAT(AFMT_U8, 2, 0),
178 SND_FORMAT(AFMT_S8, 1, 0),
179 SND_FORMAT(AFMT_S8, 2, 0),
180 SND_FORMAT(AFMT_S16_LE, 1, 0),
181 SND_FORMAT(AFMT_S16_LE, 2, 0),
182 SND_FORMAT(AFMT_U16_LE, 1, 0),
183 SND_FORMAT(AFMT_U16_LE, 2, 0),
186 static struct pcmchan_caps ds_reccaps = {4000, 48000, ds_recfmt, 0};
188 static u_int32_t ds_playfmt[] = {
189 SND_FORMAT(AFMT_U8, 1, 0),
190 SND_FORMAT(AFMT_U8, 2, 0),
191 /* SND_FORMAT(AFMT_S16_LE, 1, 0), */
192 SND_FORMAT(AFMT_S16_LE, 2, 0),
195 static struct pcmchan_caps ds_playcaps = {4000, 96000, ds_playfmt, 0};
197 /* -------------------------------------------------------------------- */
200 ds_rd(struct sc_info *sc, int regno, int size)
204 return bus_space_read_1(sc->st, sc->sh, regno);
206 return bus_space_read_2(sc->st, sc->sh, regno);
208 return bus_space_read_4(sc->st, sc->sh, regno);
215 ds_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
219 bus_space_write_1(sc->st, sc->sh, regno, data);
222 bus_space_write_2(sc->st, sc->sh, regno, data);
225 bus_space_write_4(sc->st, sc->sh, regno, data);
231 wrl(struct sc_info *sc, u_int32_t *ptr, u_int32_t val)
233 *(volatile u_int32_t *)ptr = val;
234 bus_space_barrier(sc->st, sc->sh, 0, 0, BUS_SPACE_BARRIER_WRITE);
237 /* -------------------------------------------------------------------- */
240 ds_cdbusy(struct sc_info *sc, int sec)
244 reg = sec? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
245 i = YDSXG_AC97TIMEOUT;
247 if (!(ds_rd(sc, reg, 2) & 0x8000))
255 ds_initcd(kobj_t obj, void *devinfo)
257 struct sc_info *sc = (struct sc_info *)devinfo;
260 x = pci_read_config(sc->dev, PCIR_DSXGCTRL, 1);
262 pci_write_config(sc->dev, PCIR_DSXGCTRL, x & ~0x03, 1);
263 pci_write_config(sc->dev, PCIR_DSXGCTRL, x | 0x03, 1);
264 pci_write_config(sc->dev, PCIR_DSXGCTRL, x & ~0x03, 1);
266 * The YMF740 on some Intel motherboards requires a pretty
267 * hefty delay after this reset for some reason... Otherwise:
268 * "pcm0: ac97 codec init failed"
269 * Maybe this is needed for all YMF740's?
270 * 400ms and 500ms here seem to work, 300ms does not.
272 * do it for all chips -cg
277 return ds_cdbusy(sc, 0)? 0 : 1;
281 ds_rdcd(kobj_t obj, void *devinfo, int regno)
283 struct sc_info *sc = (struct sc_info *)devinfo;
289 cid = sec? (sc->cd2id << 8) : 0;
290 reg = sec? YDSXGR_SECSTATUSDATA : YDSXGR_PRISTATUSDATA;
294 cmd = YDSXG_AC97READCMD | cid | regno;
295 ds_wr(sc, YDSXGR_AC97CMDADR, cmd, 2);
297 if (ds_cdbusy(sc, sec))
300 if (sc->type == 11 && sc->rev < 2)
301 for (i = 0; i < 600; i++)
304 return ds_rd(sc, reg, 2);
308 ds_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
310 struct sc_info *sc = (struct sc_info *)devinfo;
316 cid = sec? (sc->cd2id << 8) : 0;
320 cmd = YDSXG_AC97WRITECMD | cid | regno;
323 ds_wr(sc, YDSXGR_AC97CMDDATA, cmd, 4);
325 return ds_cdbusy(sc, sec);
328 static kobj_method_t ds_ac97_methods[] = {
329 KOBJMETHOD(ac97_init, ds_initcd),
330 KOBJMETHOD(ac97_read, ds_rdcd),
331 KOBJMETHOD(ac97_write, ds_wrcd),
334 AC97_DECLARE(ds_ac97);
336 /* -------------------------------------------------------------------- */
339 ds_enadsp(struct sc_info *sc, int on)
345 ds_wr(sc, YDSXGR_CONFIG, 0x00000001, 4);
347 if (ds_rd(sc, YDSXGR_CONFIG, 4))
348 ds_wr(sc, YDSXGR_CONFIG, 0x00000000, 4);
349 i = YDSXG_WORKBITTIMEOUT;
351 if (!(ds_rd(sc, YDSXGR_CONFIG, 4) & 0x00000002))
358 static volatile struct pbank *
359 ds_allocpslot(struct sc_info *sc)
363 if (sc->pslotfree > 63)
365 slot = sc->pslotfree++;
366 return sc->pbank[slot * 2];
370 ds_initpbank(volatile struct pbank *pb, int ch, int stereo, int b16, u_int32_t rate, bus_addr_t base, u_int32_t len)
372 u_int32_t lv[] = {1, 1, 0, 0, 0};
373 u_int32_t rv[] = {1, 0, 1, 0, 0};
374 u_int32_t e1[] = {0, 0, 0, 0, 0};
375 u_int32_t e2[] = {1, 0, 0, 1, 0};
376 u_int32_t e3[] = {1, 0, 0, 0, 1};
383 { 100, 0x00570000, 0x35280000},
384 { 2000, 0x06aa0000, 0x34a70000},
385 { 8000, 0x18b20000, 0x32020000},
386 {11025, 0x20930000, 0x31770000},
387 {16000, 0x2b9a0000, 0x31390000},
388 {22050, 0x35a10000, 0x31c90000},
389 {32000, 0x3eaa0000, 0x33d00000},
390 /* {44100, 0x04646000, 0x370a0000},
391 */ {48000, 0x40000000, 0x40000000},
396 delta = (65536 * rate) / 48000;
398 while (i < 7 && speedinfo[i].rate < rate)
401 pb->Format = stereo? 0x00010000 : 0;
402 pb->Format |= b16? 0 : 0x80000000;
403 pb->Format |= (stereo && (ch == 2 || ch == 4))? 0x00000001 : 0;
407 pb->PgLoopEnd = len >> ss;
414 pb->PgDelta = pb->PgDeltaEnd = delta << 12;
415 pb->LpfQ = speedinfo[i].fQ;
416 pb->LpfK = pb->LpfKEnd = speedinfo[i].fK;
417 pb->LpfD1 = pb->LpfD2 = 0;
418 pb->EgGain = pb->EgGainEnd = 0x40000000;
419 pb->LchGain = pb->LchGainEnd = lv[ch] * 0x40000000;
420 pb->RchGain = pb->RchGainEnd = rv[ch] * 0x40000000;
421 pb->Effect1Gain = pb->Effect1GainEnd = e1[ch] * 0x40000000;
422 pb->Effect2Gain = pb->Effect2GainEnd = e2[ch] * 0x40000000;
423 pb->Effect3Gain = pb->Effect3GainEnd = e3[ch] * 0x40000000;
429 ds_enapslot(struct sc_info *sc, int slot, int go)
431 wrl(sc, &sc->pbase[slot + 1], go? (sc->pbankbase + 2 * slot * sc->pbanksize) : 0);
432 /* printf("pbase[%d] = 0x%x\n", slot + 1, go? (sc->pbankbase + 2 * slot * sc->pbanksize) : 0); */
436 ds_setuppch(struct sc_pchinfo *ch)
438 int stereo, b16, c, sz;
441 stereo = (AFMT_CHANNEL(ch->fmt) > 1)? 1 : 0;
442 b16 = (ch->fmt & AFMT_16BIT)? 1 : 0;
444 addr = sndbuf_getbufaddr(ch->buffer);
445 sz = sndbuf_getsize(ch->buffer);
447 ds_initpbank(ch->lslot, c, stereo, b16, ch->spd, addr, sz);
448 ds_initpbank(ch->lslot + 1, c, stereo, b16, ch->spd, addr, sz);
449 ds_initpbank(ch->rslot, 2, stereo, b16, ch->spd, addr, sz);
450 ds_initpbank(ch->rslot + 1, 2, stereo, b16, ch->spd, addr, sz);
454 ds_setuprch(struct sc_rchinfo *ch)
456 struct sc_info *sc = ch->parent;
457 int stereo, b16, i, sz, pri;
461 stereo = (AFMT_CHANNEL(ch->fmt) > 1)? 1 : 0;
462 b16 = (ch->fmt & AFMT_16BIT)? 1 : 0;
463 addr = sndbuf_getbufaddr(ch->buffer);
464 sz = sndbuf_getsize(ch->buffer);
465 pri = (ch->num == DS1_RECPRIMARY)? 1 : 0;
467 for (i = 0; i < 2; i++) {
468 ch->slot[i].PgBase = addr;
469 ch->slot[i].PgLoopEnd = sz;
470 ch->slot[i].PgStart = 0;
471 ch->slot[i].NumOfLoops = 0;
473 x = (b16? 0x00 : 0x01) | (stereo? 0x02 : 0x00);
474 y = (48000 * 4096) / ch->spd;
476 /* printf("pri = %d, x = %d, y = %d\n", pri, x, y); */
477 ds_wr(sc, pri? YDSXGR_ADCFORMAT : YDSXGR_RECFORMAT, x, 4);
478 ds_wr(sc, pri? YDSXGR_ADCSLOTSR : YDSXGR_RECSLOTSR, y, 4);
481 /* -------------------------------------------------------------------- */
482 /* play channel interface */
484 ds1pchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
486 struct sc_info *sc = devinfo;
487 struct sc_pchinfo *ch;
489 KASSERT(dir == PCMDIR_PLAY, ("ds1pchan_init: bad direction"));
491 ch = &sc->pch[sc->pchn++];
496 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
499 if (sndbuf_alloc(ch->buffer, sc->buffer_dmat, 0, sc->bufsz) != 0)
502 ch->lsnum = sc->pslotfree;
503 ch->lslot = ds_allocpslot(sc);
504 ch->rsnum = sc->pslotfree;
505 ch->rslot = ds_allocpslot(sc);
512 ds1pchan_setformat(kobj_t obj, void *data, u_int32_t format)
514 struct sc_pchinfo *ch = data;
522 ds1pchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
524 struct sc_pchinfo *ch = data;
532 ds1pchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
534 struct sc_pchinfo *ch = data;
535 struct sc_info *sc = ch->parent;
538 /* irq rate is fixed at 187.5hz */
539 drate = ch->spd * sndbuf_getalign(ch->buffer);
540 blocksize = roundup2((drate << 8) / DS1_IRQHZ, 4);
541 sndbuf_resize(ch->buffer, sc->bufsz / blocksize, blocksize);
546 /* semantic note: must start at beginning of buffer */
548 ds1pchan_trigger(kobj_t obj, void *data, int go)
550 struct sc_pchinfo *ch = data;
551 struct sc_info *sc = ch->parent;
554 if (!PCMTRIG_COMMON(go))
556 stereo = (AFMT_CHANNEL(ch->fmt) > 1)? 1 : 0;
557 if (go == PCMTRIG_START) {
560 ds_enapslot(sc, ch->lsnum, 1);
561 ds_enapslot(sc, ch->rsnum, stereo);
562 snd_mtxlock(sc->lock);
563 ds_wr(sc, YDSXGR_MODE, 0x00000003, 4);
564 snd_mtxunlock(sc->lock);
567 /* ds_setuppch(ch); */
568 ds_enapslot(sc, ch->lsnum, 0);
569 ds_enapslot(sc, ch->rsnum, 0);
576 ds1pchan_getptr(kobj_t obj, void *data)
578 struct sc_pchinfo *ch = data;
579 struct sc_info *sc = ch->parent;
580 volatile struct pbank *bank;
584 ss = (AFMT_CHANNEL(ch->fmt) > 1)? 1 : 0;
585 ss += (ch->fmt & AFMT_16BIT)? 1 : 0;
587 bank = ch->lslot + sc->currbank;
588 /* printf("getptr: %d\n", bank->PgStart << ss); */
594 static struct pcmchan_caps *
595 ds1pchan_getcaps(kobj_t obj, void *data)
600 static kobj_method_t ds1pchan_methods[] = {
601 KOBJMETHOD(channel_init, ds1pchan_init),
602 KOBJMETHOD(channel_setformat, ds1pchan_setformat),
603 KOBJMETHOD(channel_setspeed, ds1pchan_setspeed),
604 KOBJMETHOD(channel_setblocksize, ds1pchan_setblocksize),
605 KOBJMETHOD(channel_trigger, ds1pchan_trigger),
606 KOBJMETHOD(channel_getptr, ds1pchan_getptr),
607 KOBJMETHOD(channel_getcaps, ds1pchan_getcaps),
610 CHANNEL_DECLARE(ds1pchan);
612 /* -------------------------------------------------------------------- */
613 /* record channel interface */
615 ds1rchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
617 struct sc_info *sc = devinfo;
618 struct sc_rchinfo *ch;
620 KASSERT(dir == PCMDIR_REC, ("ds1rchan_init: bad direction"));
622 ch = &sc->rch[sc->rchn];
623 ch->num = sc->rchn++;
628 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
630 if (sndbuf_alloc(ch->buffer, sc->buffer_dmat, 0, sc->bufsz) != 0)
633 ch->slot = (ch->num == DS1_RECPRIMARY)? sc->rbank + 2: sc->rbank;
640 ds1rchan_setformat(kobj_t obj, void *data, u_int32_t format)
642 struct sc_rchinfo *ch = data;
650 ds1rchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
652 struct sc_rchinfo *ch = data;
660 ds1rchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
662 struct sc_rchinfo *ch = data;
663 struct sc_info *sc = ch->parent;
666 /* irq rate is fixed at 187.5hz */
667 drate = ch->spd * sndbuf_getalign(ch->buffer);
668 blocksize = roundup2((drate << 8) / DS1_IRQHZ, 4);
669 sndbuf_resize(ch->buffer, sc->bufsz / blocksize, blocksize);
674 /* semantic note: must start at beginning of buffer */
676 ds1rchan_trigger(kobj_t obj, void *data, int go)
678 struct sc_rchinfo *ch = data;
679 struct sc_info *sc = ch->parent;
682 if (!PCMTRIG_COMMON(go))
684 if (go == PCMTRIG_START) {
687 snd_mtxlock(sc->lock);
688 x = ds_rd(sc, YDSXGR_MAPOFREC, 4);
689 x |= (ch->num == DS1_RECPRIMARY)? 0x02 : 0x01;
690 ds_wr(sc, YDSXGR_MAPOFREC, x, 4);
691 ds_wr(sc, YDSXGR_MODE, 0x00000003, 4);
692 snd_mtxunlock(sc->lock);
695 snd_mtxlock(sc->lock);
696 x = ds_rd(sc, YDSXGR_MAPOFREC, 4);
697 x &= ~((ch->num == DS1_RECPRIMARY)? 0x02 : 0x01);
698 ds_wr(sc, YDSXGR_MAPOFREC, x, 4);
699 snd_mtxunlock(sc->lock);
706 ds1rchan_getptr(kobj_t obj, void *data)
708 struct sc_rchinfo *ch = data;
709 struct sc_info *sc = ch->parent;
711 return ch->slot[sc->currbank].PgStart;
714 static struct pcmchan_caps *
715 ds1rchan_getcaps(kobj_t obj, void *data)
720 static kobj_method_t ds1rchan_methods[] = {
721 KOBJMETHOD(channel_init, ds1rchan_init),
722 KOBJMETHOD(channel_setformat, ds1rchan_setformat),
723 KOBJMETHOD(channel_setspeed, ds1rchan_setspeed),
724 KOBJMETHOD(channel_setblocksize, ds1rchan_setblocksize),
725 KOBJMETHOD(channel_trigger, ds1rchan_trigger),
726 KOBJMETHOD(channel_getptr, ds1rchan_getptr),
727 KOBJMETHOD(channel_getcaps, ds1rchan_getcaps),
730 CHANNEL_DECLARE(ds1rchan);
732 /* -------------------------------------------------------------------- */
733 /* The interrupt handler */
737 struct sc_info *sc = (struct sc_info *)p;
740 snd_mtxlock(sc->lock);
741 i = ds_rd(sc, YDSXGR_STATUS, 4);
743 device_printf(sc->dev, "timeout irq\n");
744 if (i & 0x80008000) {
745 ds_wr(sc, YDSXGR_STATUS, i & 0x80008000, 4);
746 sc->currbank = ds_rd(sc, YDSXGR_CTRLSELECT, 4) & 0x00000001;
749 for (i = 0; i < DS1_CHANS; i++) {
750 if (sc->pch[i].run) {
752 snd_mtxunlock(sc->lock);
753 chn_intr(sc->pch[i].channel);
754 snd_mtxlock(sc->lock);
757 for (i = 0; i < 2; i++) {
758 if (sc->rch[i].run) {
760 snd_mtxunlock(sc->lock);
761 chn_intr(sc->rch[i].channel);
762 snd_mtxlock(sc->lock);
765 i = ds_rd(sc, YDSXGR_MODE, 4);
767 ds_wr(sc, YDSXGR_MODE, i | 0x00000002, 4);
770 snd_mtxunlock(sc->lock);
773 /* -------------------------------------------------------------------- */
776 * Probe and attach the card
780 ds_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
782 struct sc_info *sc = arg;
784 sc->ctrlbase = error? 0 : (u_int32_t)segs->ds_addr;
787 printf("ds1: setmap (%lx, %lx), nseg=%d, error=%d\n",
788 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
794 ds_init(struct sc_info *sc)
797 u_int32_t *ci, r, pcs, rcs, ecs, ws, memsz, cb;
801 ci = ds_devs[sc->type].mcode;
803 ds_wr(sc, YDSXGR_NATIVEDACOUTVOL, 0x00000000, 4);
805 ds_wr(sc, YDSXGR_MODE, 0x00010000, 4);
806 ds_wr(sc, YDSXGR_MODE, 0x00000000, 4);
807 ds_wr(sc, YDSXGR_MAPOFREC, 0x00000000, 4);
808 ds_wr(sc, YDSXGR_MAPOFEFFECT, 0x00000000, 4);
809 ds_wr(sc, YDSXGR_PLAYCTRLBASE, 0x00000000, 4);
810 ds_wr(sc, YDSXGR_RECCTRLBASE, 0x00000000, 4);
811 ds_wr(sc, YDSXGR_EFFCTRLBASE, 0x00000000, 4);
812 r = ds_rd(sc, YDSXGR_GLOBALCTRL, 2);
813 ds_wr(sc, YDSXGR_GLOBALCTRL, r & ~0x0007, 2);
815 for (i = 0; i < YDSXG_DSPLENGTH; i += 4)
816 ds_wr(sc, YDSXGR_DSPINSTRAM + i, DspInst[i >> 2], 4);
818 for (i = 0; i < YDSXG_CTRLLENGTH; i += 4)
819 ds_wr(sc, YDSXGR_CTRLINSTRAM + i, ci[i >> 2], 4);
824 for (i = 100; i > 0; i--) {
825 pcs = ds_rd(sc, YDSXGR_PLAYCTRLSIZE, 4) << 2;
826 if (pcs == sizeof(struct pbank))
830 if (pcs != sizeof(struct pbank)) {
831 device_printf(sc->dev, "preposterous playctrlsize (%d)\n", pcs);
834 rcs = ds_rd(sc, YDSXGR_RECCTRLSIZE, 4) << 2;
835 ecs = ds_rd(sc, YDSXGR_EFFCTRLSIZE, 4) << 2;
836 ws = ds_rd(sc, YDSXGR_WORKSIZE, 4) << 2;
838 memsz = 64 * 2 * pcs + 2 * 2 * rcs + 5 * 2 * ecs + ws;
839 memsz += (64 + 1) * 4;
841 if (sc->regbase == NULL) {
842 if (bus_dma_tag_create(bus_get_dma_tag(sc->dev), 2, 0,
843 BUS_SPACE_MAXADDR_32BIT,
845 NULL, NULL, memsz, 1, memsz, 0, NULL,
846 NULL, &sc->control_dmat))
848 if (bus_dmamem_alloc(sc->control_dmat, &buf, BUS_DMA_NOWAIT, &sc->map))
850 if (bus_dmamap_load(sc->control_dmat, sc->map, buf, memsz, ds_setmap, sc, 0) || !sc->ctrlbase) {
851 device_printf(sc->dev, "pcs=%d, rcs=%d, ecs=%d, ws=%d, memsz=%d\n",
852 pcs, rcs, ecs, ws, memsz);
861 ds_wr(sc, YDSXGR_WORKBASE, sc->ctrlbase + cb, 4);
863 sc->pbase = (u_int32_t *)(t + cb);
864 /* printf("pbase = %p -> 0x%x\n", sc->pbase, sc->ctrlbase + cb); */
865 ds_wr(sc, YDSXGR_PLAYCTRLBASE, sc->ctrlbase + cb, 4);
867 sc->rbank = (struct rbank *)(t + cb);
868 ds_wr(sc, YDSXGR_RECCTRLBASE, sc->ctrlbase + cb, 4);
870 ds_wr(sc, YDSXGR_EFFCTRLBASE, sc->ctrlbase + cb, 4);
873 sc->pbankbase = sc->ctrlbase + cb;
875 for (i = 0; i < 64; i++) {
876 wrl(sc, &sc->pbase[i + 1], 0);
877 sc->pbank[i * 2] = (struct pbank *)(t + cb);
878 /* printf("pbank[%d] = %p -> 0x%x; ", i * 2, (struct pbank *)(t + cb), sc->ctrlbase + cb - vtophys(t + cb)); */
880 sc->pbank[i * 2 + 1] = (struct pbank *)(t + cb);
881 /* printf("pbank[%d] = %p -> 0x%x\n", i * 2 + 1, (struct pbank *)(t + cb), sc->ctrlbase + cb - vtophys(t + cb)); */
884 wrl(sc, &sc->pbase[0], DS1_CHANS * 2);
886 sc->pchn = sc->rchn = 0;
887 ds_wr(sc, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff, 4);
888 ds_wr(sc, YDSXGR_NATIVEADCINVOL, 0x3fff3fff, 4);
889 ds_wr(sc, YDSXGR_NATIVEDACINVOL, 0x3fff3fff, 4);
895 ds_uninit(struct sc_info *sc)
897 ds_wr(sc, YDSXGR_NATIVEDACOUTVOL, 0x00000000, 4);
898 ds_wr(sc, YDSXGR_NATIVEADCINVOL, 0, 4);
899 ds_wr(sc, YDSXGR_NATIVEDACINVOL, 0, 4);
901 ds_wr(sc, YDSXGR_MODE, 0x00010000, 4);
902 ds_wr(sc, YDSXGR_MAPOFREC, 0x00000000, 4);
903 ds_wr(sc, YDSXGR_MAPOFEFFECT, 0x00000000, 4);
904 ds_wr(sc, YDSXGR_PLAYCTRLBASE, 0x00000000, 4);
905 ds_wr(sc, YDSXGR_RECCTRLBASE, 0x00000000, 4);
906 ds_wr(sc, YDSXGR_EFFCTRLBASE, 0x00000000, 4);
907 ds_wr(sc, YDSXGR_GLOBALCTRL, 0, 2);
909 bus_dmamap_unload(sc->control_dmat, sc->map);
910 bus_dmamem_free(sc->control_dmat, sc->regbase, sc->map);
916 ds_finddev(u_int32_t dev, u_int32_t subdev)
920 for (i = 0; ds_devs[i].dev; i++) {
921 if (ds_devs[i].dev == dev &&
922 (ds_devs[i].subdev == subdev || ds_devs[i].subdev == 0))
929 ds_pci_probe(device_t dev)
934 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev);
935 i = ds_finddev(pci_get_devid(dev), subdev);
937 device_set_desc(dev, ds_devs[i].name);
938 return BUS_PROBE_DEFAULT;
944 ds_pci_attach(device_t dev)
948 struct ac97_info *codec = NULL;
949 char status[SND_STATUSLEN];
951 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
952 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_ds1 softc");
954 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev);
955 sc->type = ds_finddev(pci_get_devid(dev), subdev);
956 sc->rev = pci_get_revid(dev);
958 pci_enable_busmaster(dev);
960 sc->regid = PCIR_BAR(0);
961 sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->regid,
964 device_printf(dev, "unable to map register space\n");
968 sc->st = rman_get_bustag(sc->reg);
969 sc->sh = rman_get_bushandle(sc->reg);
971 sc->bufsz = pcm_getbuffersize(dev, 4096, DS1_BUFFSIZE, 65536);
973 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
975 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
976 /*highaddr*/BUS_SPACE_MAXADDR,
977 /*filter*/NULL, /*filterarg*/NULL,
978 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
979 /*flags*/0, /*lockfunc*/NULL,
980 /*lockarg*/NULL, &sc->buffer_dmat) != 0) {
981 device_printf(dev, "unable to create dma tag\n");
986 if (ds_init(sc) == -1) {
987 device_printf(dev, "unable to initialize the card\n");
991 codec = AC97_CREATE(dev, sc, ds_ac97);
995 * Turn on inverted external amplifier sense flags for few
999 case 0x81171033: /* NEC ValueStar (VT550/0) */
1000 ac97_setflags(codec, ac97_getflags(codec) | AC97_F_EAPD_INV);
1005 mixer_init(dev, ac97_getmixerclass(), codec);
1008 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
1009 RF_ACTIVE | RF_SHAREABLE);
1010 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ds_intr, sc, &sc->ih)) {
1011 device_printf(dev, "unable to map interrupt\n");
1015 snprintf(status, SND_STATUSLEN, "at memory 0x%jx irq %jd %s",
1016 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_ds1));
1018 if (pcm_register(dev, sc, DS1_CHANS, 2))
1020 for (i = 0; i < DS1_CHANS; i++)
1021 pcm_addchan(dev, PCMDIR_PLAY, &ds1pchan_class, sc);
1022 for (i = 0; i < 2; i++)
1023 pcm_addchan(dev, PCMDIR_REC, &ds1rchan_class, sc);
1024 pcm_setstatus(dev, status);
1030 ac97_destroy(codec);
1032 bus_release_resource(dev, SYS_RES_MEMORY, sc->regid, sc->reg);
1034 bus_teardown_intr(dev, sc->irq, sc->ih);
1036 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1037 if (sc->buffer_dmat)
1038 bus_dma_tag_destroy(sc->buffer_dmat);
1039 if (sc->control_dmat)
1040 bus_dma_tag_destroy(sc->control_dmat);
1042 snd_mtxfree(sc->lock);
1048 ds_pci_resume(device_t dev)
1052 sc = pcm_getdevinfo(dev);
1054 if (ds_init(sc) == -1) {
1055 device_printf(dev, "unable to reinitialize the card\n");
1058 if (mixer_reinit(dev) == -1) {
1059 device_printf(dev, "unable to reinitialize the mixer\n");
1066 ds_pci_detach(device_t dev)
1071 r = pcm_unregister(dev);
1075 sc = pcm_getdevinfo(dev);
1077 bus_release_resource(dev, SYS_RES_MEMORY, sc->regid, sc->reg);
1078 bus_teardown_intr(dev, sc->irq, sc->ih);
1079 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1080 bus_dma_tag_destroy(sc->buffer_dmat);
1081 bus_dma_tag_destroy(sc->control_dmat);
1082 snd_mtxfree(sc->lock);
1087 static device_method_t ds1_methods[] = {
1088 /* Device interface */
1089 DEVMETHOD(device_probe, ds_pci_probe),
1090 DEVMETHOD(device_attach, ds_pci_attach),
1091 DEVMETHOD(device_detach, ds_pci_detach),
1092 DEVMETHOD(device_resume, ds_pci_resume),
1096 static driver_t ds1_driver = {
1102 DRIVER_MODULE(snd_ds1, pci, ds1_driver, pcm_devclass, 0, 0);
1103 MODULE_DEPEND(snd_ds1, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1104 MODULE_VERSION(snd_ds1, 1);