2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2004 David O'Brien <obrien@FreeBSD.org>
5 * Copyright (c) 2003 Orlando Bassotto <orlando.bassotto@ieo-research.it>
6 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifdef HAVE_KERNEL_OPTION_HEADERS
35 #include <dev/sound/pcm/sound.h>
36 #include <dev/sound/pcm/ac97.h>
37 #include <dev/sound/pci/emuxkireg.h>
39 #include <dev/pci/pcireg.h>
40 #include <dev/pci/pcivar.h>
41 #include <sys/queue.h>
43 #include <dev/sound/midi/mpu401.h>
44 #include "mpufoi_if.h"
46 SND_DECLARE_FILE("$FreeBSD$");
48 /* -------------------------------------------------------------------- */
50 #define NUM_G 64 /* use all channels */
51 #define WAVEOUT_MAXBUFSIZE 32768
52 #define EMUPAGESIZE 4096 /* don't change */
53 #define EMUMAXPAGES (WAVEOUT_MAXBUFSIZE * NUM_G / EMUPAGESIZE)
54 #define EMU10K1_PCI_ID 0x00021102 /* 1102 => Creative Labs Vendor ID */
55 #define EMU10K2_PCI_ID 0x00041102
56 #define EMU10K3_PCI_ID 0x00081102
57 #define EMU_DEFAULT_BUFSZ 4096
58 #define EMU_MAX_CHANS 8
61 #define MAXREQVOICES 8
66 #define TMEMSIZE 256*1024
69 #define ENABLE 0xffffffff
70 #define DISABLE 0x00000000
71 #define ENV_ON EMU_CHAN_DCYSUSV_CHANNELENABLE_MASK
72 #define ENV_OFF 0x00 /* XXX: should this be 1? */
74 #define EMU_A_IOCFG_GPOUT_A 0x40
75 #define EMU_A_IOCFG_GPOUT_D 0x04
76 #define EMU_A_IOCFG_GPOUT_AD (EMU_A_IOCFG_GPOUT_A|EMU_A_IOCFG_GPOUT_D) /* EMU_A_IOCFG_GPOUT0 */
78 #define EMU_HCFG_GPOUT1 0x00000800
85 #define C_00000000 0x40
86 #define C_00000001 0x41
87 #define C_00000004 0x44
88 #define C_40000000 0x4d
89 /* Audigy constants */
90 #define A_C_00000000 0xc0
91 #define A_C_40000000 0xcd
94 #define FXBUS(x) (0x00 + (x))
95 #define EXTIN(x) (0x10 + (x))
96 #define EXTOUT(x) (0x20 + (x))
98 #define GPR(x) (EMU_FXGPREGBASE + (x))
99 #define A_EXTIN(x) (0x40 + (x))
100 #define A_FXBUS(x) (0x00 + (x))
101 #define A_EXTOUT(x) (0x60 + (x))
102 #define A_GPR(x) (EMU_A_FXGPREGBASE + (x))
105 #define FXBUS_PCM_LEFT 0x00
106 #define FXBUS_PCM_RIGHT 0x01
107 #define FXBUS_MIDI_LEFT 0x04
108 #define FXBUS_MIDI_RIGHT 0x05
109 #define FXBUS_MIDI_REVERB 0x0c
110 #define FXBUS_MIDI_CHORUS 0x0d
113 #define EXTIN_AC97_L 0x00
114 #define EXTIN_AC97_R 0x01
115 #define EXTIN_SPDIF_CD_L 0x02
116 #define EXTIN_SPDIF_CD_R 0x03
117 #define EXTIN_TOSLINK_L 0x06
118 #define EXTIN_TOSLINK_R 0x07
119 #define EXTIN_COAX_SPDIF_L 0x0a
120 #define EXTIN_COAX_SPDIF_R 0x0b
122 #define A_EXTIN_AC97_L 0x00
123 #define A_EXTIN_AC97_R 0x01
126 #define EXTOUT_AC97_L 0x00
127 #define EXTOUT_AC97_R 0x01
128 #define EXTOUT_TOSLINK_L 0x02
129 #define EXTOUT_TOSLINK_R 0x03
130 #define EXTOUT_AC97_CENTER 0x04
131 #define EXTOUT_AC97_LFE 0x05
132 #define EXTOUT_HEADPHONE_L 0x06
133 #define EXTOUT_HEADPHONE_R 0x07
134 #define EXTOUT_REAR_L 0x08
135 #define EXTOUT_REAR_R 0x09
136 #define EXTOUT_ADC_CAP_L 0x0a
137 #define EXTOUT_ADC_CAP_R 0x0b
138 #define EXTOUT_ACENTER 0x11
139 #define EXTOUT_ALFE 0x12
141 #define A_EXTOUT_FRONT_L 0x00
142 #define A_EXTOUT_FRONT_R 0x01
143 #define A_EXTOUT_CENTER 0x02
144 #define A_EXTOUT_LFE 0x03
145 #define A_EXTOUT_HEADPHONE_L 0x04
146 #define A_EXTOUT_HEADPHONE_R 0x05
147 #define A_EXTOUT_REAR_L 0x06
148 #define A_EXTOUT_REAR_R 0x07
149 #define A_EXTOUT_AFRONT_L 0x08
150 #define A_EXTOUT_AFRONT_R 0x09
151 #define A_EXTOUT_ACENTER 0x0a
152 #define A_EXTOUT_ALFE 0x0b
153 #define A_EXTOUT_AREAR_L 0x0e
154 #define A_EXTOUT_AREAR_R 0x0f
155 #define A_EXTOUT_AC97_L 0x10
156 #define A_EXTOUT_AC97_R 0x11
157 #define A_EXTOUT_ADC_CAP_L 0x16
158 #define A_EXTOUT_ADC_CAP_R 0x17
161 SLIST_ENTRY(emu_memblk) link;
164 u_int32_t pte_start, pte_size;
165 bus_dmamap_t buf_map;
169 u_int8_t bmap[EMUMAXPAGES / 8];
170 u_int32_t *ptb_pages;
172 bus_addr_t silent_page_addr;
173 bus_addr_t ptb_pages_addr;
174 bus_dmamap_t ptb_map;
175 bus_dmamap_t silent_map;
176 SLIST_HEAD(, emu_memblk) blocks;
181 unsigned int b16:1, stereo:1, busy:1, running:1, ismaster:1;
184 int fxrt1; /* FX routing */
185 int fxrt2; /* FX routing (only for audigy) */
187 struct emu_voice *slave;
188 struct pcm_channel *channel;
193 /* channel registers */
195 int spd, fmt, blksz, run;
196 struct emu_voice *master, *slave;
197 struct snd_dbuf *buffer;
198 struct pcm_channel *channel;
199 struct sc_info *parent;
203 int spd, fmt, run, blksz, num;
204 u_int32_t idxreg, basereg, sizereg, setupreg, irqmask;
205 struct snd_dbuf *buffer;
206 struct pcm_channel *channel;
207 struct sc_info *parent;
210 /* device private data */
214 u_int32_t tos_link:1, APS:1, audigy:1, audigy2:1;
215 u_int32_t addrmask; /* wider if audigy */
218 bus_space_handle_t sh;
219 bus_dma_tag_t parent_dmat;
221 struct resource *reg, *irq;
226 int timer, timerinterval;
230 struct emu_voice voice[64];
231 struct sc_pchinfo pch[EMU_MAX_CHANS];
232 struct sc_rchinfo rch[3];
234 mpu401_intr_t *mpu_intr;
238 /* -------------------------------------------------------------------- */
245 static int emu_init(struct sc_info *);
246 static void emu_intr(void *);
247 static void *emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr, bus_dmamap_t *map);
248 static void *emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr);
249 static int emu_memfree(struct sc_info *sc, void *buf);
250 static int emu_memstart(struct sc_info *sc, void *buf);
252 static void emu_vdump(struct sc_info *sc, struct emu_voice *v);
255 /* talk to the card */
256 static u_int32_t emu_rd(struct sc_info *, int, int);
257 static void emu_wr(struct sc_info *, int, u_int32_t, int);
259 /* -------------------------------------------------------------------- */
261 static u_int32_t emu_rfmt_ac97[] = {
262 SND_FORMAT(AFMT_S16_LE, 1, 0),
263 SND_FORMAT(AFMT_S16_LE, 2, 0),
267 static u_int32_t emu_rfmt_mic[] = {
268 SND_FORMAT(AFMT_U8, 1, 0),
272 static u_int32_t emu_rfmt_efx[] = {
273 SND_FORMAT(AFMT_S16_LE, 2, 0),
277 static struct pcmchan_caps emu_reccaps[3] = {
278 {8000, 48000, emu_rfmt_ac97, 0},
279 {8000, 8000, emu_rfmt_mic, 0},
280 {48000, 48000, emu_rfmt_efx, 0},
283 static u_int32_t emu_pfmt[] = {
284 SND_FORMAT(AFMT_U8, 1, 0),
285 SND_FORMAT(AFMT_U8, 2, 0),
286 SND_FORMAT(AFMT_S16_LE, 1, 0),
287 SND_FORMAT(AFMT_S16_LE, 2, 0),
291 static struct pcmchan_caps emu_playcaps = {4000, 48000, emu_pfmt, 0};
293 static int adcspeed[8] = {48000, 44100, 32000, 24000, 22050, 16000, 11025, 8000};
294 /* audigy supports 12kHz. */
295 static int audigy_adcspeed[9] = {
296 48000, 44100, 32000, 24000, 22050, 16000, 12000, 11025, 8000
299 /* -------------------------------------------------------------------- */
302 emu_rd(struct sc_info *sc, int regno, int size)
306 return bus_space_read_1(sc->st, sc->sh, regno);
308 return bus_space_read_2(sc->st, sc->sh, regno);
310 return bus_space_read_4(sc->st, sc->sh, regno);
317 emu_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
321 bus_space_write_1(sc->st, sc->sh, regno, data);
324 bus_space_write_2(sc->st, sc->sh, regno, data);
327 bus_space_write_4(sc->st, sc->sh, regno, data);
333 emu_rdptr(struct sc_info *sc, int chn, int reg)
335 u_int32_t ptr, val, mask, size, offset;
337 ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK);
338 emu_wr(sc, EMU_PTR, ptr, 4);
339 val = emu_rd(sc, EMU_DATA, 4);
340 if (reg & 0xff000000) {
341 size = (reg >> 24) & 0x3f;
342 offset = (reg >> 16) & 0x1f;
343 mask = ((1 << size) - 1) << offset;
351 emu_wrptr(struct sc_info *sc, int chn, int reg, u_int32_t data)
353 u_int32_t ptr, mask, size, offset;
355 ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK);
356 emu_wr(sc, EMU_PTR, ptr, 4);
357 if (reg & 0xff000000) {
358 size = (reg >> 24) & 0x3f;
359 offset = (reg >> 16) & 0x1f;
360 mask = ((1 << size) - 1) << offset;
363 data |= emu_rd(sc, EMU_DATA, 4) & ~mask;
365 emu_wr(sc, EMU_DATA, data, 4);
369 emu_wrefx(struct sc_info *sc, unsigned int pc, unsigned int data)
371 pc += sc->audigy ? EMU_A_MICROCODEBASE : EMU_MICROCODEBASE;
372 emu_wrptr(sc, 0, pc, data);
375 /* -------------------------------------------------------------------- */
377 /* no locking needed */
380 emu_rdcd(kobj_t obj, void *devinfo, int regno)
382 struct sc_info *sc = (struct sc_info *)devinfo;
384 emu_wr(sc, EMU_AC97ADDR, regno, 1);
385 return emu_rd(sc, EMU_AC97DATA, 2);
389 emu_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
391 struct sc_info *sc = (struct sc_info *)devinfo;
393 emu_wr(sc, EMU_AC97ADDR, regno, 1);
394 emu_wr(sc, EMU_AC97DATA, data, 2);
398 static kobj_method_t emu_ac97_methods[] = {
399 KOBJMETHOD(ac97_read, emu_rdcd),
400 KOBJMETHOD(ac97_write, emu_wrcd),
403 AC97_DECLARE(emu_ac97);
405 /* -------------------------------------------------------------------- */
408 emu_settimer(struct sc_info *sc)
410 struct sc_pchinfo *pch;
411 struct sc_rchinfo *rch;
415 for (i = 0; i < sc->nchans; i++) {
418 tmp = (pch->spd * sndbuf_getalign(pch->buffer))
425 for (i = 0; i < 3; i++) {
428 tmp = (rch->spd * sndbuf_getalign(rch->buffer))
434 RANGE(rate, 48, 9600);
435 sc->timerinterval = 48000 / rate;
436 emu_wr(sc, EMU_TIMER, sc->timerinterval & 0x03ff, 2);
438 return sc->timerinterval;
442 emu_enatimer(struct sc_info *sc, int go)
446 if (sc->timer++ == 0) {
447 x = emu_rd(sc, EMU_INTE, 4);
448 x |= EMU_INTE_INTERTIMERENB;
449 emu_wr(sc, EMU_INTE, x, 4);
453 x = emu_rd(sc, EMU_INTE, 4);
454 x &= ~EMU_INTE_INTERTIMERENB;
455 emu_wr(sc, EMU_INTE, x, 4);
461 emu_enastop(struct sc_info *sc, char channel, int enable)
463 int reg = (channel & 0x20) ? EMU_SOLEH : EMU_SOLEL;
466 reg |= channel << 16;
467 emu_wrptr(sc, 0, reg, enable);
471 emu_recval(int speed) {
475 while (val < 7 && speed < adcspeed[val])
481 audigy_recval(int speed) {
485 while (val < 8 && speed < audigy_adcspeed[val])
491 emu_rate_to_pitch(u_int32_t rate)
493 static u_int32_t logMagTable[128] = {
494 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2,
495 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5,
496 0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081,
497 0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191,
498 0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7,
499 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829,
500 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e,
501 0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26,
502 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d,
503 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885,
504 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899,
505 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c,
506 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3,
507 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3,
508 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83,
509 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df
511 static char logSlopeTable[128] = {
512 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58,
513 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53,
514 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f,
515 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b,
516 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47,
517 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44,
518 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41,
519 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e,
520 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c,
521 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39,
522 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37,
523 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35,
524 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34,
525 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32,
526 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30,
527 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f
532 return 0; /* Bail out if no leading "1" */
533 rate *= 11185; /* Scale 48000 to 0x20002380 */
534 for (i = 31; i > 0; i--) {
535 if (rate & 0x80000000) { /* Detect leading "1" */
536 return (((u_int32_t) (i - 15) << 20) +
537 logMagTable[0x7f & (rate >> 24)] +
538 (0x7f & (rate >> 17)) *
539 logSlopeTable[0x7f & (rate >> 24)]);
544 return 0; /* Should never reach this point */
548 emu_rate_to_linearpitch(u_int32_t rate)
550 rate = (rate << 8) / 375;
551 return (rate >> 1) + (rate & 1);
554 static struct emu_voice *
555 emu_valloc(struct sc_info *sc)
561 for (i = 0; i < 64 && sc->voice[i].busy; i++);
570 emu_vinit(struct sc_info *sc, struct emu_voice *m, struct emu_voice *s,
571 u_int32_t sz, struct snd_dbuf *b)
576 buf = emu_memalloc(sc, sz, &tmp_addr);
580 sndbuf_setup(b, buf, sz);
581 m->start = emu_memstart(sc, buf) * EMUPAGESIZE;
582 m->end = m->start + sz;
593 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 8 |
594 FXBUS_PCM_LEFT << 16 | FXBUS_MIDI_REVERB << 24;
595 m->fxrt2 = 0x3f3f3f3f; /* No effects on second route */
597 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 4 |
598 FXBUS_PCM_LEFT << 8 | FXBUS_MIDI_REVERB << 12;
621 emu_vsetup(struct sc_pchinfo *ch)
623 struct emu_voice *v = ch->master;
626 v->b16 = (ch->fmt & AFMT_16BIT) ? 1 : 0;
627 v->stereo = (AFMT_CHANNEL(ch->fmt) > 1) ? 1 : 0;
628 if (v->slave != NULL) {
629 v->slave->b16 = v->b16;
630 v->slave->stereo = v->stereo;
635 if (v->slave != NULL)
636 v->slave->speed = v->speed;
641 emu_vwrite(struct sc_info *sc, struct emu_voice *v)
645 u_int32_t sa, ea, start, val, silent_page;
647 s = (v->stereo ? 1 : 0) + (v->b16 ? 1 : 0);
652 l = r = x = y = v->vol;
654 l = v->ismaster ? l : 0;
655 r = v->ismaster ? 0 : r;
658 emu_wrptr(sc, v->vnum, EMU_CHAN_CPF, v->stereo ? EMU_CHAN_CPF_STEREO_MASK : 0);
659 val = v->stereo ? 28 : 30;
660 val *= v->b16 ? 1 : 2;
664 emu_wrptr(sc, v->vnum, EMU_A_CHAN_FXRT1, v->fxrt1);
665 emu_wrptr(sc, v->vnum, EMU_A_CHAN_FXRT2, v->fxrt2);
666 emu_wrptr(sc, v->vnum, EMU_A_CHAN_SENDAMOUNTS, 0);
669 emu_wrptr(sc, v->vnum, EMU_CHAN_FXRT, v->fxrt1 << 16);
671 emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX, (x << 8) | r);
672 emu_wrptr(sc, v->vnum, EMU_CHAN_DSL, ea | (y << 24));
673 emu_wrptr(sc, v->vnum, EMU_CHAN_PSST, sa | (l << 24));
674 emu_wrptr(sc, v->vnum, EMU_CHAN_CCCA, start | (v->b16 ? 0 : EMU_CHAN_CCCA_8BITSELECT));
676 emu_wrptr(sc, v->vnum, EMU_CHAN_Z1, 0);
677 emu_wrptr(sc, v->vnum, EMU_CHAN_Z2, 0);
679 silent_page = ((u_int32_t)(sc->mem.silent_page_addr) << 1)
680 | EMU_CHAN_MAP_PTI_MASK;
681 emu_wrptr(sc, v->vnum, EMU_CHAN_MAPA, silent_page);
682 emu_wrptr(sc, v->vnum, EMU_CHAN_MAPB, silent_page);
684 emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, EMU_CHAN_CVCF_CURRFILTER_MASK);
685 emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, EMU_CHAN_VTFT_FILTERTARGET_MASK);
686 emu_wrptr(sc, v->vnum, EMU_CHAN_ATKHLDM, 0);
687 emu_wrptr(sc, v->vnum, EMU_CHAN_DCYSUSM, EMU_CHAN_DCYSUSM_DECAYTIME_MASK);
688 emu_wrptr(sc, v->vnum, EMU_CHAN_LFOVAL1, 0x8000);
689 emu_wrptr(sc, v->vnum, EMU_CHAN_LFOVAL2, 0x8000);
690 emu_wrptr(sc, v->vnum, EMU_CHAN_FMMOD, 0);
691 emu_wrptr(sc, v->vnum, EMU_CHAN_TREMFRQ, 0);
692 emu_wrptr(sc, v->vnum, EMU_CHAN_FM2FRQ2, 0);
693 emu_wrptr(sc, v->vnum, EMU_CHAN_ENVVAL, 0x8000);
695 emu_wrptr(sc, v->vnum, EMU_CHAN_ATKHLDV,
696 EMU_CHAN_ATKHLDV_HOLDTIME_MASK | EMU_CHAN_ATKHLDV_ATTACKTIME_MASK);
697 emu_wrptr(sc, v->vnum, EMU_CHAN_ENVVOL, 0x8000);
699 emu_wrptr(sc, v->vnum, EMU_CHAN_PEFE_FILTERAMOUNT, 0x7f);
700 emu_wrptr(sc, v->vnum, EMU_CHAN_PEFE_PITCHAMOUNT, 0);
702 if (v->slave != NULL)
703 emu_vwrite(sc, v->slave);
707 emu_vtrigger(struct sc_info *sc, struct emu_voice *v, int go)
709 u_int32_t pitch_target, initial_pitch;
710 u_int32_t cra, cs, ccis;
715 cs = v->stereo ? 4 : 2;
716 ccis = v->stereo ? 28 : 30;
717 ccis *= v->b16 ? 1 : 2;
718 sample = v->b16 ? 0x00000000 : 0x80808080;
720 for (i = 0; i < cs; i++)
721 emu_wrptr(sc, v->vnum, EMU_CHAN_CD0 + i, sample);
722 emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_CACHEINVALIDSIZE, 0);
723 emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_READADDRESS, cra);
724 emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_CACHEINVALIDSIZE, ccis);
726 emu_wrptr(sc, v->vnum, EMU_CHAN_IFATN, 0xff00);
727 emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, 0xffffffff);
728 emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, 0xffffffff);
729 emu_wrptr(sc, v->vnum, EMU_CHAN_DCYSUSV, 0x00007f7f);
730 emu_enastop(sc, v->vnum, 0);
732 pitch_target = emu_rate_to_linearpitch(v->speed);
733 initial_pitch = emu_rate_to_pitch(v->speed) >> 8;
734 emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX_PITCHTARGET, pitch_target);
735 emu_wrptr(sc, v->vnum, EMU_CHAN_CPF_PITCH, pitch_target);
736 emu_wrptr(sc, v->vnum, EMU_CHAN_IP, initial_pitch);
738 emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX_PITCHTARGET, 0);
739 emu_wrptr(sc, v->vnum, EMU_CHAN_CPF_PITCH, 0);
740 emu_wrptr(sc, v->vnum, EMU_CHAN_IFATN, 0xffff);
741 emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, 0x0000ffff);
742 emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, 0x0000ffff);
743 emu_wrptr(sc, v->vnum, EMU_CHAN_IP, 0);
744 emu_enastop(sc, v->vnum, 1);
746 if (v->slave != NULL)
747 emu_vtrigger(sc, v->slave, go);
751 emu_vpos(struct sc_info *sc, struct emu_voice *v)
755 s = (v->b16 ? 1 : 0) + (v->stereo ? 1 : 0);
756 ptr = (emu_rdptr(sc, v->vnum, EMU_CHAN_CCCA_CURRADDR) - (v->start >> s)) << s;
757 return ptr & ~0x0000001f;
762 emu_vdump(struct sc_info *sc, struct emu_voice *v)
765 "cpf", "ptrx", "cvcf", "vtft", "z2", "z1", "psst", "dsl",
766 "ccca", "ccr", "clp", "fxrt", "mapa", "mapb", NULL, NULL,
767 "envvol", "atkhldv", "dcysusv", "lfoval1",
768 "envval", "atkhldm", "dcysusm", "lfoval2",
769 "ip", "ifatn", "pefe", "fmmod", "tremfrq", "fmfrq2",
773 "mudata1", "mustat1", "mudata2", "mustat2",
774 "fxwc1", "fxwc2", "spdrate", NULL, NULL,
775 NULL, NULL, NULL, "fxrt2", "sndamnt", "fxrt1",
780 printf("voice number %d\n", v->vnum);
781 for (i = 0, x = 0; i <= 0x1e; i++) {
782 if (regname[i] == NULL)
784 printf("%s\t[%08x]", regname[i], emu_rdptr(sc, v->vnum, i));
785 printf("%s", (x == 2) ? "\n" : "\t");
791 /* Print out audigy extra registers */
793 for (i = 0; i <= 0xe; i++) {
794 if (regname2[i] == NULL)
796 printf("%s\t[%08x]", regname2[i],
797 emu_rdptr(sc, v->vnum, i + 0x70));
798 printf("%s", (x == 2)? "\n" : "\t");
808 /* channel interface */
810 emupchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
811 struct pcm_channel *c, int dir)
813 struct sc_info *sc = devinfo;
814 struct sc_pchinfo *ch;
817 KASSERT(dir == PCMDIR_PLAY, ("emupchan_init: bad direction"));
818 ch = &sc->pch[sc->pnum++];
822 ch->blksz = sc->bufsz / 2;
823 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
825 snd_mtxlock(sc->lock);
826 ch->master = emu_valloc(sc);
827 ch->slave = emu_valloc(sc);
828 snd_mtxunlock(sc->lock);
829 r = (emu_vinit(sc, ch->master, ch->slave, sc->bufsz, ch->buffer))
836 emupchan_free(kobj_t obj, void *data)
838 struct sc_pchinfo *ch = data;
839 struct sc_info *sc = ch->parent;
842 snd_mtxlock(sc->lock);
843 r = emu_memfree(sc, sndbuf_getbuf(ch->buffer));
844 snd_mtxunlock(sc->lock);
850 emupchan_setformat(kobj_t obj, void *data, u_int32_t format)
852 struct sc_pchinfo *ch = data;
859 emupchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
861 struct sc_pchinfo *ch = data;
868 emupchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
870 struct sc_pchinfo *ch = data;
871 struct sc_info *sc = ch->parent;
874 ch->blksz = blocksize;
875 snd_mtxlock(sc->lock);
877 irqrate = 48000 / sc->timerinterval;
878 snd_mtxunlock(sc->lock);
879 blksz = (ch->spd * sndbuf_getalign(ch->buffer)) / irqrate;
884 emupchan_trigger(kobj_t obj, void *data, int go)
886 struct sc_pchinfo *ch = data;
887 struct sc_info *sc = ch->parent;
889 if (!PCMTRIG_COMMON(go))
892 snd_mtxlock(sc->lock);
893 if (go == PCMTRIG_START) {
895 emu_vwrite(sc, ch->master);
899 printf("start [%d bit, %s, %d hz]\n",
900 ch->master->b16 ? 16 : 8,
901 ch->master->stereo ? "stereo" : "mono",
903 emu_vdump(sc, ch->master);
904 emu_vdump(sc, ch->slave);
907 ch->run = (go == PCMTRIG_START) ? 1 : 0;
908 emu_vtrigger(sc, ch->master, ch->run);
909 snd_mtxunlock(sc->lock);
914 emupchan_getptr(kobj_t obj, void *data)
916 struct sc_pchinfo *ch = data;
917 struct sc_info *sc = ch->parent;
920 snd_mtxlock(sc->lock);
921 r = emu_vpos(sc, ch->master);
922 snd_mtxunlock(sc->lock);
927 static struct pcmchan_caps *
928 emupchan_getcaps(kobj_t obj, void *data)
930 return &emu_playcaps;
933 static kobj_method_t emupchan_methods[] = {
934 KOBJMETHOD(channel_init, emupchan_init),
935 KOBJMETHOD(channel_free, emupchan_free),
936 KOBJMETHOD(channel_setformat, emupchan_setformat),
937 KOBJMETHOD(channel_setspeed, emupchan_setspeed),
938 KOBJMETHOD(channel_setblocksize, emupchan_setblocksize),
939 KOBJMETHOD(channel_trigger, emupchan_trigger),
940 KOBJMETHOD(channel_getptr, emupchan_getptr),
941 KOBJMETHOD(channel_getcaps, emupchan_getcaps),
944 CHANNEL_DECLARE(emupchan);
946 /* channel interface */
948 emurchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
949 struct pcm_channel *c, int dir)
951 struct sc_info *sc = devinfo;
952 struct sc_rchinfo *ch;
954 KASSERT(dir == PCMDIR_REC, ("emurchan_init: bad direction"));
955 ch = &sc->rch[sc->rnum];
959 ch->blksz = sc->bufsz / 2;
960 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
965 ch->idxreg = sc->audigy ? EMU_A_ADCIDX : EMU_ADCIDX;
966 ch->basereg = EMU_ADCBA;
967 ch->sizereg = EMU_ADCBS;
968 ch->setupreg = EMU_ADCCR;
969 ch->irqmask = EMU_INTE_ADCBUFENABLE;
973 ch->idxreg = EMU_FXIDX;
974 ch->basereg = EMU_FXBA;
975 ch->sizereg = EMU_FXBS;
976 ch->setupreg = EMU_FXWC;
977 ch->irqmask = EMU_INTE_EFXBUFENABLE;
981 ch->idxreg = EMU_MICIDX;
982 ch->basereg = EMU_MICBA;
983 ch->sizereg = EMU_MICBS;
985 ch->irqmask = EMU_INTE_MICBUFENABLE;
989 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0)
992 snd_mtxlock(sc->lock);
993 emu_wrptr(sc, 0, ch->basereg, sndbuf_getbufaddr(ch->buffer));
994 emu_wrptr(sc, 0, ch->sizereg, 0); /* off */
995 snd_mtxunlock(sc->lock);
1001 emurchan_setformat(kobj_t obj, void *data, u_int32_t format)
1003 struct sc_rchinfo *ch = data;
1010 emurchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
1012 struct sc_rchinfo *ch = data;
1015 if (ch->parent->audigy)
1016 speed = audigy_adcspeed[audigy_recval(speed)];
1018 speed = adcspeed[emu_recval(speed)];
1029 emurchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1031 struct sc_rchinfo *ch = data;
1032 struct sc_info *sc = ch->parent;
1035 ch->blksz = blocksize;
1036 snd_mtxlock(sc->lock);
1038 irqrate = 48000 / sc->timerinterval;
1039 snd_mtxunlock(sc->lock);
1040 blksz = (ch->spd * sndbuf_getalign(ch->buffer)) / irqrate;
1044 /* semantic note: must start at beginning of buffer */
1046 emurchan_trigger(kobj_t obj, void *data, int go)
1048 struct sc_rchinfo *ch = data;
1049 struct sc_info *sc = ch->parent;
1052 if (!PCMTRIG_COMMON(go))
1057 sz = EMU_RECBS_BUFSIZE_4096;
1061 sz = EMU_RECBS_BUFSIZE_8192;
1065 sz = EMU_RECBS_BUFSIZE_16384;
1069 sz = EMU_RECBS_BUFSIZE_32768;
1073 sz = EMU_RECBS_BUFSIZE_65536;
1077 sz = EMU_RECBS_BUFSIZE_4096;
1080 snd_mtxlock(sc->lock);
1084 emu_wrptr(sc, 0, ch->sizereg, sz);
1087 val = EMU_A_ADCCR_LCHANENABLE;
1088 if (AFMT_CHANNEL(ch->fmt) > 1)
1089 val |= EMU_A_ADCCR_RCHANENABLE;
1090 val |= audigy_recval(ch->spd);
1092 val = EMU_ADCCR_LCHANENABLE;
1093 if (AFMT_CHANNEL(ch->fmt) > 1)
1094 val |= EMU_ADCCR_RCHANENABLE;
1095 val |= emu_recval(ch->spd);
1098 emu_wrptr(sc, 0, ch->setupreg, 0);
1099 emu_wrptr(sc, 0, ch->setupreg, val);
1101 val = emu_rd(sc, EMU_INTE, 4);
1103 emu_wr(sc, EMU_INTE, val, 4);
1109 emu_wrptr(sc, 0, ch->sizereg, 0);
1111 emu_wrptr(sc, 0, ch->setupreg, 0);
1112 val = emu_rd(sc, EMU_INTE, 4);
1113 val &= ~ch->irqmask;
1114 emu_wr(sc, EMU_INTE, val, 4);
1117 case PCMTRIG_EMLDMAWR:
1118 case PCMTRIG_EMLDMARD:
1122 snd_mtxunlock(sc->lock);
1128 emurchan_getptr(kobj_t obj, void *data)
1130 struct sc_rchinfo *ch = data;
1131 struct sc_info *sc = ch->parent;
1134 snd_mtxlock(sc->lock);
1135 r = emu_rdptr(sc, 0, ch->idxreg) & 0x0000ffff;
1136 snd_mtxunlock(sc->lock);
1141 static struct pcmchan_caps *
1142 emurchan_getcaps(kobj_t obj, void *data)
1144 struct sc_rchinfo *ch = data;
1146 return &emu_reccaps[ch->num];
1149 static kobj_method_t emurchan_methods[] = {
1150 KOBJMETHOD(channel_init, emurchan_init),
1151 KOBJMETHOD(channel_setformat, emurchan_setformat),
1152 KOBJMETHOD(channel_setspeed, emurchan_setspeed),
1153 KOBJMETHOD(channel_setblocksize, emurchan_setblocksize),
1154 KOBJMETHOD(channel_trigger, emurchan_trigger),
1155 KOBJMETHOD(channel_getptr, emurchan_getptr),
1156 KOBJMETHOD(channel_getcaps, emurchan_getcaps),
1159 CHANNEL_DECLARE(emurchan);
1161 static unsigned char
1162 emu_mread(struct mpu401 *arg, void *sc, int reg)
1166 d = emu_rd((struct sc_info *)sc, 0x18 + reg, 1);
1171 emu_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b)
1174 emu_wr((struct sc_info *)sc, 0x18 + reg, b, 1);
1178 emu_muninit(struct mpu401 *arg, void *cookie)
1180 struct sc_info *sc = cookie;
1182 snd_mtxlock(sc->lock);
1183 sc->mpu_intr = NULL;
1184 snd_mtxunlock(sc->lock);
1189 static kobj_method_t emu_mpu_methods[] = {
1190 KOBJMETHOD(mpufoi_read, emu_mread),
1191 KOBJMETHOD(mpufoi_write, emu_mwrite),
1192 KOBJMETHOD(mpufoi_uninit, emu_muninit),
1196 static DEFINE_CLASS(emu_mpu, emu_mpu_methods, 0);
1201 struct sc_info *sc = (struct sc_info *)p;
1204 (sc->mpu_intr)(sc->mpu);
1208 emu_midiattach(struct sc_info *sc)
1212 i = emu_rd(sc, EMU_INTE, 4);
1213 i |= EMU_INTE_MIDIRXENABLE;
1214 emu_wr(sc, EMU_INTE, i, 4);
1216 sc->mpu = mpu401_init(&emu_mpu_class, sc, emu_intr2, &sc->mpu_intr);
1218 /* -------------------------------------------------------------------- */
1219 /* The interrupt handler */
1222 emu_intr(void *data)
1224 struct sc_info *sc = data;
1225 u_int32_t stat, ack, i, x;
1227 snd_mtxlock(sc->lock);
1229 stat = emu_rd(sc, EMU_IPR, 4);
1235 if (stat & EMU_IPR_INTERVALTIMER)
1236 ack |= EMU_IPR_INTERVALTIMER;
1238 if (stat & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL))
1239 ack |= stat & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL);
1241 if (stat & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL))
1242 ack |= stat & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL);
1244 if (stat & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL))
1245 ack |= stat & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL);
1247 if (stat & EMU_PCIERROR) {
1248 ack |= EMU_PCIERROR;
1249 device_printf(sc->dev, "pci error\n");
1250 /* we still get an nmi with ecc ram even if we ack this */
1252 if (stat & EMU_IPR_RATETRCHANGE) {
1253 ack |= EMU_IPR_RATETRCHANGE;
1255 device_printf(sc->dev,
1256 "sample rate tracker lock status change\n");
1260 if (stat & EMU_IPR_MIDIRECVBUFE) {
1262 (sc->mpu_intr)(sc->mpu);
1263 ack |= EMU_IPR_MIDIRECVBUFE | EMU_IPR_MIDITRANSBUFE;
1267 device_printf(sc->dev, "dodgy irq: %x (harmless)\n",
1270 emu_wr(sc, EMU_IPR, stat, 4);
1273 snd_mtxunlock(sc->lock);
1275 if (ack & EMU_IPR_INTERVALTIMER) {
1277 for (i = 0; i < sc->nchans; i++) {
1278 if (sc->pch[i].run) {
1280 chn_intr(sc->pch[i].channel);
1284 emu_enatimer(sc, 0);
1287 if (ack & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL)) {
1288 if (sc->rch[0].channel)
1289 chn_intr(sc->rch[0].channel);
1291 if (ack & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL)) {
1292 if (sc->rch[1].channel)
1293 chn_intr(sc->rch[1].channel);
1295 if (ack & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL)) {
1296 if (sc->rch[2].channel)
1297 chn_intr(sc->rch[2].channel);
1300 snd_mtxlock(sc->lock);
1303 snd_mtxunlock(sc->lock);
1306 /* -------------------------------------------------------------------- */
1309 emu_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1311 bus_addr_t *phys = arg;
1313 *phys = error ? 0 : (bus_addr_t)segs->ds_addr;
1316 printf("emu: setmap (%lx, %lx), nseg=%d, error=%d\n",
1317 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
1323 emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr,
1329 if (bus_dmamem_alloc(sc->parent_dmat, &buf, BUS_DMA_NOWAIT, map))
1331 if (bus_dmamap_load(sc->parent_dmat, *map, buf, sz, emu_setmap, addr, 0)
1333 bus_dmamem_free(sc->parent_dmat, buf, *map);
1340 emu_free(struct sc_info *sc, void *buf, bus_dmamap_t map)
1342 bus_dmamap_unload(sc->parent_dmat, map);
1343 bus_dmamem_free(sc->parent_dmat, buf, map);
1347 emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr)
1349 u_int32_t blksz, start, idx, ofs, tmp, found;
1350 struct emu_mem *mem = &sc->mem;
1351 struct emu_memblk *blk;
1354 blksz = sz / EMUPAGESIZE;
1355 if (sz > (blksz * EMUPAGESIZE))
1357 /* find a free block in the bitmap */
1360 while (!found && start + blksz < EMUMAXPAGES) {
1362 for (idx = start; idx < start + blksz; idx++)
1363 if (mem->bmap[idx >> 3] & (1 << (idx & 7)))
1370 blk = malloc(sizeof(*blk), M_DEVBUF, M_NOWAIT);
1373 buf = emu_malloc(sc, sz, &blk->buf_addr, &blk->buf_map);
1374 *addr = blk->buf_addr;
1376 free(blk, M_DEVBUF);
1380 blk->pte_start = start;
1381 blk->pte_size = blksz;
1383 printf("buf %p, pte_start %d, pte_size %d\n", blk->buf,
1384 blk->pte_start, blk->pte_size);
1387 for (idx = start; idx < start + blksz; idx++) {
1388 mem->bmap[idx >> 3] |= 1 << (idx & 7);
1389 tmp = (uint32_t)(blk->buf_addr + ofs);
1391 printf("pte[%d] -> %x phys, %x virt\n", idx, tmp,
1392 ((u_int32_t)buf) + ofs);
1394 mem->ptb_pages[idx] = (tmp << 1) | idx;
1397 SLIST_INSERT_HEAD(&mem->blocks, blk, link);
1402 emu_memfree(struct sc_info *sc, void *buf)
1405 struct emu_mem *mem = &sc->mem;
1406 struct emu_memblk *blk, *i;
1409 SLIST_FOREACH(i, &mem->blocks, link) {
1415 SLIST_REMOVE(&mem->blocks, blk, emu_memblk, link);
1416 emu_free(sc, buf, blk->buf_map);
1417 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1;
1418 for (idx = blk->pte_start; idx < blk->pte_start + blk->pte_size; idx++) {
1419 mem->bmap[idx >> 3] &= ~(1 << (idx & 7));
1420 mem->ptb_pages[idx] = tmp | idx;
1422 free(blk, M_DEVBUF);
1427 emu_memstart(struct sc_info *sc, void *buf)
1429 struct emu_mem *mem = &sc->mem;
1430 struct emu_memblk *blk, *i;
1433 SLIST_FOREACH(i, &mem->blocks, link) {
1439 return blk->pte_start;
1443 emu_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y,
1446 emu_wrefx(sc, (*pc) * 2, (x << 10) | y);
1447 emu_wrefx(sc, (*pc) * 2 + 1, (op << 20) | (z << 10) | w);
1452 audigy_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y,
1455 emu_wrefx(sc, (*pc) * 2, (x << 12) | y);
1456 emu_wrefx(sc, (*pc) * 2 + 1, (op << 24) | (z << 12) | w);
1461 audigy_initefx(struct sc_info *sc)
1466 /* skip 0, 0, -1, 0 - NOPs */
1467 for (i = 0; i < 512; i++)
1468 audigy_addefxop(sc, 0x0f, 0x0c0, 0x0c0, 0x0cf, 0x0c0, &pc);
1470 for (i = 0; i < 512; i++)
1471 emu_wrptr(sc, 0, EMU_A_FXGPREGBASE + i, 0x0);
1475 /* stop fx processor */
1476 emu_wrptr(sc, 0, EMU_A_DBG, EMU_A_DBG_SINGLE_STEP);
1478 /* Audigy 2 (EMU10K2) DSP Registers:
1480 0x000-0x00f : 16 registers (?)
1482 0x040/0x041 : AC97 Codec (l/r)
1483 0x042/0x043 : ADC, S/PDIF (l/r)
1484 0x044/0x045 : Optical S/PDIF in (l/r)
1486 0x048/0x049 : Line/Mic 2 (l/r)
1487 0x04a/0x04b : RCA S/PDIF (l/r)
1488 0x04c/0x04d : Aux 2 (l/r)
1490 0x060/0x061 : Digital Front (l/r)
1491 0x062/0x063 : Digital Center/LFE
1492 0x064/0x065 : AudigyDrive Heaphone (l/r)
1493 0x066/0x067 : Digital Rear (l/r)
1494 0x068/0x069 : Analog Front (l/r)
1495 0x06a/0x06b : Analog Center/LFE
1497 0x06e/0x06f : Analog Rear (l/r)
1498 0x070/0x071 : AC97 Output (l/r)
1501 0x076/0x077 : ADC Recording Buffer (l/r)
1503 0x0c0 - 0x0c4 = 0 - 4
1504 0x0c5 = 0x8, 0x0c6 = 0x10, 0x0c7 = 0x20
1505 0x0c8 = 0x100, 0x0c9 = 0x10000, 0x0ca = 0x80000
1506 0x0cb = 0x10000000, 0x0cc = 0x20000000, 0x0cd = 0x40000000
1507 0x0ce = 0x80000000, 0x0cf = 0x7fffffff, 0x0d0 = 0xffffffff
1508 0x0d1 = 0xfffffffe, 0x0d2 = 0xc0000000, 0x0d3 = 0x41fbbcdc
1509 0x0d4 = 0x5a7ef9db, 0x0d5 = 0x00100000, 0x0dc = 0x00000001 (?)
1511 0x0d6 : Accumulator (?)
1512 0x0d7 : Condition Register
1513 0x0d8 : Noise source
1514 0x0d9 : Noise source
1515 Tank Memory Data Registers
1517 Tank Memory Address Registers
1519 General Purpose Registers
1523 /* AC97Output[l/r] = FXBus PCM[l/r] */
1524 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_L), A_C_00000000,
1525 A_C_00000000, A_FXBUS(FXBUS_PCM_LEFT), &pc);
1526 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_R), A_C_00000000,
1527 A_C_00000000, A_FXBUS(FXBUS_PCM_RIGHT), &pc);
1529 /* GPR[0/1] = RCA S/PDIF[l/r] -- Master volume */
1530 audigy_addefxop(sc, iACC3, A_GPR(0), A_C_00000000,
1531 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_L), &pc);
1532 audigy_addefxop(sc, iACC3, A_GPR(1), A_C_00000000,
1533 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_R), &pc);
1535 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */
1536 audigy_addefxop(sc, iINTERP, A_GPR(2), A_GPR(1),
1537 A_C_40000000, A_GPR(0), &pc);
1539 /* Headphones[l/r] = GPR[0/1] */
1540 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_L),
1541 A_C_00000000, A_C_00000000, A_GPR(0), &pc);
1542 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_R),
1543 A_C_00000000, A_C_00000000, A_GPR(1), &pc);
1545 /* Analog Front[l/r] = GPR[0/1] */
1546 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_L), A_C_00000000,
1547 A_C_00000000, A_GPR(0), &pc);
1548 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_R), A_C_00000000,
1549 A_C_00000000, A_GPR(1), &pc);
1551 /* Digital Front[l/r] = GPR[0/1] */
1552 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L), A_C_00000000,
1553 A_C_00000000, A_GPR(0), &pc);
1554 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_R), A_C_00000000,
1555 A_C_00000000, A_GPR(1), &pc);
1557 /* Center and Subwoofer configuration */
1558 /* Analog Center = GPR[0] + GPR[2] */
1559 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ACENTER), A_C_00000000,
1560 A_GPR(0), A_GPR(2), &pc);
1561 /* Analog Sub = GPR[1] + GPR[2] */
1562 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ALFE), A_C_00000000,
1563 A_GPR(1), A_GPR(2), &pc);
1565 /* Digital Center = GPR[0] + GPR[2] */
1566 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_CENTER), A_C_00000000,
1567 A_GPR(0), A_GPR(2), &pc);
1568 /* Digital Sub = GPR[1] + GPR[2] */
1569 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_LFE), A_C_00000000,
1570 A_GPR(1), A_GPR(2), &pc);
1573 /* Analog Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */
1574 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */
1575 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000,
1576 A_GPR(16), A_GPR(0), &pc);
1577 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000,
1578 A_GPR(17), A_GPR(1), &pc);
1580 /* Digital Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */
1581 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */
1582 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000,
1583 A_GPR(16), A_GPR(0), &pc);
1584 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000,
1585 A_GPR(17), A_GPR(1), &pc);
1587 /* XXX This is just a copy to the channel, since we do not have
1588 * a patch manager, it is useful for have another output enabled.
1591 /* Analog Rear[l/r] = GPR[0/1] */
1592 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000,
1593 A_C_00000000, A_GPR(0), &pc);
1594 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000,
1595 A_C_00000000, A_GPR(1), &pc);
1597 /* Digital Rear[l/r] = GPR[0/1] */
1598 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000,
1599 A_C_00000000, A_GPR(0), &pc);
1600 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000,
1601 A_C_00000000, A_GPR(1), &pc);
1604 /* ADC Recording buffer[l/r] = AC97Input[l/r] */
1605 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_L), A_C_00000000,
1606 A_C_00000000, A_EXTIN(A_EXTIN_AC97_L), &pc);
1607 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_R), A_C_00000000,
1608 A_C_00000000, A_EXTIN(A_EXTIN_AC97_R), &pc);
1610 /* resume normal operations */
1611 emu_wrptr(sc, 0, EMU_A_DBG, 0);
1615 emu_initefx(struct sc_info *sc)
1620 /* acc3 0,0,0,0 - NOPs */
1621 for (i = 0; i < 512; i++) {
1622 emu_wrefx(sc, i * 2, 0x10040);
1623 emu_wrefx(sc, i * 2 + 1, 0x610040);
1626 for (i = 0; i < 256; i++)
1627 emu_wrptr(sc, 0, EMU_FXGPREGBASE + i, 0);
1629 /* FX-8010 DSP Registers:
1631 0x000-0x00f : 16 registers
1633 0x010/0x011 : AC97 Codec (l/r)
1634 0x012/0x013 : ADC, S/PDIF (l/r)
1635 0x014/0x015 : Mic(left), Zoom (l/r)
1636 0x016/0x017 : TOS link in (l/r)
1637 0x018/0x019 : Line/Mic 1 (l/r)
1638 0x01a/0x01b : COAX S/PDIF (l/r)
1639 0x01c/0x01d : Line/Mic 2 (l/r)
1641 0x020/0x021 : AC97 Output (l/r)
1642 0x022/0x023 : TOS link out (l/r)
1643 0x024/0x025 : Center/LFE
1644 0x026/0x027 : LiveDrive Headphone (l/r)
1645 0x028/0x029 : Rear Channel (l/r)
1646 0x02a/0x02b : ADC Recording Buffer (l/r)
1647 0x02c : Mic Recording Buffer
1648 0x031/0x032 : Analog Center/LFE
1650 0x040 - 0x044 = 0 - 4
1651 0x045 = 0x8, 0x046 = 0x10, 0x047 = 0x20
1652 0x048 = 0x100, 0x049 = 0x10000, 0x04a = 0x80000
1653 0x04b = 0x10000000, 0x04c = 0x20000000, 0x04d = 0x40000000
1654 0x04e = 0x80000000, 0x04f = 0x7fffffff, 0x050 = 0xffffffff
1655 0x051 = 0xfffffffe, 0x052 = 0xc0000000, 0x053 = 0x41fbbcdc
1656 0x054 = 0x5a7ef9db, 0x055 = 0x00100000
1659 0x057 : Condition Register
1660 0x058 : Noise source
1661 0x059 : Noise source
1662 0x05a : IRQ Register
1663 0x05b : TRAM Delay Base Address Count
1664 General Purpose Registers
1666 Tank Memory Data Registers
1668 Tank Memory Address Registers
1672 /* Routing - this will be configurable in later version */
1674 /* GPR[0/1] = FX * 4 + SPDIF-in */
1675 emu_addefxop(sc, iMACINT0, GPR(0), EXTIN(EXTIN_SPDIF_CD_L),
1676 FXBUS(FXBUS_PCM_LEFT), C_00000004, &pc);
1677 emu_addefxop(sc, iMACINT0, GPR(1), EXTIN(EXTIN_SPDIF_CD_R),
1678 FXBUS(FXBUS_PCM_RIGHT), C_00000004, &pc);
1680 /* GPR[0/1] += APS-input */
1681 emu_addefxop(sc, iACC3, GPR(0), GPR(0), C_00000000,
1682 sc->APS ? EXTIN(EXTIN_TOSLINK_L) : C_00000000, &pc);
1683 emu_addefxop(sc, iACC3, GPR(1), GPR(1), C_00000000,
1684 sc->APS ? EXTIN(EXTIN_TOSLINK_R) : C_00000000, &pc);
1686 /* FrontOut (AC97) = GPR[0/1] */
1687 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_L), C_00000000,
1688 C_00000000, GPR(0), &pc);
1689 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_R), C_00000000,
1690 C_00000001, GPR(1), &pc);
1692 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */
1693 emu_addefxop(sc, iINTERP, GPR(2), GPR(1), C_40000000, GPR(0), &pc);
1696 /* RearOut = (GPR[0/1] * RearVolume) >> 31 */
1697 /* RearVolume = GPR[0x10/0x11] */
1698 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_L), C_00000000,
1699 GPR(16), GPR(0), &pc);
1700 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_R), C_00000000,
1701 GPR(17), GPR(1), &pc);
1703 /* XXX This is just a copy to the channel, since we do not have
1704 * a patch manager, it is useful for have another output enabled.
1707 /* Rear[l/r] = GPR[0/1] */
1708 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_L), C_00000000,
1709 C_00000000, GPR(0), &pc);
1710 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_R), C_00000000,
1711 C_00000000, GPR(1), &pc);
1714 /* TOS out[l/r] = GPR[0/1] */
1715 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_L), C_00000000,
1716 C_00000000, GPR(0), &pc);
1717 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_R), C_00000000,
1718 C_00000000, GPR(1), &pc);
1720 /* Center and Subwoofer configuration */
1721 /* Analog Center = GPR[0] + GPR[2] */
1722 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ACENTER), C_00000000,
1723 GPR(0), GPR(2), &pc);
1724 /* Analog Sub = GPR[1] + GPR[2] */
1725 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ALFE), C_00000000,
1726 GPR(1), GPR(2), &pc);
1727 /* Digital Center = GPR[0] + GPR[2] */
1728 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_CENTER), C_00000000,
1729 GPR(0), GPR(2), &pc);
1730 /* Digital Sub = GPR[1] + GPR[2] */
1731 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_LFE), C_00000000,
1732 GPR(1), GPR(2), &pc);
1734 /* Headphones[l/r] = GPR[0/1] */
1735 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_L), C_00000000,
1736 C_00000000, GPR(0), &pc);
1737 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_R), C_00000000,
1738 C_00000000, GPR(1), &pc);
1740 /* ADC Recording buffer[l/r] = AC97Input[l/r] */
1741 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_L), C_00000000,
1742 C_00000000, EXTIN(EXTIN_AC97_L), &pc);
1743 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_R), C_00000000,
1744 C_00000000, EXTIN(EXTIN_AC97_R), &pc);
1746 /* resume normal operations */
1747 emu_wrptr(sc, 0, EMU_DBG, 0);
1750 /* Probe and attach the card */
1752 emu_init(struct sc_info *sc)
1754 u_int32_t spcs, ch, tmp, i;
1757 /* enable additional AC97 slots */
1758 emu_wrptr(sc, 0, EMU_AC97SLOT, EMU_AC97SLOT_CENTER | EMU_AC97SLOT_LFE);
1761 /* disable audio and lock cache */
1762 emu_wr(sc, EMU_HCFG,
1763 EMU_HCFG_LOCKSOUNDCACHE | EMU_HCFG_LOCKTANKCACHE_MASK | EMU_HCFG_MUTEBUTTONENABLE,
1766 /* reset recording buffers */
1767 emu_wrptr(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE);
1768 emu_wrptr(sc, 0, EMU_MICBA, 0);
1769 emu_wrptr(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE);
1770 emu_wrptr(sc, 0, EMU_FXBA, 0);
1771 emu_wrptr(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE);
1772 emu_wrptr(sc, 0, EMU_ADCBA, 0);
1774 /* disable channel interrupt */
1775 emu_wr(sc, EMU_INTE,
1776 EMU_INTE_INTERTIMERENB | EMU_INTE_SAMPLERATER | EMU_INTE_PCIERRENABLE,
1778 emu_wrptr(sc, 0, EMU_CLIEL, 0);
1779 emu_wrptr(sc, 0, EMU_CLIEH, 0);
1780 emu_wrptr(sc, 0, EMU_SOLEL, 0);
1781 emu_wrptr(sc, 0, EMU_SOLEH, 0);
1783 /* wonder what these do... */
1785 emu_wrptr(sc, 0, EMU_SPBYPASS, 0xf00);
1786 emu_wrptr(sc, 0, EMU_AC97SLOT, 0x3);
1789 /* init envelope engine */
1790 for (ch = 0; ch < NUM_G; ch++) {
1791 emu_wrptr(sc, ch, EMU_CHAN_DCYSUSV, ENV_OFF);
1792 emu_wrptr(sc, ch, EMU_CHAN_IP, 0);
1793 emu_wrptr(sc, ch, EMU_CHAN_VTFT, 0xffff);
1794 emu_wrptr(sc, ch, EMU_CHAN_CVCF, 0xffff);
1795 emu_wrptr(sc, ch, EMU_CHAN_PTRX, 0);
1796 emu_wrptr(sc, ch, EMU_CHAN_CPF, 0);
1797 emu_wrptr(sc, ch, EMU_CHAN_CCR, 0);
1799 emu_wrptr(sc, ch, EMU_CHAN_PSST, 0);
1800 emu_wrptr(sc, ch, EMU_CHAN_DSL, 0x10);
1801 emu_wrptr(sc, ch, EMU_CHAN_CCCA, 0);
1802 emu_wrptr(sc, ch, EMU_CHAN_Z1, 0);
1803 emu_wrptr(sc, ch, EMU_CHAN_Z2, 0);
1804 emu_wrptr(sc, ch, EMU_CHAN_FXRT, 0xd01c0000);
1806 emu_wrptr(sc, ch, EMU_CHAN_ATKHLDM, 0);
1807 emu_wrptr(sc, ch, EMU_CHAN_DCYSUSM, 0);
1808 emu_wrptr(sc, ch, EMU_CHAN_IFATN, 0xffff);
1809 emu_wrptr(sc, ch, EMU_CHAN_PEFE, 0);
1810 emu_wrptr(sc, ch, EMU_CHAN_FMMOD, 0);
1811 emu_wrptr(sc, ch, EMU_CHAN_TREMFRQ, 24); /* 1 Hz */
1812 emu_wrptr(sc, ch, EMU_CHAN_FM2FRQ2, 24); /* 1 Hz */
1813 emu_wrptr(sc, ch, EMU_CHAN_TEMPENV, 0);
1815 /*** these are last so OFF prevents writing ***/
1816 emu_wrptr(sc, ch, EMU_CHAN_LFOVAL2, 0);
1817 emu_wrptr(sc, ch, EMU_CHAN_LFOVAL1, 0);
1818 emu_wrptr(sc, ch, EMU_CHAN_ATKHLDV, 0);
1819 emu_wrptr(sc, ch, EMU_CHAN_ENVVOL, 0);
1820 emu_wrptr(sc, ch, EMU_CHAN_ENVVAL, 0);
1823 /* audigy cards need this to initialize correctly */
1824 emu_wrptr(sc, ch, 0x4c, 0);
1825 emu_wrptr(sc, ch, 0x4d, 0);
1826 emu_wrptr(sc, ch, 0x4e, 0);
1827 emu_wrptr(sc, ch, 0x4f, 0);
1828 /* set default routing */
1829 emu_wrptr(sc, ch, EMU_A_CHAN_FXRT1, 0x03020100);
1830 emu_wrptr(sc, ch, EMU_A_CHAN_FXRT2, 0x3f3f3f3f);
1831 emu_wrptr(sc, ch, EMU_A_CHAN_SENDAMOUNTS, 0);
1834 sc->voice[ch].vnum = ch;
1835 sc->voice[ch].slave = NULL;
1836 sc->voice[ch].busy = 0;
1837 sc->voice[ch].ismaster = 0;
1838 sc->voice[ch].running = 0;
1839 sc->voice[ch].b16 = 0;
1840 sc->voice[ch].stereo = 0;
1841 sc->voice[ch].speed = 0;
1842 sc->voice[ch].start = 0;
1843 sc->voice[ch].end = 0;
1844 sc->voice[ch].channel = NULL;
1846 sc->pnum = sc->rnum = 0;
1849 * Init to 0x02109204 :
1850 * Clock accuracy = 0 (1000ppm)
1851 * Sample Rate = 2 (48kHz)
1852 * Audio Channel = 1 (Left of 2)
1853 * Source Number = 0 (Unspecified)
1854 * Generation Status = 1 (Original for Cat Code 12)
1855 * Cat Code = 12 (Digital Signal Mixer)
1857 * Emphasis = 0 (None)
1858 * CP = 1 (Copyright unasserted)
1859 * AN = 0 (Audio data)
1862 spcs = EMU_SPCS_CLKACCY_1000PPM | EMU_SPCS_SAMPLERATE_48 |
1863 EMU_SPCS_CHANNELNUM_LEFT | EMU_SPCS_SOURCENUM_UNSPEC |
1864 EMU_SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 |
1865 EMU_SPCS_EMPHASIS_NONE | EMU_SPCS_COPYRIGHT;
1866 emu_wrptr(sc, 0, EMU_SPCS0, spcs);
1867 emu_wrptr(sc, 0, EMU_SPCS1, spcs);
1868 emu_wrptr(sc, 0, EMU_SPCS2, spcs);
1872 else if (sc->audigy2) { /* Audigy 2 */
1873 /* from ALSA initialization code: */
1875 /* Hack for Alice3 to work independent of haP16V driver */
1878 /* Setup SRCMulti_I2S SamplingRate */
1879 tmp = emu_rdptr(sc, 0, EMU_A_SPDIF_SAMPLERATE) & 0xfffff1ff;
1880 emu_wrptr(sc, 0, EMU_A_SPDIF_SAMPLERATE, tmp | 0x400);
1882 /* Setup SRCSel (Enable SPDIF, I2S SRCMulti) */
1883 emu_wr(sc, 0x20, 0x00600000, 4);
1884 emu_wr(sc, 0x24, 0x00000014, 4);
1886 /* Setup SRCMulti Input Audio Enable */
1887 emu_wr(sc, 0x20, 0x006e0000, 4);
1888 emu_wr(sc, 0x24, 0xff00ff00, 4);
1891 SLIST_INIT(&sc->mem.blocks);
1892 sc->mem.ptb_pages = emu_malloc(sc, EMUMAXPAGES * sizeof(u_int32_t),
1893 &sc->mem.ptb_pages_addr, &sc->mem.ptb_map);
1894 if (sc->mem.ptb_pages == NULL)
1897 sc->mem.silent_page = emu_malloc(sc, EMUPAGESIZE,
1898 &sc->mem.silent_page_addr, &sc->mem.silent_map);
1899 if (sc->mem.silent_page == NULL) {
1900 emu_free(sc, sc->mem.ptb_pages, sc->mem.ptb_map);
1903 /* Clear page with silence & setup all pointers to this page */
1904 bzero(sc->mem.silent_page, EMUPAGESIZE);
1905 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1;
1906 for (i = 0; i < EMUMAXPAGES; i++)
1907 sc->mem.ptb_pages[i] = tmp | i;
1909 emu_wrptr(sc, 0, EMU_PTB, (sc->mem.ptb_pages_addr));
1910 emu_wrptr(sc, 0, EMU_TCB, 0); /* taken from original driver */
1911 emu_wrptr(sc, 0, EMU_TCBS, 0); /* taken from original driver */
1913 for (ch = 0; ch < NUM_G; ch++) {
1914 emu_wrptr(sc, ch, EMU_CHAN_MAPA, tmp | EMU_CHAN_MAP_PTI_MASK);
1915 emu_wrptr(sc, ch, EMU_CHAN_MAPB, tmp | EMU_CHAN_MAP_PTI_MASK);
1918 /* emu_memalloc(sc, EMUPAGESIZE); */
1920 * Hokay, now enable the AUD bit
1923 * Enable Audio = 0 (enabled after fx processor initialization)
1924 * Mute Disable Audio = 0
1929 * Mute Disable Audio = 0
1931 * GP S/PDIF AC3 Enable = 1
1932 * CD S/PDIF AC3 Enable = 1
1936 * Mute Disable Audio = 0
1937 * Lock Tank Memory = 1
1938 * Lock Sound Memory = 0
1943 tmp = EMU_HCFG_AUTOMUTE | EMU_HCFG_JOYENABLE;
1944 if (sc->audigy2) /* Audigy 2 */
1945 tmp = EMU_HCFG_AUDIOENABLE | EMU_HCFG_AC3ENABLE_CDSPDIF |
1946 EMU_HCFG_AC3ENABLE_GPSPDIF;
1947 emu_wr(sc, EMU_HCFG, tmp, 4);
1951 /* from ALSA initialization code: */
1953 /* enable audio and disable both audio/digital outputs */
1954 emu_wr(sc, EMU_HCFG, emu_rd(sc, EMU_HCFG, 4) | EMU_HCFG_AUDIOENABLE, 4);
1955 emu_wr(sc, EMU_A_IOCFG, emu_rd(sc, EMU_A_IOCFG, 4) & ~EMU_A_IOCFG_GPOUT_AD,
1957 if (sc->audigy2) { /* Audigy 2 */
1959 * Set GPO6 to 1 for Apollo. This has to be done after
1960 * init Alice3 I2SOut beyond 48kHz.
1961 * So, sequence is important.
1963 emu_wr(sc, EMU_A_IOCFG,
1964 emu_rd(sc, EMU_A_IOCFG, 4) | EMU_A_IOCFG_GPOUT_A, 4);
1967 /* EMU10K1 initialization code */
1968 tmp = EMU_HCFG_AUDIOENABLE | EMU_HCFG_LOCKTANKCACHE_MASK
1969 | EMU_HCFG_AUTOMUTE;
1971 tmp |= EMU_HCFG_JOYENABLE;
1973 emu_wr(sc, EMU_HCFG, tmp, 4);
1975 /* TOSLink detection */
1977 tmp = emu_rd(sc, EMU_HCFG, 4);
1978 if (tmp & (EMU_HCFG_GPINPUT0 | EMU_HCFG_GPINPUT1)) {
1979 emu_wr(sc, EMU_HCFG, tmp | EMU_HCFG_GPOUT1, 4);
1981 if (tmp != (emu_rd(sc, EMU_HCFG, 4) & ~EMU_HCFG_GPOUT1)) {
1983 emu_wr(sc, EMU_HCFG, tmp, 4);
1992 emu_uninit(struct sc_info *sc)
1996 emu_wr(sc, EMU_INTE, 0, 4);
1997 for (ch = 0; ch < NUM_G; ch++)
1998 emu_wrptr(sc, ch, EMU_CHAN_DCYSUSV, ENV_OFF);
1999 for (ch = 0; ch < NUM_G; ch++) {
2000 emu_wrptr(sc, ch, EMU_CHAN_VTFT, 0);
2001 emu_wrptr(sc, ch, EMU_CHAN_CVCF, 0);
2002 emu_wrptr(sc, ch, EMU_CHAN_PTRX, 0);
2003 emu_wrptr(sc, ch, EMU_CHAN_CPF, 0);
2006 if (sc->audigy) { /* stop fx processor */
2007 emu_wrptr(sc, 0, EMU_A_DBG, EMU_A_DBG_SINGLE_STEP);
2010 /* disable audio and lock cache */
2011 emu_wr(sc, EMU_HCFG,
2012 EMU_HCFG_LOCKSOUNDCACHE | EMU_HCFG_LOCKTANKCACHE_MASK | EMU_HCFG_MUTEBUTTONENABLE,
2015 emu_wrptr(sc, 0, EMU_PTB, 0);
2016 /* reset recording buffers */
2017 emu_wrptr(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE);
2018 emu_wrptr(sc, 0, EMU_MICBA, 0);
2019 emu_wrptr(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE);
2020 emu_wrptr(sc, 0, EMU_FXBA, 0);
2021 emu_wrptr(sc, 0, EMU_FXWC, 0);
2022 emu_wrptr(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE);
2023 emu_wrptr(sc, 0, EMU_ADCBA, 0);
2024 emu_wrptr(sc, 0, EMU_TCB, 0);
2025 emu_wrptr(sc, 0, EMU_TCBS, 0);
2027 /* disable channel interrupt */
2028 emu_wrptr(sc, 0, EMU_CLIEL, 0);
2029 emu_wrptr(sc, 0, EMU_CLIEH, 0);
2030 emu_wrptr(sc, 0, EMU_SOLEL, 0);
2031 emu_wrptr(sc, 0, EMU_SOLEH, 0);
2033 /* init envelope engine */
2034 if (!SLIST_EMPTY(&sc->mem.blocks))
2035 device_printf(sc->dev, "warning: memblock list not empty\n");
2036 emu_free(sc, sc->mem.ptb_pages, sc->mem.ptb_map);
2037 emu_free(sc, sc->mem.silent_page, sc->mem.silent_map);
2040 mpu401_uninit(sc->mpu);
2045 emu_pci_probe(device_t dev)
2049 switch (pci_get_devid(dev)) {
2050 case EMU10K1_PCI_ID:
2051 s = "Creative EMU10K1";
2054 case EMU10K2_PCI_ID:
2055 if (pci_get_revid(dev) == 0x04)
2056 s = "Creative Audigy 2 (EMU10K2)";
2058 s = "Creative Audigy (EMU10K2)";
2061 case EMU10K3_PCI_ID:
2062 s = "Creative Audigy 2 (EMU10K3)";
2069 device_set_desc(dev, s);
2070 return BUS_PROBE_LOW_PRIORITY;
2074 emu_pci_attach(device_t dev)
2076 struct ac97_info *codec = NULL;
2079 char status[SND_STATUSLEN];
2081 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
2082 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_emu10k1 softc");
2084 sc->type = pci_get_devid(dev);
2085 sc->rev = pci_get_revid(dev);
2086 sc->audigy = sc->type == EMU10K2_PCI_ID || sc->type == EMU10K3_PCI_ID;
2087 sc->audigy2 = (sc->audigy && sc->rev == 0x04);
2088 sc->nchans = sc->audigy ? 8 : 4;
2089 sc->addrmask = sc->audigy ? EMU_A_PTR_ADDR_MASK : EMU_PTR_ADDR_MASK;
2091 pci_enable_busmaster(dev);
2094 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE);
2095 if (sc->reg == NULL) {
2096 device_printf(dev, "unable to map register space\n");
2099 sc->st = rman_get_bustag(sc->reg);
2100 sc->sh = rman_get_bushandle(sc->reg);
2102 sc->bufsz = pcm_getbuffersize(dev, 4096, EMU_DEFAULT_BUFSZ, 65536);
2104 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
2106 /*lowaddr*/(1U << 31) - 1, /* can only access 0-2gb */
2107 /*highaddr*/BUS_SPACE_MAXADDR,
2108 /*filter*/NULL, /*filterarg*/NULL,
2109 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
2110 /*flags*/0, /*lockfunc*/busdma_lock_mutex,
2111 /*lockarg*/&Giant, &sc->parent_dmat) != 0) {
2112 device_printf(dev, "unable to create dma tag\n");
2116 if (emu_init(sc) == -1) {
2117 device_printf(dev, "unable to initialize the card\n");
2121 codec = AC97_CREATE(dev, sc, emu_ac97);
2122 if (codec == NULL) goto bad;
2123 gotmic = (ac97_getcaps(codec) & AC97_CAP_MICCHANNEL) ? 1 : 0;
2124 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad;
2129 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i,
2130 RF_ACTIVE | RF_SHAREABLE);
2132 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, emu_intr, sc, &sc->ih)) {
2133 device_printf(dev, "unable to map interrupt\n");
2137 snprintf(status, SND_STATUSLEN, "at io 0x%jx irq %jd %s",
2138 rman_get_start(sc->reg), rman_get_start(sc->irq),
2139 PCM_KLDSTRING(snd_emu10k1));
2141 if (pcm_register(dev, sc, sc->nchans, gotmic ? 3 : 2)) goto bad;
2142 for (i = 0; i < sc->nchans; i++)
2143 pcm_addchan(dev, PCMDIR_PLAY, &emupchan_class, sc);
2144 for (i = 0; i < (gotmic ? 3 : 2); i++)
2145 pcm_addchan(dev, PCMDIR_REC, &emurchan_class, sc);
2147 pcm_setstatus(dev, status);
2152 if (codec) ac97_destroy(codec);
2153 if (sc->reg) bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);
2154 if (sc->ih) bus_teardown_intr(dev, sc->irq, sc->ih);
2155 if (sc->irq) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
2156 if (sc->parent_dmat) bus_dma_tag_destroy(sc->parent_dmat);
2157 if (sc->lock) snd_mtxfree(sc->lock);
2163 emu_pci_detach(device_t dev)
2168 r = pcm_unregister(dev);
2172 sc = pcm_getdevinfo(dev);
2176 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);
2177 bus_teardown_intr(dev, sc->irq, sc->ih);
2178 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
2179 bus_dma_tag_destroy(sc->parent_dmat);
2180 snd_mtxfree(sc->lock);
2186 /* add suspend, resume */
2187 static device_method_t emu_methods[] = {
2188 /* Device interface */
2189 DEVMETHOD(device_probe, emu_pci_probe),
2190 DEVMETHOD(device_attach, emu_pci_attach),
2191 DEVMETHOD(device_detach, emu_pci_detach),
2196 static driver_t emu_driver = {
2202 DRIVER_MODULE(snd_emu10k1, pci, emu_driver, pcm_devclass, NULL, NULL);
2203 MODULE_DEPEND(snd_emu10k1, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2204 MODULE_VERSION(snd_emu10k1, 1);
2205 MODULE_DEPEND(snd_emu10k1, midi, 1, 1, 1);
2207 /* dummy driver to silence the joystick device */
2209 emujoy_pci_probe(device_t dev)
2213 switch (pci_get_devid(dev)) {
2215 s = "Creative EMU10K1 Joystick";
2219 s = "Creative EMU10K2 Joystick";
2224 if (s) device_set_desc(dev, s);
2225 return s ? -1000 : ENXIO;
2229 emujoy_pci_attach(device_t dev)
2236 emujoy_pci_detach(device_t dev)
2242 static device_method_t emujoy_methods[] = {
2243 DEVMETHOD(device_probe, emujoy_pci_probe),
2244 DEVMETHOD(device_attach, emujoy_pci_attach),
2245 DEVMETHOD(device_detach, emujoy_pci_detach),
2250 static driver_t emujoy_driver = {
2256 static devclass_t emujoy_devclass;
2258 DRIVER_MODULE(emujoy, pci, emujoy_driver, emujoy_devclass, NULL, NULL);