2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 /****************************************************************************
34 ****************************************************************************/
37 #define HDA_CMD_VERB_MASK 0x000fffff
38 #define HDA_CMD_VERB_SHIFT 0
39 #define HDA_CMD_NID_MASK 0x0ff00000
40 #define HDA_CMD_NID_SHIFT 20
41 #define HDA_CMD_CAD_MASK 0xf0000000
42 #define HDA_CMD_CAD_SHIFT 28
44 #define HDA_CMD_VERB_4BIT_SHIFT 16
45 #define HDA_CMD_VERB_12BIT_SHIFT 8
47 #define HDA_CMD_VERB_4BIT(verb, payload) \
48 (((verb) << HDA_CMD_VERB_4BIT_SHIFT) | (payload))
49 #define HDA_CMD_4BIT(cad, nid, verb, payload) \
50 (((cad) << HDA_CMD_CAD_SHIFT) | \
51 ((nid) << HDA_CMD_NID_SHIFT) | \
52 (HDA_CMD_VERB_4BIT((verb), (payload))))
54 #define HDA_CMD_VERB_12BIT(verb, payload) \
55 (((verb) << HDA_CMD_VERB_12BIT_SHIFT) | (payload))
56 #define HDA_CMD_12BIT(cad, nid, verb, payload) \
57 (((cad) << HDA_CMD_CAD_SHIFT) | \
58 ((nid) << HDA_CMD_NID_SHIFT) | \
59 (HDA_CMD_VERB_12BIT((verb), (payload))))
62 #define HDA_CMD_VERB_GET_PARAMETER 0xf00
64 #define HDA_CMD_GET_PARAMETER(cad, nid, payload) \
65 (HDA_CMD_12BIT((cad), (nid), \
66 HDA_CMD_VERB_GET_PARAMETER, (payload)))
68 /* Connection Select Control */
69 #define HDA_CMD_VERB_GET_CONN_SELECT_CONTROL 0xf01
70 #define HDA_CMD_VERB_SET_CONN_SELECT_CONTROL 0x701
72 #define HDA_CMD_GET_CONN_SELECT_CONTROL(cad, nid) \
73 (HDA_CMD_12BIT((cad), (nid), \
74 HDA_CMD_VERB_GET_CONN_SELECT_CONTROL, 0x0))
75 #define HDA_CMD_SET_CONNECTION_SELECT_CONTROL(cad, nid, payload) \
76 (HDA_CMD_12BIT((cad), (nid), \
77 HDA_CMD_VERB_SET_CONN_SELECT_CONTROL, (payload)))
79 /* Connection List Entry */
80 #define HDA_CMD_VERB_GET_CONN_LIST_ENTRY 0xf02
82 #define HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, payload) \
83 (HDA_CMD_12BIT((cad), (nid), \
84 HDA_CMD_VERB_GET_CONN_LIST_ENTRY, (payload)))
86 #define HDA_CMD_GET_CONN_LIST_ENTRY_SIZE_SHORT 1
87 #define HDA_CMD_GET_CONN_LIST_ENTRY_SIZE_LONG 2
89 /* Processing State */
90 #define HDA_CMD_VERB_GET_PROCESSING_STATE 0xf03
91 #define HDA_CMD_VERB_SET_PROCESSING_STATE 0x703
93 #define HDA_CMD_GET_PROCESSING_STATE(cad, nid) \
94 (HDA_CMD_12BIT((cad), (nid), \
95 HDA_CMD_VERB_GET_PROCESSING_STATE, 0x0))
96 #define HDA_CMD_SET_PROCESSING_STATE(cad, nid, payload) \
97 (HDA_CMD_12BIT((cad), (nid), \
98 HDA_CMD_VERB_SET_PROCESSING_STATE, (payload)))
100 #define HDA_CMD_GET_PROCESSING_STATE_STATE_OFF 0x00
101 #define HDA_CMD_GET_PROCESSING_STATE_STATE_ON 0x01
102 #define HDA_CMD_GET_PROCESSING_STATE_STATE_BENIGN 0x02
104 /* Coefficient Index */
105 #define HDA_CMD_VERB_GET_COEFF_INDEX 0xd
106 #define HDA_CMD_VERB_SET_COEFF_INDEX 0x5
108 #define HDA_CMD_GET_COEFF_INDEX(cad, nid) \
109 (HDA_CMD_4BIT((cad), (nid), \
110 HDA_CMD_VERB_GET_COEFF_INDEX, 0x0))
111 #define HDA_CMD_SET_COEFF_INDEX(cad, nid, payload) \
112 (HDA_CMD_4BIT((cad), (nid), \
113 HDA_CMD_VERB_SET_COEFF_INDEX, (payload)))
115 /* Processing Coefficient */
116 #define HDA_CMD_VERB_GET_PROCESSING_COEFF 0xc
117 #define HDA_CMD_VERB_SET_PROCESSING_COEFF 0x4
119 #define HDA_CMD_GET_PROCESSING_COEFF(cad, nid) \
120 (HDA_CMD_4BIT((cad), (nid), \
121 HDA_CMD_VERB_GET_PROCESSING_COEFF, 0x0))
122 #define HDA_CMD_SET_PROCESSING_COEFF(cad, nid, payload) \
123 (HDA_CMD_4BIT((cad), (nid), \
124 HDA_CMD_VERB_SET_PROCESSING_COEFF, (payload)))
126 /* Amplifier Gain/Mute */
127 #define HDA_CMD_VERB_GET_AMP_GAIN_MUTE 0xb
128 #define HDA_CMD_VERB_SET_AMP_GAIN_MUTE 0x3
130 #define HDA_CMD_GET_AMP_GAIN_MUTE(cad, nid, payload) \
131 (HDA_CMD_4BIT((cad), (nid), \
132 HDA_CMD_VERB_GET_AMP_GAIN_MUTE, (payload)))
133 #define HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, payload) \
134 (HDA_CMD_4BIT((cad), (nid), \
135 HDA_CMD_VERB_SET_AMP_GAIN_MUTE, (payload)))
137 #define HDA_CMD_GET_AMP_GAIN_MUTE_INPUT 0x0000
138 #define HDA_CMD_GET_AMP_GAIN_MUTE_OUTPUT 0x8000
139 #define HDA_CMD_GET_AMP_GAIN_MUTE_RIGHT 0x0000
140 #define HDA_CMD_GET_AMP_GAIN_MUTE_LEFT 0x2000
142 #define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_MASK 0x00000008
143 #define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_SHIFT 7
144 #define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_MASK 0x00000007
145 #define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_SHIFT 0
147 #define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE(rsp) \
148 (((rsp) & HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_MASK) >> \
149 HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_SHIFT)
150 #define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN(rsp) \
151 (((rsp) & HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_MASK) >> \
152 HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_SHIFT)
154 #define HDA_CMD_SET_AMP_GAIN_MUTE_OUTPUT 0x8000
155 #define HDA_CMD_SET_AMP_GAIN_MUTE_INPUT 0x4000
156 #define HDA_CMD_SET_AMP_GAIN_MUTE_LEFT 0x2000
157 #define HDA_CMD_SET_AMP_GAIN_MUTE_RIGHT 0x1000
158 #define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_MASK 0x0f00
159 #define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_SHIFT 8
160 #define HDA_CMD_SET_AMP_GAIN_MUTE_MUTE 0x0080
161 #define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_MASK 0x0007
162 #define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_SHIFT 0
164 #define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX(index) \
165 (((index) << HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_SHIFT) & \
166 HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_MASK)
167 #define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN(index) \
168 (((index) << HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_SHIFT) & \
169 HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_MASK)
171 /* Converter format */
172 #define HDA_CMD_VERB_GET_CONV_FMT 0xa
173 #define HDA_CMD_VERB_SET_CONV_FMT 0x2
175 #define HDA_CMD_GET_CONV_FMT(cad, nid) \
176 (HDA_CMD_4BIT((cad), (nid), \
177 HDA_CMD_VERB_GET_CONV_FMT, 0x0))
178 #define HDA_CMD_SET_CONV_FMT(cad, nid, payload) \
179 (HDA_CMD_4BIT((cad), (nid), \
180 HDA_CMD_VERB_SET_CONV_FMT, (payload)))
182 /* Digital Converter Control */
183 #define HDA_CMD_VERB_GET_DIGITAL_CONV_FMT1 0xf0d
184 #define HDA_CMD_VERB_GET_DIGITAL_CONV_FMT2 0xf0e
185 #define HDA_CMD_VERB_SET_DIGITAL_CONV_FMT1 0x70d
186 #define HDA_CMD_VERB_SET_DIGITAL_CONV_FMT2 0x70e
188 #define HDA_CMD_GET_DIGITAL_CONV_FMT(cad, nid) \
189 (HDA_CMD_12BIT((cad), (nid), \
190 HDA_CMD_VERB_GET_DIGITAL_CONV_FMT1, 0x0))
191 #define HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, nid, payload) \
192 (HDA_CMD_12BIT((cad), (nid), \
193 HDA_CMD_VERB_SET_DIGITAL_CONV_FMT1, (payload)))
194 #define HDA_CMD_SET_DIGITAL_CONV_FMT2(cad, nid, payload) \
195 (HDA_CMD_12BIT((cad), (nid), \
196 HDA_CMD_VERB_SET_DIGITAL_CONV_FMT2, (payload)))
198 #define HDA_CMD_GET_DIGITAL_CONV_FMT_CC_MASK 0x7f00
199 #define HDA_CMD_GET_DIGITAL_CONV_FMT_CC_SHIFT 8
200 #define HDA_CMD_GET_DIGITAL_CONV_FMT_L_MASK 0x0080
201 #define HDA_CMD_GET_DIGITAL_CONV_FMT_L_SHIFT 7
202 #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_MASK 0x0040
203 #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_SHIFT 6
204 #define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_MASK 0x0020
205 #define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_SHIFT 5
206 #define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_MASK 0x0010
207 #define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_SHIFT 4
208 #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_MASK 0x0008
209 #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_SHIFT 3
210 #define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_MASK 0x0004
211 #define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_SHIFT 2
212 #define HDA_CMD_GET_DIGITAL_CONV_FMT_V_MASK 0x0002
213 #define HDA_CMD_GET_DIGITAL_CONV_FMT_V_SHIFT 1
214 #define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_MASK 0x0001
215 #define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_SHIFT 0
217 #define HDA_CMD_GET_DIGITAL_CONV_FMT_CC(rsp) \
218 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_CC_MASK) >> \
219 HDA_CMD_GET_DIGITAL_CONV_FMT_CC_SHIFT)
220 #define HDA_CMD_GET_DIGITAL_CONV_FMT_L(rsp) \
221 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_L_MASK) >> \
222 HDA_CMD_GET_DIGITAL_CONV_FMT_L_SHIFT)
223 #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO(rsp) \
224 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_MASK) >> \
225 HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_SHIFT)
226 #define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO(rsp) \
227 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_MASK) >> \
228 HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_SHIFT)
229 #define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY(rsp) \
230 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_MASK) >> \
231 HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_SHIFT)
232 #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE(rsp) \
233 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_MASK) >> \
234 HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_SHIFT)
235 #define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG(rsp) \
236 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_MASK) >> \
237 HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_SHIFT)
238 #define HDA_CMD_GET_DIGITAL_CONV_FMT_V(rsp) \
239 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_V_MASK) >> \
240 HDA_CMD_GET_DIGITAL_CONV_FMT_V_SHIFT)
241 #define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN(rsp) \
242 (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_MASK) >> \
243 HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_SHIFT)
245 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_L 0x80
246 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_PRO 0x40
247 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO 0x20
248 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_COPY 0x10
249 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_PRE 0x08
250 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_VCFG 0x04
251 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_V 0x02
252 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN 0x01
255 #define HDA_CMD_VERB_GET_POWER_STATE 0xf05
256 #define HDA_CMD_VERB_SET_POWER_STATE 0x705
258 #define HDA_CMD_GET_POWER_STATE(cad, nid) \
259 (HDA_CMD_12BIT((cad), (nid), \
260 HDA_CMD_VERB_GET_POWER_STATE, 0x0))
261 #define HDA_CMD_SET_POWER_STATE(cad, nid, payload) \
262 (HDA_CMD_12BIT((cad), (nid), \
263 HDA_CMD_VERB_SET_POWER_STATE, (payload)))
265 #define HDA_CMD_POWER_STATE_D0 0x00
266 #define HDA_CMD_POWER_STATE_D1 0x01
267 #define HDA_CMD_POWER_STATE_D2 0x02
268 #define HDA_CMD_POWER_STATE_D3 0x03
270 #define HDA_CMD_POWER_STATE_ACT_MASK 0x000000f0
271 #define HDA_CMD_POWER_STATE_ACT_SHIFT 4
272 #define HDA_CMD_POWER_STATE_SET_MASK 0x0000000f
273 #define HDA_CMD_POWER_STATE_SET_SHIFT 0
275 #define HDA_CMD_GET_POWER_STATE_ACT(rsp) \
276 (((rsp) & HDA_CMD_POWER_STATE_ACT_MASK) >> \
277 HDA_CMD_POWER_STATE_ACT_SHIFT)
278 #define HDA_CMD_GET_POWER_STATE_SET(rsp) \
279 (((rsp) & HDA_CMD_POWER_STATE_SET_MASK) >> \
280 HDA_CMD_POWER_STATE_SET_SHIFT)
282 #define HDA_CMD_SET_POWER_STATE_ACT(ps) \
283 (((ps) << HDA_CMD_POWER_STATE_ACT_SHIFT) & \
284 HDA_CMD_POWER_STATE_ACT_MASK)
285 #define HDA_CMD_SET_POWER_STATE_SET(ps) \
286 (((ps) << HDA_CMD_POWER_STATE_SET_SHIFT) & \
287 HDA_CMD_POWER_STATE_ACT_MASK)
289 /* Converter Stream, Channel */
290 #define HDA_CMD_VERB_GET_CONV_STREAM_CHAN 0xf06
291 #define HDA_CMD_VERB_SET_CONV_STREAM_CHAN 0x706
293 #define HDA_CMD_GET_CONV_STREAM_CHAN(cad, nid) \
294 (HDA_CMD_12BIT((cad), (nid), \
295 HDA_CMD_VERB_GET_CONV_STREAM_CHAN, 0x0))
296 #define HDA_CMD_SET_CONV_STREAM_CHAN(cad, nid, payload) \
297 (HDA_CMD_12BIT((cad), (nid), \
298 HDA_CMD_VERB_SET_CONV_STREAM_CHAN, (payload)))
300 #define HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK 0x000000f0
301 #define HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT 4
302 #define HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK 0x0000000f
303 #define HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT 0
305 #define HDA_CMD_GET_CONV_STREAM_CHAN_STREAM(rsp) \
306 (((rsp) & HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK) >> \
307 HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT)
308 #define HDA_CMD_GET_CONV_STREAM_CHAN_CHAN(rsp) \
309 (((rsp) & HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK) >> \
310 HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT)
312 #define HDA_CMD_SET_CONV_STREAM_CHAN_STREAM(param) \
313 (((param) << HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT) & \
314 HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK)
315 #define HDA_CMD_SET_CONV_STREAM_CHAN_CHAN(param) \
316 (((param) << HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT) & \
317 HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK)
319 /* Input Converter SDI Select */
320 #define HDA_CMD_VERB_GET_INPUT_CONVERTER_SDI_SELECT 0xf04
321 #define HDA_CMD_VERB_SET_INPUT_CONVERTER_SDI_SELECT 0x704
323 #define HDA_CMD_GET_INPUT_CONVERTER_SDI_SELECT(cad, nid) \
324 (HDA_CMD_12BIT((cad), (nid), \
325 HDA_CMD_VERB_GET_INPUT_CONVERTER_SDI_SELECT, 0x0))
326 #define HDA_CMD_SET_INPUT_CONVERTER_SDI_SELECT(cad, nid, payload) \
327 (HDA_CMD_12BIT((cad), (nid), \
328 HDA_CMD_VERB_SET_INPUT_CONVERTER_SDI_SELECT, (payload)))
330 /* Pin Widget Control */
331 #define HDA_CMD_VERB_GET_PIN_WIDGET_CTRL 0xf07
332 #define HDA_CMD_VERB_SET_PIN_WIDGET_CTRL 0x707
334 #define HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid) \
335 (HDA_CMD_12BIT((cad), (nid), \
336 HDA_CMD_VERB_GET_PIN_WIDGET_CTRL, 0x0))
337 #define HDA_CMD_SET_PIN_WIDGET_CTRL(cad, nid, payload) \
338 (HDA_CMD_12BIT((cad), (nid), \
339 HDA_CMD_VERB_SET_PIN_WIDGET_CTRL, (payload)))
341 #define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_MASK 0x00000080
342 #define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_SHIFT 7
343 #define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_MASK 0x00000040
344 #define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_SHIFT 6
345 #define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_MASK 0x00000020
346 #define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_SHIFT 5
347 #define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK 0x00000007
348 #define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT 0
350 #define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE(rsp) \
351 (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_MASK) >> \
352 HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_SHIFT)
353 #define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE(rsp) \
354 (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_MASK) >> \
355 HDA_GET_CMD_PIN_WIDGET_CTRL_OUT_ENABLE_SHIFT)
356 #define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE(rsp) \
357 (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_MASK) >> \
358 HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_SHIFT)
359 #define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE(rsp) \
360 (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) >> \
361 HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT)
363 #define HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE 0x80
364 #define HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE 0x40
365 #define HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE 0x20
366 #define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK 0x07
367 #define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT 0
369 #define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(param) \
370 (((param) << HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT) & \
371 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK)
373 #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_HIZ 0
374 #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 1
375 #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_GROUND 2
376 #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4
377 #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 5
379 /* Unsolicited Response */
380 #define HDA_CMD_VERB_GET_UNSOLICITED_RESPONSE 0xf08
381 #define HDA_CMD_VERB_SET_UNSOLICITED_RESPONSE 0x708
383 #define HDA_CMD_GET_UNSOLICITED_RESPONSE(cad, nid) \
384 (HDA_CMD_12BIT((cad), (nid), \
385 HDA_CMD_VERB_GET_UNSOLICITED_RESPONSE, 0x0))
386 #define HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, nid, payload) \
387 (HDA_CMD_12BIT((cad), (nid), \
388 HDA_CMD_VERB_SET_UNSOLICITED_RESPONSE, (payload)))
390 #define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_MASK 0x00000080
391 #define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_SHIFT 7
392 #define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_MASK 0x0000001f
393 #define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_SHIFT 0
395 #define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE(rsp) \
396 (((rsp) & HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_MASK) >> \
397 HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_SHIFT)
398 #define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG(rsp) \
399 (((rsp) & HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_MASK) >> \
400 HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_SHIFT)
402 #define HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE 0x80
403 #define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_MASK 0x3f
404 #define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_SHIFT 0
406 #define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG(param) \
407 (((param) << HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_SHIFT) & \
408 HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_MASK)
411 #define HDA_CMD_VERB_GET_PIN_SENSE 0xf09
412 #define HDA_CMD_VERB_SET_PIN_SENSE 0x709
414 #define HDA_CMD_GET_PIN_SENSE(cad, nid) \
415 (HDA_CMD_12BIT((cad), (nid), \
416 HDA_CMD_VERB_GET_PIN_SENSE, 0x0))
417 #define HDA_CMD_SET_PIN_SENSE(cad, nid, payload) \
418 (HDA_CMD_12BIT((cad), (nid), \
419 HDA_CMD_VERB_SET_PIN_SENSE, (payload)))
421 #define HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT 0x80000000
422 #define HDA_CMD_GET_PIN_SENSE_ELD_VALID 0x40000000
423 #define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_MASK 0x7fffffff
424 #define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_SHIFT 0
426 #define HDA_CMD_GET_PIN_SENSE_IMP_SENSE(rsp) \
427 (((rsp) & HDA_CMD_GET_PIN_SENSE_IMP_SENSE_MASK) >> \
428 HDA_CMD_GET_PIN_SENSE_IMP_SENSE_SHIFT)
430 #define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_INVALID 0x7fffffff
432 #define HDA_CMD_SET_PIN_SENSE_LEFT_CHANNEL 0x00
433 #define HDA_CMD_SET_PIN_SENSE_RIGHT_CHANNEL 0x01
435 /* EAPD/BTL Enable */
436 #define HDA_CMD_VERB_GET_EAPD_BTL_ENABLE 0xf0c
437 #define HDA_CMD_VERB_SET_EAPD_BTL_ENABLE 0x70c
439 #define HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid) \
440 (HDA_CMD_12BIT((cad), (nid), \
441 HDA_CMD_VERB_GET_EAPD_BTL_ENABLE, 0x0))
442 #define HDA_CMD_SET_EAPD_BTL_ENABLE(cad, nid, payload) \
443 (HDA_CMD_12BIT((cad), (nid), \
444 HDA_CMD_VERB_SET_EAPD_BTL_ENABLE, (payload)))
446 #define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_MASK 0x00000004
447 #define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_SHIFT 2
448 #define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_MASK 0x00000002
449 #define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_SHIFT 1
450 #define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_MASK 0x00000001
451 #define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_SHIFT 0
453 #define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP(rsp) \
454 (((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_MASK) >> \
455 HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_SHIFT)
456 #define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD(rsp) \
457 (((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_MASK) >> \
458 HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_SHIFT)
459 #define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL(rsp) \
460 (((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_MASK) >> \
461 HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_SHIFT)
463 #define HDA_CMD_SET_EAPD_BTL_ENABLE_LR_SWAP 0x04
464 #define HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD 0x02
465 #define HDA_CMD_SET_EAPD_BTL_ENABLE_BTL 0x01
468 #define HDA_CMD_VERB_GET_GPI_DATA 0xf10
469 #define HDA_CMD_VERB_SET_GPI_DATA 0x710
471 #define HDA_CMD_GET_GPI_DATA(cad, nid) \
472 (HDA_CMD_12BIT((cad), (nid), \
473 HDA_CMD_VERB_GET_GPI_DATA, 0x0))
474 #define HDA_CMD_SET_GPI_DATA(cad, nid) \
475 (HDA_CMD_12BIT((cad), (nid), \
476 HDA_CMD_VERB_SET_GPI_DATA, (payload)))
478 /* GPI Wake Enable Mask */
479 #define HDA_CMD_VERB_GET_GPI_WAKE_ENABLE_MASK 0xf11
480 #define HDA_CMD_VERB_SET_GPI_WAKE_ENABLE_MASK 0x711
482 #define HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, nid) \
483 (HDA_CMD_12BIT((cad), (nid), \
484 HDA_CMD_VERB_GET_GPI_WAKE_ENABLE_MASK, 0x0))
485 #define HDA_CMD_SET_GPI_WAKE_ENABLE_MASK(cad, nid, payload) \
486 (HDA_CMD_12BIT((cad), (nid), \
487 HDA_CMD_VERB_SET_GPI_WAKE_ENABLE_MASK, (payload)))
489 /* GPI Unsolicited Enable Mask */
490 #define HDA_CMD_VERB_GET_GPI_UNSOLICITED_ENABLE_MASK 0xf12
491 #define HDA_CMD_VERB_SET_GPI_UNSOLICITED_ENABLE_MASK 0x712
493 #define HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, nid) \
494 (HDA_CMD_12BIT((cad), (nid), \
495 HDA_CMD_VERB_GET_GPI_UNSOLICITED_ENABLE_MASK, 0x0))
496 #define HDA_CMD_SET_GPI_UNSOLICITED_ENABLE_MASK(cad, nid, payload) \
497 (HDA_CMD_12BIT((cad), (nid), \
498 HDA_CMD_VERB_SET_GPI_UNSOLICITED_ENABLE_MASK, (payload)))
500 /* GPI Sticky Mask */
501 #define HDA_CMD_VERB_GET_GPI_STICKY_MASK 0xf13
502 #define HDA_CMD_VERB_SET_GPI_STICKY_MASK 0x713
504 #define HDA_CMD_GET_GPI_STICKY_MASK(cad, nid) \
505 (HDA_CMD_12BIT((cad), (nid), \
506 HDA_CMD_VERB_GET_GPI_STICKY_MASK, 0x0))
507 #define HDA_CMD_SET_GPI_STICKY_MASK(cad, nid, payload) \
508 (HDA_CMD_12BIT((cad), (nid), \
509 HDA_CMD_VERB_SET_GPI_STICKY_MASK, (payload)))
512 #define HDA_CMD_VERB_GET_GPO_DATA 0xf14
513 #define HDA_CMD_VERB_SET_GPO_DATA 0x714
515 #define HDA_CMD_GET_GPO_DATA(cad, nid) \
516 (HDA_CMD_12BIT((cad), (nid), \
517 HDA_CMD_VERB_GET_GPO_DATA, 0x0))
518 #define HDA_CMD_SET_GPO_DATA(cad, nid, payload) \
519 (HDA_CMD_12BIT((cad), (nid), \
520 HDA_CMD_VERB_SET_GPO_DATA, (payload)))
523 #define HDA_CMD_VERB_GET_GPIO_DATA 0xf15
524 #define HDA_CMD_VERB_SET_GPIO_DATA 0x715
526 #define HDA_CMD_GET_GPIO_DATA(cad, nid) \
527 (HDA_CMD_12BIT((cad), (nid), \
528 HDA_CMD_VERB_GET_GPIO_DATA, 0x0))
529 #define HDA_CMD_SET_GPIO_DATA(cad, nid, payload) \
530 (HDA_CMD_12BIT((cad), (nid), \
531 HDA_CMD_VERB_SET_GPIO_DATA, (payload)))
533 /* GPIO Enable Mask */
534 #define HDA_CMD_VERB_GET_GPIO_ENABLE_MASK 0xf16
535 #define HDA_CMD_VERB_SET_GPIO_ENABLE_MASK 0x716
537 #define HDA_CMD_GET_GPIO_ENABLE_MASK(cad, nid) \
538 (HDA_CMD_12BIT((cad), (nid), \
539 HDA_CMD_VERB_GET_GPIO_ENABLE_MASK, 0x0))
540 #define HDA_CMD_SET_GPIO_ENABLE_MASK(cad, nid, payload) \
541 (HDA_CMD_12BIT((cad), (nid), \
542 HDA_CMD_VERB_SET_GPIO_ENABLE_MASK, (payload)))
545 #define HDA_CMD_VERB_GET_GPIO_DIRECTION 0xf17
546 #define HDA_CMD_VERB_SET_GPIO_DIRECTION 0x717
548 #define HDA_CMD_GET_GPIO_DIRECTION(cad, nid) \
549 (HDA_CMD_12BIT((cad), (nid), \
550 HDA_CMD_VERB_GET_GPIO_DIRECTION, 0x0))
551 #define HDA_CMD_SET_GPIO_DIRECTION(cad, nid, payload) \
552 (HDA_CMD_12BIT((cad), (nid), \
553 HDA_CMD_VERB_SET_GPIO_DIRECTION, (payload)))
555 /* GPIO Wake Enable Mask */
556 #define HDA_CMD_VERB_GET_GPIO_WAKE_ENABLE_MASK 0xf18
557 #define HDA_CMD_VERB_SET_GPIO_WAKE_ENABLE_MASK 0x718
559 #define HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, nid) \
560 (HDA_CMD_12BIT((cad), (nid), \
561 HDA_CMD_VERB_GET_GPIO_WAKE_ENABLE_MASK, 0x0))
562 #define HDA_CMD_SET_GPIO_WAKE_ENABLE_MASK(cad, nid, payload) \
563 (HDA_CMD_12BIT((cad), (nid), \
564 HDA_CMD_VERB_SET_GPIO_WAKE_ENABLE_MASK, (payload)))
566 /* GPIO Unsolicited Enable Mask */
567 #define HDA_CMD_VERB_GET_GPIO_UNSOLICITED_ENABLE_MASK 0xf19
568 #define HDA_CMD_VERB_SET_GPIO_UNSOLICITED_ENABLE_MASK 0x719
570 #define HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, nid) \
571 (HDA_CMD_12BIT((cad), (nid), \
572 HDA_CMD_VERB_GET_GPIO_UNSOLICITED_ENABLE_MASK, 0x0))
573 #define HDA_CMD_SET_GPIO_UNSOLICITED_ENABLE_MASK(cad, nid, payload) \
574 (HDA_CMD_12BIT((cad), (nid), \
575 HDA_CMD_VERB_SET_GPIO_UNSOLICITED_ENABLE_MASK, (payload)))
577 /* GPIO_STICKY_MASK */
578 #define HDA_CMD_VERB_GET_GPIO_STICKY_MASK 0xf1a
579 #define HDA_CMD_VERB_SET_GPIO_STICKY_MASK 0x71a
581 #define HDA_CMD_GET_GPIO_STICKY_MASK(cad, nid) \
582 (HDA_CMD_12BIT((cad), (nid), \
583 HDA_CMD_VERB_GET_GPIO_STICKY_MASK, 0x0))
584 #define HDA_CMD_SET_GPIO_STICKY_MASK(cad, nid, payload) \
585 (HDA_CMD_12BIT((cad), (nid), \
586 HDA_CMD_VERB_SET_GPIO_STICKY_MASK, (payload)))
588 /* Beep Generation */
589 #define HDA_CMD_VERB_GET_BEEP_GENERATION 0xf0a
590 #define HDA_CMD_VERB_SET_BEEP_GENERATION 0x70a
592 #define HDA_CMD_GET_BEEP_GENERATION(cad, nid) \
593 (HDA_CMD_12BIT((cad), (nid), \
594 HDA_CMD_VERB_GET_BEEP_GENERATION, 0x0))
595 #define HDA_CMD_SET_BEEP_GENERATION(cad, nid, payload) \
596 (HDA_CMD_12BIT((cad), (nid), \
597 HDA_CMD_VERB_SET_BEEP_GENERATION, (payload)))
600 #define HDA_CMD_VERB_GET_VOLUME_KNOB 0xf0f
601 #define HDA_CMD_VERB_SET_VOLUME_KNOB 0x70f
603 #define HDA_CMD_GET_VOLUME_KNOB(cad, nid) \
604 (HDA_CMD_12BIT((cad), (nid), \
605 HDA_CMD_VERB_GET_VOLUME_KNOB, 0x0))
606 #define HDA_CMD_SET_VOLUME_KNOB(cad, nid, payload) \
607 (HDA_CMD_12BIT((cad), (nid), \
608 HDA_CMD_VERB_SET_VOLUME_KNOB, (payload)))
611 #define HDA_CMD_VERB_GET_SUBSYSTEM_ID 0xf20
612 #define HDA_CMD_VERB_SET_SUSBYSTEM_ID1 0x720
613 #define HDA_CMD_VERB_SET_SUBSYSTEM_ID2 0x721
614 #define HDA_CMD_VERB_SET_SUBSYSTEM_ID3 0x722
615 #define HDA_CMD_VERB_SET_SUBSYSTEM_ID4 0x723
617 #define HDA_CMD_GET_SUBSYSTEM_ID(cad, nid) \
618 (HDA_CMD_12BIT((cad), (nid), \
619 HDA_CMD_VERB_GET_SUBSYSTEM_ID, 0x0))
620 #define HDA_CMD_SET_SUBSYSTEM_ID1(cad, nid, payload) \
621 (HDA_CMD_12BIT((cad), (nid), \
622 HDA_CMD_VERB_SET_SUSBYSTEM_ID1, (payload)))
623 #define HDA_CMD_SET_SUBSYSTEM_ID2(cad, nid, payload) \
624 (HDA_CMD_12BIT((cad), (nid), \
625 HDA_CMD_VERB_SET_SUSBYSTEM_ID2, (payload)))
626 #define HDA_CMD_SET_SUBSYSTEM_ID3(cad, nid, payload) \
627 (HDA_CMD_12BIT((cad), (nid), \
628 HDA_CMD_VERB_SET_SUSBYSTEM_ID3, (payload)))
629 #define HDA_CMD_SET_SUBSYSTEM_ID4(cad, nid, payload) \
630 (HDA_CMD_12BIT((cad), (nid), \
631 HDA_CMD_VERB_SET_SUSBYSTEM_ID4, (payload)))
633 /* Configuration Default */
634 #define HDA_CMD_VERB_GET_CONFIGURATION_DEFAULT 0xf1c
635 #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT1 0x71c
636 #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT2 0x71d
637 #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT3 0x71e
638 #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT4 0x71f
640 #define HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid) \
641 (HDA_CMD_12BIT((cad), (nid), \
642 HDA_CMD_VERB_GET_CONFIGURATION_DEFAULT, 0x0))
643 #define HDA_CMD_SET_CONFIGURATION_DEFAULT1(cad, nid, payload) \
644 (HDA_CMD_12BIT((cad), (nid), \
645 HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT1, (payload)))
646 #define HDA_CMD_SET_CONFIGURATION_DEFAULT2(cad, nid, payload) \
647 (HDA_CMD_12BIT((cad), (nid), \
648 HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT2, (payload)))
649 #define HDA_CMD_SET_CONFIGURATION_DEFAULT3(cad, nid, payload) \
650 (HDA_CMD_12BIT((cad), (nid), \
651 HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT3, (payload)))
652 #define HDA_CMD_SET_CONFIGURATION_DEFAULT4(cad, nid, payload) \
653 (HDA_CMD_12BIT((cad), (nid), \
654 HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT4, (payload)))
657 #define HDA_CMD_VERB_GET_STRIPE_CONTROL 0xf24
658 #define HDA_CMD_VERB_SET_STRIPE_CONTROL 0x724
660 #define HDA_CMD_GET_STRIPE_CONTROL(cad, nid) \
661 (HDA_CMD_12BIT((cad), (nid), \
662 HDA_CMD_VERB_GET_STRIPE_CONTROL, 0x0))
663 #define HDA_CMD_SET_STRIPE_CONTROL(cad, nid, payload) \
664 (HDA_CMD_12BIT((cad), (nid), \
665 HDA_CMD_VERB_SET_STRIPE_CONTROL, (payload)))
667 /* Channel Count Control */
668 #define HDA_CMD_VERB_GET_CONV_CHAN_COUNT 0xf2d
669 #define HDA_CMD_VERB_SET_CONV_CHAN_COUNT 0x72d
671 #define HDA_CMD_GET_CONV_CHAN_COUNT(cad, nid) \
672 (HDA_CMD_12BIT((cad), (nid), \
673 HDA_CMD_VERB_GET_CONV_CHAN_COUNT, 0x0))
674 #define HDA_CMD_SET_CONV_CHAN_COUNT(cad, nid, payload) \
675 (HDA_CMD_12BIT((cad), (nid), \
676 HDA_CMD_VERB_SET_CONV_CHAN_COUNT, (payload)))
678 #define HDA_CMD_VERB_GET_HDMI_DIP_SIZE 0xf2e
680 #define HDA_CMD_GET_HDMI_DIP_SIZE(cad, nid, arg) \
681 (HDA_CMD_12BIT((cad), (nid), \
682 HDA_CMD_VERB_GET_HDMI_DIP_SIZE, (arg)))
684 #define HDA_CMD_VERB_GET_HDMI_ELDD 0xf2f
686 #define HDA_CMD_GET_HDMI_ELDD(cad, nid, off) \
687 (HDA_CMD_12BIT((cad), (nid), \
688 HDA_CMD_VERB_GET_HDMI_ELDD, (off)))
690 #define HDA_CMD_VERB_GET_HDMI_DIP_INDEX 0xf30
691 #define HDA_CMD_VERB_SET_HDMI_DIP_INDEX 0x730
693 #define HDA_CMD_GET_HDMI_DIP_INDEX(cad, nid) \
694 (HDA_CMD_12BIT((cad), (nid), \
695 HDA_CMD_VERB_GET_HDMI_DIP_INDEX, 0x0))
696 #define HDA_CMD_SET_HDMI_DIP_INDEX(cad, nid, payload) \
697 (HDA_CMD_12BIT((cad), (nid), \
698 HDA_CMD_VERB_SET_HDMI_DIP_INDEX, (payload)))
700 #define HDA_CMD_VERB_GET_HDMI_DIP_DATA 0xf31
701 #define HDA_CMD_VERB_SET_HDMI_DIP_DATA 0x731
703 #define HDA_CMD_GET_HDMI_DIP_DATA(cad, nid) \
704 (HDA_CMD_12BIT((cad), (nid), \
705 HDA_CMD_VERB_GET_HDMI_DIP_DATA, 0x0))
706 #define HDA_CMD_SET_HDMI_DIP_DATA(cad, nid, payload) \
707 (HDA_CMD_12BIT((cad), (nid), \
708 HDA_CMD_VERB_SET_HDMI_DIP_DATA, (payload)))
710 #define HDA_CMD_VERB_GET_HDMI_DIP_XMIT 0xf32
711 #define HDA_CMD_VERB_SET_HDMI_DIP_XMIT 0x732
713 #define HDA_CMD_GET_HDMI_DIP_XMIT(cad, nid) \
714 (HDA_CMD_12BIT((cad), (nid), \
715 HDA_CMD_VERB_GET_HDMI_DIP_XMIT, 0x0))
716 #define HDA_CMD_SET_HDMI_DIP_XMIT(cad, nid, payload) \
717 (HDA_CMD_12BIT((cad), (nid), \
718 HDA_CMD_VERB_SET_HDMI_DIP_XMIT, (payload)))
720 #define HDA_CMD_VERB_GET_HDMI_CP_CTRL 0xf33
721 #define HDA_CMD_VERB_SET_HDMI_CP_CTRL 0x733
723 #define HDA_CMD_VERB_GET_HDMI_CHAN_SLOT 0xf34
724 #define HDA_CMD_VERB_SET_HDMI_CHAN_SLOT 0x734
726 #define HDA_CMD_GET_HDMI_CHAN_SLOT(cad, nid) \
727 (HDA_CMD_12BIT((cad), (nid), \
728 HDA_CMD_VERB_GET_HDMI_CHAN_SLOT, 0x0))
729 #define HDA_CMD_SET_HDMI_CHAN_SLOT(cad, nid, payload) \
730 (HDA_CMD_12BIT((cad), (nid), \
731 HDA_CMD_VERB_SET_HDMI_CHAN_SLOT, (payload)))
733 #define HDA_HDMI_CODING_TYPE_REF_STREAM_HEADER 0
734 #define HDA_HDMI_CODING_TYPE_LPCM 1
735 #define HDA_HDMI_CODING_TYPE_AC3 2
736 #define HDA_HDMI_CODING_TYPE_MPEG1 3
737 #define HDA_HDMI_CODING_TYPE_MP3 4
738 #define HDA_HDMI_CODING_TYPE_MPEG2 5
739 #define HDA_HDMI_CODING_TYPE_AACLC 6
740 #define HDA_HDMI_CODING_TYPE_DTS 7
741 #define HDA_HDMI_CODING_TYPE_ATRAC 8
742 #define HDA_HDMI_CODING_TYPE_SACD 9
743 #define HDA_HDMI_CODING_TYPE_EAC3 10
744 #define HDA_HDMI_CODING_TYPE_DTS_HD 11
745 #define HDA_HDMI_CODING_TYPE_MLP 12
746 #define HDA_HDMI_CODING_TYPE_DST 13
747 #define HDA_HDMI_CODING_TYPE_WMAPRO 14
748 #define HDA_HDMI_CODING_TYPE_REF_CTX 15
751 #define HDA_CMD_VERB_FUNCTION_RESET 0x7ff
753 #define HDA_CMD_FUNCTION_RESET(cad, nid) \
754 (HDA_CMD_12BIT((cad), (nid), \
755 HDA_CMD_VERB_FUNCTION_RESET, 0x0))
758 /****************************************************************************
759 * HDA Device Parameters
760 ****************************************************************************/
763 #define HDA_PARAM_VENDOR_ID 0x00
765 #define HDA_PARAM_VENDOR_ID_VENDOR_ID_MASK 0xffff0000
766 #define HDA_PARAM_VENDOR_ID_VENDOR_ID_SHIFT 16
767 #define HDA_PARAM_VENDOR_ID_DEVICE_ID_MASK 0x0000ffff
768 #define HDA_PARAM_VENDOR_ID_DEVICE_ID_SHIFT 0
770 #define HDA_PARAM_VENDOR_ID_VENDOR_ID(param) \
771 (((param) & HDA_PARAM_VENDOR_ID_VENDOR_ID_MASK) >> \
772 HDA_PARAM_VENDOR_ID_VENDOR_ID_SHIFT)
773 #define HDA_PARAM_VENDOR_ID_DEVICE_ID(param) \
774 (((param) & HDA_PARAM_VENDOR_ID_DEVICE_ID_MASK) >> \
775 HDA_PARAM_VENDOR_ID_DEVICE_ID_SHIFT)
778 #define HDA_PARAM_REVISION_ID 0x02
780 #define HDA_PARAM_REVISION_ID_MAJREV_MASK 0x00f00000
781 #define HDA_PARAM_REVISION_ID_MAJREV_SHIFT 20
782 #define HDA_PARAM_REVISION_ID_MINREV_MASK 0x000f0000
783 #define HDA_PARAM_REVISION_ID_MINREV_SHIFT 16
784 #define HDA_PARAM_REVISION_ID_REVISION_ID_MASK 0x0000ff00
785 #define HDA_PARAM_REVISION_ID_REVISION_ID_SHIFT 8
786 #define HDA_PARAM_REVISION_ID_STEPPING_ID_MASK 0x000000ff
787 #define HDA_PARAM_REVISION_ID_STEPPING_ID_SHIFT 0
789 #define HDA_PARAM_REVISION_ID_MAJREV(param) \
790 (((param) & HDA_PARAM_REVISION_ID_MAJREV_MASK) >> \
791 HDA_PARAM_REVISION_ID_MAJREV_SHIFT)
792 #define HDA_PARAM_REVISION_ID_MINREV(param) \
793 (((param) & HDA_PARAM_REVISION_ID_MINREV_MASK) >> \
794 HDA_PARAM_REVISION_ID_MINREV_SHIFT)
795 #define HDA_PARAM_REVISION_ID_REVISION_ID(param) \
796 (((param) & HDA_PARAM_REVISION_ID_REVISION_ID_MASK) >> \
797 HDA_PARAM_REVISION_ID_REVISION_ID_SHIFT)
798 #define HDA_PARAM_REVISION_ID_STEPPING_ID(param) \
799 (((param) & HDA_PARAM_REVISION_ID_STEPPING_ID_MASK) >> \
800 HDA_PARAM_REVISION_ID_STEPPING_ID_SHIFT)
802 /* Subordinate Node Cound */
803 #define HDA_PARAM_SUB_NODE_COUNT 0x04
805 #define HDA_PARAM_SUB_NODE_COUNT_START_MASK 0x00ff0000
806 #define HDA_PARAM_SUB_NODE_COUNT_START_SHIFT 16
807 #define HDA_PARAM_SUB_NODE_COUNT_TOTAL_MASK 0x000000ff
808 #define HDA_PARAM_SUB_NODE_COUNT_TOTAL_SHIFT 0
810 #define HDA_PARAM_SUB_NODE_COUNT_START(param) \
811 (((param) & HDA_PARAM_SUB_NODE_COUNT_START_MASK) >> \
812 HDA_PARAM_SUB_NODE_COUNT_START_SHIFT)
813 #define HDA_PARAM_SUB_NODE_COUNT_TOTAL(param) \
814 (((param) & HDA_PARAM_SUB_NODE_COUNT_TOTAL_MASK) >> \
815 HDA_PARAM_SUB_NODE_COUNT_TOTAL_SHIFT)
817 /* Function Group Type */
818 #define HDA_PARAM_FCT_GRP_TYPE 0x05
820 #define HDA_PARAM_FCT_GRP_TYPE_UNSOL_MASK 0x00000100
821 #define HDA_PARAM_FCT_GRP_TYPE_UNSOL_SHIFT 8
822 #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MASK 0x000000ff
823 #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_SHIFT 0
825 #define HDA_PARAM_FCT_GRP_TYPE_UNSOL(param) \
826 (((param) & HDA_PARAM_FCT_GRP_TYPE_UNSOL_MASK) >> \
827 HDA_PARAM_FCT_GROUP_TYPE_UNSOL_SHIFT)
828 #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(param) \
829 (((param) & HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MASK) >> \
830 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_SHIFT)
832 #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO 0x01
833 #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM 0x02
835 /* Audio Function Group Capabilities */
836 #define HDA_PARAM_AUDIO_FCT_GRP_CAP 0x08
838 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_MASK 0x00010000
839 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_SHIFT 16
840 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_MASK 0x00000f00
841 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_SHIFT 8
842 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_MASK 0x0000000f
843 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_SHIFT 0
845 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN(param) \
846 (((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_MASK) >> \
847 HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_SHIFT)
848 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY(param) \
849 (((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_MASK) >> \
850 HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_SHIFT)
851 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY(param) \
852 (((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_MASK) >> \
853 HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_SHIFT)
855 /* Audio Widget Capabilities */
856 #define HDA_PARAM_AUDIO_WIDGET_CAP 0x09
858 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK 0x00f00000
859 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT 20
860 #define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_MASK 0x000f0000
861 #define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_SHIFT 16
862 #define HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_MASK 0x0000e000
863 #define HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_SHIFT 13
864 #define HDA_PARAM_AUDIO_WIDGET_CAP_CP_MASK 0x00001000
865 #define HDA_PARAM_AUDIO_WIDGET_CAP_CP_SHIFT 12
866 #define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_MASK 0x00000800
867 #define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_SHIFT 11
868 #define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_MASK 0x00000400
869 #define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_SHIFT 10
870 #define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_MASK 0x00000200
871 #define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_SHIFT 9
872 #define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_MASK 0x00000100
873 #define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_SHIFT 8
874 #define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_MASK 0x00000080
875 #define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_SHIFT 7
876 #define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_MASK 0x00000040
877 #define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_SHIFT 6
878 #define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_MASK 0x00000020
879 #define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_SHIFT 5
880 #define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_MASK 0x00000010
881 #define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_SHIFT 4
882 #define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_MASK 0x00000008
883 #define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_SHIFT 3
884 #define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_MASK 0x00000004
885 #define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_SHIFT 2
886 #define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_MASK 0x00000002
887 #define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_SHIFT 1
888 #define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK 0x00000001
889 #define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT 0
891 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(param) \
892 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK) >> \
893 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT)
894 #define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY(param) \
895 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_MASK) >> \
896 HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_SHIFT)
897 #define HDA_PARAM_AUDIO_WIDGET_CAP_CC(param) \
898 ((((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_MASK) >> \
899 (HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_SHIFT - 1)) | \
900 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK) >> \
901 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT))
902 #define HDA_PARAM_AUDIO_WIDGET_CAP_CP(param) \
903 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CP_MASK) >> \
904 HDA_PARAM_AUDIO_WIDGET_CAP_CP_SHIFT)
905 #define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(param) \
906 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_MASK) >> \
907 HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_SHIFT)
908 #define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(param) \
909 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_MASK) >> \
910 HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_SHIFT)
911 #define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(param) \
912 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_MASK) >> \
913 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_SHIFT)
914 #define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST(param) \
915 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_MASK) >> \
916 HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_SHIFT)
917 #define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(param) \
918 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_MASK) >> \
919 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_SHIFT)
920 #define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(param) \
921 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_MASK) >> \
922 HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_SHIFT)
923 #define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(param) \
924 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_MASK) >> \
925 HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_SHIFT)
926 #define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(param) \
927 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_MASK) >> \
928 HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_SHIFT)
929 #define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(param) \
930 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_MASK) >> \
931 HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_SHIFT)
932 #define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(param) \
933 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_MASK) >> \
934 HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_SHIFT)
935 #define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(param) \
936 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_MASK) >> \
937 HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_SHIFT)
938 #define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(param) \
939 (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK) >> \
940 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT)
942 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT 0x0
943 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT 0x1
944 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 0x2
945 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR 0x3
946 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX 0x4
947 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET 0x5
948 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET 0x6
949 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET 0x7
950 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET 0xf
952 /* Supported PCM Size, Rates */
954 #define HDA_PARAM_SUPP_PCM_SIZE_RATE 0x0a
956 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_MASK 0x00100000
957 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_SHIFT 20
958 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_MASK 0x00080000
959 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_SHIFT 19
960 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_MASK 0x00040000
961 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_SHIFT 18
962 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_MASK 0x00020000
963 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_SHIFT 17
964 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_MASK 0x00010000
965 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_SHIFT 16
966 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_MASK 0x00000001
967 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_SHIFT 0
968 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_MASK 0x00000002
969 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_SHIFT 1
970 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_MASK 0x00000004
971 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_SHIFT 2
972 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_MASK 0x00000008
973 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_SHIFT 3
974 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_MASK 0x00000010
975 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_SHIFT 4
976 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_MASK 0x00000020
977 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_SHIFT 5
978 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_MASK 0x00000040
979 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_SHIFT 6
980 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_MASK 0x00000080
981 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_SHIFT 7
982 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_MASK 0x00000100
983 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_SHIFT 8
984 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_MASK 0x00000200
985 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_SHIFT 9
986 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_MASK 0x00000400
987 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_SHIFT 10
988 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_MASK 0x00000800
989 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_SHIFT 11
991 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(param) \
992 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_MASK) >> \
993 HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_SHIFT)
994 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(param) \
995 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_MASK) >> \
996 HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_SHIFT)
997 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(param) \
998 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_MASK) >> \
999 HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_SHIFT)
1000 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(param) \
1001 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_MASK) >> \
1002 HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_SHIFT)
1003 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(param) \
1004 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_MASK) >> \
1005 HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_SHIFT)
1006 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(param) \
1007 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_MASK) >> \
1008 HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_SHIFT)
1009 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(param) \
1010 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_MASK) >> \
1011 HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_SHIFT)
1012 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(param) \
1013 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_MASK) >> \
1014 HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_SHIFT)
1015 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(param) \
1016 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_MASK) >> \
1017 HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_SHIFT)
1018 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(param) \
1019 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_MASK) >> \
1020 HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_SHIFT)
1021 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(param) \
1022 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_MASK) >> \
1023 HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_SHIFT)
1024 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(param) \
1025 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_MASK) >> \
1026 HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_SHIFT)
1027 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(param) \
1028 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_MASK) >> \
1029 HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_SHIFT)
1030 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(param) \
1031 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_MASK) >> \
1032 HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_SHIFT)
1033 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(param) \
1034 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_MASK) >> \
1035 HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_SHIFT)
1036 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(param) \
1037 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_MASK) >> \
1038 HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_SHIFT)
1039 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(param) \
1040 (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_MASK) >> \
1041 HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_SHIFT)
1043 /* Supported Stream Formats */
1044 #define HDA_PARAM_SUPP_STREAM_FORMATS 0x0b
1046 #define HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK 0x00000004
1047 #define HDA_PARAM_SUPP_STREAM_FORMATS_AC3_SHIFT 2
1048 #define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_MASK 0x00000002
1049 #define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_SHIFT 1
1050 #define HDA_PARAM_SUPP_STREAM_FORMATS_PCM_MASK 0x00000001
1051 #define HDA_PARAM_SUPP_STREAM_FORMATS_PCM_SHIFT 0
1053 #define HDA_PARAM_SUPP_STREAM_FORMATS_AC3(param) \
1054 (((param) & HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK) >> \
1055 HDA_PARAM_SUPP_STREAM_FORMATS_AC3_SHIFT)
1056 #define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(param) \
1057 (((param) & HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_MASK) >> \
1058 HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_SHIFT)
1059 #define HDA_PARAM_SUPP_STREAM_FORMATS_PCM(param) \
1060 (((param) & HDA_PARAM_SUPP_STREAM_FORMATS_PCM_MASK) >> \
1061 HDA_PARAM_SUPP_STREAM_FORMATS_PCM_SHIFT)
1063 /* Pin Capabilities */
1064 #define HDA_PARAM_PIN_CAP 0x0c
1066 #define HDA_PARAM_PIN_CAP_HBR_MASK 0x08000000
1067 #define HDA_PARAM_PIN_CAP_HBR_SHIFT 27
1068 #define HDA_PARAM_PIN_CAP_DP_MASK 0x01000000
1069 #define HDA_PARAM_PIN_CAP_DP_SHIFT 24
1070 #define HDA_PARAM_PIN_CAP_EAPD_CAP_MASK 0x00010000
1071 #define HDA_PARAM_PIN_CAP_EAPD_CAP_SHIFT 16
1072 #define HDA_PARAM_PIN_CAP_VREF_CTRL_MASK 0x0000ff00
1073 #define HDA_PARAM_PIN_CAP_VREF_CTRL_SHIFT 8
1074 #define HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK 0x00002000
1075 #define HDA_PARAM_PIN_CAP_VREF_CTRL_100_SHIFT 13
1076 #define HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK 0x00001000
1077 #define HDA_PARAM_PIN_CAP_VREF_CTRL_80_SHIFT 12
1078 #define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_MASK 0x00000400
1079 #define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_SHIFT 10
1080 #define HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK 0x00000200
1081 #define HDA_PARAM_PIN_CAP_VREF_CTRL_50_SHIFT 9
1082 #define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_MASK 0x00000100
1083 #define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_SHIFT 8
1084 #define HDA_PARAM_PIN_CAP_HDMI_MASK 0x00000080
1085 #define HDA_PARAM_PIN_CAP_HDMI_SHIFT 7
1086 #define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_MASK 0x00000040
1087 #define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_SHIFT 6
1088 #define HDA_PARAM_PIN_CAP_INPUT_CAP_MASK 0x00000020
1089 #define HDA_PARAM_PIN_CAP_INPUT_CAP_SHIFT 5
1090 #define HDA_PARAM_PIN_CAP_OUTPUT_CAP_MASK 0x00000010
1091 #define HDA_PARAM_PIN_CAP_OUTPUT_CAP_SHIFT 4
1092 #define HDA_PARAM_PIN_CAP_HEADPHONE_CAP_MASK 0x00000008
1093 #define HDA_PARAM_PIN_CAP_HEADPHONE_CAP_SHIFT 3
1094 #define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_MASK 0x00000004
1095 #define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_SHIFT 2
1096 #define HDA_PARAM_PIN_CAP_TRIGGER_REQD_MASK 0x00000002
1097 #define HDA_PARAM_PIN_CAP_TRIGGER_REQD_SHIFT 1
1098 #define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_MASK 0x00000001
1099 #define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_SHIFT 0
1101 #define HDA_PARAM_PIN_CAP_HBR(param) \
1102 (((param) & HDA_PARAM_PIN_CAP_HBR_MASK) >> \
1103 HDA_PARAM_PIN_CAP_HBR_SHIFT)
1104 #define HDA_PARAM_PIN_CAP_DP(param) \
1105 (((param) & HDA_PARAM_PIN_CAP_DP_MASK) >> \
1106 HDA_PARAM_PIN_CAP_DP_SHIFT)
1107 #define HDA_PARAM_PIN_CAP_EAPD_CAP(param) \
1108 (((param) & HDA_PARAM_PIN_CAP_EAPD_CAP_MASK) >> \
1109 HDA_PARAM_PIN_CAP_EAPD_CAP_SHIFT)
1110 #define HDA_PARAM_PIN_CAP_VREF_CTRL(param) \
1111 (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_MASK) >> \
1112 HDA_PARAM_PIN_CAP_VREF_CTRL_SHIFT)
1113 #define HDA_PARAM_PIN_CAP_VREF_CTRL_100(param) \
1114 (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK) >> \
1115 HDA_PARAM_PIN_CAP_VREF_CTRL_100_SHIFT)
1116 #define HDA_PARAM_PIN_CAP_VREF_CTRL_80(param) \
1117 (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK) >> \
1118 HDA_PARAM_PIN_CAP_VREF_CTRL_80_SHIFT)
1119 #define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(param) \
1120 (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_MASK) >> \
1121 HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_SHIFT)
1122 #define HDA_PARAM_PIN_CAP_VREF_CTRL_50(param) \
1123 (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK) >> \
1124 HDA_PARAM_PIN_CAP_VREF_CTRL_50_SHIFT)
1125 #define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(param) \
1126 (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_MASK) >> \
1127 HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_SHIFT)
1128 #define HDA_PARAM_PIN_CAP_HDMI(param) \
1129 (((param) & HDA_PARAM_PIN_CAP_HDMI_MASK) >> \
1130 HDA_PARAM_PIN_CAP_HDMI_SHIFT)
1131 #define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(param) \
1132 (((param) & HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_MASK) >> \
1133 HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_SHIFT)
1134 #define HDA_PARAM_PIN_CAP_INPUT_CAP(param) \
1135 (((param) & HDA_PARAM_PIN_CAP_INPUT_CAP_MASK) >> \
1136 HDA_PARAM_PIN_CAP_INPUT_CAP_SHIFT)
1137 #define HDA_PARAM_PIN_CAP_OUTPUT_CAP(param) \
1138 (((param) & HDA_PARAM_PIN_CAP_OUTPUT_CAP_MASK) >> \
1139 HDA_PARAM_PIN_CAP_OUTPUT_CAP_SHIFT)
1140 #define HDA_PARAM_PIN_CAP_HEADPHONE_CAP(param) \
1141 (((param) & HDA_PARAM_PIN_CAP_HEADPHONE_CAP_MASK) >> \
1142 HDA_PARAM_PIN_CAP_HEADPHONE_CAP_SHIFT)
1143 #define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(param) \
1144 (((param) & HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_MASK) >> \
1145 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_SHIFT)
1146 #define HDA_PARAM_PIN_CAP_TRIGGER_REQD(param) \
1147 (((param) & HDA_PARAM_PIN_CAP_TRIGGER_REQD_MASK) >> \
1148 HDA_PARAM_PIN_CAP_TRIGGER_REQD_SHIFT)
1149 #define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(param) \
1150 (((param) & HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_MASK) >> \
1151 HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_SHIFT)
1153 /* Input Amplifier Capabilities */
1154 #define HDA_PARAM_INPUT_AMP_CAP 0x0d
1156 #define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_MASK 0x80000000
1157 #define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_SHIFT 31
1158 #define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_MASK 0x007f0000
1159 #define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_SHIFT 16
1160 #define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_MASK 0x00007f00
1161 #define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_SHIFT 8
1162 #define HDA_PARAM_INPUT_AMP_CAP_OFFSET_MASK 0x0000007f
1163 #define HDA_PARAM_INPUT_AMP_CAP_OFFSET_SHIFT 0
1165 #define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP(param) \
1166 (((param) & HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_MASK) >> \
1167 HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_SHIFT)
1168 #define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE(param) \
1169 (((param) & HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_MASK) >> \
1170 HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_SHIFT)
1171 #define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS(param) \
1172 (((param) & HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_MASK) >> \
1173 HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_SHIFT)
1174 #define HDA_PARAM_INPUT_AMP_CAP_OFFSET(param) \
1175 (((param) & HDA_PARAM_INPUT_AMP_CAP_OFFSET_MASK) >> \
1176 HDA_PARAM_INPUT_AMP_CAP_OFFSET_SHIFT)
1178 /* Output Amplifier Capabilities */
1179 #define HDA_PARAM_OUTPUT_AMP_CAP 0x12
1181 #define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_MASK 0x80000000
1182 #define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_SHIFT 31
1183 #define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_MASK 0x007f0000
1184 #define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT 16
1185 #define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_MASK 0x00007f00
1186 #define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT 8
1187 #define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_MASK 0x0000007f
1188 #define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT 0
1190 #define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(param) \
1191 (((param) & HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_MASK) >> \
1192 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_SHIFT)
1193 #define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(param) \
1194 (((param) & HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_MASK) >> \
1195 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT)
1196 #define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(param) \
1197 (((param) & HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_MASK) >> \
1198 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT)
1199 #define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(param) \
1200 (((param) & HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_MASK) >> \
1201 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT)
1203 /* Connection List Length */
1204 #define HDA_PARAM_CONN_LIST_LENGTH 0x0e
1206 #define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_MASK 0x00000080
1207 #define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_SHIFT 7
1208 #define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_MASK 0x0000007f
1209 #define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_SHIFT 0
1211 #define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(param) \
1212 (((param) & HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_MASK) >> \
1213 HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_SHIFT)
1214 #define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(param) \
1215 (((param) & HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_MASK) >> \
1216 HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_SHIFT)
1218 /* Supported Power States */
1219 #define HDA_PARAM_SUPP_POWER_STATES 0x0f
1221 #define HDA_PARAM_SUPP_POWER_STATES_D3_MASK 0x00000008
1222 #define HDA_PARAM_SUPP_POWER_STATES_D3_SHIFT 3
1223 #define HDA_PARAM_SUPP_POWER_STATES_D2_MASK 0x00000004
1224 #define HDA_PARAM_SUPP_POWER_STATES_D2_SHIFT 2
1225 #define HDA_PARAM_SUPP_POWER_STATES_D1_MASK 0x00000002
1226 #define HDA_PARAM_SUPP_POWER_STATES_D1_SHIFT 1
1227 #define HDA_PARAM_SUPP_POWER_STATES_D0_MASK 0x00000001
1228 #define HDA_PARAM_SUPP_POWER_STATES_D0_SHIFT 0
1230 #define HDA_PARAM_SUPP_POWER_STATES_D3(param) \
1231 (((param) & HDA_PARAM_SUPP_POWER_STATES_D3_MASK) >> \
1232 HDA_PARAM_SUPP_POWER_STATES_D3_SHIFT)
1233 #define HDA_PARAM_SUPP_POWER_STATES_D2(param) \
1234 (((param) & HDA_PARAM_SUPP_POWER_STATES_D2_MASK) >> \
1235 HDA_PARAM_SUPP_POWER_STATES_D2_SHIFT)
1236 #define HDA_PARAM_SUPP_POWER_STATES_D1(param) \
1237 (((param) & HDA_PARAM_SUPP_POWER_STATES_D1_MASK) >> \
1238 HDA_PARAM_SUPP_POWER_STATES_D1_SHIFT)
1239 #define HDA_PARAM_SUPP_POWER_STATES_D0(param) \
1240 (((param) & HDA_PARAM_SUPP_POWER_STATES_D0_MASK) >> \
1241 HDA_PARAM_SUPP_POWER_STATES_D0_SHIFT)
1243 /* Processing Capabilities */
1244 #define HDA_PARAM_PROCESSING_CAP 0x10
1246 #define HDA_PARAM_PROCESSING_CAP_NUMCOEFF_MASK 0x0000ff00
1247 #define HDA_PARAM_PROCESSING_CAP_NUMCOEFF_SHIFT 8
1248 #define HDA_PARAM_PROCESSING_CAP_BENIGN_MASK 0x00000001
1249 #define HDA_PARAM_PROCESSING_CAP_BENIGN_SHIFT 0
1251 #define HDA_PARAM_PROCESSING_CAP_NUMCOEFF(param) \
1252 (((param) & HDA_PARAM_PROCESSING_CAP_NUMCOEFF_MASK) >> \
1253 HDA_PARAM_PROCESSING_CAP_NUMCOEFF_SHIFT)
1254 #define HDA_PARAM_PROCESSING_CAP_BENIGN(param) \
1255 (((param) & HDA_PARAM_PROCESSING_CAP_BENIGN_MASK) >> \
1256 HDA_PARAM_PROCESSING_CAP_BENIGN_SHIFT)
1259 #define HDA_PARAM_GPIO_COUNT 0x11
1261 #define HDA_PARAM_GPIO_COUNT_GPI_WAKE_MASK 0x80000000
1262 #define HDA_PARAM_GPIO_COUNT_GPI_WAKE_SHIFT 31
1263 #define HDA_PARAM_GPIO_COUNT_GPI_UNSOL_MASK 0x40000000
1264 #define HDA_PARAM_GPIO_COUNT_GPI_UNSOL_SHIFT 30
1265 #define HDA_PARAM_GPIO_COUNT_NUM_GPI_MASK 0x00ff0000
1266 #define HDA_PARAM_GPIO_COUNT_NUM_GPI_SHIFT 16
1267 #define HDA_PARAM_GPIO_COUNT_NUM_GPO_MASK 0x0000ff00
1268 #define HDA_PARAM_GPIO_COUNT_NUM_GPO_SHIFT 8
1269 #define HDA_PARAM_GPIO_COUNT_NUM_GPIO_MASK 0x000000ff
1270 #define HDA_PARAM_GPIO_COUNT_NUM_GPIO_SHIFT 0
1272 #define HDA_PARAM_GPIO_COUNT_GPI_WAKE(param) \
1273 (((param) & HDA_PARAM_GPIO_COUNT_GPI_WAKE_MASK) >> \
1274 HDA_PARAM_GPIO_COUNT_GPI_WAKE_SHIFT)
1275 #define HDA_PARAM_GPIO_COUNT_GPI_UNSOL(param) \
1276 (((param) & HDA_PARAM_GPIO_COUNT_GPI_UNSOL_MASK) >> \
1277 HDA_PARAM_GPIO_COUNT_GPI_UNSOL_SHIFT)
1278 #define HDA_PARAM_GPIO_COUNT_NUM_GPI(param) \
1279 (((param) & HDA_PARAM_GPIO_COUNT_NUM_GPI_MASK) >> \
1280 HDA_PARAM_GPIO_COUNT_NUM_GPI_SHIFT)
1281 #define HDA_PARAM_GPIO_COUNT_NUM_GPO(param) \
1282 (((param) & HDA_PARAM_GPIO_COUNT_NUM_GPO_MASK) >> \
1283 HDA_PARAM_GPIO_COUNT_NUM_GPO_SHIFT)
1284 #define HDA_PARAM_GPIO_COUNT_NUM_GPIO(param) \
1285 (((param) & HDA_PARAM_GPIO_COUNT_NUM_GPIO_MASK) >> \
1286 HDA_PARAM_GPIO_COUNT_NUM_GPIO_SHIFT)
1288 /* Volume Knob Capabilities */
1289 #define HDA_PARAM_VOLUME_KNOB_CAP 0x13
1291 #define HDA_PARAM_VOLUME_KNOB_CAP_DELTA_MASK 0x00000080
1292 #define HDA_PARAM_VOLUME_KNOB_CAP_DELTA_SHIFT 7
1293 #define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_MASK 0x0000007f
1294 #define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_SHIFT 0
1296 #define HDA_PARAM_VOLUME_KNOB_CAP_DELTA(param) \
1297 (((param) & HDA_PARAM_VOLUME_KNOB_CAP_DELTA_MASK) >> \
1298 HDA_PARAM_VOLUME_KNOB_CAP_DELTA_SHIFT)
1299 #define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS(param) \
1300 (((param) & HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_MASK) >> \
1301 HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_SHIFT)
1304 #define HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK 0x0000000f
1305 #define HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT 0
1306 #define HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK 0x000000f0
1307 #define HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT 4
1308 #define HDA_CONFIG_DEFAULTCONF_MISC_MASK 0x00000f00
1309 #define HDA_CONFIG_DEFAULTCONF_MISC_SHIFT 8
1310 #define HDA_CONFIG_DEFAULTCONF_COLOR_MASK 0x0000f000
1311 #define HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT 12
1312 #define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK 0x000f0000
1313 #define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT 16
1314 #define HDA_CONFIG_DEFAULTCONF_DEVICE_MASK 0x00f00000
1315 #define HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT 20
1316 #define HDA_CONFIG_DEFAULTCONF_LOCATION_MASK 0x3f000000
1317 #define HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT 24
1318 #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK 0xc0000000
1319 #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT 30
1321 #define HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf) \
1322 (((conf) & HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK) >> \
1323 HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT)
1324 #define HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf) \
1325 (((conf) & HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) >> \
1326 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT)
1327 #define HDA_CONFIG_DEFAULTCONF_MISC(conf) \
1328 (((conf) & HDA_CONFIG_DEFAULTCONF_MISC_MASK) >> \
1329 HDA_CONFIG_DEFAULTCONF_MISC_SHIFT)
1330 #define HDA_CONFIG_DEFAULTCONF_COLOR(conf) \
1331 (((conf) & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> \
1332 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT)
1333 #define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf) \
1334 (((conf) & HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK) >> \
1335 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT)
1336 #define HDA_CONFIG_DEFAULTCONF_DEVICE(conf) \
1337 (((conf) & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> \
1338 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT)
1339 #define HDA_CONFIG_DEFAULTCONF_LOCATION(conf) \
1340 (((conf) & HDA_CONFIG_DEFAULTCONF_LOCATION_MASK) >> \
1341 HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT)
1342 #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf) \
1343 (((conf) & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> \
1344 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT)
1346 #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK (0<<30)
1347 #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE (1<<30)
1348 #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED (2<<30)
1349 #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH (3<<30)
1351 #define HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT (0<<20)
1352 #define HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER (1<<20)
1353 #define HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT (2<<20)
1354 #define HDA_CONFIG_DEFAULTCONF_DEVICE_CD (3<<20)
1355 #define HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT (4<<20)
1356 #define HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT (5<<20)
1357 #define HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE (6<<20)
1358 #define HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET (7<<20)
1359 #define HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN (8<<20)
1360 #define HDA_CONFIG_DEFAULTCONF_DEVICE_AUX (9<<20)
1361 #define HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN (10<<20)
1362 #define HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY (11<<20)
1363 #define HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN (12<<20)
1364 #define HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN (13<<20)
1365 #define HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER (15<<20)