sys/dev/sound/pci/hda/hdac.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
   5  * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
   6  * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  */
  30
  31 /*
  32  * Intel High Definition Audio (Controller) driver for FreeBSD.
  33  */
  34
  35 #ifdef HAVE_KERNEL_OPTION_HEADERS
  36 #include "opt_snd.h"
  37 #endif
  38
  39 #include <dev/sound/pcm/sound.h>
  40 #include <dev/pci/pcireg.h>
  41 #include <dev/pci/pcivar.h>
  42
  43 #include <sys/ctype.h>
  44 #include <sys/endian.h>
  45 #include <sys/taskqueue.h>
  46
  47 #include <dev/sound/pci/hda/hdac_private.h>
  48 #include <dev/sound/pci/hda/hdac_reg.h>
  49 #include <dev/sound/pci/hda/hda_reg.h>
  50 #include <dev/sound/pci/hda/hdac.h>
  51
  52 #define HDA_DRV_TEST_REV        "20120126_0002"
  53
  54 SND_DECLARE_FILE("$FreeBSD$");
  55
  56 #define hdac_lock(sc)           snd_mtxlock((sc)->lock)
  57 #define hdac_unlock(sc)         snd_mtxunlock((sc)->lock)
  58 #define hdac_lockassert(sc)     snd_mtxassert((sc)->lock)
  59 #define hdac_lockowned(sc)      mtx_owned((sc)->lock)
  60
  61 #define HDAC_QUIRK_64BIT        (1 << 0)
  62 #define HDAC_QUIRK_DMAPOS       (1 << 1)
  63 #define HDAC_QUIRK_MSI          (1 << 2)
  64
  65 static const struct {
  66         const char *key;
  67         uint32_t value;
  68 } hdac_quirks_tab[] = {
  69         { "64bit", HDAC_QUIRK_DMAPOS },
  70         { "dmapos", HDAC_QUIRK_DMAPOS },
  71         { "msi", HDAC_QUIRK_MSI },
  72 };
  73
  74 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller");
  75
  76 static const struct {
  77         uint32_t        model;
  78         const char      *desc;
  79         char            quirks_on;
  80         char            quirks_off;
  81 } hdac_devices[] = {
  82         { HDA_INTEL_OAK,     "Intel Oaktrail",  0, 0 },
  83         { HDA_INTEL_BAY,     "Intel BayTrail",  0, 0 },
  84         { HDA_INTEL_HSW1,    "Intel Haswell",   0, 0 },
  85         { HDA_INTEL_HSW2,    "Intel Haswell",   0, 0 },
  86         { HDA_INTEL_HSW3,    "Intel Haswell",   0, 0 },
  87         { HDA_INTEL_BDW1,    "Intel Broadwell", 0, 0 },
  88         { HDA_INTEL_BDW2,    "Intel Broadwell", 0, 0 },
  89         { HDA_INTEL_CPT,     "Intel Cougar Point",      0, 0 },
  90         { HDA_INTEL_PATSBURG,"Intel Patsburg",  0, 0 },
  91         { HDA_INTEL_PPT1,    "Intel Panther Point",     0, 0 },
  92         { HDA_INTEL_LPT1,    "Intel Lynx Point",        0, 0 },
  93         { HDA_INTEL_LPT2,    "Intel Lynx Point",        0, 0 },
  94         { HDA_INTEL_WCPT,    "Intel Wildcat Point",     0, 0 },
  95         { HDA_INTEL_WELLS1,  "Intel Wellsburg", 0, 0 },
  96         { HDA_INTEL_WELLS2,  "Intel Wellsburg", 0, 0 },
  97         { HDA_INTEL_LPTLP1,  "Intel Lynx Point-LP",     0, 0 },
  98         { HDA_INTEL_LPTLP2,  "Intel Lynx Point-LP",     0, 0 },
  99         { HDA_INTEL_SRPTLP,  "Intel Sunrise Point-LP",  0, 0 },
 100         { HDA_INTEL_KBLKLP,  "Intel Kaby Lake-LP",      0, 0 },
 101         { HDA_INTEL_SRPT,    "Intel Sunrise Point",     0, 0 },
 102         { HDA_INTEL_KBLK,    "Intel Kaby Lake", 0, 0 },
 103         { HDA_INTEL_KBLKH,   "Intel Kaby Lake-H",       0, 0 },
 104         { HDA_INTEL_CFLK,    "Intel Coffee Lake",       0, 0 },
 105         { HDA_INTEL_82801F,  "Intel 82801F",    0, 0 },
 106         { HDA_INTEL_63XXESB, "Intel 631x/632xESB",      0, 0 },
 107         { HDA_INTEL_82801G,  "Intel 82801G",    0, 0 },
 108         { HDA_INTEL_82801H,  "Intel 82801H",    0, 0 },
 109         { HDA_INTEL_82801I,  "Intel 82801I",    0, 0 },
 110         { HDA_INTEL_82801JI, "Intel 82801JI",   0, 0 },
 111         { HDA_INTEL_82801JD, "Intel 82801JD",   0, 0 },
 112         { HDA_INTEL_PCH,     "Intel Ibex Peak", 0, 0 },
 113         { HDA_INTEL_PCH2,    "Intel Ibex Peak", 0, 0 },
 114         { HDA_INTEL_SCH,     "Intel SCH",       0, 0 },
 115         { HDA_NVIDIA_MCP51,  "NVIDIA MCP51",    0, HDAC_QUIRK_MSI },
 116         { HDA_NVIDIA_MCP55,  "NVIDIA MCP55",    0, HDAC_QUIRK_MSI },
 117         { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61",   0, 0 },
 118         { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61",   0, 0 },
 119         { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65",   0, 0 },
 120         { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65",   0, 0 },
 121         { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67",   0, 0 },
 122         { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67",   0, 0 },
 123         { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73",   0, 0 },
 124         { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73",   0, 0 },
 125         { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 126         { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 127         { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 128         { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 129         { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79",   0, 0 },
 130         { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79",   0, 0 },
 131         { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79",   0, 0 },
 132         { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79",   0, 0 },
 133         { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89",   0, 0 },
 134         { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89",   0, 0 },
 135         { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89",   0, 0 },
 136         { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89",   0, 0 },
 137         { HDA_NVIDIA_0BE2,   "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI },
 138         { HDA_NVIDIA_0BE3,   "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI },
 139         { HDA_NVIDIA_0BE4,   "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI },
 140         { HDA_NVIDIA_GT100,  "NVIDIA GT100",    0, HDAC_QUIRK_MSI },
 141         { HDA_NVIDIA_GT104,  "NVIDIA GT104",    0, HDAC_QUIRK_MSI },
 142         { HDA_NVIDIA_GT106,  "NVIDIA GT106",    0, HDAC_QUIRK_MSI },
 143         { HDA_NVIDIA_GT108,  "NVIDIA GT108",    0, HDAC_QUIRK_MSI },
 144         { HDA_NVIDIA_GT116,  "NVIDIA GT116",    0, HDAC_QUIRK_MSI },
 145         { HDA_NVIDIA_GF119,  "NVIDIA GF119",    0, 0 },
 146         { HDA_NVIDIA_GF110_1, "NVIDIA GF110",   0, HDAC_QUIRK_MSI },
 147         { HDA_NVIDIA_GF110_2, "NVIDIA GF110",   0, HDAC_QUIRK_MSI },
 148         { HDA_ATI_SB450,     "ATI SB450",       0, 0 },
 149         { HDA_ATI_SB600,     "ATI SB600",       0, 0 },
 150         { HDA_ATI_RS600,     "ATI RS600",       0, 0 },
 151         { HDA_ATI_RS690,     "ATI RS690",       0, 0 },
 152         { HDA_ATI_RS780,     "ATI RS780",       0, 0 },
 153         { HDA_ATI_R600,      "ATI R600",        0, 0 },
 154         { HDA_ATI_RV610,     "ATI RV610",       0, 0 },
 155         { HDA_ATI_RV620,     "ATI RV620",       0, 0 },
 156         { HDA_ATI_RV630,     "ATI RV630",       0, 0 },
 157         { HDA_ATI_RV635,     "ATI RV635",       0, 0 },
 158         { HDA_ATI_RV710,     "ATI RV710",       0, 0 },
 159         { HDA_ATI_RV730,     "ATI RV730",       0, 0 },
 160         { HDA_ATI_RV740,     "ATI RV740",       0, 0 },
 161         { HDA_ATI_RV770,     "ATI RV770",       0, 0 },
 162         { HDA_ATI_RV810,     "ATI RV810",       0, 0 },
 163         { HDA_ATI_RV830,     "ATI RV830",       0, 0 },
 164         { HDA_ATI_RV840,     "ATI RV840",       0, 0 },
 165         { HDA_ATI_RV870,     "ATI RV870",       0, 0 },
 166         { HDA_ATI_RV910,     "ATI RV910",       0, 0 },
 167         { HDA_ATI_RV930,     "ATI RV930",       0, 0 },
 168         { HDA_ATI_RV940,     "ATI RV940",       0, 0 },
 169         { HDA_ATI_RV970,     "ATI RV970",       0, 0 },
 170         { HDA_ATI_R1000,     "ATI R1000",       0, 0 },
 171         { HDA_AMD_HUDSON2,   "AMD Hudson-2",    0, 0 },
 172         { HDA_RDC_M3010,     "RDC M3010",       0, 0 },
 173         { HDA_VIA_VT82XX,    "VIA VT8251/8237A",0, 0 },
 174         { HDA_SIS_966,       "SiS 966/968",     0, 0 },
 175         { HDA_ULI_M5461,     "ULI M5461",       0, 0 },
 176         /* Unknown */
 177         { HDA_INTEL_ALL,  "Intel",              0, 0 },
 178         { HDA_NVIDIA_ALL, "NVIDIA",             0, 0 },
 179         { HDA_ATI_ALL,    "ATI",                0, 0 },
 180         { HDA_AMD_ALL,    "AMD",                0, 0 },
 181         { HDA_CREATIVE_ALL,    "Creative",      0, 0 },
 182         { HDA_VIA_ALL,    "VIA",                0, 0 },
 183         { HDA_SIS_ALL,    "SiS",                0, 0 },
 184         { HDA_ULI_ALL,    "ULI",                0, 0 },
 185 };
 186
 187 static const struct {
 188         uint16_t vendor;
 189         uint8_t reg;
 190         uint8_t mask;
 191         uint8_t enable;
 192 } hdac_pcie_snoop[] = {
 193         {  INTEL_VENDORID, 0x00, 0x00, 0x00 },
 194         {    ATI_VENDORID, 0x42, 0xf8, 0x02 },
 195         { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
 196 };
 197
 198 /****************************************************************************
 199  * Function prototypes
 200  ****************************************************************************/
 201 static void     hdac_intr_handler(void *);
 202 static int      hdac_reset(struct hdac_softc *, int);
 203 static int      hdac_get_capabilities(struct hdac_softc *);
 204 static void     hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
 205 static int      hdac_dma_alloc(struct hdac_softc *,
 206                                         struct hdac_dma *, bus_size_t);
 207 static void     hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
 208 static int      hdac_mem_alloc(struct hdac_softc *);
 209 static void     hdac_mem_free(struct hdac_softc *);
 210 static int      hdac_irq_alloc(struct hdac_softc *);
 211 static void     hdac_irq_free(struct hdac_softc *);
 212 static void     hdac_corb_init(struct hdac_softc *);
 213 static void     hdac_rirb_init(struct hdac_softc *);
 214 static void     hdac_corb_start(struct hdac_softc *);
 215 static void     hdac_rirb_start(struct hdac_softc *);
 216
 217 static void     hdac_attach2(void *);
 218
 219 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t);
 220
 221 static int      hdac_probe(device_t);
 222 static int      hdac_attach(device_t);
 223 static int      hdac_detach(device_t);
 224 static int      hdac_suspend(device_t);
 225 static int      hdac_resume(device_t);
 226
 227 static int      hdac_rirb_flush(struct hdac_softc *sc);
 228 static int      hdac_unsolq_flush(struct hdac_softc *sc);
 229
 230 #define hdac_command(a1, a2, a3)        \
 231                 hdac_send_command(a1, a3, a2)
 232
 233 /* This function surely going to make its way into upper level someday. */
 234 static void
 235 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
 236 {
 237         const char *res = NULL;
 238         int i = 0, j, k, len, inv;
 239
 240         if (resource_string_value(device_get_name(sc->dev),
 241             device_get_unit(sc->dev), "config", &res) != 0)
 242                 return;
 243         if (!(res != NULL && strlen(res) > 0))
 244                 return;
 245         HDA_BOOTVERBOSE(
 246                 device_printf(sc->dev, "Config options:");
 247         );
 248         for (;;) {
 249                 while (res[i] != '\0' &&
 250                     (res[i] == ',' || isspace(res[i]) != 0))
 251                         i++;
 252                 if (res[i] == '\0') {
 253                         HDA_BOOTVERBOSE(
 254                                 printf("\n");
 255                         );
 256                         return;
 257                 }
 258                 j = i;
 259                 while (res[j] != '\0' &&
 260                     !(res[j] == ',' || isspace(res[j]) != 0))
 261                         j++;
 262                 len = j - i;
 263                 if (len > 2 && strncmp(res + i, "no", 2) == 0)
 264                         inv = 2;
 265                 else
 266                         inv = 0;
 267                 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) {
 268                         if (strncmp(res + i + inv,
 269                             hdac_quirks_tab[k].key, len - inv) != 0)
 270                                 continue;
 271                         if (len - inv != strlen(hdac_quirks_tab[k].key))
 272                                 continue;
 273                         HDA_BOOTVERBOSE(
 274                                 printf(" %s%s", (inv != 0) ? "no" : "",
 275                                     hdac_quirks_tab[k].key);
 276                         );
 277                         if (inv == 0) {
 278                                 *on |= hdac_quirks_tab[k].value;
 279                                 *on &= ~hdac_quirks_tab[k].value;
 280                         } else if (inv != 0) {
 281                                 *off |= hdac_quirks_tab[k].value;
 282                                 *off &= ~hdac_quirks_tab[k].value;
 283                         }
 284                         break;
 285                 }
 286                 i = j;
 287         }
 288 }
 289
 290 /****************************************************************************
 291  * void hdac_intr_handler(void *)
 292  *
 293  * Interrupt handler. Processes interrupts received from the hdac.
 294  ****************************************************************************/
 295 static void
 296 hdac_intr_handler(void *context)
 297 {
 298         struct hdac_softc *sc;
 299         device_t dev;
 300         uint32_t intsts;
 301         uint8_t rirbsts;
 302         int i;
 303
 304         sc = (struct hdac_softc *)context;
 305         hdac_lock(sc);
 306
 307         /* Do we have anything to do? */
 308         intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
 309         if ((intsts & HDAC_INTSTS_GIS) == 0) {
 310                 hdac_unlock(sc);
 311                 return;
 312         }
 313
 314         /* Was this a controller interrupt? */
 315         if (intsts & HDAC_INTSTS_CIS) {
 316                 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
 317                 /* Get as many responses that we can */
 318                 while (rirbsts & HDAC_RIRBSTS_RINTFL) {
 319                         HDAC_WRITE_1(&sc->mem,
 320                             HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
 321                         hdac_rirb_flush(sc);
 322                         rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
 323                 }
 324                 if (sc->unsolq_rp != sc->unsolq_wp)
 325                         taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
 326         }
 327
 328         if (intsts & HDAC_INTSTS_SIS_MASK) {
 329                 for (i = 0; i < sc->num_ss; i++) {
 330                         if ((intsts & (1 << i)) == 0)
 331                                 continue;
 332                         HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS,
 333                             HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
 334                         if ((dev = sc->streams[i].dev) != NULL) {
 335                                 HDAC_STREAM_INTR(dev,
 336                                     sc->streams[i].dir, sc->streams[i].stream);
 337                         }
 338                 }
 339         }
 340
 341         HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts);
 342         hdac_unlock(sc);
 343 }
 344
 345 static void
 346 hdac_poll_callback(void *arg)
 347 {
 348         struct hdac_softc *sc = arg;
 349
 350         if (sc == NULL)
 351                 return;
 352
 353         hdac_lock(sc);
 354         if (sc->polling == 0) {
 355                 hdac_unlock(sc);
 356                 return;
 357         }
 358         callout_reset(&sc->poll_callout, sc->poll_ival,
 359             hdac_poll_callback, sc);
 360         hdac_unlock(sc);
 361
 362         hdac_intr_handler(sc);
 363 }
 364
 365 /****************************************************************************
 366  * int hdac_reset(hdac_softc *, int)
 367  *
 368  * Reset the hdac to a quiescent and known state.
 369  ****************************************************************************/
 370 static int
 371 hdac_reset(struct hdac_softc *sc, int wakeup)
 372 {
 373         uint32_t gctl;
 374         int count, i;
 375
 376         /*
 377          * Stop all Streams DMA engine
 378          */
 379         for (i = 0; i < sc->num_iss; i++)
 380                 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
 381         for (i = 0; i < sc->num_oss; i++)
 382                 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
 383         for (i = 0; i < sc->num_bss; i++)
 384                 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
 385
 386         /*
 387          * Stop Control DMA engines.
 388          */
 389         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
 390         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
 391
 392         /*
 393          * Reset DMA position buffer.
 394          */
 395         HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
 396         HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
 397
 398         /*
 399          * Reset the controller. The reset must remain asserted for
 400          * a minimum of 100us.
 401          */
 402         gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 403         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
 404         count = 10000;
 405         do {
 406                 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 407                 if (!(gctl & HDAC_GCTL_CRST))
 408                         break;
 409                 DELAY(10);
 410         } while (--count);
 411         if (gctl & HDAC_GCTL_CRST) {
 412                 device_printf(sc->dev, "Unable to put hdac in reset\n");
 413                 return (ENXIO);
 414         }
 415
 416         /* If wakeup is not requested - leave the controller in reset state. */
 417         if (!wakeup)
 418                 return (0);
 419
 420         DELAY(100);
 421         gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 422         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
 423         count = 10000;
 424         do {
 425                 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 426                 if (gctl & HDAC_GCTL_CRST)
 427                         break;
 428                 DELAY(10);
 429         } while (--count);
 430         if (!(gctl & HDAC_GCTL_CRST)) {
 431                 device_printf(sc->dev, "Device stuck in reset\n");
 432                 return (ENXIO);
 433         }
 434
 435         /*
 436          * Wait for codecs to finish their own reset sequence. The delay here
 437          * should be of 250us but for some reasons, it's not enough on my
 438          * computer. Let's use twice as much as necessary to make sure that
 439          * it's reset properly.
 440          */
 441         DELAY(1000);
 442
 443         return (0);
 444 }
 445
 446
 447 /****************************************************************************
 448  * int hdac_get_capabilities(struct hdac_softc *);
 449  *
 450  * Retreive the general capabilities of the hdac;
 451  *      Number of Input Streams
 452  *      Number of Output Streams
 453  *      Number of bidirectional Streams
 454  *      64bit ready
 455  *      CORB and RIRB sizes
 456  ****************************************************************************/
 457 static int
 458 hdac_get_capabilities(struct hdac_softc *sc)
 459 {
 460         uint16_t gcap;
 461         uint8_t corbsize, rirbsize;
 462
 463         gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
 464         sc->num_iss = HDAC_GCAP_ISS(gcap);
 465         sc->num_oss = HDAC_GCAP_OSS(gcap);
 466         sc->num_bss = HDAC_GCAP_BSS(gcap);
 467         sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss;
 468         sc->num_sdo = HDAC_GCAP_NSDO(gcap);
 469         sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0;
 470         if (sc->quirks_on & HDAC_QUIRK_64BIT)
 471                 sc->support_64bit = 1;
 472         else if (sc->quirks_off & HDAC_QUIRK_64BIT)
 473                 sc->support_64bit = 0;
 474
 475         corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
 476         if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
 477             HDAC_CORBSIZE_CORBSZCAP_256)
 478                 sc->corb_size = 256;
 479         else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
 480             HDAC_CORBSIZE_CORBSZCAP_16)
 481                 sc->corb_size = 16;
 482         else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
 483             HDAC_CORBSIZE_CORBSZCAP_2)
 484                 sc->corb_size = 2;
 485         else {
 486                 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
 487                     __func__, corbsize);
 488                 return (ENXIO);
 489         }
 490
 491         rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
 492         if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
 493             HDAC_RIRBSIZE_RIRBSZCAP_256)
 494                 sc->rirb_size = 256;
 495         else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
 496             HDAC_RIRBSIZE_RIRBSZCAP_16)
 497                 sc->rirb_size = 16;
 498         else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
 499             HDAC_RIRBSIZE_RIRBSZCAP_2)
 500                 sc->rirb_size = 2;
 501         else {
 502                 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
 503                     __func__, rirbsize);
 504                 return (ENXIO);
 505         }
 506
 507         HDA_BOOTVERBOSE(
 508                 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, "
 509                     "NSDO %d%s, CORB %d, RIRB %d\n",
 510                     sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo,
 511                     sc->support_64bit ? ", 64bit" : "",
 512                     sc->corb_size, sc->rirb_size);
 513         );
 514
 515         return (0);
 516 }
 517
 518
 519 /****************************************************************************
 520  * void hdac_dma_cb
 521  *
 522  * This function is called by bus_dmamap_load when the mapping has been
 523  * established. We just record the physical address of the mapping into
 524  * the struct hdac_dma passed in.
 525  ****************************************************************************/
 526 static void
 527 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
 528 {
 529         struct hdac_dma *dma;
 530
 531         if (error == 0) {
 532                 dma = (struct hdac_dma *)callback_arg;
 533                 dma->dma_paddr = segs[0].ds_addr;
 534         }
 535 }
 536
 537
 538 /****************************************************************************
 539  * int hdac_dma_alloc
 540  *
 541  * This function allocate and setup a dma region (struct hdac_dma).
 542  * It must be freed by a corresponding hdac_dma_free.
 543  ****************************************************************************/
 544 static int
 545 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
 546 {
 547         bus_size_t roundsz;
 548         int result;
 549
 550         roundsz = roundup2(size, HDA_DMA_ALIGNMENT);
 551         bzero(dma, sizeof(*dma));
 552
 553         /*
 554          * Create a DMA tag
 555          */
 556         result = bus_dma_tag_create(
 557             bus_get_dma_tag(sc->dev),           /* parent */
 558             HDA_DMA_ALIGNMENT,                  /* alignment */
 559             0,                                  /* boundary */
 560             (sc->support_64bit) ? BUS_SPACE_MAXADDR :
 561                 BUS_SPACE_MAXADDR_32BIT,        /* lowaddr */
 562             BUS_SPACE_MAXADDR,                  /* highaddr */
 563             NULL,                               /* filtfunc */
 564             NULL,                               /* fistfuncarg */
 565             roundsz,                            /* maxsize */
 566             1,                                  /* nsegments */
 567             roundsz,                            /* maxsegsz */
 568             0,                                  /* flags */
 569             NULL,                               /* lockfunc */
 570             NULL,                               /* lockfuncarg */
 571             &dma->dma_tag);                     /* dmat */
 572         if (result != 0) {
 573                 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%d)\n",
 574                     __func__, result);
 575                 goto hdac_dma_alloc_fail;
 576         }
 577
 578         /*
 579          * Allocate DMA memory
 580          */
 581         result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
 582             BUS_DMA_NOWAIT | BUS_DMA_ZERO |
 583             ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE :
 584              BUS_DMA_COHERENT),
 585             &dma->dma_map);
 586         if (result != 0) {
 587                 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%d)\n",
 588                     __func__, result);
 589                 goto hdac_dma_alloc_fail;
 590         }
 591
 592         dma->dma_size = roundsz;
 593
 594         /*
 595          * Map the memory
 596          */
 597         result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
 598             (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
 599         if (result != 0 || dma->dma_paddr == 0) {
 600                 if (result == 0)
 601                         result = ENOMEM;
 602                 device_printf(sc->dev, "%s: bus_dmamem_load failed (%d)\n",
 603                     __func__, result);
 604                 goto hdac_dma_alloc_fail;
 605         }
 606
 607         HDA_BOOTHVERBOSE(
 608                 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
 609                     __func__, (uintmax_t)size, (uintmax_t)roundsz);
 610         );
 611
 612         return (0);
 613
 614 hdac_dma_alloc_fail:
 615         hdac_dma_free(sc, dma);
 616
 617         return (result);
 618 }
 619
 620
 621 /****************************************************************************
 622  * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
 623  *
 624  * Free a struct dhac_dma that has been previously allocated via the
 625  * hdac_dma_alloc function.
 626  ****************************************************************************/
 627 static void
 628 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
 629 {
 630         if (dma->dma_paddr != 0) {
 631                 /* Flush caches */
 632                 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
 633                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 634                 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
 635                 dma->dma_paddr = 0;
 636         }
 637         if (dma->dma_vaddr != NULL) {
 638                 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
 639                 dma->dma_vaddr = NULL;
 640         }
 641         if (dma->dma_tag != NULL) {
 642                 bus_dma_tag_destroy(dma->dma_tag);
 643                 dma->dma_tag = NULL;
 644         }
 645         dma->dma_size = 0;
 646 }
 647
 648 /****************************************************************************
 649  * int hdac_mem_alloc(struct hdac_softc *)
 650  *
 651  * Allocate all the bus resources necessary to speak with the physical
 652  * controller.
 653  ****************************************************************************/
 654 static int
 655 hdac_mem_alloc(struct hdac_softc *sc)
 656 {
 657         struct hdac_mem *mem;
 658
 659         mem = &sc->mem;
 660         mem->mem_rid = PCIR_BAR(0);
 661         mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
 662             &mem->mem_rid, RF_ACTIVE);
 663         if (mem->mem_res == NULL) {
 664                 device_printf(sc->dev,
 665                     "%s: Unable to allocate memory resource\n", __func__);
 666                 return (ENOMEM);
 667         }
 668         mem->mem_tag = rman_get_bustag(mem->mem_res);
 669         mem->mem_handle = rman_get_bushandle(mem->mem_res);
 670
 671         return (0);
 672 }
 673
 674 /****************************************************************************
 675  * void hdac_mem_free(struct hdac_softc *)
 676  *
 677  * Free up resources previously allocated by hdac_mem_alloc.
 678  ****************************************************************************/
 679 static void
 680 hdac_mem_free(struct hdac_softc *sc)
 681 {
 682         struct hdac_mem *mem;
 683
 684         mem = &sc->mem;
 685         if (mem->mem_res != NULL)
 686                 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
 687                     mem->mem_res);
 688         mem->mem_res = NULL;
 689 }
 690
 691 /****************************************************************************
 692  * int hdac_irq_alloc(struct hdac_softc *)
 693  *
 694  * Allocate and setup the resources necessary for interrupt handling.
 695  ****************************************************************************/
 696 static int
 697 hdac_irq_alloc(struct hdac_softc *sc)
 698 {
 699         struct hdac_irq *irq;
 700         int result;
 701
 702         irq = &sc->irq;
 703         irq->irq_rid = 0x0;
 704
 705         if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 &&
 706             (result = pci_msi_count(sc->dev)) == 1 &&
 707             pci_alloc_msi(sc->dev, &result) == 0)
 708                 irq->irq_rid = 0x1;
 709
 710         irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
 711             &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
 712         if (irq->irq_res == NULL) {
 713                 device_printf(sc->dev, "%s: Unable to allocate irq\n",
 714                     __func__);
 715                 goto hdac_irq_alloc_fail;
 716         }
 717         result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV,
 718             NULL, hdac_intr_handler, sc, &irq->irq_handle);
 719         if (result != 0) {
 720                 device_printf(sc->dev,
 721                     "%s: Unable to setup interrupt handler (%d)\n",
 722                     __func__, result);
 723                 goto hdac_irq_alloc_fail;
 724         }
 725
 726         return (0);
 727
 728 hdac_irq_alloc_fail:
 729         hdac_irq_free(sc);
 730
 731         return (ENXIO);
 732 }
 733
 734 /****************************************************************************
 735  * void hdac_irq_free(struct hdac_softc *)
 736  *
 737  * Free up resources previously allocated by hdac_irq_alloc.
 738  ****************************************************************************/
 739 static void
 740 hdac_irq_free(struct hdac_softc *sc)
 741 {
 742         struct hdac_irq *irq;
 743
 744         irq = &sc->irq;
 745         if (irq->irq_res != NULL && irq->irq_handle != NULL)
 746                 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
 747         if (irq->irq_res != NULL)
 748                 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
 749                     irq->irq_res);
 750         if (irq->irq_rid == 0x1)
 751                 pci_release_msi(sc->dev);
 752         irq->irq_handle = NULL;
 753         irq->irq_res = NULL;
 754         irq->irq_rid = 0x0;
 755 }
 756
 757 /****************************************************************************
 758  * void hdac_corb_init(struct hdac_softc *)
 759  *
 760  * Initialize the corb registers for operations but do not start it up yet.
 761  * The CORB engine must not be running when this function is called.
 762  ****************************************************************************/
 763 static void
 764 hdac_corb_init(struct hdac_softc *sc)
 765 {
 766         uint8_t corbsize;
 767         uint64_t corbpaddr;
 768
 769         /* Setup the CORB size. */
 770         switch (sc->corb_size) {
 771         case 256:
 772                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
 773                 break;
 774         case 16:
 775                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
 776                 break;
 777         case 2:
 778                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
 779                 break;
 780         default:
 781                 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
 782         }
 783         HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
 784
 785         /* Setup the CORB Address in the hdac */
 786         corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
 787         HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
 788         HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
 789
 790         /* Set the WP and RP */
 791         sc->corb_wp = 0;
 792         HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
 793         HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
 794         /*
 795          * The HDA specification indicates that the CORBRPRST bit will always
 796          * read as zero. Unfortunately, it seems that at least the 82801G
 797          * doesn't reset the bit to zero, which stalls the corb engine.
 798          * manually reset the bit to zero before continuing.
 799          */
 800         HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
 801
 802         /* Enable CORB error reporting */
 803 #if 0
 804         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
 805 #endif
 806 }
 807
 808 /****************************************************************************
 809  * void hdac_rirb_init(struct hdac_softc *)
 810  *
 811  * Initialize the rirb registers for operations but do not start it up yet.
 812  * The RIRB engine must not be running when this function is called.
 813  ****************************************************************************/
 814 static void
 815 hdac_rirb_init(struct hdac_softc *sc)
 816 {
 817         uint8_t rirbsize;
 818         uint64_t rirbpaddr;
 819
 820         /* Setup the RIRB size. */
 821         switch (sc->rirb_size) {
 822         case 256:
 823                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
 824                 break;
 825         case 16:
 826                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
 827                 break;
 828         case 2:
 829                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
 830                 break;
 831         default:
 832                 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
 833         }
 834         HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
 835
 836         /* Setup the RIRB Address in the hdac */
 837         rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
 838         HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
 839         HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
 840
 841         /* Setup the WP and RP */
 842         sc->rirb_rp = 0;
 843         HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
 844
 845         /* Setup the interrupt threshold */
 846         HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
 847
 848         /* Enable Overrun and response received reporting */
 849 #if 0
 850         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
 851             HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
 852 #else
 853         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
 854 #endif
 855
 856         /*
 857          * Make sure that the Host CPU cache doesn't contain any dirty
 858          * cache lines that falls in the rirb. If I understood correctly, it
 859          * should be sufficient to do this only once as the rirb is purely
 860          * read-only from now on.
 861          */
 862         bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
 863             BUS_DMASYNC_PREREAD);
 864 }
 865
 866 /****************************************************************************
 867  * void hdac_corb_start(hdac_softc *)
 868  *
 869  * Startup the corb DMA engine
 870  ****************************************************************************/
 871 static void
 872 hdac_corb_start(struct hdac_softc *sc)
 873 {
 874         uint32_t corbctl;
 875
 876         corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
 877         corbctl |= HDAC_CORBCTL_CORBRUN;
 878         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
 879 }
 880
 881 /****************************************************************************
 882  * void hdac_rirb_start(hdac_softc *)
 883  *
 884  * Startup the rirb DMA engine
 885  ****************************************************************************/
 886 static void
 887 hdac_rirb_start(struct hdac_softc *sc)
 888 {
 889         uint32_t rirbctl;
 890
 891         rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
 892         rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
 893         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
 894 }
 895
 896 static int
 897 hdac_rirb_flush(struct hdac_softc *sc)
 898 {
 899         struct hdac_rirb *rirb_base, *rirb;
 900         nid_t cad;
 901         uint32_t resp, resp_ex;
 902         uint8_t rirbwp;
 903         int ret;
 904
 905         rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
 906         rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
 907         bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
 908             BUS_DMASYNC_POSTREAD);
 909
 910         ret = 0;
 911         while (sc->rirb_rp != rirbwp) {
 912                 sc->rirb_rp++;
 913                 sc->rirb_rp %= sc->rirb_size;
 914                 rirb = &rirb_base[sc->rirb_rp];
 915                 resp = le32toh(rirb->response);
 916                 resp_ex = le32toh(rirb->response_ex);
 917                 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(resp_ex);
 918                 if (resp_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
 919                         sc->unsolq[sc->unsolq_wp++] = resp;
 920                         sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
 921                         sc->unsolq[sc->unsolq_wp++] = cad;
 922                         sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
 923                 } else if (sc->codecs[cad].pending <= 0) {
 924                         device_printf(sc->dev, "Unexpected unsolicited "
 925                             "response from address %d: %08x\n", cad, resp);
 926                 } else {
 927                         sc->codecs[cad].response = resp;
 928                         sc->codecs[cad].pending--;
 929                 }
 930                 ret++;
 931         }
 932
 933         bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
 934             BUS_DMASYNC_PREREAD);
 935         return (ret);
 936 }
 937
 938 static int
 939 hdac_unsolq_flush(struct hdac_softc *sc)
 940 {
 941         device_t child;
 942         nid_t cad;
 943         uint32_t resp;
 944         int ret = 0;
 945
 946         if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
 947                 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
 948                 while (sc->unsolq_rp != sc->unsolq_wp) {
 949                         resp = sc->unsolq[sc->unsolq_rp++];
 950                         sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
 951                         cad = sc->unsolq[sc->unsolq_rp++];
 952                         sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
 953                         if ((child = sc->codecs[cad].dev) != NULL)
 954                                 HDAC_UNSOL_INTR(child, resp);
 955                         ret++;
 956                 }
 957                 sc->unsolq_st = HDAC_UNSOLQ_READY;
 958         }
 959
 960         return (ret);
 961 }
 962
 963 /****************************************************************************
 964  * uint32_t hdac_command_sendone_internal
 965  *
 966  * Wrapper function that sends only one command to a given codec
 967  ****************************************************************************/
 968 static uint32_t
 969 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb)
 970 {
 971         int timeout;
 972         uint32_t *corb;
 973
 974         if (!hdac_lockowned(sc))
 975                 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
 976         verb &= ~HDA_CMD_CAD_MASK;
 977         verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT;
 978         sc->codecs[cad].response = HDA_INVALID;
 979
 980         sc->codecs[cad].pending++;
 981         sc->corb_wp++;
 982         sc->corb_wp %= sc->corb_size;
 983         corb = (uint32_t *)sc->corb_dma.dma_vaddr;
 984         bus_dmamap_sync(sc->corb_dma.dma_tag,
 985             sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
 986         corb[sc->corb_wp] = htole32(verb);
 987         bus_dmamap_sync(sc->corb_dma.dma_tag,
 988             sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
 989         HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
 990
 991         timeout = 10000;
 992         do {
 993                 if (hdac_rirb_flush(sc) == 0)
 994                         DELAY(10);
 995         } while (sc->codecs[cad].pending != 0 && --timeout);
 996
 997         if (sc->codecs[cad].pending != 0) {
 998                 device_printf(sc->dev, "Command timeout on address %d\n", cad);
 999                 sc->codecs[cad].pending = 0;
1000         }
1001
1002         if (sc->unsolq_rp != sc->unsolq_wp)
1003                 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
1004         return (sc->codecs[cad].response);
1005 }
1006
1007 /****************************************************************************
1008  * Device Methods
1009  ****************************************************************************/
1010
1011 /****************************************************************************
1012  * int hdac_probe(device_t)
1013  *
1014  * Probe for the presence of an hdac. If none is found, check for a generic
1015  * match using the subclass of the device.
1016  ****************************************************************************/
1017 static int
1018 hdac_probe(device_t dev)
1019 {
1020         int i, result;
1021         uint32_t model;
1022         uint16_t class, subclass;
1023         char desc[64];
1024
1025         model = (uint32_t)pci_get_device(dev) << 16;
1026         model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1027         class = pci_get_class(dev);
1028         subclass = pci_get_subclass(dev);
1029
1030         bzero(desc, sizeof(desc));
1031         result = ENXIO;
1032         for (i = 0; i < nitems(hdac_devices); i++) {
1033                 if (hdac_devices[i].model == model) {
1034                         strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
1035                         result = BUS_PROBE_DEFAULT;
1036                         break;
1037                 }
1038                 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1039                     class == PCIC_MULTIMEDIA &&
1040                     subclass == PCIS_MULTIMEDIA_HDA) {
1041                         snprintf(desc, sizeof(desc),
1042                             "%s (0x%04x)",
1043                             hdac_devices[i].desc, pci_get_device(dev));
1044                         result = BUS_PROBE_GENERIC;
1045                         break;
1046                 }
1047         }
1048         if (result == ENXIO && class == PCIC_MULTIMEDIA &&
1049             subclass == PCIS_MULTIMEDIA_HDA) {
1050                 snprintf(desc, sizeof(desc), "Generic (0x%08x)", model);
1051                 result = BUS_PROBE_GENERIC;
1052         }
1053         if (result != ENXIO) {
1054                 strlcat(desc, " HDA Controller", sizeof(desc));
1055                 device_set_desc_copy(dev, desc);
1056         }
1057
1058         return (result);
1059 }
1060
1061 static void
1062 hdac_unsolq_task(void *context, int pending)
1063 {
1064         struct hdac_softc *sc;
1065
1066         sc = (struct hdac_softc *)context;
1067
1068         hdac_lock(sc);
1069         hdac_unsolq_flush(sc);
1070         hdac_unlock(sc);
1071 }
1072
1073 /****************************************************************************
1074  * int hdac_attach(device_t)
1075  *
1076  * Attach the device into the kernel. Interrupts usually won't be enabled
1077  * when this function is called. Setup everything that doesn't require
1078  * interrupts and defer probing of codecs until interrupts are enabled.
1079  ****************************************************************************/
1080 static int
1081 hdac_attach(device_t dev)
1082 {
1083         struct hdac_softc *sc;
1084         int result;
1085         int i, devid = -1;
1086         uint32_t model;
1087         uint16_t class, subclass;
1088         uint16_t vendor;
1089         uint8_t v;
1090
1091         sc = device_get_softc(dev);
1092         HDA_BOOTVERBOSE(
1093                 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n",
1094                     pci_get_subvendor(dev), pci_get_subdevice(dev));
1095                 device_printf(dev, "HDA Driver Revision: %s\n",
1096                     HDA_DRV_TEST_REV);
1097         );
1098
1099         model = (uint32_t)pci_get_device(dev) << 16;
1100         model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1101         class = pci_get_class(dev);
1102         subclass = pci_get_subclass(dev);
1103
1104         for (i = 0; i < nitems(hdac_devices); i++) {
1105                 if (hdac_devices[i].model == model) {
1106                         devid = i;
1107                         break;
1108                 }
1109                 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1110                     class == PCIC_MULTIMEDIA &&
1111                     subclass == PCIS_MULTIMEDIA_HDA) {
1112                         devid = i;
1113                         break;
1114                 }
1115         }
1116
1117         sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex");
1118         sc->dev = dev;
1119         TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
1120         callout_init(&sc->poll_callout, 1);
1121         for (i = 0; i < HDAC_CODEC_MAX; i++)
1122                 sc->codecs[i].dev = NULL;
1123         if (devid >= 0) {
1124                 sc->quirks_on = hdac_devices[devid].quirks_on;
1125                 sc->quirks_off = hdac_devices[devid].quirks_off;
1126         } else {
1127                 sc->quirks_on = 0;
1128                 sc->quirks_off = 0;
1129         }
1130         if (resource_int_value(device_get_name(dev),
1131             device_get_unit(dev), "msi", &i) == 0) {
1132                 if (i == 0)
1133                         sc->quirks_off |= HDAC_QUIRK_MSI;
1134                 else {
1135                         sc->quirks_on |= HDAC_QUIRK_MSI;
1136                         sc->quirks_off |= ~HDAC_QUIRK_MSI;
1137                 }
1138         }
1139         hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off);
1140         HDA_BOOTVERBOSE(
1141                 device_printf(sc->dev,
1142                     "Config options: on=0x%08x off=0x%08x\n",
1143                     sc->quirks_on, sc->quirks_off);
1144         );
1145         sc->poll_ival = hz;
1146         if (resource_int_value(device_get_name(dev),
1147             device_get_unit(dev), "polling", &i) == 0 && i != 0)
1148                 sc->polling = 1;
1149         else
1150                 sc->polling = 0;
1151
1152         pci_enable_busmaster(dev);
1153
1154         vendor = pci_get_vendor(dev);
1155         if (vendor == INTEL_VENDORID) {
1156                 /* TCSEL -> TC0 */
1157                 v = pci_read_config(dev, 0x44, 1);
1158                 pci_write_config(dev, 0x44, v & 0xf8, 1);
1159                 HDA_BOOTHVERBOSE(
1160                         device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
1161                             pci_read_config(dev, 0x44, 1));
1162                 );
1163         }
1164
1165 #if defined(__i386__) || defined(__amd64__)
1166         sc->flags |= HDAC_F_DMA_NOCACHE;
1167
1168         if (resource_int_value(device_get_name(dev),
1169             device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
1170 #else
1171         sc->flags &= ~HDAC_F_DMA_NOCACHE;
1172 #endif
1173                 /*
1174                  * Try to enable PCIe snoop to avoid messing around with
1175                  * uncacheable DMA attribute. Since PCIe snoop register
1176                  * config is pretty much vendor specific, there are no
1177                  * general solutions on how to enable it, forcing us (even
1178                  * Microsoft) to enable uncacheable or write combined DMA
1179                  * by default.
1180                  *
1181                  * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
1182                  */
1183                 for (i = 0; i < nitems(hdac_pcie_snoop); i++) {
1184                         if (hdac_pcie_snoop[i].vendor != vendor)
1185                                 continue;
1186                         sc->flags &= ~HDAC_F_DMA_NOCACHE;
1187                         if (hdac_pcie_snoop[i].reg == 0x00)
1188                                 break;
1189                         v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
1190                         if ((v & hdac_pcie_snoop[i].enable) ==
1191                             hdac_pcie_snoop[i].enable)
1192                                 break;
1193                         v &= hdac_pcie_snoop[i].mask;
1194                         v |= hdac_pcie_snoop[i].enable;
1195                         pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
1196                         v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
1197                         if ((v & hdac_pcie_snoop[i].enable) !=
1198                             hdac_pcie_snoop[i].enable) {
1199                                 HDA_BOOTVERBOSE(
1200                                         device_printf(dev,
1201                                             "WARNING: Failed to enable PCIe "
1202                                             "snoop!\n");
1203                                 );
1204 #if defined(__i386__) || defined(__amd64__)
1205                                 sc->flags |= HDAC_F_DMA_NOCACHE;
1206 #endif
1207                         }
1208                         break;
1209                 }
1210 #if defined(__i386__) || defined(__amd64__)
1211         }
1212 #endif
1213
1214         HDA_BOOTHVERBOSE(
1215                 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
1216                     (sc->flags & HDAC_F_DMA_NOCACHE) ?
1217                     "Uncacheable" : "PCIe snoop", vendor);
1218         );
1219
1220         /* Allocate resources */
1221         result = hdac_mem_alloc(sc);
1222         if (result != 0)
1223                 goto hdac_attach_fail;
1224         result = hdac_irq_alloc(sc);
1225         if (result != 0)
1226                 goto hdac_attach_fail;
1227
1228         /* Get Capabilities */
1229         result = hdac_get_capabilities(sc);
1230         if (result != 0)
1231                 goto hdac_attach_fail;
1232
1233         /* Allocate CORB, RIRB, POS and BDLs dma memory */
1234         result = hdac_dma_alloc(sc, &sc->corb_dma,
1235             sc->corb_size * sizeof(uint32_t));
1236         if (result != 0)
1237                 goto hdac_attach_fail;
1238         result = hdac_dma_alloc(sc, &sc->rirb_dma,
1239             sc->rirb_size * sizeof(struct hdac_rirb));
1240         if (result != 0)
1241                 goto hdac_attach_fail;
1242         sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss,
1243             M_HDAC, M_ZERO | M_WAITOK);
1244         for (i = 0; i < sc->num_ss; i++) {
1245                 result = hdac_dma_alloc(sc, &sc->streams[i].bdl,
1246                     sizeof(struct hdac_bdle) * HDA_BDL_MAX);
1247                 if (result != 0)
1248                         goto hdac_attach_fail;
1249         }
1250         if (sc->quirks_on & HDAC_QUIRK_DMAPOS) {
1251                 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) {
1252                         HDA_BOOTVERBOSE(
1253                                 device_printf(dev, "Failed to "
1254                                     "allocate DMA pos buffer "
1255                                     "(non-fatal)\n");
1256                         );
1257                 } else {
1258                         uint64_t addr = sc->pos_dma.dma_paddr;
1259
1260                         HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32);
1261                         HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
1262                             (addr & HDAC_DPLBASE_DPLBASE_MASK) |
1263                             HDAC_DPLBASE_DPLBASE_DMAPBE);
1264                 }
1265         }
1266
1267         result = bus_dma_tag_create(
1268             bus_get_dma_tag(sc->dev),           /* parent */
1269             HDA_DMA_ALIGNMENT,                  /* alignment */
1270             0,                                  /* boundary */
1271             (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1272                 BUS_SPACE_MAXADDR_32BIT,        /* lowaddr */
1273             BUS_SPACE_MAXADDR,                  /* highaddr */
1274             NULL,                               /* filtfunc */
1275             NULL,                               /* fistfuncarg */
1276             HDA_BUFSZ_MAX,                      /* maxsize */
1277             1,                                  /* nsegments */
1278             HDA_BUFSZ_MAX,                      /* maxsegsz */
1279             0,                                  /* flags */
1280             NULL,                               /* lockfunc */
1281             NULL,                               /* lockfuncarg */
1282             &sc->chan_dmat);                    /* dmat */
1283         if (result != 0) {
1284                 device_printf(dev, "%s: bus_dma_tag_create failed (%d)\n",
1285                      __func__, result);
1286                 goto hdac_attach_fail;
1287         }
1288
1289         /* Quiesce everything */
1290         HDA_BOOTHVERBOSE(
1291                 device_printf(dev, "Reset controller...\n");
1292         );
1293         hdac_reset(sc, 1);
1294
1295         /* Initialize the CORB and RIRB */
1296         hdac_corb_init(sc);
1297         hdac_rirb_init(sc);
1298
1299         /* Defer remaining of initialization until interrupts are enabled */
1300         sc->intrhook.ich_func = hdac_attach2;
1301         sc->intrhook.ich_arg = (void *)sc;
1302         if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
1303                 sc->intrhook.ich_func = NULL;
1304                 hdac_attach2((void *)sc);
1305         }
1306
1307         return (0);
1308
1309 hdac_attach_fail:
1310         hdac_irq_free(sc);
1311         if (sc->streams != NULL)
1312                 for (i = 0; i < sc->num_ss; i++)
1313                         hdac_dma_free(sc, &sc->streams[i].bdl);
1314         free(sc->streams, M_HDAC);
1315         hdac_dma_free(sc, &sc->rirb_dma);
1316         hdac_dma_free(sc, &sc->corb_dma);
1317         hdac_mem_free(sc);
1318         snd_mtxfree(sc->lock);
1319
1320         return (ENXIO);
1321 }
1322
1323 static int
1324 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
1325 {
1326         struct hdac_softc *sc;
1327         device_t *devlist;
1328         device_t dev;
1329         int devcount, i, err, val;
1330
1331         dev = oidp->oid_arg1;
1332         sc = device_get_softc(dev);
1333         if (sc == NULL)
1334                 return (EINVAL);
1335         val = 0;
1336         err = sysctl_handle_int(oidp, &val, 0, req);
1337         if (err != 0 || req->newptr == NULL || val == 0)
1338                 return (err);
1339
1340         /* XXX: Temporary. For debugging. */
1341         if (val == 100) {
1342                 hdac_suspend(dev);
1343                 return (0);
1344         } else if (val == 101) {
1345                 hdac_resume(dev);
1346                 return (0);
1347         }
1348
1349         if ((err = device_get_children(dev, &devlist, &devcount)) != 0)
1350                 return (err);
1351         hdac_lock(sc);
1352         for (i = 0; i < devcount; i++)
1353                 HDAC_PINDUMP(devlist[i]);
1354         hdac_unlock(sc);
1355         free(devlist, M_TEMP);
1356         return (0);
1357 }
1358
1359 static int
1360 hdac_mdata_rate(uint16_t fmt)
1361 {
1362         static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 };
1363         int rate, bits;
1364
1365         if (fmt & (1 << 14))
1366                 rate = 44100;
1367         else
1368                 rate = 48000;
1369         rate *= ((fmt >> 11) & 0x07) + 1;
1370         rate /= ((fmt >> 8) & 0x07) + 1;
1371         bits = mbits[(fmt >> 4) & 0x03];
1372         bits *= (fmt & 0x0f) + 1;
1373         return (rate * bits);
1374 }
1375
1376 static int
1377 hdac_bdata_rate(uint16_t fmt, int output)
1378 {
1379         static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 };
1380         int rate, bits;
1381
1382         rate = 48000;
1383         rate *= ((fmt >> 11) & 0x07) + 1;
1384         bits = bbits[(fmt >> 4) & 0x03];
1385         bits *= (fmt & 0x0f) + 1;
1386         if (!output)
1387                 bits = ((bits + 7) & ~0x07) + 10;
1388         return (rate * bits);
1389 }
1390
1391 static void
1392 hdac_poll_reinit(struct hdac_softc *sc)
1393 {
1394         int i, pollticks, min = 1000000;
1395         struct hdac_stream *s;
1396
1397         if (sc->polling == 0)
1398                 return;
1399         if (sc->unsol_registered > 0)
1400                 min = hz / 2;
1401         for (i = 0; i < sc->num_ss; i++) {
1402                 s = &sc->streams[i];
1403                 if (s->running == 0)
1404                         continue;
1405                 pollticks = ((uint64_t)hz * s->blksz) /
1406                     (hdac_mdata_rate(s->format) / 8);
1407                 pollticks >>= 1;
1408                 if (pollticks > hz)
1409                         pollticks = hz;
1410                 if (pollticks < 1) {
1411                         HDA_BOOTVERBOSE(
1412                                 device_printf(sc->dev,
1413                                     "poll interval < 1 tick !\n");
1414                         );
1415                         pollticks = 1;
1416                 }
1417                 if (min > pollticks)
1418                         min = pollticks;
1419         }
1420         HDA_BOOTVERBOSE(
1421                 device_printf(sc->dev,
1422                     "poll interval %d -> %d ticks\n",
1423                     sc->poll_ival, min);
1424         );
1425         sc->poll_ival = min;
1426         if (min == 1000000)
1427                 callout_stop(&sc->poll_callout);
1428         else
1429                 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc);
1430 }
1431
1432 static int
1433 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
1434 {
1435         struct hdac_softc *sc;
1436         device_t dev;
1437         uint32_t ctl;
1438         int err, val;
1439
1440         dev = oidp->oid_arg1;
1441         sc = device_get_softc(dev);
1442         if (sc == NULL)
1443                 return (EINVAL);
1444         hdac_lock(sc);
1445         val = sc->polling;
1446         hdac_unlock(sc);
1447         err = sysctl_handle_int(oidp, &val, 0, req);
1448
1449         if (err != 0 || req->newptr == NULL)
1450                 return (err);
1451         if (val < 0 || val > 1)
1452                 return (EINVAL);
1453
1454         hdac_lock(sc);
1455         if (val != sc->polling) {
1456                 if (val == 0) {
1457                         callout_stop(&sc->poll_callout);
1458                         hdac_unlock(sc);
1459                         callout_drain(&sc->poll_callout);
1460                         hdac_lock(sc);
1461                         sc->polling = 0;
1462                         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1463                         ctl |= HDAC_INTCTL_GIE;
1464                         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1465                 } else {
1466                         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1467                         ctl &= ~HDAC_INTCTL_GIE;
1468                         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1469                         sc->polling = 1;
1470                         hdac_poll_reinit(sc);
1471                 }
1472         }
1473         hdac_unlock(sc);
1474
1475         return (err);
1476 }
1477
1478 static void
1479 hdac_attach2(void *arg)
1480 {
1481         struct hdac_softc *sc;
1482         device_t child;
1483         uint32_t vendorid, revisionid;
1484         int i;
1485         uint16_t statests;
1486
1487         sc = (struct hdac_softc *)arg;
1488
1489         hdac_lock(sc);
1490
1491         /* Remove ourselves from the config hooks */
1492         if (sc->intrhook.ich_func != NULL) {
1493                 config_intrhook_disestablish(&sc->intrhook);
1494                 sc->intrhook.ich_func = NULL;
1495         }
1496
1497         HDA_BOOTHVERBOSE(
1498                 device_printf(sc->dev, "Starting CORB Engine...\n");
1499         );
1500         hdac_corb_start(sc);
1501         HDA_BOOTHVERBOSE(
1502                 device_printf(sc->dev, "Starting RIRB Engine...\n");
1503         );
1504         hdac_rirb_start(sc);
1505         HDA_BOOTHVERBOSE(
1506                 device_printf(sc->dev,
1507                     "Enabling controller interrupt...\n");
1508         );
1509         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1510             HDAC_GCTL_UNSOL);
1511         if (sc->polling == 0) {
1512                 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
1513                     HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1514         }
1515         DELAY(1000);
1516
1517         HDA_BOOTHVERBOSE(
1518                 device_printf(sc->dev, "Scanning HDA codecs ...\n");
1519         );
1520         statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1521         hdac_unlock(sc);
1522         for (i = 0; i < HDAC_CODEC_MAX; i++) {
1523                 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1524                         HDA_BOOTHVERBOSE(
1525                                 device_printf(sc->dev,
1526                                     "Found CODEC at address %d\n", i);
1527                         );
1528                         hdac_lock(sc);
1529                         vendorid = hdac_send_command(sc, i,
1530                             HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID));
1531                         revisionid = hdac_send_command(sc, i,
1532                             HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID));
1533                         hdac_unlock(sc);
1534                         if (vendorid == HDA_INVALID &&
1535                             revisionid == HDA_INVALID) {
1536                                 device_printf(sc->dev,
1537                                     "CODEC is not responding!\n");
1538                                 continue;
1539                         }
1540                         sc->codecs[i].vendor_id =
1541                             HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1542                         sc->codecs[i].device_id =
1543                             HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1544                         sc->codecs[i].revision_id =
1545                             HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1546                         sc->codecs[i].stepping_id =
1547                             HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1548                         child = device_add_child(sc->dev, "hdacc", -1);
1549                         if (child == NULL) {
1550                                 device_printf(sc->dev,
1551                                     "Failed to add CODEC device\n");
1552                                 continue;
1553                         }
1554                         device_set_ivars(child, (void *)(intptr_t)i);
1555                         sc->codecs[i].dev = child;
1556                 }
1557         }
1558         bus_generic_attach(sc->dev);
1559
1560         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1561             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1562             "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1563             sysctl_hdac_pindump, "I", "Dump pin states/data");
1564         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1565             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1566             "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1567             sysctl_hdac_polling, "I", "Enable polling mode");
1568 }
1569
1570 /****************************************************************************
1571  * int hdac_suspend(device_t)
1572  *
1573  * Suspend and power down HDA bus and codecs.
1574  ****************************************************************************/
1575 static int
1576 hdac_suspend(device_t dev)
1577 {
1578         struct hdac_softc *sc = device_get_softc(dev);
1579
1580         HDA_BOOTHVERBOSE(
1581                 device_printf(dev, "Suspend...\n");
1582         );
1583         bus_generic_suspend(dev);
1584
1585         hdac_lock(sc);
1586         HDA_BOOTHVERBOSE(
1587                 device_printf(dev, "Reset controller...\n");
1588         );
1589         callout_stop(&sc->poll_callout);
1590         hdac_reset(sc, 0);
1591         hdac_unlock(sc);
1592         callout_drain(&sc->poll_callout);
1593         taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1594         HDA_BOOTHVERBOSE(
1595                 device_printf(dev, "Suspend done\n");
1596         );
1597         return (0);
1598 }
1599
1600 /****************************************************************************
1601  * int hdac_resume(device_t)
1602  *
1603  * Powerup and restore HDA bus and codecs state.
1604  ****************************************************************************/
1605 static int
1606 hdac_resume(device_t dev)
1607 {
1608         struct hdac_softc *sc = device_get_softc(dev);
1609         int error;
1610
1611         HDA_BOOTHVERBOSE(
1612                 device_printf(dev, "Resume...\n");
1613         );
1614         hdac_lock(sc);
1615
1616         /* Quiesce everything */
1617         HDA_BOOTHVERBOSE(
1618                 device_printf(dev, "Reset controller...\n");
1619         );
1620         hdac_reset(sc, 1);
1621
1622         /* Initialize the CORB and RIRB */
1623         hdac_corb_init(sc);
1624         hdac_rirb_init(sc);
1625
1626         HDA_BOOTHVERBOSE(
1627                 device_printf(dev, "Starting CORB Engine...\n");
1628         );
1629         hdac_corb_start(sc);
1630         HDA_BOOTHVERBOSE(
1631                 device_printf(dev, "Starting RIRB Engine...\n");
1632         );
1633         hdac_rirb_start(sc);
1634         HDA_BOOTHVERBOSE(
1635                 device_printf(dev, "Enabling controller interrupt...\n");
1636         );
1637         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1638             HDAC_GCTL_UNSOL);
1639         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1640         DELAY(1000);
1641         hdac_poll_reinit(sc);
1642         hdac_unlock(sc);
1643
1644         error = bus_generic_resume(dev);
1645         HDA_BOOTHVERBOSE(
1646                 device_printf(dev, "Resume done\n");
1647         );
1648         return (error);
1649 }
1650
1651 /****************************************************************************
1652  * int hdac_detach(device_t)
1653  *
1654  * Detach and free up resources utilized by the hdac device.
1655  ****************************************************************************/
1656 static int
1657 hdac_detach(device_t dev)
1658 {
1659         struct hdac_softc *sc = device_get_softc(dev);
1660         device_t *devlist;
1661         int cad, i, devcount, error;
1662
1663         if ((error = device_get_children(dev, &devlist, &devcount)) != 0)
1664                 return (error);
1665         for (i = 0; i < devcount; i++) {
1666                 cad = (intptr_t)device_get_ivars(devlist[i]);
1667                 if ((error = device_delete_child(dev, devlist[i])) != 0) {
1668                         free(devlist, M_TEMP);
1669                         return (error);
1670                 }
1671                 sc->codecs[cad].dev = NULL;
1672         }
1673         free(devlist, M_TEMP);
1674
1675         hdac_lock(sc);
1676         hdac_reset(sc, 0);
1677         hdac_unlock(sc);
1678         taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1679         hdac_irq_free(sc);
1680
1681         for (i = 0; i < sc->num_ss; i++)
1682                 hdac_dma_free(sc, &sc->streams[i].bdl);
1683         free(sc->streams, M_HDAC);
1684         hdac_dma_free(sc, &sc->pos_dma);
1685         hdac_dma_free(sc, &sc->rirb_dma);
1686         hdac_dma_free(sc, &sc->corb_dma);
1687         if (sc->chan_dmat != NULL) {
1688                 bus_dma_tag_destroy(sc->chan_dmat);
1689                 sc->chan_dmat = NULL;
1690         }
1691         hdac_mem_free(sc);
1692         snd_mtxfree(sc->lock);
1693         return (0);
1694 }
1695
1696 static bus_dma_tag_t
1697 hdac_get_dma_tag(device_t dev, device_t child)
1698 {
1699         struct hdac_softc *sc = device_get_softc(dev);
1700
1701         return (sc->chan_dmat);
1702 }
1703
1704 static int
1705 hdac_print_child(device_t dev, device_t child)
1706 {
1707         int retval;
1708
1709         retval = bus_print_child_header(dev, child);
1710         retval += printf(" at cad %d",
1711             (int)(intptr_t)device_get_ivars(child));
1712         retval += bus_print_child_footer(dev, child);
1713
1714         return (retval);
1715 }
1716
1717 static int
1718 hdac_child_location_str(device_t dev, device_t child, char *buf,
1719     size_t buflen)
1720 {
1721
1722         snprintf(buf, buflen, "cad=%d",
1723             (int)(intptr_t)device_get_ivars(child));
1724         return (0);
1725 }
1726
1727 static int
1728 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
1729     size_t buflen)
1730 {
1731         struct hdac_softc *sc = device_get_softc(dev);
1732         nid_t cad = (uintptr_t)device_get_ivars(child);
1733
1734         snprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x "
1735             "stepping=0x%02x",
1736             sc->codecs[cad].vendor_id, sc->codecs[cad].device_id,
1737             sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id);
1738         return (0);
1739 }
1740
1741 static int
1742 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1743 {
1744         struct hdac_softc *sc = device_get_softc(dev);
1745         nid_t cad = (uintptr_t)device_get_ivars(child);
1746
1747         switch (which) {
1748         case HDA_IVAR_CODEC_ID:
1749                 *result = cad;
1750                 break;
1751         case HDA_IVAR_VENDOR_ID:
1752                 *result = sc->codecs[cad].vendor_id;
1753                 break;
1754         case HDA_IVAR_DEVICE_ID:
1755                 *result = sc->codecs[cad].device_id;
1756                 break;
1757         case HDA_IVAR_REVISION_ID:
1758                 *result = sc->codecs[cad].revision_id;
1759                 break;
1760         case HDA_IVAR_STEPPING_ID:
1761                 *result = sc->codecs[cad].stepping_id;
1762                 break;
1763         case HDA_IVAR_SUBVENDOR_ID:
1764                 *result = pci_get_subvendor(dev);
1765                 break;
1766         case HDA_IVAR_SUBDEVICE_ID:
1767                 *result = pci_get_subdevice(dev);
1768                 break;
1769         case HDA_IVAR_DMA_NOCACHE:
1770                 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0;
1771                 break;
1772         case HDA_IVAR_STRIPES_MASK:
1773                 *result = (1 << (1 << sc->num_sdo)) - 1;
1774                 break;
1775         default:
1776                 return (ENOENT);
1777         }
1778         return (0);
1779 }
1780
1781 static struct mtx *
1782 hdac_get_mtx(device_t dev, device_t child)
1783 {
1784         struct hdac_softc *sc = device_get_softc(dev);
1785
1786         return (sc->lock);
1787 }
1788
1789 static uint32_t
1790 hdac_codec_command(device_t dev, device_t child, uint32_t verb)
1791 {
1792
1793         return (hdac_send_command(device_get_softc(dev),
1794             (intptr_t)device_get_ivars(child), verb));
1795 }
1796
1797 static int
1798 hdac_find_stream(struct hdac_softc *sc, int dir, int stream)
1799 {
1800         int i, ss;
1801
1802         ss = -1;
1803         /* Allocate ISS/OSS first. */
1804         if (dir == 0) {
1805                 for (i = 0; i < sc->num_iss; i++) {
1806                         if (sc->streams[i].stream == stream) {
1807                                 ss = i;
1808                                 break;
1809                         }
1810                 }
1811         } else {
1812                 for (i = 0; i < sc->num_oss; i++) {
1813                         if (sc->streams[i + sc->num_iss].stream == stream) {
1814                                 ss = i + sc->num_iss;
1815                                 break;
1816                         }
1817                 }
1818         }
1819         /* Fallback to BSS. */
1820         if (ss == -1) {
1821                 for (i = 0; i < sc->num_bss; i++) {
1822                         if (sc->streams[i + sc->num_iss + sc->num_oss].stream
1823                             == stream) {
1824                                 ss = i + sc->num_iss + sc->num_oss;
1825                                 break;
1826                         }
1827                 }
1828         }
1829         return (ss);
1830 }
1831
1832 static int
1833 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe,
1834     uint32_t **dmapos)
1835 {
1836         struct hdac_softc *sc = device_get_softc(dev);
1837         nid_t cad = (uintptr_t)device_get_ivars(child);
1838         int stream, ss, bw, maxbw, prevbw;
1839
1840         /* Look for empty stream. */
1841         ss = hdac_find_stream(sc, dir, 0);
1842
1843         /* Return if found nothing. */
1844         if (ss < 0)
1845                 return (0);
1846
1847         /* Check bus bandwidth. */
1848         bw = hdac_bdata_rate(format, dir);
1849         if (dir == 1) {
1850                 bw *= 1 << (sc->num_sdo - stripe);
1851                 prevbw = sc->sdo_bw_used;
1852                 maxbw = 48000 * 960 * (1 << sc->num_sdo);
1853         } else {
1854                 prevbw = sc->codecs[cad].sdi_bw_used;
1855                 maxbw = 48000 * 464;
1856         }
1857         HDA_BOOTHVERBOSE(
1858                 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n",
1859                     (bw + prevbw) / 1000, maxbw / 1000,
1860                     bw + prevbw > maxbw ? " -- OVERFLOW!" : "");
1861         );
1862         if (bw + prevbw > maxbw)
1863                 return (0);
1864         if (dir == 1)
1865                 sc->sdo_bw_used += bw;
1866         else
1867                 sc->codecs[cad].sdi_bw_used += bw;
1868
1869         /* Allocate stream number */
1870         if (ss >= sc->num_iss + sc->num_oss)
1871                 stream = 15 - (ss - sc->num_iss - sc->num_oss);
1872         else if (ss >= sc->num_iss)
1873                 stream = ss - sc->num_iss + 1;
1874         else
1875                 stream = ss + 1;
1876
1877         sc->streams[ss].dev = child;
1878         sc->streams[ss].dir = dir;
1879         sc->streams[ss].stream = stream;
1880         sc->streams[ss].bw = bw;
1881         sc->streams[ss].format = format;
1882         sc->streams[ss].stripe = stripe;
1883         if (dmapos != NULL) {
1884                 if (sc->pos_dma.dma_vaddr != NULL)
1885                         *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8);
1886                 else
1887                         *dmapos = NULL;
1888         }
1889         return (stream);
1890 }
1891
1892 static void
1893 hdac_stream_free(device_t dev, device_t child, int dir, int stream)
1894 {
1895         struct hdac_softc *sc = device_get_softc(dev);
1896         nid_t cad = (uintptr_t)device_get_ivars(child);
1897         int ss;
1898
1899         ss = hdac_find_stream(sc, dir, stream);
1900         KASSERT(ss >= 0,
1901             ("Free for not allocated stream (%d/%d)\n", dir, stream));
1902         if (dir == 1)
1903                 sc->sdo_bw_used -= sc->streams[ss].bw;
1904         else
1905                 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw;
1906         sc->streams[ss].stream = 0;
1907         sc->streams[ss].dev = NULL;
1908 }
1909
1910 static int
1911 hdac_stream_start(device_t dev, device_t child,
1912     int dir, int stream, bus_addr_t buf, int blksz, int blkcnt)
1913 {
1914         struct hdac_softc *sc = device_get_softc(dev);
1915         struct hdac_bdle *bdle;
1916         uint64_t addr;
1917         int i, ss, off;
1918         uint32_t ctl;
1919
1920         ss = hdac_find_stream(sc, dir, stream);
1921         KASSERT(ss >= 0,
1922             ("Start for not allocated stream (%d/%d)\n", dir, stream));
1923
1924         addr = (uint64_t)buf;
1925         bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr;
1926         for (i = 0; i < blkcnt; i++, bdle++) {
1927                 bdle->addrl = htole32((uint32_t)addr);
1928                 bdle->addrh = htole32((uint32_t)(addr >> 32));
1929                 bdle->len = htole32(blksz);
1930                 bdle->ioc = htole32(1);
1931                 addr += blksz;
1932         }
1933
1934         bus_dmamap_sync(sc->streams[ss].bdl.dma_tag,
1935             sc->streams[ss].bdl.dma_map, BUS_DMASYNC_PREWRITE);
1936
1937         off = ss << 5;
1938         HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt);
1939         HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1);
1940         addr = sc->streams[ss].bdl.dma_paddr;
1941         HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr);
1942         HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
1943
1944         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2);
1945         if (dir)
1946                 ctl |= HDAC_SDCTL2_DIR;
1947         else
1948                 ctl &= ~HDAC_SDCTL2_DIR;
1949         ctl &= ~HDAC_SDCTL2_STRM_MASK;
1950         ctl |= stream << HDAC_SDCTL2_STRM_SHIFT;
1951         ctl &= ~HDAC_SDCTL2_STRIPE_MASK;
1952         ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT;
1953         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl);
1954
1955         HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format);
1956
1957         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1958         ctl |= 1 << ss;
1959         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1960
1961         HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS,
1962             HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS);
1963         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1964         ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1965             HDAC_SDCTL_RUN;
1966         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1967
1968         sc->streams[ss].blksz = blksz;
1969         sc->streams[ss].running = 1;
1970         hdac_poll_reinit(sc);
1971         return (0);
1972 }
1973
1974 static void
1975 hdac_stream_stop(device_t dev, device_t child, int dir, int stream)
1976 {
1977         struct hdac_softc *sc = device_get_softc(dev);
1978         int ss, off;
1979         uint32_t ctl;
1980
1981         ss = hdac_find_stream(sc, dir, stream);
1982         KASSERT(ss >= 0,
1983             ("Stop for not allocated stream (%d/%d)\n", dir, stream));
1984
1985         bus_dmamap_sync(sc->streams[ss].bdl.dma_tag,
1986             sc->streams[ss].bdl.dma_map, BUS_DMASYNC_POSTWRITE);
1987
1988         off = ss << 5;
1989         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1990         ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1991             HDAC_SDCTL_RUN);
1992         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1993
1994         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1995         ctl &= ~(1 << ss);
1996         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1997
1998         sc->streams[ss].running = 0;
1999         hdac_poll_reinit(sc);
2000 }
2001
2002 static void
2003 hdac_stream_reset(device_t dev, device_t child, int dir, int stream)
2004 {
2005         struct hdac_softc *sc = device_get_softc(dev);
2006         int timeout = 1000;
2007         int to = timeout;
2008         int ss, off;
2009         uint32_t ctl;
2010
2011         ss = hdac_find_stream(sc, dir, stream);
2012         KASSERT(ss >= 0,
2013             ("Reset for not allocated stream (%d/%d)\n", dir, stream));
2014
2015         off = ss << 5;
2016         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2017         ctl |= HDAC_SDCTL_SRST;
2018         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2019         do {
2020                 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2021                 if (ctl & HDAC_SDCTL_SRST)
2022                         break;
2023                 DELAY(10);
2024         } while (--to);
2025         if (!(ctl & HDAC_SDCTL_SRST))
2026                 device_printf(dev, "Reset setting timeout\n");
2027         ctl &= ~HDAC_SDCTL_SRST;
2028         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2029         to = timeout;
2030         do {
2031                 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2032                 if (!(ctl & HDAC_SDCTL_SRST))
2033                         break;
2034                 DELAY(10);
2035         } while (--to);
2036         if (ctl & HDAC_SDCTL_SRST)
2037                 device_printf(dev, "Reset timeout!\n");
2038 }
2039
2040 static uint32_t
2041 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream)
2042 {
2043         struct hdac_softc *sc = device_get_softc(dev);
2044         int ss, off;
2045
2046         ss = hdac_find_stream(sc, dir, stream);
2047         KASSERT(ss >= 0,
2048             ("Reset for not allocated stream (%d/%d)\n", dir, stream));
2049
2050         off = ss << 5;
2051         return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB));
2052 }
2053
2054 static int
2055 hdac_unsol_alloc(device_t dev, device_t child, int tag)
2056 {
2057         struct hdac_softc *sc = device_get_softc(dev);
2058
2059         sc->unsol_registered++;
2060         hdac_poll_reinit(sc);
2061         return (tag);
2062 }
2063
2064 static void
2065 hdac_unsol_free(device_t dev, device_t child, int tag)
2066 {
2067         struct hdac_softc *sc = device_get_softc(dev);
2068
2069         sc->unsol_registered--;
2070         hdac_poll_reinit(sc);
2071 }
2072
2073 static device_method_t hdac_methods[] = {
2074         /* device interface */
2075         DEVMETHOD(device_probe,         hdac_probe),
2076         DEVMETHOD(device_attach,        hdac_attach),
2077         DEVMETHOD(device_detach,        hdac_detach),
2078         DEVMETHOD(device_suspend,       hdac_suspend),
2079         DEVMETHOD(device_resume,        hdac_resume),
2080         /* Bus interface */
2081         DEVMETHOD(bus_get_dma_tag,      hdac_get_dma_tag),
2082         DEVMETHOD(bus_print_child,      hdac_print_child),
2083         DEVMETHOD(bus_child_location_str, hdac_child_location_str),
2084         DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method),
2085         DEVMETHOD(bus_read_ivar,        hdac_read_ivar),
2086         DEVMETHOD(hdac_get_mtx,         hdac_get_mtx),
2087         DEVMETHOD(hdac_codec_command,   hdac_codec_command),
2088         DEVMETHOD(hdac_stream_alloc,    hdac_stream_alloc),
2089         DEVMETHOD(hdac_stream_free,     hdac_stream_free),
2090         DEVMETHOD(hdac_stream_start,    hdac_stream_start),
2091         DEVMETHOD(hdac_stream_stop,     hdac_stream_stop),
2092         DEVMETHOD(hdac_stream_reset,    hdac_stream_reset),
2093         DEVMETHOD(hdac_stream_getptr,   hdac_stream_getptr),
2094         DEVMETHOD(hdac_unsol_alloc,     hdac_unsol_alloc),
2095         DEVMETHOD(hdac_unsol_free,      hdac_unsol_free),
2096         DEVMETHOD_END
2097 };
2098
2099 static driver_t hdac_driver = {
2100         "hdac",
2101         hdac_methods,
2102         sizeof(struct hdac_softc),
2103 };
2104
2105 static devclass_t hdac_devclass;
2106
2107 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL);