2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
5 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
6 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Intel High Definition Audio (Controller) driver for FreeBSD.
35 #ifdef HAVE_KERNEL_OPTION_HEADERS
39 #include <dev/sound/pcm/sound.h>
40 #include <dev/pci/pcireg.h>
41 #include <dev/pci/pcivar.h>
43 #include <sys/ctype.h>
44 #include <sys/endian.h>
45 #include <sys/taskqueue.h>
47 #include <dev/sound/pci/hda/hdac_private.h>
48 #include <dev/sound/pci/hda/hdac_reg.h>
49 #include <dev/sound/pci/hda/hda_reg.h>
50 #include <dev/sound/pci/hda/hdac.h>
52 #define HDA_DRV_TEST_REV "20120126_0002"
54 SND_DECLARE_FILE("$FreeBSD$");
56 #define hdac_lock(sc) snd_mtxlock((sc)->lock)
57 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
58 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
59 #define hdac_lockowned(sc) mtx_owned((sc)->lock)
61 #define HDAC_QUIRK_64BIT (1 << 0)
62 #define HDAC_QUIRK_DMAPOS (1 << 1)
63 #define HDAC_QUIRK_MSI (1 << 2)
68 } hdac_quirks_tab[] = {
69 { "64bit", HDAC_QUIRK_DMAPOS },
70 { "dmapos", HDAC_QUIRK_DMAPOS },
71 { "msi", HDAC_QUIRK_MSI },
74 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller");
82 { HDA_INTEL_OAK, "Intel Oaktrail", 0, 0 },
83 { HDA_INTEL_BAY, "Intel BayTrail", 0, 0 },
84 { HDA_INTEL_HSW1, "Intel Haswell", 0, 0 },
85 { HDA_INTEL_HSW2, "Intel Haswell", 0, 0 },
86 { HDA_INTEL_HSW3, "Intel Haswell", 0, 0 },
87 { HDA_INTEL_BDW1, "Intel Broadwell", 0, 0 },
88 { HDA_INTEL_BDW2, "Intel Broadwell", 0, 0 },
89 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 },
90 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 },
91 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 },
92 { HDA_INTEL_LPT1, "Intel Lynx Point", 0, 0 },
93 { HDA_INTEL_LPT2, "Intel Lynx Point", 0, 0 },
94 { HDA_INTEL_WCPT, "Intel Wildcat Point", 0, 0 },
95 { HDA_INTEL_WELLS1, "Intel Wellsburg", 0, 0 },
96 { HDA_INTEL_WELLS2, "Intel Wellsburg", 0, 0 },
97 { HDA_INTEL_LPTLP1, "Intel Lynx Point-LP", 0, 0 },
98 { HDA_INTEL_LPTLP2, "Intel Lynx Point-LP", 0, 0 },
99 { HDA_INTEL_SRPTLP, "Intel Sunrise Point-LP", 0, 0 },
100 { HDA_INTEL_KBLKLP, "Intel Kaby Lake-LP", 0, 0 },
101 { HDA_INTEL_SRPT, "Intel Sunrise Point", 0, 0 },
102 { HDA_INTEL_KBLK, "Intel Kaby Lake", 0, 0 },
103 { HDA_INTEL_KBLKH, "Intel Kaby Lake-H", 0, 0 },
104 { HDA_INTEL_CFLK, "Intel Coffee Lake", 0, 0 },
105 { HDA_INTEL_CNLK, "Intel Cannon Lake", 0, 0 },
106 { HDA_INTEL_ICLK, "Intel Ice Lake", 0, 0 },
107 { HDA_INTEL_CMLKLP, "Intel Comet Lake-LP", 0, 0 },
108 { HDA_INTEL_CMLKH, "Intel Comet Lake-H", 0, 0 },
109 { HDA_INTEL_TGLK, "Intel Tiger Lake", 0, 0 },
110 { HDA_INTEL_GMLK, "Intel Gemini Lake", 0, 0 },
111 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 },
112 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 },
113 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 },
114 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 },
115 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 },
116 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 },
117 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 },
118 { HDA_INTEL_PCH, "Intel Ibex Peak", 0, 0 },
119 { HDA_INTEL_PCH2, "Intel Ibex Peak", 0, 0 },
120 { HDA_INTEL_SCH, "Intel SCH", 0, 0 },
121 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI },
122 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI },
123 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 },
124 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 },
125 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 },
126 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 },
127 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 },
128 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 },
129 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 },
130 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 },
131 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT },
132 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT },
133 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT },
134 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT },
135 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 },
136 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 },
137 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 },
138 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 },
139 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 },
140 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 },
141 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 },
142 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 },
143 { HDA_NVIDIA_0BE2, "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI },
144 { HDA_NVIDIA_0BE3, "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI },
145 { HDA_NVIDIA_0BE4, "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI },
146 { HDA_NVIDIA_GT100, "NVIDIA GT100", 0, HDAC_QUIRK_MSI },
147 { HDA_NVIDIA_GT104, "NVIDIA GT104", 0, HDAC_QUIRK_MSI },
148 { HDA_NVIDIA_GT106, "NVIDIA GT106", 0, HDAC_QUIRK_MSI },
149 { HDA_NVIDIA_GT108, "NVIDIA GT108", 0, HDAC_QUIRK_MSI },
150 { HDA_NVIDIA_GT116, "NVIDIA GT116", 0, HDAC_QUIRK_MSI },
151 { HDA_NVIDIA_GF119, "NVIDIA GF119", 0, 0 },
152 { HDA_NVIDIA_GF110_1, "NVIDIA GF110", 0, HDAC_QUIRK_MSI },
153 { HDA_NVIDIA_GF110_2, "NVIDIA GF110", 0, HDAC_QUIRK_MSI },
154 { HDA_ATI_SB450, "ATI SB450", 0, 0 },
155 { HDA_ATI_SB600, "ATI SB600", 0, 0 },
156 { HDA_ATI_RS600, "ATI RS600", 0, 0 },
157 { HDA_ATI_RS690, "ATI RS690", 0, 0 },
158 { HDA_ATI_RS780, "ATI RS780", 0, 0 },
159 { HDA_ATI_R600, "ATI R600", 0, 0 },
160 { HDA_ATI_RV610, "ATI RV610", 0, 0 },
161 { HDA_ATI_RV620, "ATI RV620", 0, 0 },
162 { HDA_ATI_RV630, "ATI RV630", 0, 0 },
163 { HDA_ATI_RV635, "ATI RV635", 0, 0 },
164 { HDA_ATI_RV710, "ATI RV710", 0, 0 },
165 { HDA_ATI_RV730, "ATI RV730", 0, 0 },
166 { HDA_ATI_RV740, "ATI RV740", 0, 0 },
167 { HDA_ATI_RV770, "ATI RV770", 0, 0 },
168 { HDA_ATI_RV810, "ATI RV810", 0, 0 },
169 { HDA_ATI_RV830, "ATI RV830", 0, 0 },
170 { HDA_ATI_RV840, "ATI RV840", 0, 0 },
171 { HDA_ATI_RV870, "ATI RV870", 0, 0 },
172 { HDA_ATI_RV910, "ATI RV910", 0, 0 },
173 { HDA_ATI_RV930, "ATI RV930", 0, 0 },
174 { HDA_ATI_RV940, "ATI RV940", 0, 0 },
175 { HDA_ATI_RV970, "ATI RV970", 0, 0 },
176 { HDA_ATI_R1000, "ATI R1000", 0, 0 },
177 { HDA_AMD_HUDSON2, "AMD Hudson-2", 0, 0 },
178 { HDA_RDC_M3010, "RDC M3010", 0, 0 },
179 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 },
180 { HDA_SIS_966, "SiS 966/968", 0, 0 },
181 { HDA_ULI_M5461, "ULI M5461", 0, 0 },
183 { HDA_INTEL_ALL, "Intel", 0, 0 },
184 { HDA_NVIDIA_ALL, "NVIDIA", 0, 0 },
185 { HDA_ATI_ALL, "ATI", 0, 0 },
186 { HDA_AMD_ALL, "AMD", 0, 0 },
187 { HDA_CREATIVE_ALL, "Creative", 0, 0 },
188 { HDA_VIA_ALL, "VIA", 0, 0 },
189 { HDA_SIS_ALL, "SiS", 0, 0 },
190 { HDA_ULI_ALL, "ULI", 0, 0 },
193 static const struct {
198 } hdac_pcie_snoop[] = {
199 { INTEL_VENDORID, 0x00, 0x00, 0x00 },
200 { ATI_VENDORID, 0x42, 0xf8, 0x02 },
201 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
204 /****************************************************************************
205 * Function prototypes
206 ****************************************************************************/
207 static void hdac_intr_handler(void *);
208 static int hdac_reset(struct hdac_softc *, int);
209 static int hdac_get_capabilities(struct hdac_softc *);
210 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
211 static int hdac_dma_alloc(struct hdac_softc *,
212 struct hdac_dma *, bus_size_t);
213 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
214 static int hdac_mem_alloc(struct hdac_softc *);
215 static void hdac_mem_free(struct hdac_softc *);
216 static int hdac_irq_alloc(struct hdac_softc *);
217 static void hdac_irq_free(struct hdac_softc *);
218 static void hdac_corb_init(struct hdac_softc *);
219 static void hdac_rirb_init(struct hdac_softc *);
220 static void hdac_corb_start(struct hdac_softc *);
221 static void hdac_rirb_start(struct hdac_softc *);
223 static void hdac_attach2(void *);
225 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t);
227 static int hdac_probe(device_t);
228 static int hdac_attach(device_t);
229 static int hdac_detach(device_t);
230 static int hdac_suspend(device_t);
231 static int hdac_resume(device_t);
233 static int hdac_rirb_flush(struct hdac_softc *sc);
234 static int hdac_unsolq_flush(struct hdac_softc *sc);
236 #define hdac_command(a1, a2, a3) \
237 hdac_send_command(a1, a3, a2)
239 /* This function surely going to make its way into upper level someday. */
241 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
243 const char *res = NULL;
244 int i = 0, j, k, len, inv;
246 if (resource_string_value(device_get_name(sc->dev),
247 device_get_unit(sc->dev), "config", &res) != 0)
249 if (!(res != NULL && strlen(res) > 0))
252 device_printf(sc->dev, "Config options:");
255 while (res[i] != '\0' &&
256 (res[i] == ',' || isspace(res[i]) != 0))
258 if (res[i] == '\0') {
265 while (res[j] != '\0' &&
266 !(res[j] == ',' || isspace(res[j]) != 0))
269 if (len > 2 && strncmp(res + i, "no", 2) == 0)
273 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) {
274 if (strncmp(res + i + inv,
275 hdac_quirks_tab[k].key, len - inv) != 0)
277 if (len - inv != strlen(hdac_quirks_tab[k].key))
280 printf(" %s%s", (inv != 0) ? "no" : "",
281 hdac_quirks_tab[k].key);
284 *on |= hdac_quirks_tab[k].value;
285 *on &= ~hdac_quirks_tab[k].value;
286 } else if (inv != 0) {
287 *off |= hdac_quirks_tab[k].value;
288 *off &= ~hdac_quirks_tab[k].value;
296 /****************************************************************************
297 * void hdac_intr_handler(void *)
299 * Interrupt handler. Processes interrupts received from the hdac.
300 ****************************************************************************/
302 hdac_intr_handler(void *context)
304 struct hdac_softc *sc;
310 sc = (struct hdac_softc *)context;
313 /* Do we have anything to do? */
314 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
315 if ((intsts & HDAC_INTSTS_GIS) == 0) {
320 /* Was this a controller interrupt? */
321 if (intsts & HDAC_INTSTS_CIS) {
322 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
323 /* Get as many responses that we can */
324 while (rirbsts & HDAC_RIRBSTS_RINTFL) {
325 HDAC_WRITE_1(&sc->mem,
326 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
328 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
330 if (sc->unsolq_rp != sc->unsolq_wp)
331 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
334 if (intsts & HDAC_INTSTS_SIS_MASK) {
335 for (i = 0; i < sc->num_ss; i++) {
336 if ((intsts & (1 << i)) == 0)
338 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS,
339 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
340 if ((dev = sc->streams[i].dev) != NULL) {
341 HDAC_STREAM_INTR(dev,
342 sc->streams[i].dir, sc->streams[i].stream);
347 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts);
352 hdac_poll_callback(void *arg)
354 struct hdac_softc *sc = arg;
360 if (sc->polling == 0) {
364 callout_reset(&sc->poll_callout, sc->poll_ival,
365 hdac_poll_callback, sc);
368 hdac_intr_handler(sc);
371 /****************************************************************************
372 * int hdac_reset(hdac_softc *, int)
374 * Reset the hdac to a quiescent and known state.
375 ****************************************************************************/
377 hdac_reset(struct hdac_softc *sc, int wakeup)
383 * Stop all Streams DMA engine
385 for (i = 0; i < sc->num_iss; i++)
386 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
387 for (i = 0; i < sc->num_oss; i++)
388 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
389 for (i = 0; i < sc->num_bss; i++)
390 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
393 * Stop Control DMA engines.
395 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
396 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
399 * Reset DMA position buffer.
401 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
402 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
405 * Reset the controller. The reset must remain asserted for
406 * a minimum of 100us.
408 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
409 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
412 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
413 if (!(gctl & HDAC_GCTL_CRST))
417 if (gctl & HDAC_GCTL_CRST) {
418 device_printf(sc->dev, "Unable to put hdac in reset\n");
422 /* If wakeup is not requested - leave the controller in reset state. */
427 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
428 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
431 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
432 if (gctl & HDAC_GCTL_CRST)
436 if (!(gctl & HDAC_GCTL_CRST)) {
437 device_printf(sc->dev, "Device stuck in reset\n");
442 * Wait for codecs to finish their own reset sequence. The delay here
443 * should be of 250us but for some reasons, it's not enough on my
444 * computer. Let's use twice as much as necessary to make sure that
445 * it's reset properly.
453 /****************************************************************************
454 * int hdac_get_capabilities(struct hdac_softc *);
456 * Retreive the general capabilities of the hdac;
457 * Number of Input Streams
458 * Number of Output Streams
459 * Number of bidirectional Streams
461 * CORB and RIRB sizes
462 ****************************************************************************/
464 hdac_get_capabilities(struct hdac_softc *sc)
467 uint8_t corbsize, rirbsize;
469 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
470 sc->num_iss = HDAC_GCAP_ISS(gcap);
471 sc->num_oss = HDAC_GCAP_OSS(gcap);
472 sc->num_bss = HDAC_GCAP_BSS(gcap);
473 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss;
474 sc->num_sdo = HDAC_GCAP_NSDO(gcap);
475 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0;
476 if (sc->quirks_on & HDAC_QUIRK_64BIT)
477 sc->support_64bit = 1;
478 else if (sc->quirks_off & HDAC_QUIRK_64BIT)
479 sc->support_64bit = 0;
481 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
482 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
483 HDAC_CORBSIZE_CORBSZCAP_256)
485 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
486 HDAC_CORBSIZE_CORBSZCAP_16)
488 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
489 HDAC_CORBSIZE_CORBSZCAP_2)
492 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
497 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
498 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
499 HDAC_RIRBSIZE_RIRBSZCAP_256)
501 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
502 HDAC_RIRBSIZE_RIRBSZCAP_16)
504 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
505 HDAC_RIRBSIZE_RIRBSZCAP_2)
508 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
514 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, "
515 "NSDO %d%s, CORB %d, RIRB %d\n",
516 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo,
517 sc->support_64bit ? ", 64bit" : "",
518 sc->corb_size, sc->rirb_size);
525 /****************************************************************************
528 * This function is called by bus_dmamap_load when the mapping has been
529 * established. We just record the physical address of the mapping into
530 * the struct hdac_dma passed in.
531 ****************************************************************************/
533 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
535 struct hdac_dma *dma;
538 dma = (struct hdac_dma *)callback_arg;
539 dma->dma_paddr = segs[0].ds_addr;
544 /****************************************************************************
547 * This function allocate and setup a dma region (struct hdac_dma).
548 * It must be freed by a corresponding hdac_dma_free.
549 ****************************************************************************/
551 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
556 roundsz = roundup2(size, HDA_DMA_ALIGNMENT);
557 bzero(dma, sizeof(*dma));
562 result = bus_dma_tag_create(
563 bus_get_dma_tag(sc->dev), /* parent */
564 HDA_DMA_ALIGNMENT, /* alignment */
566 (sc->support_64bit) ? BUS_SPACE_MAXADDR :
567 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
568 BUS_SPACE_MAXADDR, /* highaddr */
570 NULL, /* fistfuncarg */
571 roundsz, /* maxsize */
573 roundsz, /* maxsegsz */
576 NULL, /* lockfuncarg */
577 &dma->dma_tag); /* dmat */
579 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%d)\n",
581 goto hdac_dma_alloc_fail;
585 * Allocate DMA memory
587 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
588 BUS_DMA_NOWAIT | BUS_DMA_ZERO |
589 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE :
593 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%d)\n",
595 goto hdac_dma_alloc_fail;
598 dma->dma_size = roundsz;
603 result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
604 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
605 if (result != 0 || dma->dma_paddr == 0) {
608 device_printf(sc->dev, "%s: bus_dmamem_load failed (%d)\n",
610 goto hdac_dma_alloc_fail;
614 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
615 __func__, (uintmax_t)size, (uintmax_t)roundsz);
621 hdac_dma_free(sc, dma);
627 /****************************************************************************
628 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
630 * Free a struct dhac_dma that has been previously allocated via the
631 * hdac_dma_alloc function.
632 ****************************************************************************/
634 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
636 if (dma->dma_paddr != 0) {
638 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
639 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
640 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
643 if (dma->dma_vaddr != NULL) {
644 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
645 dma->dma_vaddr = NULL;
647 if (dma->dma_tag != NULL) {
648 bus_dma_tag_destroy(dma->dma_tag);
654 /****************************************************************************
655 * int hdac_mem_alloc(struct hdac_softc *)
657 * Allocate all the bus resources necessary to speak with the physical
659 ****************************************************************************/
661 hdac_mem_alloc(struct hdac_softc *sc)
663 struct hdac_mem *mem;
666 mem->mem_rid = PCIR_BAR(0);
667 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
668 &mem->mem_rid, RF_ACTIVE);
669 if (mem->mem_res == NULL) {
670 device_printf(sc->dev,
671 "%s: Unable to allocate memory resource\n", __func__);
674 mem->mem_tag = rman_get_bustag(mem->mem_res);
675 mem->mem_handle = rman_get_bushandle(mem->mem_res);
680 /****************************************************************************
681 * void hdac_mem_free(struct hdac_softc *)
683 * Free up resources previously allocated by hdac_mem_alloc.
684 ****************************************************************************/
686 hdac_mem_free(struct hdac_softc *sc)
688 struct hdac_mem *mem;
691 if (mem->mem_res != NULL)
692 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
697 /****************************************************************************
698 * int hdac_irq_alloc(struct hdac_softc *)
700 * Allocate and setup the resources necessary for interrupt handling.
701 ****************************************************************************/
703 hdac_irq_alloc(struct hdac_softc *sc)
705 struct hdac_irq *irq;
711 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 &&
712 (result = pci_msi_count(sc->dev)) == 1 &&
713 pci_alloc_msi(sc->dev, &result) == 0)
716 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
717 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
718 if (irq->irq_res == NULL) {
719 device_printf(sc->dev, "%s: Unable to allocate irq\n",
721 goto hdac_irq_alloc_fail;
723 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV,
724 NULL, hdac_intr_handler, sc, &irq->irq_handle);
726 device_printf(sc->dev,
727 "%s: Unable to setup interrupt handler (%d)\n",
729 goto hdac_irq_alloc_fail;
740 /****************************************************************************
741 * void hdac_irq_free(struct hdac_softc *)
743 * Free up resources previously allocated by hdac_irq_alloc.
744 ****************************************************************************/
746 hdac_irq_free(struct hdac_softc *sc)
748 struct hdac_irq *irq;
751 if (irq->irq_res != NULL && irq->irq_handle != NULL)
752 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
753 if (irq->irq_res != NULL)
754 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
756 if (irq->irq_rid == 0x1)
757 pci_release_msi(sc->dev);
758 irq->irq_handle = NULL;
763 /****************************************************************************
764 * void hdac_corb_init(struct hdac_softc *)
766 * Initialize the corb registers for operations but do not start it up yet.
767 * The CORB engine must not be running when this function is called.
768 ****************************************************************************/
770 hdac_corb_init(struct hdac_softc *sc)
775 /* Setup the CORB size. */
776 switch (sc->corb_size) {
778 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
781 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
784 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
787 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
789 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
791 /* Setup the CORB Address in the hdac */
792 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
793 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
794 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
796 /* Set the WP and RP */
798 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
799 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
801 * The HDA specification indicates that the CORBRPRST bit will always
802 * read as zero. Unfortunately, it seems that at least the 82801G
803 * doesn't reset the bit to zero, which stalls the corb engine.
804 * manually reset the bit to zero before continuing.
806 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
808 /* Enable CORB error reporting */
810 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
814 /****************************************************************************
815 * void hdac_rirb_init(struct hdac_softc *)
817 * Initialize the rirb registers for operations but do not start it up yet.
818 * The RIRB engine must not be running when this function is called.
819 ****************************************************************************/
821 hdac_rirb_init(struct hdac_softc *sc)
826 /* Setup the RIRB size. */
827 switch (sc->rirb_size) {
829 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
832 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
835 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
838 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
840 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
842 /* Setup the RIRB Address in the hdac */
843 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
844 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
845 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
847 /* Setup the WP and RP */
849 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
851 /* Setup the interrupt threshold */
852 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
854 /* Enable Overrun and response received reporting */
856 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
857 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
859 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
863 * Make sure that the Host CPU cache doesn't contain any dirty
864 * cache lines that falls in the rirb. If I understood correctly, it
865 * should be sufficient to do this only once as the rirb is purely
866 * read-only from now on.
868 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
869 BUS_DMASYNC_PREREAD);
872 /****************************************************************************
873 * void hdac_corb_start(hdac_softc *)
875 * Startup the corb DMA engine
876 ****************************************************************************/
878 hdac_corb_start(struct hdac_softc *sc)
882 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
883 corbctl |= HDAC_CORBCTL_CORBRUN;
884 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
887 /****************************************************************************
888 * void hdac_rirb_start(hdac_softc *)
890 * Startup the rirb DMA engine
891 ****************************************************************************/
893 hdac_rirb_start(struct hdac_softc *sc)
897 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
898 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
899 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
903 hdac_rirb_flush(struct hdac_softc *sc)
905 struct hdac_rirb *rirb_base, *rirb;
907 uint32_t resp, resp_ex;
911 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
912 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
913 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
914 BUS_DMASYNC_POSTREAD);
917 while (sc->rirb_rp != rirbwp) {
919 sc->rirb_rp %= sc->rirb_size;
920 rirb = &rirb_base[sc->rirb_rp];
921 resp = le32toh(rirb->response);
922 resp_ex = le32toh(rirb->response_ex);
923 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(resp_ex);
924 if (resp_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
925 sc->unsolq[sc->unsolq_wp++] = resp;
926 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
927 sc->unsolq[sc->unsolq_wp++] = cad;
928 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
929 } else if (sc->codecs[cad].pending <= 0) {
930 device_printf(sc->dev, "Unexpected unsolicited "
931 "response from address %d: %08x\n", cad, resp);
933 sc->codecs[cad].response = resp;
934 sc->codecs[cad].pending--;
939 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
940 BUS_DMASYNC_PREREAD);
945 hdac_unsolq_flush(struct hdac_softc *sc)
952 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
953 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
954 while (sc->unsolq_rp != sc->unsolq_wp) {
955 resp = sc->unsolq[sc->unsolq_rp++];
956 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
957 cad = sc->unsolq[sc->unsolq_rp++];
958 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
959 if ((child = sc->codecs[cad].dev) != NULL)
960 HDAC_UNSOL_INTR(child, resp);
963 sc->unsolq_st = HDAC_UNSOLQ_READY;
969 /****************************************************************************
970 * uint32_t hdac_command_sendone_internal
972 * Wrapper function that sends only one command to a given codec
973 ****************************************************************************/
975 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb)
980 if (!hdac_lockowned(sc))
981 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
982 verb &= ~HDA_CMD_CAD_MASK;
983 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT;
984 sc->codecs[cad].response = HDA_INVALID;
986 sc->codecs[cad].pending++;
988 sc->corb_wp %= sc->corb_size;
989 corb = (uint32_t *)sc->corb_dma.dma_vaddr;
990 bus_dmamap_sync(sc->corb_dma.dma_tag,
991 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
992 corb[sc->corb_wp] = htole32(verb);
993 bus_dmamap_sync(sc->corb_dma.dma_tag,
994 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
995 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
999 if (hdac_rirb_flush(sc) == 0)
1001 } while (sc->codecs[cad].pending != 0 && --timeout);
1003 if (sc->codecs[cad].pending != 0) {
1004 device_printf(sc->dev, "Command timeout on address %d\n", cad);
1005 sc->codecs[cad].pending = 0;
1008 if (sc->unsolq_rp != sc->unsolq_wp)
1009 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
1010 return (sc->codecs[cad].response);
1013 /****************************************************************************
1015 ****************************************************************************/
1017 /****************************************************************************
1018 * int hdac_probe(device_t)
1020 * Probe for the presence of an hdac. If none is found, check for a generic
1021 * match using the subclass of the device.
1022 ****************************************************************************/
1024 hdac_probe(device_t dev)
1028 uint16_t class, subclass;
1031 model = (uint32_t)pci_get_device(dev) << 16;
1032 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1033 class = pci_get_class(dev);
1034 subclass = pci_get_subclass(dev);
1036 bzero(desc, sizeof(desc));
1038 for (i = 0; i < nitems(hdac_devices); i++) {
1039 if (hdac_devices[i].model == model) {
1040 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
1041 result = BUS_PROBE_DEFAULT;
1044 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1045 class == PCIC_MULTIMEDIA &&
1046 subclass == PCIS_MULTIMEDIA_HDA) {
1047 snprintf(desc, sizeof(desc),
1049 hdac_devices[i].desc, pci_get_device(dev));
1050 result = BUS_PROBE_GENERIC;
1054 if (result == ENXIO && class == PCIC_MULTIMEDIA &&
1055 subclass == PCIS_MULTIMEDIA_HDA) {
1056 snprintf(desc, sizeof(desc), "Generic (0x%08x)", model);
1057 result = BUS_PROBE_GENERIC;
1059 if (result != ENXIO) {
1060 strlcat(desc, " HDA Controller", sizeof(desc));
1061 device_set_desc_copy(dev, desc);
1068 hdac_unsolq_task(void *context, int pending)
1070 struct hdac_softc *sc;
1072 sc = (struct hdac_softc *)context;
1075 hdac_unsolq_flush(sc);
1079 /****************************************************************************
1080 * int hdac_attach(device_t)
1082 * Attach the device into the kernel. Interrupts usually won't be enabled
1083 * when this function is called. Setup everything that doesn't require
1084 * interrupts and defer probing of codecs until interrupts are enabled.
1085 ****************************************************************************/
1087 hdac_attach(device_t dev)
1089 struct hdac_softc *sc;
1093 uint16_t class, subclass;
1097 sc = device_get_softc(dev);
1099 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n",
1100 pci_get_subvendor(dev), pci_get_subdevice(dev));
1101 device_printf(dev, "HDA Driver Revision: %s\n",
1105 model = (uint32_t)pci_get_device(dev) << 16;
1106 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1107 class = pci_get_class(dev);
1108 subclass = pci_get_subclass(dev);
1110 for (i = 0; i < nitems(hdac_devices); i++) {
1111 if (hdac_devices[i].model == model) {
1115 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1116 class == PCIC_MULTIMEDIA &&
1117 subclass == PCIS_MULTIMEDIA_HDA) {
1123 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex");
1125 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
1126 callout_init(&sc->poll_callout, 1);
1127 for (i = 0; i < HDAC_CODEC_MAX; i++)
1128 sc->codecs[i].dev = NULL;
1130 sc->quirks_on = hdac_devices[devid].quirks_on;
1131 sc->quirks_off = hdac_devices[devid].quirks_off;
1136 if (resource_int_value(device_get_name(dev),
1137 device_get_unit(dev), "msi", &i) == 0) {
1139 sc->quirks_off |= HDAC_QUIRK_MSI;
1141 sc->quirks_on |= HDAC_QUIRK_MSI;
1142 sc->quirks_off |= ~HDAC_QUIRK_MSI;
1145 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off);
1147 device_printf(sc->dev,
1148 "Config options: on=0x%08x off=0x%08x\n",
1149 sc->quirks_on, sc->quirks_off);
1152 if (resource_int_value(device_get_name(dev),
1153 device_get_unit(dev), "polling", &i) == 0 && i != 0)
1158 pci_enable_busmaster(dev);
1160 vendor = pci_get_vendor(dev);
1161 if (vendor == INTEL_VENDORID) {
1163 v = pci_read_config(dev, 0x44, 1);
1164 pci_write_config(dev, 0x44, v & 0xf8, 1);
1166 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
1167 pci_read_config(dev, 0x44, 1));
1171 #if defined(__i386__) || defined(__amd64__)
1172 sc->flags |= HDAC_F_DMA_NOCACHE;
1174 if (resource_int_value(device_get_name(dev),
1175 device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
1177 sc->flags &= ~HDAC_F_DMA_NOCACHE;
1180 * Try to enable PCIe snoop to avoid messing around with
1181 * uncacheable DMA attribute. Since PCIe snoop register
1182 * config is pretty much vendor specific, there are no
1183 * general solutions on how to enable it, forcing us (even
1184 * Microsoft) to enable uncacheable or write combined DMA
1187 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
1189 for (i = 0; i < nitems(hdac_pcie_snoop); i++) {
1190 if (hdac_pcie_snoop[i].vendor != vendor)
1192 sc->flags &= ~HDAC_F_DMA_NOCACHE;
1193 if (hdac_pcie_snoop[i].reg == 0x00)
1195 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
1196 if ((v & hdac_pcie_snoop[i].enable) ==
1197 hdac_pcie_snoop[i].enable)
1199 v &= hdac_pcie_snoop[i].mask;
1200 v |= hdac_pcie_snoop[i].enable;
1201 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
1202 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
1203 if ((v & hdac_pcie_snoop[i].enable) !=
1204 hdac_pcie_snoop[i].enable) {
1207 "WARNING: Failed to enable PCIe "
1210 #if defined(__i386__) || defined(__amd64__)
1211 sc->flags |= HDAC_F_DMA_NOCACHE;
1216 #if defined(__i386__) || defined(__amd64__)
1221 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
1222 (sc->flags & HDAC_F_DMA_NOCACHE) ?
1223 "Uncacheable" : "PCIe snoop", vendor);
1226 /* Allocate resources */
1227 result = hdac_mem_alloc(sc);
1229 goto hdac_attach_fail;
1230 result = hdac_irq_alloc(sc);
1232 goto hdac_attach_fail;
1234 /* Get Capabilities */
1235 result = hdac_get_capabilities(sc);
1237 goto hdac_attach_fail;
1239 /* Allocate CORB, RIRB, POS and BDLs dma memory */
1240 result = hdac_dma_alloc(sc, &sc->corb_dma,
1241 sc->corb_size * sizeof(uint32_t));
1243 goto hdac_attach_fail;
1244 result = hdac_dma_alloc(sc, &sc->rirb_dma,
1245 sc->rirb_size * sizeof(struct hdac_rirb));
1247 goto hdac_attach_fail;
1248 sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss,
1249 M_HDAC, M_ZERO | M_WAITOK);
1250 for (i = 0; i < sc->num_ss; i++) {
1251 result = hdac_dma_alloc(sc, &sc->streams[i].bdl,
1252 sizeof(struct hdac_bdle) * HDA_BDL_MAX);
1254 goto hdac_attach_fail;
1256 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) {
1257 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) {
1259 device_printf(dev, "Failed to "
1260 "allocate DMA pos buffer "
1264 uint64_t addr = sc->pos_dma.dma_paddr;
1266 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32);
1267 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
1268 (addr & HDAC_DPLBASE_DPLBASE_MASK) |
1269 HDAC_DPLBASE_DPLBASE_DMAPBE);
1273 result = bus_dma_tag_create(
1274 bus_get_dma_tag(sc->dev), /* parent */
1275 HDA_DMA_ALIGNMENT, /* alignment */
1277 (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1278 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1279 BUS_SPACE_MAXADDR, /* highaddr */
1280 NULL, /* filtfunc */
1281 NULL, /* fistfuncarg */
1282 HDA_BUFSZ_MAX, /* maxsize */
1284 HDA_BUFSZ_MAX, /* maxsegsz */
1286 NULL, /* lockfunc */
1287 NULL, /* lockfuncarg */
1288 &sc->chan_dmat); /* dmat */
1290 device_printf(dev, "%s: bus_dma_tag_create failed (%d)\n",
1292 goto hdac_attach_fail;
1295 /* Quiesce everything */
1297 device_printf(dev, "Reset controller...\n");
1301 /* Initialize the CORB and RIRB */
1305 /* Defer remaining of initialization until interrupts are enabled */
1306 sc->intrhook.ich_func = hdac_attach2;
1307 sc->intrhook.ich_arg = (void *)sc;
1308 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
1309 sc->intrhook.ich_func = NULL;
1310 hdac_attach2((void *)sc);
1317 if (sc->streams != NULL)
1318 for (i = 0; i < sc->num_ss; i++)
1319 hdac_dma_free(sc, &sc->streams[i].bdl);
1320 free(sc->streams, M_HDAC);
1321 hdac_dma_free(sc, &sc->rirb_dma);
1322 hdac_dma_free(sc, &sc->corb_dma);
1324 snd_mtxfree(sc->lock);
1330 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
1332 struct hdac_softc *sc;
1335 int devcount, i, err, val;
1337 dev = oidp->oid_arg1;
1338 sc = device_get_softc(dev);
1342 err = sysctl_handle_int(oidp, &val, 0, req);
1343 if (err != 0 || req->newptr == NULL || val == 0)
1346 /* XXX: Temporary. For debugging. */
1350 } else if (val == 101) {
1355 if ((err = device_get_children(dev, &devlist, &devcount)) != 0)
1358 for (i = 0; i < devcount; i++)
1359 HDAC_PINDUMP(devlist[i]);
1361 free(devlist, M_TEMP);
1366 hdac_mdata_rate(uint16_t fmt)
1368 static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 };
1371 if (fmt & (1 << 14))
1375 rate *= ((fmt >> 11) & 0x07) + 1;
1376 rate /= ((fmt >> 8) & 0x07) + 1;
1377 bits = mbits[(fmt >> 4) & 0x03];
1378 bits *= (fmt & 0x0f) + 1;
1379 return (rate * bits);
1383 hdac_bdata_rate(uint16_t fmt, int output)
1385 static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 };
1389 rate *= ((fmt >> 11) & 0x07) + 1;
1390 bits = bbits[(fmt >> 4) & 0x03];
1391 bits *= (fmt & 0x0f) + 1;
1393 bits = ((bits + 7) & ~0x07) + 10;
1394 return (rate * bits);
1398 hdac_poll_reinit(struct hdac_softc *sc)
1400 int i, pollticks, min = 1000000;
1401 struct hdac_stream *s;
1403 if (sc->polling == 0)
1405 if (sc->unsol_registered > 0)
1407 for (i = 0; i < sc->num_ss; i++) {
1408 s = &sc->streams[i];
1409 if (s->running == 0)
1411 pollticks = ((uint64_t)hz * s->blksz) /
1412 (hdac_mdata_rate(s->format) / 8);
1418 if (min > pollticks)
1421 sc->poll_ival = min;
1423 callout_stop(&sc->poll_callout);
1425 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc);
1429 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
1431 struct hdac_softc *sc;
1436 dev = oidp->oid_arg1;
1437 sc = device_get_softc(dev);
1443 err = sysctl_handle_int(oidp, &val, 0, req);
1445 if (err != 0 || req->newptr == NULL)
1447 if (val < 0 || val > 1)
1451 if (val != sc->polling) {
1453 callout_stop(&sc->poll_callout);
1455 callout_drain(&sc->poll_callout);
1458 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1459 ctl |= HDAC_INTCTL_GIE;
1460 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1462 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1463 ctl &= ~HDAC_INTCTL_GIE;
1464 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1466 hdac_poll_reinit(sc);
1475 hdac_attach2(void *arg)
1477 struct hdac_softc *sc;
1479 uint32_t vendorid, revisionid;
1483 sc = (struct hdac_softc *)arg;
1487 /* Remove ourselves from the config hooks */
1488 if (sc->intrhook.ich_func != NULL) {
1489 config_intrhook_disestablish(&sc->intrhook);
1490 sc->intrhook.ich_func = NULL;
1494 device_printf(sc->dev, "Starting CORB Engine...\n");
1496 hdac_corb_start(sc);
1498 device_printf(sc->dev, "Starting RIRB Engine...\n");
1500 hdac_rirb_start(sc);
1502 device_printf(sc->dev,
1503 "Enabling controller interrupt...\n");
1505 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1507 if (sc->polling == 0) {
1508 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
1509 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1514 device_printf(sc->dev, "Scanning HDA codecs ...\n");
1516 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1518 for (i = 0; i < HDAC_CODEC_MAX; i++) {
1519 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1521 device_printf(sc->dev,
1522 "Found CODEC at address %d\n", i);
1525 vendorid = hdac_send_command(sc, i,
1526 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID));
1527 revisionid = hdac_send_command(sc, i,
1528 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID));
1530 if (vendorid == HDA_INVALID &&
1531 revisionid == HDA_INVALID) {
1532 device_printf(sc->dev,
1533 "CODEC is not responding!\n");
1536 sc->codecs[i].vendor_id =
1537 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1538 sc->codecs[i].device_id =
1539 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1540 sc->codecs[i].revision_id =
1541 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1542 sc->codecs[i].stepping_id =
1543 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1544 child = device_add_child(sc->dev, "hdacc", -1);
1545 if (child == NULL) {
1546 device_printf(sc->dev,
1547 "Failed to add CODEC device\n");
1550 device_set_ivars(child, (void *)(intptr_t)i);
1551 sc->codecs[i].dev = child;
1554 bus_generic_attach(sc->dev);
1556 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1557 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1558 "pindump", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc->dev,
1559 sizeof(sc->dev), sysctl_hdac_pindump, "I", "Dump pin states/data");
1560 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1561 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1562 "polling", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc->dev,
1563 sizeof(sc->dev), sysctl_hdac_polling, "I", "Enable polling mode");
1566 /****************************************************************************
1567 * int hdac_suspend(device_t)
1569 * Suspend and power down HDA bus and codecs.
1570 ****************************************************************************/
1572 hdac_suspend(device_t dev)
1574 struct hdac_softc *sc = device_get_softc(dev);
1577 device_printf(dev, "Suspend...\n");
1579 bus_generic_suspend(dev);
1583 device_printf(dev, "Reset controller...\n");
1585 callout_stop(&sc->poll_callout);
1588 callout_drain(&sc->poll_callout);
1589 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1591 device_printf(dev, "Suspend done\n");
1596 /****************************************************************************
1597 * int hdac_resume(device_t)
1599 * Powerup and restore HDA bus and codecs state.
1600 ****************************************************************************/
1602 hdac_resume(device_t dev)
1604 struct hdac_softc *sc = device_get_softc(dev);
1608 device_printf(dev, "Resume...\n");
1612 /* Quiesce everything */
1614 device_printf(dev, "Reset controller...\n");
1618 /* Initialize the CORB and RIRB */
1623 device_printf(dev, "Starting CORB Engine...\n");
1625 hdac_corb_start(sc);
1627 device_printf(dev, "Starting RIRB Engine...\n");
1629 hdac_rirb_start(sc);
1631 device_printf(dev, "Enabling controller interrupt...\n");
1633 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1635 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1637 hdac_poll_reinit(sc);
1640 error = bus_generic_resume(dev);
1642 device_printf(dev, "Resume done\n");
1647 /****************************************************************************
1648 * int hdac_detach(device_t)
1650 * Detach and free up resources utilized by the hdac device.
1651 ****************************************************************************/
1653 hdac_detach(device_t dev)
1655 struct hdac_softc *sc = device_get_softc(dev);
1657 int cad, i, devcount, error;
1659 if ((error = device_get_children(dev, &devlist, &devcount)) != 0)
1661 for (i = 0; i < devcount; i++) {
1662 cad = (intptr_t)device_get_ivars(devlist[i]);
1663 if ((error = device_delete_child(dev, devlist[i])) != 0) {
1664 free(devlist, M_TEMP);
1667 sc->codecs[cad].dev = NULL;
1669 free(devlist, M_TEMP);
1674 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1677 for (i = 0; i < sc->num_ss; i++)
1678 hdac_dma_free(sc, &sc->streams[i].bdl);
1679 free(sc->streams, M_HDAC);
1680 hdac_dma_free(sc, &sc->pos_dma);
1681 hdac_dma_free(sc, &sc->rirb_dma);
1682 hdac_dma_free(sc, &sc->corb_dma);
1683 if (sc->chan_dmat != NULL) {
1684 bus_dma_tag_destroy(sc->chan_dmat);
1685 sc->chan_dmat = NULL;
1688 snd_mtxfree(sc->lock);
1692 static bus_dma_tag_t
1693 hdac_get_dma_tag(device_t dev, device_t child)
1695 struct hdac_softc *sc = device_get_softc(dev);
1697 return (sc->chan_dmat);
1701 hdac_print_child(device_t dev, device_t child)
1705 retval = bus_print_child_header(dev, child);
1706 retval += printf(" at cad %d",
1707 (int)(intptr_t)device_get_ivars(child));
1708 retval += bus_print_child_footer(dev, child);
1714 hdac_child_location_str(device_t dev, device_t child, char *buf,
1718 snprintf(buf, buflen, "cad=%d",
1719 (int)(intptr_t)device_get_ivars(child));
1724 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
1727 struct hdac_softc *sc = device_get_softc(dev);
1728 nid_t cad = (uintptr_t)device_get_ivars(child);
1730 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x "
1732 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id,
1733 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id);
1738 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1740 struct hdac_softc *sc = device_get_softc(dev);
1741 nid_t cad = (uintptr_t)device_get_ivars(child);
1744 case HDA_IVAR_CODEC_ID:
1747 case HDA_IVAR_VENDOR_ID:
1748 *result = sc->codecs[cad].vendor_id;
1750 case HDA_IVAR_DEVICE_ID:
1751 *result = sc->codecs[cad].device_id;
1753 case HDA_IVAR_REVISION_ID:
1754 *result = sc->codecs[cad].revision_id;
1756 case HDA_IVAR_STEPPING_ID:
1757 *result = sc->codecs[cad].stepping_id;
1759 case HDA_IVAR_SUBVENDOR_ID:
1760 *result = pci_get_subvendor(dev);
1762 case HDA_IVAR_SUBDEVICE_ID:
1763 *result = pci_get_subdevice(dev);
1765 case HDA_IVAR_DMA_NOCACHE:
1766 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0;
1768 case HDA_IVAR_STRIPES_MASK:
1769 *result = (1 << (1 << sc->num_sdo)) - 1;
1778 hdac_get_mtx(device_t dev, device_t child)
1780 struct hdac_softc *sc = device_get_softc(dev);
1786 hdac_codec_command(device_t dev, device_t child, uint32_t verb)
1789 return (hdac_send_command(device_get_softc(dev),
1790 (intptr_t)device_get_ivars(child), verb));
1794 hdac_find_stream(struct hdac_softc *sc, int dir, int stream)
1799 /* Allocate ISS/OSS first. */
1801 for (i = 0; i < sc->num_iss; i++) {
1802 if (sc->streams[i].stream == stream) {
1808 for (i = 0; i < sc->num_oss; i++) {
1809 if (sc->streams[i + sc->num_iss].stream == stream) {
1810 ss = i + sc->num_iss;
1815 /* Fallback to BSS. */
1817 for (i = 0; i < sc->num_bss; i++) {
1818 if (sc->streams[i + sc->num_iss + sc->num_oss].stream
1820 ss = i + sc->num_iss + sc->num_oss;
1829 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe,
1832 struct hdac_softc *sc = device_get_softc(dev);
1833 nid_t cad = (uintptr_t)device_get_ivars(child);
1834 int stream, ss, bw, maxbw, prevbw;
1836 /* Look for empty stream. */
1837 ss = hdac_find_stream(sc, dir, 0);
1839 /* Return if found nothing. */
1843 /* Check bus bandwidth. */
1844 bw = hdac_bdata_rate(format, dir);
1846 bw *= 1 << (sc->num_sdo - stripe);
1847 prevbw = sc->sdo_bw_used;
1848 maxbw = 48000 * 960 * (1 << sc->num_sdo);
1850 prevbw = sc->codecs[cad].sdi_bw_used;
1851 maxbw = 48000 * 464;
1854 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n",
1855 (bw + prevbw) / 1000, maxbw / 1000,
1856 bw + prevbw > maxbw ? " -- OVERFLOW!" : "");
1858 if (bw + prevbw > maxbw)
1861 sc->sdo_bw_used += bw;
1863 sc->codecs[cad].sdi_bw_used += bw;
1865 /* Allocate stream number */
1866 if (ss >= sc->num_iss + sc->num_oss)
1867 stream = 15 - (ss - sc->num_iss - sc->num_oss);
1868 else if (ss >= sc->num_iss)
1869 stream = ss - sc->num_iss + 1;
1873 sc->streams[ss].dev = child;
1874 sc->streams[ss].dir = dir;
1875 sc->streams[ss].stream = stream;
1876 sc->streams[ss].bw = bw;
1877 sc->streams[ss].format = format;
1878 sc->streams[ss].stripe = stripe;
1879 if (dmapos != NULL) {
1880 if (sc->pos_dma.dma_vaddr != NULL)
1881 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8);
1889 hdac_stream_free(device_t dev, device_t child, int dir, int stream)
1891 struct hdac_softc *sc = device_get_softc(dev);
1892 nid_t cad = (uintptr_t)device_get_ivars(child);
1895 ss = hdac_find_stream(sc, dir, stream);
1897 ("Free for not allocated stream (%d/%d)\n", dir, stream));
1899 sc->sdo_bw_used -= sc->streams[ss].bw;
1901 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw;
1902 sc->streams[ss].stream = 0;
1903 sc->streams[ss].dev = NULL;
1907 hdac_stream_start(device_t dev, device_t child,
1908 int dir, int stream, bus_addr_t buf, int blksz, int blkcnt)
1910 struct hdac_softc *sc = device_get_softc(dev);
1911 struct hdac_bdle *bdle;
1916 ss = hdac_find_stream(sc, dir, stream);
1918 ("Start for not allocated stream (%d/%d)\n", dir, stream));
1920 addr = (uint64_t)buf;
1921 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr;
1922 for (i = 0; i < blkcnt; i++, bdle++) {
1923 bdle->addrl = htole32((uint32_t)addr);
1924 bdle->addrh = htole32((uint32_t)(addr >> 32));
1925 bdle->len = htole32(blksz);
1926 bdle->ioc = htole32(1);
1930 bus_dmamap_sync(sc->streams[ss].bdl.dma_tag,
1931 sc->streams[ss].bdl.dma_map, BUS_DMASYNC_PREWRITE);
1934 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt);
1935 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1);
1936 addr = sc->streams[ss].bdl.dma_paddr;
1937 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr);
1938 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
1940 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2);
1942 ctl |= HDAC_SDCTL2_DIR;
1944 ctl &= ~HDAC_SDCTL2_DIR;
1945 ctl &= ~HDAC_SDCTL2_STRM_MASK;
1946 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT;
1947 ctl &= ~HDAC_SDCTL2_STRIPE_MASK;
1948 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT;
1949 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl);
1951 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format);
1953 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1955 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1957 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS,
1958 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS);
1959 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1960 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1962 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1964 sc->streams[ss].blksz = blksz;
1965 sc->streams[ss].running = 1;
1966 hdac_poll_reinit(sc);
1971 hdac_stream_stop(device_t dev, device_t child, int dir, int stream)
1973 struct hdac_softc *sc = device_get_softc(dev);
1977 ss = hdac_find_stream(sc, dir, stream);
1979 ("Stop for not allocated stream (%d/%d)\n", dir, stream));
1981 bus_dmamap_sync(sc->streams[ss].bdl.dma_tag,
1982 sc->streams[ss].bdl.dma_map, BUS_DMASYNC_POSTWRITE);
1985 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1986 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1988 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1990 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1992 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1994 sc->streams[ss].running = 0;
1995 hdac_poll_reinit(sc);
1999 hdac_stream_reset(device_t dev, device_t child, int dir, int stream)
2001 struct hdac_softc *sc = device_get_softc(dev);
2007 ss = hdac_find_stream(sc, dir, stream);
2009 ("Reset for not allocated stream (%d/%d)\n", dir, stream));
2012 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2013 ctl |= HDAC_SDCTL_SRST;
2014 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2016 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2017 if (ctl & HDAC_SDCTL_SRST)
2021 if (!(ctl & HDAC_SDCTL_SRST))
2022 device_printf(dev, "Reset setting timeout\n");
2023 ctl &= ~HDAC_SDCTL_SRST;
2024 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2027 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2028 if (!(ctl & HDAC_SDCTL_SRST))
2032 if (ctl & HDAC_SDCTL_SRST)
2033 device_printf(dev, "Reset timeout!\n");
2037 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream)
2039 struct hdac_softc *sc = device_get_softc(dev);
2042 ss = hdac_find_stream(sc, dir, stream);
2044 ("Reset for not allocated stream (%d/%d)\n", dir, stream));
2047 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB));
2051 hdac_unsol_alloc(device_t dev, device_t child, int tag)
2053 struct hdac_softc *sc = device_get_softc(dev);
2055 sc->unsol_registered++;
2056 hdac_poll_reinit(sc);
2061 hdac_unsol_free(device_t dev, device_t child, int tag)
2063 struct hdac_softc *sc = device_get_softc(dev);
2065 sc->unsol_registered--;
2066 hdac_poll_reinit(sc);
2069 static device_method_t hdac_methods[] = {
2070 /* device interface */
2071 DEVMETHOD(device_probe, hdac_probe),
2072 DEVMETHOD(device_attach, hdac_attach),
2073 DEVMETHOD(device_detach, hdac_detach),
2074 DEVMETHOD(device_suspend, hdac_suspend),
2075 DEVMETHOD(device_resume, hdac_resume),
2077 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag),
2078 DEVMETHOD(bus_print_child, hdac_print_child),
2079 DEVMETHOD(bus_child_location_str, hdac_child_location_str),
2080 DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method),
2081 DEVMETHOD(bus_read_ivar, hdac_read_ivar),
2082 DEVMETHOD(hdac_get_mtx, hdac_get_mtx),
2083 DEVMETHOD(hdac_codec_command, hdac_codec_command),
2084 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc),
2085 DEVMETHOD(hdac_stream_free, hdac_stream_free),
2086 DEVMETHOD(hdac_stream_start, hdac_stream_start),
2087 DEVMETHOD(hdac_stream_stop, hdac_stream_stop),
2088 DEVMETHOD(hdac_stream_reset, hdac_stream_reset),
2089 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr),
2090 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc),
2091 DEVMETHOD(hdac_unsol_free, hdac_unsol_free),
2095 static driver_t hdac_driver = {
2098 sizeof(struct hdac_softc),
2101 static devclass_t hdac_devclass;
2103 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL);