2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
5 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
6 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Intel High Definition Audio (Controller) driver for FreeBSD.
35 #ifdef HAVE_KERNEL_OPTION_HEADERS
39 #include <dev/sound/pcm/sound.h>
40 #include <dev/pci/pcireg.h>
41 #include <dev/pci/pcivar.h>
43 #include <sys/ctype.h>
44 #include <sys/taskqueue.h>
46 #include <dev/sound/pci/hda/hdac_private.h>
47 #include <dev/sound/pci/hda/hdac_reg.h>
48 #include <dev/sound/pci/hda/hda_reg.h>
49 #include <dev/sound/pci/hda/hdac.h>
51 #define HDA_DRV_TEST_REV "20120126_0002"
53 SND_DECLARE_FILE("$FreeBSD$");
55 #define hdac_lock(sc) snd_mtxlock((sc)->lock)
56 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
57 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
58 #define hdac_lockowned(sc) mtx_owned((sc)->lock)
60 #define HDAC_QUIRK_64BIT (1 << 0)
61 #define HDAC_QUIRK_DMAPOS (1 << 1)
62 #define HDAC_QUIRK_MSI (1 << 2)
67 } hdac_quirks_tab[] = {
68 { "64bit", HDAC_QUIRK_DMAPOS },
69 { "dmapos", HDAC_QUIRK_DMAPOS },
70 { "msi", HDAC_QUIRK_MSI },
73 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller");
81 { HDA_INTEL_OAK, "Intel Oaktrail", 0, 0 },
82 { HDA_INTEL_BAY, "Intel BayTrail", 0, 0 },
83 { HDA_INTEL_HSW1, "Intel Haswell", 0, 0 },
84 { HDA_INTEL_HSW2, "Intel Haswell", 0, 0 },
85 { HDA_INTEL_HSW3, "Intel Haswell", 0, 0 },
86 { HDA_INTEL_BDW1, "Intel Broadwell", 0, 0 },
87 { HDA_INTEL_BDW2, "Intel Broadwell", 0, 0 },
88 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 },
89 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 },
90 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 },
91 { HDA_INTEL_LPT1, "Intel Lynx Point", 0, 0 },
92 { HDA_INTEL_LPT2, "Intel Lynx Point", 0, 0 },
93 { HDA_INTEL_WCPT, "Intel Wildcat Point", 0, 0 },
94 { HDA_INTEL_WELLS1, "Intel Wellsburg", 0, 0 },
95 { HDA_INTEL_WELLS2, "Intel Wellsburg", 0, 0 },
96 { HDA_INTEL_LPTLP1, "Intel Lynx Point-LP", 0, 0 },
97 { HDA_INTEL_LPTLP2, "Intel Lynx Point-LP", 0, 0 },
98 { HDA_INTEL_SRPTLP, "Intel Sunrise Point-LP", 0, 0 },
99 { HDA_INTEL_KBLKLP, "Intel Kabylake-LP", 0, 0 },
100 { HDA_INTEL_SRPT, "Intel Sunrise Point", 0, 0 },
101 { HDA_INTEL_KBLK, "Intel Kabylake", 0, 0 },
102 { HDA_INTEL_KBLKH, "Intel Kabylake-H", 0, 0 },
103 { HDA_INTEL_CFLK, "Intel Coffelake", 0, 0 },
104 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 },
105 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 },
106 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 },
107 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 },
108 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 },
109 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 },
110 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 },
111 { HDA_INTEL_PCH, "Intel Ibex Peak", 0, 0 },
112 { HDA_INTEL_PCH2, "Intel Ibex Peak", 0, 0 },
113 { HDA_INTEL_SCH, "Intel SCH", 0, 0 },
114 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI },
115 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI },
116 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 },
117 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 },
118 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 },
119 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 },
120 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 },
121 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 },
122 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 },
123 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 },
124 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT },
125 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT },
126 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT },
127 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT },
128 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 },
129 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 },
130 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 },
131 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 },
132 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 },
133 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 },
134 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 },
135 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 },
136 { HDA_NVIDIA_0BE2, "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI },
137 { HDA_NVIDIA_0BE3, "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI },
138 { HDA_NVIDIA_0BE4, "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI },
139 { HDA_NVIDIA_GT100, "NVIDIA GT100", 0, HDAC_QUIRK_MSI },
140 { HDA_NVIDIA_GT104, "NVIDIA GT104", 0, HDAC_QUIRK_MSI },
141 { HDA_NVIDIA_GT106, "NVIDIA GT106", 0, HDAC_QUIRK_MSI },
142 { HDA_NVIDIA_GT108, "NVIDIA GT108", 0, HDAC_QUIRK_MSI },
143 { HDA_NVIDIA_GT116, "NVIDIA GT116", 0, HDAC_QUIRK_MSI },
144 { HDA_NVIDIA_GF119, "NVIDIA GF119", 0, 0 },
145 { HDA_NVIDIA_GF110_1, "NVIDIA GF110", 0, HDAC_QUIRK_MSI },
146 { HDA_NVIDIA_GF110_2, "NVIDIA GF110", 0, HDAC_QUIRK_MSI },
147 { HDA_ATI_SB450, "ATI SB450", 0, 0 },
148 { HDA_ATI_SB600, "ATI SB600", 0, 0 },
149 { HDA_ATI_RS600, "ATI RS600", 0, 0 },
150 { HDA_ATI_RS690, "ATI RS690", 0, 0 },
151 { HDA_ATI_RS780, "ATI RS780", 0, 0 },
152 { HDA_ATI_R600, "ATI R600", 0, 0 },
153 { HDA_ATI_RV610, "ATI RV610", 0, 0 },
154 { HDA_ATI_RV620, "ATI RV620", 0, 0 },
155 { HDA_ATI_RV630, "ATI RV630", 0, 0 },
156 { HDA_ATI_RV635, "ATI RV635", 0, 0 },
157 { HDA_ATI_RV710, "ATI RV710", 0, 0 },
158 { HDA_ATI_RV730, "ATI RV730", 0, 0 },
159 { HDA_ATI_RV740, "ATI RV740", 0, 0 },
160 { HDA_ATI_RV770, "ATI RV770", 0, 0 },
161 { HDA_ATI_RV810, "ATI RV810", 0, 0 },
162 { HDA_ATI_RV830, "ATI RV830", 0, 0 },
163 { HDA_ATI_RV840, "ATI RV840", 0, 0 },
164 { HDA_ATI_RV870, "ATI RV870", 0, 0 },
165 { HDA_ATI_RV910, "ATI RV910", 0, 0 },
166 { HDA_ATI_RV930, "ATI RV930", 0, 0 },
167 { HDA_ATI_RV940, "ATI RV940", 0, 0 },
168 { HDA_ATI_RV970, "ATI RV970", 0, 0 },
169 { HDA_ATI_R1000, "ATI R1000", 0, 0 },
170 { HDA_AMD_HUDSON2, "AMD Hudson-2", 0, 0 },
171 { HDA_RDC_M3010, "RDC M3010", 0, 0 },
172 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 },
173 { HDA_SIS_966, "SiS 966", 0, 0 },
174 { HDA_ULI_M5461, "ULI M5461", 0, 0 },
176 { HDA_INTEL_ALL, "Intel", 0, 0 },
177 { HDA_NVIDIA_ALL, "NVIDIA", 0, 0 },
178 { HDA_ATI_ALL, "ATI", 0, 0 },
179 { HDA_AMD_ALL, "AMD", 0, 0 },
180 { HDA_CREATIVE_ALL, "Creative", 0, 0 },
181 { HDA_VIA_ALL, "VIA", 0, 0 },
182 { HDA_SIS_ALL, "SiS", 0, 0 },
183 { HDA_ULI_ALL, "ULI", 0, 0 },
186 static const struct {
191 } hdac_pcie_snoop[] = {
192 { INTEL_VENDORID, 0x00, 0x00, 0x00 },
193 { ATI_VENDORID, 0x42, 0xf8, 0x02 },
194 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
197 /****************************************************************************
198 * Function prototypes
199 ****************************************************************************/
200 static void hdac_intr_handler(void *);
201 static int hdac_reset(struct hdac_softc *, int);
202 static int hdac_get_capabilities(struct hdac_softc *);
203 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
204 static int hdac_dma_alloc(struct hdac_softc *,
205 struct hdac_dma *, bus_size_t);
206 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
207 static int hdac_mem_alloc(struct hdac_softc *);
208 static void hdac_mem_free(struct hdac_softc *);
209 static int hdac_irq_alloc(struct hdac_softc *);
210 static void hdac_irq_free(struct hdac_softc *);
211 static void hdac_corb_init(struct hdac_softc *);
212 static void hdac_rirb_init(struct hdac_softc *);
213 static void hdac_corb_start(struct hdac_softc *);
214 static void hdac_rirb_start(struct hdac_softc *);
216 static void hdac_attach2(void *);
218 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t);
220 static int hdac_probe(device_t);
221 static int hdac_attach(device_t);
222 static int hdac_detach(device_t);
223 static int hdac_suspend(device_t);
224 static int hdac_resume(device_t);
226 static int hdac_rirb_flush(struct hdac_softc *sc);
227 static int hdac_unsolq_flush(struct hdac_softc *sc);
229 #define hdac_command(a1, a2, a3) \
230 hdac_send_command(a1, a3, a2)
232 /* This function surely going to make its way into upper level someday. */
234 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
236 const char *res = NULL;
237 int i = 0, j, k, len, inv;
239 if (resource_string_value(device_get_name(sc->dev),
240 device_get_unit(sc->dev), "config", &res) != 0)
242 if (!(res != NULL && strlen(res) > 0))
245 device_printf(sc->dev, "Config options:");
248 while (res[i] != '\0' &&
249 (res[i] == ',' || isspace(res[i]) != 0))
251 if (res[i] == '\0') {
258 while (res[j] != '\0' &&
259 !(res[j] == ',' || isspace(res[j]) != 0))
262 if (len > 2 && strncmp(res + i, "no", 2) == 0)
266 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) {
267 if (strncmp(res + i + inv,
268 hdac_quirks_tab[k].key, len - inv) != 0)
270 if (len - inv != strlen(hdac_quirks_tab[k].key))
273 printf(" %s%s", (inv != 0) ? "no" : "",
274 hdac_quirks_tab[k].key);
277 *on |= hdac_quirks_tab[k].value;
278 *on &= ~hdac_quirks_tab[k].value;
279 } else if (inv != 0) {
280 *off |= hdac_quirks_tab[k].value;
281 *off &= ~hdac_quirks_tab[k].value;
289 /****************************************************************************
290 * void hdac_intr_handler(void *)
292 * Interrupt handler. Processes interrupts received from the hdac.
293 ****************************************************************************/
295 hdac_intr_handler(void *context)
297 struct hdac_softc *sc;
303 sc = (struct hdac_softc *)context;
306 /* Do we have anything to do? */
307 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
308 if ((intsts & HDAC_INTSTS_GIS) == 0) {
313 /* Was this a controller interrupt? */
314 if (intsts & HDAC_INTSTS_CIS) {
315 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
316 /* Get as many responses that we can */
317 while (rirbsts & HDAC_RIRBSTS_RINTFL) {
318 HDAC_WRITE_1(&sc->mem,
319 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
321 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
323 if (sc->unsolq_rp != sc->unsolq_wp)
324 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
327 if (intsts & HDAC_INTSTS_SIS_MASK) {
328 for (i = 0; i < sc->num_ss; i++) {
329 if ((intsts & (1 << i)) == 0)
331 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS,
332 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
333 if ((dev = sc->streams[i].dev) != NULL) {
334 HDAC_STREAM_INTR(dev,
335 sc->streams[i].dir, sc->streams[i].stream);
340 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts);
345 hdac_poll_callback(void *arg)
347 struct hdac_softc *sc = arg;
353 if (sc->polling == 0) {
357 callout_reset(&sc->poll_callout, sc->poll_ival,
358 hdac_poll_callback, sc);
361 hdac_intr_handler(sc);
364 /****************************************************************************
365 * int hdac_reset(hdac_softc *, int)
367 * Reset the hdac to a quiescent and known state.
368 ****************************************************************************/
370 hdac_reset(struct hdac_softc *sc, int wakeup)
376 * Stop all Streams DMA engine
378 for (i = 0; i < sc->num_iss; i++)
379 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
380 for (i = 0; i < sc->num_oss; i++)
381 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
382 for (i = 0; i < sc->num_bss; i++)
383 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
386 * Stop Control DMA engines.
388 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
389 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
392 * Reset DMA position buffer.
394 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
395 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
398 * Reset the controller. The reset must remain asserted for
399 * a minimum of 100us.
401 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
402 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
405 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
406 if (!(gctl & HDAC_GCTL_CRST))
410 if (gctl & HDAC_GCTL_CRST) {
411 device_printf(sc->dev, "Unable to put hdac in reset\n");
415 /* If wakeup is not requested - leave the controller in reset state. */
420 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
421 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
424 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
425 if (gctl & HDAC_GCTL_CRST)
429 if (!(gctl & HDAC_GCTL_CRST)) {
430 device_printf(sc->dev, "Device stuck in reset\n");
435 * Wait for codecs to finish their own reset sequence. The delay here
436 * should be of 250us but for some reasons, it's not enough on my
437 * computer. Let's use twice as much as necessary to make sure that
438 * it's reset properly.
446 /****************************************************************************
447 * int hdac_get_capabilities(struct hdac_softc *);
449 * Retreive the general capabilities of the hdac;
450 * Number of Input Streams
451 * Number of Output Streams
452 * Number of bidirectional Streams
454 * CORB and RIRB sizes
455 ****************************************************************************/
457 hdac_get_capabilities(struct hdac_softc *sc)
460 uint8_t corbsize, rirbsize;
462 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
463 sc->num_iss = HDAC_GCAP_ISS(gcap);
464 sc->num_oss = HDAC_GCAP_OSS(gcap);
465 sc->num_bss = HDAC_GCAP_BSS(gcap);
466 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss;
467 sc->num_sdo = HDAC_GCAP_NSDO(gcap);
468 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0;
469 if (sc->quirks_on & HDAC_QUIRK_64BIT)
470 sc->support_64bit = 1;
471 else if (sc->quirks_off & HDAC_QUIRK_64BIT)
472 sc->support_64bit = 0;
474 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
475 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
476 HDAC_CORBSIZE_CORBSZCAP_256)
478 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
479 HDAC_CORBSIZE_CORBSZCAP_16)
481 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
482 HDAC_CORBSIZE_CORBSZCAP_2)
485 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
490 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
491 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
492 HDAC_RIRBSIZE_RIRBSZCAP_256)
494 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
495 HDAC_RIRBSIZE_RIRBSZCAP_16)
497 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
498 HDAC_RIRBSIZE_RIRBSZCAP_2)
501 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
507 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, "
508 "NSDO %d%s, CORB %d, RIRB %d\n",
509 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo,
510 sc->support_64bit ? ", 64bit" : "",
511 sc->corb_size, sc->rirb_size);
518 /****************************************************************************
521 * This function is called by bus_dmamap_load when the mapping has been
522 * established. We just record the physical address of the mapping into
523 * the struct hdac_dma passed in.
524 ****************************************************************************/
526 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
528 struct hdac_dma *dma;
531 dma = (struct hdac_dma *)callback_arg;
532 dma->dma_paddr = segs[0].ds_addr;
537 /****************************************************************************
540 * This function allocate and setup a dma region (struct hdac_dma).
541 * It must be freed by a corresponding hdac_dma_free.
542 ****************************************************************************/
544 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
549 roundsz = roundup2(size, HDA_DMA_ALIGNMENT);
550 bzero(dma, sizeof(*dma));
555 result = bus_dma_tag_create(
556 bus_get_dma_tag(sc->dev), /* parent */
557 HDA_DMA_ALIGNMENT, /* alignment */
559 (sc->support_64bit) ? BUS_SPACE_MAXADDR :
560 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
561 BUS_SPACE_MAXADDR, /* highaddr */
563 NULL, /* fistfuncarg */
564 roundsz, /* maxsize */
566 roundsz, /* maxsegsz */
569 NULL, /* lockfuncarg */
570 &dma->dma_tag); /* dmat */
572 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
574 goto hdac_dma_alloc_fail;
578 * Allocate DMA memory
580 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
581 BUS_DMA_NOWAIT | BUS_DMA_ZERO |
582 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
585 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
587 goto hdac_dma_alloc_fail;
590 dma->dma_size = roundsz;
595 result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
596 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
597 if (result != 0 || dma->dma_paddr == 0) {
600 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
602 goto hdac_dma_alloc_fail;
606 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
607 __func__, (uintmax_t)size, (uintmax_t)roundsz);
613 hdac_dma_free(sc, dma);
619 /****************************************************************************
620 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
622 * Free a struct dhac_dma that has been previously allocated via the
623 * hdac_dma_alloc function.
624 ****************************************************************************/
626 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
628 if (dma->dma_paddr != 0) {
631 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
632 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
634 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
637 if (dma->dma_vaddr != NULL) {
638 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
639 dma->dma_vaddr = NULL;
641 if (dma->dma_tag != NULL) {
642 bus_dma_tag_destroy(dma->dma_tag);
648 /****************************************************************************
649 * int hdac_mem_alloc(struct hdac_softc *)
651 * Allocate all the bus resources necessary to speak with the physical
653 ****************************************************************************/
655 hdac_mem_alloc(struct hdac_softc *sc)
657 struct hdac_mem *mem;
660 mem->mem_rid = PCIR_BAR(0);
661 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
662 &mem->mem_rid, RF_ACTIVE);
663 if (mem->mem_res == NULL) {
664 device_printf(sc->dev,
665 "%s: Unable to allocate memory resource\n", __func__);
668 mem->mem_tag = rman_get_bustag(mem->mem_res);
669 mem->mem_handle = rman_get_bushandle(mem->mem_res);
674 /****************************************************************************
675 * void hdac_mem_free(struct hdac_softc *)
677 * Free up resources previously allocated by hdac_mem_alloc.
678 ****************************************************************************/
680 hdac_mem_free(struct hdac_softc *sc)
682 struct hdac_mem *mem;
685 if (mem->mem_res != NULL)
686 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
691 /****************************************************************************
692 * int hdac_irq_alloc(struct hdac_softc *)
694 * Allocate and setup the resources necessary for interrupt handling.
695 ****************************************************************************/
697 hdac_irq_alloc(struct hdac_softc *sc)
699 struct hdac_irq *irq;
705 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 &&
706 (result = pci_msi_count(sc->dev)) == 1 &&
707 pci_alloc_msi(sc->dev, &result) == 0)
710 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
711 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
712 if (irq->irq_res == NULL) {
713 device_printf(sc->dev, "%s: Unable to allocate irq\n",
715 goto hdac_irq_alloc_fail;
717 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV,
718 NULL, hdac_intr_handler, sc, &irq->irq_handle);
720 device_printf(sc->dev,
721 "%s: Unable to setup interrupt handler (%x)\n",
723 goto hdac_irq_alloc_fail;
734 /****************************************************************************
735 * void hdac_irq_free(struct hdac_softc *)
737 * Free up resources previously allocated by hdac_irq_alloc.
738 ****************************************************************************/
740 hdac_irq_free(struct hdac_softc *sc)
742 struct hdac_irq *irq;
745 if (irq->irq_res != NULL && irq->irq_handle != NULL)
746 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
747 if (irq->irq_res != NULL)
748 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
750 if (irq->irq_rid == 0x1)
751 pci_release_msi(sc->dev);
752 irq->irq_handle = NULL;
757 /****************************************************************************
758 * void hdac_corb_init(struct hdac_softc *)
760 * Initialize the corb registers for operations but do not start it up yet.
761 * The CORB engine must not be running when this function is called.
762 ****************************************************************************/
764 hdac_corb_init(struct hdac_softc *sc)
769 /* Setup the CORB size. */
770 switch (sc->corb_size) {
772 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
775 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
778 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
781 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
783 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
785 /* Setup the CORB Address in the hdac */
786 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
787 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
788 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
790 /* Set the WP and RP */
792 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
793 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
795 * The HDA specification indicates that the CORBRPRST bit will always
796 * read as zero. Unfortunately, it seems that at least the 82801G
797 * doesn't reset the bit to zero, which stalls the corb engine.
798 * manually reset the bit to zero before continuing.
800 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
802 /* Enable CORB error reporting */
804 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
808 /****************************************************************************
809 * void hdac_rirb_init(struct hdac_softc *)
811 * Initialize the rirb registers for operations but do not start it up yet.
812 * The RIRB engine must not be running when this function is called.
813 ****************************************************************************/
815 hdac_rirb_init(struct hdac_softc *sc)
820 /* Setup the RIRB size. */
821 switch (sc->rirb_size) {
823 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
826 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
829 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
832 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
834 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
836 /* Setup the RIRB Address in the hdac */
837 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
838 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
839 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
841 /* Setup the WP and RP */
843 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
845 /* Setup the interrupt threshold */
846 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
848 /* Enable Overrun and response received reporting */
850 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
851 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
853 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
858 * Make sure that the Host CPU cache doesn't contain any dirty
859 * cache lines that falls in the rirb. If I understood correctly, it
860 * should be sufficient to do this only once as the rirb is purely
861 * read-only from now on.
863 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
864 BUS_DMASYNC_PREREAD);
868 /****************************************************************************
869 * void hdac_corb_start(hdac_softc *)
871 * Startup the corb DMA engine
872 ****************************************************************************/
874 hdac_corb_start(struct hdac_softc *sc)
878 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
879 corbctl |= HDAC_CORBCTL_CORBRUN;
880 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
883 /****************************************************************************
884 * void hdac_rirb_start(hdac_softc *)
886 * Startup the rirb DMA engine
887 ****************************************************************************/
889 hdac_rirb_start(struct hdac_softc *sc)
893 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
894 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
895 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
899 hdac_rirb_flush(struct hdac_softc *sc)
901 struct hdac_rirb *rirb_base, *rirb;
907 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
908 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
910 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
911 BUS_DMASYNC_POSTREAD);
915 while (sc->rirb_rp != rirbwp) {
917 sc->rirb_rp %= sc->rirb_size;
918 rirb = &rirb_base[sc->rirb_rp];
919 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
920 resp = rirb->response;
921 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
922 sc->unsolq[sc->unsolq_wp++] = resp;
923 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
924 sc->unsolq[sc->unsolq_wp++] = cad;
925 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
926 } else if (sc->codecs[cad].pending <= 0) {
927 device_printf(sc->dev, "Unexpected unsolicited "
928 "response from address %d: %08x\n", cad, resp);
930 sc->codecs[cad].response = resp;
931 sc->codecs[cad].pending--;
939 hdac_unsolq_flush(struct hdac_softc *sc)
946 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
947 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
948 while (sc->unsolq_rp != sc->unsolq_wp) {
949 resp = sc->unsolq[sc->unsolq_rp++];
950 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
951 cad = sc->unsolq[sc->unsolq_rp++];
952 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
953 if ((child = sc->codecs[cad].dev) != NULL)
954 HDAC_UNSOL_INTR(child, resp);
957 sc->unsolq_st = HDAC_UNSOLQ_READY;
963 /****************************************************************************
964 * uint32_t hdac_command_sendone_internal
966 * Wrapper function that sends only one command to a given codec
967 ****************************************************************************/
969 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb)
974 if (!hdac_lockowned(sc))
975 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
976 verb &= ~HDA_CMD_CAD_MASK;
977 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT;
978 sc->codecs[cad].response = HDA_INVALID;
980 sc->codecs[cad].pending++;
982 sc->corb_wp %= sc->corb_size;
983 corb = (uint32_t *)sc->corb_dma.dma_vaddr;
985 bus_dmamap_sync(sc->corb_dma.dma_tag,
986 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
988 corb[sc->corb_wp] = verb;
990 bus_dmamap_sync(sc->corb_dma.dma_tag,
991 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
993 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
997 if (hdac_rirb_flush(sc) == 0)
999 } while (sc->codecs[cad].pending != 0 && --timeout);
1001 if (sc->codecs[cad].pending != 0) {
1002 device_printf(sc->dev, "Command timeout on address %d\n", cad);
1003 sc->codecs[cad].pending = 0;
1006 if (sc->unsolq_rp != sc->unsolq_wp)
1007 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
1008 return (sc->codecs[cad].response);
1011 /****************************************************************************
1013 ****************************************************************************/
1015 /****************************************************************************
1016 * int hdac_probe(device_t)
1018 * Probe for the presence of an hdac. If none is found, check for a generic
1019 * match using the subclass of the device.
1020 ****************************************************************************/
1022 hdac_probe(device_t dev)
1026 uint16_t class, subclass;
1029 model = (uint32_t)pci_get_device(dev) << 16;
1030 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1031 class = pci_get_class(dev);
1032 subclass = pci_get_subclass(dev);
1034 bzero(desc, sizeof(desc));
1036 for (i = 0; i < nitems(hdac_devices); i++) {
1037 if (hdac_devices[i].model == model) {
1038 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
1039 result = BUS_PROBE_DEFAULT;
1042 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1043 class == PCIC_MULTIMEDIA &&
1044 subclass == PCIS_MULTIMEDIA_HDA) {
1045 snprintf(desc, sizeof(desc),
1047 hdac_devices[i].desc, pci_get_device(dev));
1048 result = BUS_PROBE_GENERIC;
1052 if (result == ENXIO && class == PCIC_MULTIMEDIA &&
1053 subclass == PCIS_MULTIMEDIA_HDA) {
1054 snprintf(desc, sizeof(desc), "Generic (0x%08x)", model);
1055 result = BUS_PROBE_GENERIC;
1057 if (result != ENXIO) {
1058 strlcat(desc, " HDA Controller", sizeof(desc));
1059 device_set_desc_copy(dev, desc);
1066 hdac_unsolq_task(void *context, int pending)
1068 struct hdac_softc *sc;
1070 sc = (struct hdac_softc *)context;
1073 hdac_unsolq_flush(sc);
1077 /****************************************************************************
1078 * int hdac_attach(device_t)
1080 * Attach the device into the kernel. Interrupts usually won't be enabled
1081 * when this function is called. Setup everything that doesn't require
1082 * interrupts and defer probing of codecs until interrupts are enabled.
1083 ****************************************************************************/
1085 hdac_attach(device_t dev)
1087 struct hdac_softc *sc;
1091 uint16_t class, subclass;
1095 sc = device_get_softc(dev);
1097 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n",
1098 pci_get_subvendor(dev), pci_get_subdevice(dev));
1099 device_printf(dev, "HDA Driver Revision: %s\n",
1103 model = (uint32_t)pci_get_device(dev) << 16;
1104 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1105 class = pci_get_class(dev);
1106 subclass = pci_get_subclass(dev);
1108 for (i = 0; i < nitems(hdac_devices); i++) {
1109 if (hdac_devices[i].model == model) {
1113 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1114 class == PCIC_MULTIMEDIA &&
1115 subclass == PCIS_MULTIMEDIA_HDA) {
1121 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex");
1123 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
1124 callout_init(&sc->poll_callout, 1);
1125 for (i = 0; i < HDAC_CODEC_MAX; i++)
1126 sc->codecs[i].dev = NULL;
1128 sc->quirks_on = hdac_devices[devid].quirks_on;
1129 sc->quirks_off = hdac_devices[devid].quirks_off;
1134 if (resource_int_value(device_get_name(dev),
1135 device_get_unit(dev), "msi", &i) == 0) {
1137 sc->quirks_off |= HDAC_QUIRK_MSI;
1139 sc->quirks_on |= HDAC_QUIRK_MSI;
1140 sc->quirks_off |= ~HDAC_QUIRK_MSI;
1143 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off);
1145 device_printf(sc->dev,
1146 "Config options: on=0x%08x off=0x%08x\n",
1147 sc->quirks_on, sc->quirks_off);
1150 if (resource_int_value(device_get_name(dev),
1151 device_get_unit(dev), "polling", &i) == 0 && i != 0)
1156 pci_enable_busmaster(dev);
1158 vendor = pci_get_vendor(dev);
1159 if (vendor == INTEL_VENDORID) {
1161 v = pci_read_config(dev, 0x44, 1);
1162 pci_write_config(dev, 0x44, v & 0xf8, 1);
1164 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
1165 pci_read_config(dev, 0x44, 1));
1169 #if defined(__i386__) || defined(__amd64__)
1170 sc->flags |= HDAC_F_DMA_NOCACHE;
1172 if (resource_int_value(device_get_name(dev),
1173 device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
1175 sc->flags &= ~HDAC_F_DMA_NOCACHE;
1178 * Try to enable PCIe snoop to avoid messing around with
1179 * uncacheable DMA attribute. Since PCIe snoop register
1180 * config is pretty much vendor specific, there are no
1181 * general solutions on how to enable it, forcing us (even
1182 * Microsoft) to enable uncacheable or write combined DMA
1185 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
1187 for (i = 0; i < nitems(hdac_pcie_snoop); i++) {
1188 if (hdac_pcie_snoop[i].vendor != vendor)
1190 sc->flags &= ~HDAC_F_DMA_NOCACHE;
1191 if (hdac_pcie_snoop[i].reg == 0x00)
1193 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
1194 if ((v & hdac_pcie_snoop[i].enable) ==
1195 hdac_pcie_snoop[i].enable)
1197 v &= hdac_pcie_snoop[i].mask;
1198 v |= hdac_pcie_snoop[i].enable;
1199 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
1200 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
1201 if ((v & hdac_pcie_snoop[i].enable) !=
1202 hdac_pcie_snoop[i].enable) {
1205 "WARNING: Failed to enable PCIe "
1208 #if defined(__i386__) || defined(__amd64__)
1209 sc->flags |= HDAC_F_DMA_NOCACHE;
1214 #if defined(__i386__) || defined(__amd64__)
1219 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
1220 (sc->flags & HDAC_F_DMA_NOCACHE) ?
1221 "Uncacheable" : "PCIe snoop", vendor);
1224 /* Allocate resources */
1225 result = hdac_mem_alloc(sc);
1227 goto hdac_attach_fail;
1228 result = hdac_irq_alloc(sc);
1230 goto hdac_attach_fail;
1232 /* Get Capabilities */
1233 result = hdac_get_capabilities(sc);
1235 goto hdac_attach_fail;
1237 /* Allocate CORB, RIRB, POS and BDLs dma memory */
1238 result = hdac_dma_alloc(sc, &sc->corb_dma,
1239 sc->corb_size * sizeof(uint32_t));
1241 goto hdac_attach_fail;
1242 result = hdac_dma_alloc(sc, &sc->rirb_dma,
1243 sc->rirb_size * sizeof(struct hdac_rirb));
1245 goto hdac_attach_fail;
1246 sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss,
1247 M_HDAC, M_ZERO | M_WAITOK);
1248 for (i = 0; i < sc->num_ss; i++) {
1249 result = hdac_dma_alloc(sc, &sc->streams[i].bdl,
1250 sizeof(struct hdac_bdle) * HDA_BDL_MAX);
1252 goto hdac_attach_fail;
1254 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) {
1255 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) {
1257 device_printf(dev, "Failed to "
1258 "allocate DMA pos buffer "
1262 uint64_t addr = sc->pos_dma.dma_paddr;
1264 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32);
1265 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
1266 (addr & HDAC_DPLBASE_DPLBASE_MASK) |
1267 HDAC_DPLBASE_DPLBASE_DMAPBE);
1271 result = bus_dma_tag_create(
1272 bus_get_dma_tag(sc->dev), /* parent */
1273 HDA_DMA_ALIGNMENT, /* alignment */
1275 (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1276 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1277 BUS_SPACE_MAXADDR, /* highaddr */
1278 NULL, /* filtfunc */
1279 NULL, /* fistfuncarg */
1280 HDA_BUFSZ_MAX, /* maxsize */
1282 HDA_BUFSZ_MAX, /* maxsegsz */
1284 NULL, /* lockfunc */
1285 NULL, /* lockfuncarg */
1286 &sc->chan_dmat); /* dmat */
1288 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
1290 goto hdac_attach_fail;
1293 /* Quiesce everything */
1295 device_printf(dev, "Reset controller...\n");
1299 /* Initialize the CORB and RIRB */
1303 /* Defer remaining of initialization until interrupts are enabled */
1304 sc->intrhook.ich_func = hdac_attach2;
1305 sc->intrhook.ich_arg = (void *)sc;
1306 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
1307 sc->intrhook.ich_func = NULL;
1308 hdac_attach2((void *)sc);
1315 for (i = 0; i < sc->num_ss; i++)
1316 hdac_dma_free(sc, &sc->streams[i].bdl);
1317 free(sc->streams, M_HDAC);
1318 hdac_dma_free(sc, &sc->rirb_dma);
1319 hdac_dma_free(sc, &sc->corb_dma);
1321 snd_mtxfree(sc->lock);
1327 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
1329 struct hdac_softc *sc;
1332 int devcount, i, err, val;
1334 dev = oidp->oid_arg1;
1335 sc = device_get_softc(dev);
1339 err = sysctl_handle_int(oidp, &val, 0, req);
1340 if (err != 0 || req->newptr == NULL || val == 0)
1343 /* XXX: Temporary. For debugging. */
1347 } else if (val == 101) {
1352 if ((err = device_get_children(dev, &devlist, &devcount)) != 0)
1355 for (i = 0; i < devcount; i++)
1356 HDAC_PINDUMP(devlist[i]);
1358 free(devlist, M_TEMP);
1363 hdac_mdata_rate(uint16_t fmt)
1365 static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 };
1368 if (fmt & (1 << 14))
1372 rate *= ((fmt >> 11) & 0x07) + 1;
1373 rate /= ((fmt >> 8) & 0x07) + 1;
1374 bits = mbits[(fmt >> 4) & 0x03];
1375 bits *= (fmt & 0x0f) + 1;
1376 return (rate * bits);
1380 hdac_bdata_rate(uint16_t fmt, int output)
1382 static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 };
1386 rate *= ((fmt >> 11) & 0x07) + 1;
1387 bits = bbits[(fmt >> 4) & 0x03];
1388 bits *= (fmt & 0x0f) + 1;
1390 bits = ((bits + 7) & ~0x07) + 10;
1391 return (rate * bits);
1395 hdac_poll_reinit(struct hdac_softc *sc)
1397 int i, pollticks, min = 1000000;
1398 struct hdac_stream *s;
1400 if (sc->polling == 0)
1402 if (sc->unsol_registered > 0)
1404 for (i = 0; i < sc->num_ss; i++) {
1405 s = &sc->streams[i];
1406 if (s->running == 0)
1408 pollticks = ((uint64_t)hz * s->blksz) /
1409 (hdac_mdata_rate(s->format) / 8);
1413 if (pollticks < 1) {
1415 device_printf(sc->dev,
1416 "poll interval < 1 tick !\n");
1420 if (min > pollticks)
1424 device_printf(sc->dev,
1425 "poll interval %d -> %d ticks\n",
1426 sc->poll_ival, min);
1428 sc->poll_ival = min;
1430 callout_stop(&sc->poll_callout);
1432 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc);
1436 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
1438 struct hdac_softc *sc;
1443 dev = oidp->oid_arg1;
1444 sc = device_get_softc(dev);
1450 err = sysctl_handle_int(oidp, &val, 0, req);
1452 if (err != 0 || req->newptr == NULL)
1454 if (val < 0 || val > 1)
1458 if (val != sc->polling) {
1460 callout_stop(&sc->poll_callout);
1462 callout_drain(&sc->poll_callout);
1465 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1466 ctl |= HDAC_INTCTL_GIE;
1467 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1469 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1470 ctl &= ~HDAC_INTCTL_GIE;
1471 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1473 hdac_poll_reinit(sc);
1482 hdac_attach2(void *arg)
1484 struct hdac_softc *sc;
1486 uint32_t vendorid, revisionid;
1490 sc = (struct hdac_softc *)arg;
1494 /* Remove ourselves from the config hooks */
1495 if (sc->intrhook.ich_func != NULL) {
1496 config_intrhook_disestablish(&sc->intrhook);
1497 sc->intrhook.ich_func = NULL;
1501 device_printf(sc->dev, "Starting CORB Engine...\n");
1503 hdac_corb_start(sc);
1505 device_printf(sc->dev, "Starting RIRB Engine...\n");
1507 hdac_rirb_start(sc);
1509 device_printf(sc->dev,
1510 "Enabling controller interrupt...\n");
1512 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1514 if (sc->polling == 0) {
1515 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
1516 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1521 device_printf(sc->dev, "Scanning HDA codecs ...\n");
1523 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1525 for (i = 0; i < HDAC_CODEC_MAX; i++) {
1526 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1528 device_printf(sc->dev,
1529 "Found CODEC at address %d\n", i);
1532 vendorid = hdac_send_command(sc, i,
1533 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID));
1534 revisionid = hdac_send_command(sc, i,
1535 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID));
1537 if (vendorid == HDA_INVALID &&
1538 revisionid == HDA_INVALID) {
1539 device_printf(sc->dev,
1540 "CODEC is not responding!\n");
1543 sc->codecs[i].vendor_id =
1544 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1545 sc->codecs[i].device_id =
1546 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1547 sc->codecs[i].revision_id =
1548 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1549 sc->codecs[i].stepping_id =
1550 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1551 child = device_add_child(sc->dev, "hdacc", -1);
1552 if (child == NULL) {
1553 device_printf(sc->dev,
1554 "Failed to add CODEC device\n");
1557 device_set_ivars(child, (void *)(intptr_t)i);
1558 sc->codecs[i].dev = child;
1561 bus_generic_attach(sc->dev);
1563 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1564 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1565 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1566 sysctl_hdac_pindump, "I", "Dump pin states/data");
1567 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1568 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1569 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1570 sysctl_hdac_polling, "I", "Enable polling mode");
1573 /****************************************************************************
1574 * int hdac_suspend(device_t)
1576 * Suspend and power down HDA bus and codecs.
1577 ****************************************************************************/
1579 hdac_suspend(device_t dev)
1581 struct hdac_softc *sc = device_get_softc(dev);
1584 device_printf(dev, "Suspend...\n");
1586 bus_generic_suspend(dev);
1590 device_printf(dev, "Reset controller...\n");
1592 callout_stop(&sc->poll_callout);
1595 callout_drain(&sc->poll_callout);
1596 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1598 device_printf(dev, "Suspend done\n");
1603 /****************************************************************************
1604 * int hdac_resume(device_t)
1606 * Powerup and restore HDA bus and codecs state.
1607 ****************************************************************************/
1609 hdac_resume(device_t dev)
1611 struct hdac_softc *sc = device_get_softc(dev);
1615 device_printf(dev, "Resume...\n");
1619 /* Quiesce everything */
1621 device_printf(dev, "Reset controller...\n");
1625 /* Initialize the CORB and RIRB */
1630 device_printf(dev, "Starting CORB Engine...\n");
1632 hdac_corb_start(sc);
1634 device_printf(dev, "Starting RIRB Engine...\n");
1636 hdac_rirb_start(sc);
1638 device_printf(dev, "Enabling controller interrupt...\n");
1640 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1642 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1644 hdac_poll_reinit(sc);
1647 error = bus_generic_resume(dev);
1649 device_printf(dev, "Resume done\n");
1654 /****************************************************************************
1655 * int hdac_detach(device_t)
1657 * Detach and free up resources utilized by the hdac device.
1658 ****************************************************************************/
1660 hdac_detach(device_t dev)
1662 struct hdac_softc *sc = device_get_softc(dev);
1664 int cad, i, devcount, error;
1666 if ((error = device_get_children(dev, &devlist, &devcount)) != 0)
1668 for (i = 0; i < devcount; i++) {
1669 cad = (intptr_t)device_get_ivars(devlist[i]);
1670 if ((error = device_delete_child(dev, devlist[i])) != 0) {
1671 free(devlist, M_TEMP);
1674 sc->codecs[cad].dev = NULL;
1676 free(devlist, M_TEMP);
1681 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1684 for (i = 0; i < sc->num_ss; i++)
1685 hdac_dma_free(sc, &sc->streams[i].bdl);
1686 free(sc->streams, M_HDAC);
1687 hdac_dma_free(sc, &sc->pos_dma);
1688 hdac_dma_free(sc, &sc->rirb_dma);
1689 hdac_dma_free(sc, &sc->corb_dma);
1690 if (sc->chan_dmat != NULL) {
1691 bus_dma_tag_destroy(sc->chan_dmat);
1692 sc->chan_dmat = NULL;
1695 snd_mtxfree(sc->lock);
1699 static bus_dma_tag_t
1700 hdac_get_dma_tag(device_t dev, device_t child)
1702 struct hdac_softc *sc = device_get_softc(dev);
1704 return (sc->chan_dmat);
1708 hdac_print_child(device_t dev, device_t child)
1712 retval = bus_print_child_header(dev, child);
1713 retval += printf(" at cad %d",
1714 (int)(intptr_t)device_get_ivars(child));
1715 retval += bus_print_child_footer(dev, child);
1721 hdac_child_location_str(device_t dev, device_t child, char *buf,
1725 snprintf(buf, buflen, "cad=%d",
1726 (int)(intptr_t)device_get_ivars(child));
1731 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
1734 struct hdac_softc *sc = device_get_softc(dev);
1735 nid_t cad = (uintptr_t)device_get_ivars(child);
1737 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x "
1739 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id,
1740 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id);
1745 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1747 struct hdac_softc *sc = device_get_softc(dev);
1748 nid_t cad = (uintptr_t)device_get_ivars(child);
1751 case HDA_IVAR_CODEC_ID:
1754 case HDA_IVAR_VENDOR_ID:
1755 *result = sc->codecs[cad].vendor_id;
1757 case HDA_IVAR_DEVICE_ID:
1758 *result = sc->codecs[cad].device_id;
1760 case HDA_IVAR_REVISION_ID:
1761 *result = sc->codecs[cad].revision_id;
1763 case HDA_IVAR_STEPPING_ID:
1764 *result = sc->codecs[cad].stepping_id;
1766 case HDA_IVAR_SUBVENDOR_ID:
1767 *result = pci_get_subvendor(dev);
1769 case HDA_IVAR_SUBDEVICE_ID:
1770 *result = pci_get_subdevice(dev);
1772 case HDA_IVAR_DMA_NOCACHE:
1773 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0;
1775 case HDA_IVAR_STRIPES_MASK:
1776 *result = (1 << (1 << sc->num_sdo)) - 1;
1785 hdac_get_mtx(device_t dev, device_t child)
1787 struct hdac_softc *sc = device_get_softc(dev);
1793 hdac_codec_command(device_t dev, device_t child, uint32_t verb)
1796 return (hdac_send_command(device_get_softc(dev),
1797 (intptr_t)device_get_ivars(child), verb));
1801 hdac_find_stream(struct hdac_softc *sc, int dir, int stream)
1806 /* Allocate ISS/OSS first. */
1808 for (i = 0; i < sc->num_iss; i++) {
1809 if (sc->streams[i].stream == stream) {
1815 for (i = 0; i < sc->num_oss; i++) {
1816 if (sc->streams[i + sc->num_iss].stream == stream) {
1817 ss = i + sc->num_iss;
1822 /* Fallback to BSS. */
1824 for (i = 0; i < sc->num_bss; i++) {
1825 if (sc->streams[i + sc->num_iss + sc->num_oss].stream
1827 ss = i + sc->num_iss + sc->num_oss;
1836 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe,
1839 struct hdac_softc *sc = device_get_softc(dev);
1840 nid_t cad = (uintptr_t)device_get_ivars(child);
1841 int stream, ss, bw, maxbw, prevbw;
1843 /* Look for empty stream. */
1844 ss = hdac_find_stream(sc, dir, 0);
1846 /* Return if found nothing. */
1850 /* Check bus bandwidth. */
1851 bw = hdac_bdata_rate(format, dir);
1853 bw *= 1 << (sc->num_sdo - stripe);
1854 prevbw = sc->sdo_bw_used;
1855 maxbw = 48000 * 960 * (1 << sc->num_sdo);
1857 prevbw = sc->codecs[cad].sdi_bw_used;
1858 maxbw = 48000 * 464;
1861 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n",
1862 (bw + prevbw) / 1000, maxbw / 1000,
1863 bw + prevbw > maxbw ? " -- OVERFLOW!" : "");
1865 if (bw + prevbw > maxbw)
1868 sc->sdo_bw_used += bw;
1870 sc->codecs[cad].sdi_bw_used += bw;
1872 /* Allocate stream number */
1873 if (ss >= sc->num_iss + sc->num_oss)
1874 stream = 15 - (ss - sc->num_iss - sc->num_oss);
1875 else if (ss >= sc->num_iss)
1876 stream = ss - sc->num_iss + 1;
1880 sc->streams[ss].dev = child;
1881 sc->streams[ss].dir = dir;
1882 sc->streams[ss].stream = stream;
1883 sc->streams[ss].bw = bw;
1884 sc->streams[ss].format = format;
1885 sc->streams[ss].stripe = stripe;
1886 if (dmapos != NULL) {
1887 if (sc->pos_dma.dma_vaddr != NULL)
1888 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8);
1896 hdac_stream_free(device_t dev, device_t child, int dir, int stream)
1898 struct hdac_softc *sc = device_get_softc(dev);
1899 nid_t cad = (uintptr_t)device_get_ivars(child);
1902 ss = hdac_find_stream(sc, dir, stream);
1904 ("Free for not allocated stream (%d/%d)\n", dir, stream));
1906 sc->sdo_bw_used -= sc->streams[ss].bw;
1908 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw;
1909 sc->streams[ss].stream = 0;
1910 sc->streams[ss].dev = NULL;
1914 hdac_stream_start(device_t dev, device_t child,
1915 int dir, int stream, bus_addr_t buf, int blksz, int blkcnt)
1917 struct hdac_softc *sc = device_get_softc(dev);
1918 struct hdac_bdle *bdle;
1923 ss = hdac_find_stream(sc, dir, stream);
1925 ("Start for not allocated stream (%d/%d)\n", dir, stream));
1927 addr = (uint64_t)buf;
1928 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr;
1929 for (i = 0; i < blkcnt; i++, bdle++) {
1930 bdle->addrl = (uint32_t)addr;
1931 bdle->addrh = (uint32_t)(addr >> 32);
1938 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt);
1939 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1);
1940 addr = sc->streams[ss].bdl.dma_paddr;
1941 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr);
1942 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
1944 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2);
1946 ctl |= HDAC_SDCTL2_DIR;
1948 ctl &= ~HDAC_SDCTL2_DIR;
1949 ctl &= ~HDAC_SDCTL2_STRM_MASK;
1950 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT;
1951 ctl &= ~HDAC_SDCTL2_STRIPE_MASK;
1952 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT;
1953 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl);
1955 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format);
1957 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1959 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1961 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS,
1962 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS);
1963 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1964 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1966 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1968 sc->streams[ss].blksz = blksz;
1969 sc->streams[ss].running = 1;
1970 hdac_poll_reinit(sc);
1975 hdac_stream_stop(device_t dev, device_t child, int dir, int stream)
1977 struct hdac_softc *sc = device_get_softc(dev);
1981 ss = hdac_find_stream(sc, dir, stream);
1983 ("Stop for not allocated stream (%d/%d)\n", dir, stream));
1986 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1987 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1989 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1991 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1993 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1995 sc->streams[ss].running = 0;
1996 hdac_poll_reinit(sc);
2000 hdac_stream_reset(device_t dev, device_t child, int dir, int stream)
2002 struct hdac_softc *sc = device_get_softc(dev);
2008 ss = hdac_find_stream(sc, dir, stream);
2010 ("Reset for not allocated stream (%d/%d)\n", dir, stream));
2013 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2014 ctl |= HDAC_SDCTL_SRST;
2015 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2017 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2018 if (ctl & HDAC_SDCTL_SRST)
2022 if (!(ctl & HDAC_SDCTL_SRST))
2023 device_printf(dev, "Reset setting timeout\n");
2024 ctl &= ~HDAC_SDCTL_SRST;
2025 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2028 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2029 if (!(ctl & HDAC_SDCTL_SRST))
2033 if (ctl & HDAC_SDCTL_SRST)
2034 device_printf(dev, "Reset timeout!\n");
2038 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream)
2040 struct hdac_softc *sc = device_get_softc(dev);
2043 ss = hdac_find_stream(sc, dir, stream);
2045 ("Reset for not allocated stream (%d/%d)\n", dir, stream));
2048 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB));
2052 hdac_unsol_alloc(device_t dev, device_t child, int tag)
2054 struct hdac_softc *sc = device_get_softc(dev);
2056 sc->unsol_registered++;
2057 hdac_poll_reinit(sc);
2062 hdac_unsol_free(device_t dev, device_t child, int tag)
2064 struct hdac_softc *sc = device_get_softc(dev);
2066 sc->unsol_registered--;
2067 hdac_poll_reinit(sc);
2070 static device_method_t hdac_methods[] = {
2071 /* device interface */
2072 DEVMETHOD(device_probe, hdac_probe),
2073 DEVMETHOD(device_attach, hdac_attach),
2074 DEVMETHOD(device_detach, hdac_detach),
2075 DEVMETHOD(device_suspend, hdac_suspend),
2076 DEVMETHOD(device_resume, hdac_resume),
2078 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag),
2079 DEVMETHOD(bus_print_child, hdac_print_child),
2080 DEVMETHOD(bus_child_location_str, hdac_child_location_str),
2081 DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method),
2082 DEVMETHOD(bus_read_ivar, hdac_read_ivar),
2083 DEVMETHOD(hdac_get_mtx, hdac_get_mtx),
2084 DEVMETHOD(hdac_codec_command, hdac_codec_command),
2085 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc),
2086 DEVMETHOD(hdac_stream_free, hdac_stream_free),
2087 DEVMETHOD(hdac_stream_start, hdac_stream_start),
2088 DEVMETHOD(hdac_stream_stop, hdac_stream_stop),
2089 DEVMETHOD(hdac_stream_reset, hdac_stream_reset),
2090 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr),
2091 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc),
2092 DEVMETHOD(hdac_unsol_free, hdac_unsol_free),
2096 static driver_t hdac_driver = {
2099 sizeof(struct hdac_softc),
2102 static devclass_t hdac_devclass;
2104 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL);