2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
4 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Intel High Definition Audio (Controller) driver for FreeBSD.
33 #ifdef HAVE_KERNEL_OPTION_HEADERS
37 #include <dev/sound/pcm/sound.h>
38 #include <dev/pci/pcireg.h>
39 #include <dev/pci/pcivar.h>
41 #include <sys/ctype.h>
42 #include <sys/taskqueue.h>
44 #include <dev/sound/pci/hda/hdac_private.h>
45 #include <dev/sound/pci/hda/hdac_reg.h>
46 #include <dev/sound/pci/hda/hda_reg.h>
47 #include <dev/sound/pci/hda/hdac.h>
49 #define HDA_DRV_TEST_REV "20120126_0002"
51 SND_DECLARE_FILE("$FreeBSD$");
53 #define hdac_lock(sc) snd_mtxlock((sc)->lock)
54 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
55 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
56 #define hdac_lockowned(sc) mtx_owned((sc)->lock)
58 #define HDAC_QUIRK_64BIT (1 << 0)
59 #define HDAC_QUIRK_DMAPOS (1 << 1)
60 #define HDAC_QUIRK_MSI (1 << 2)
65 } hdac_quirks_tab[] = {
66 { "64bit", HDAC_QUIRK_DMAPOS },
67 { "dmapos", HDAC_QUIRK_DMAPOS },
68 { "msi", HDAC_QUIRK_MSI },
71 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller");
79 { HDA_INTEL_OAK, "Intel Oaktrail", 0, 0 },
80 { HDA_INTEL_BAY, "Intel BayTrail", 0, 0 },
81 { HDA_INTEL_HSW1, "Intel Haswell", 0, 0 },
82 { HDA_INTEL_HSW2, "Intel Haswell", 0, 0 },
83 { HDA_INTEL_HSW3, "Intel Haswell", 0, 0 },
84 { HDA_INTEL_BDW1, "Intel Broadwell", 0, 0 },
85 { HDA_INTEL_BDW2, "Intel Broadwell", 0, 0 },
86 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 },
87 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 },
88 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 },
89 { HDA_INTEL_LPT1, "Intel Lynx Point", 0, 0 },
90 { HDA_INTEL_LPT2, "Intel Lynx Point", 0, 0 },
91 { HDA_INTEL_WCPT, "Intel Wildcat Point", 0, 0 },
92 { HDA_INTEL_WELLS1, "Intel Wellsburg", 0, 0 },
93 { HDA_INTEL_WELLS2, "Intel Wellsburg", 0, 0 },
94 { HDA_INTEL_LPTLP1, "Intel Lynx Point-LP", 0, 0 },
95 { HDA_INTEL_LPTLP2, "Intel Lynx Point-LP", 0, 0 },
96 { HDA_INTEL_SRPTLP, "Intel Sunrise Point-LP", 0, 0 },
97 { HDA_INTEL_KBLKLP, "Intel Kabylake-LP", 0, 0 },
98 { HDA_INTEL_SRPT, "Intel Sunrise Point", 0, 0 },
99 { HDA_INTEL_KBLK, "Intel Kabylake", 0, 0 },
100 { HDA_INTEL_KBLKH, "Intel Kabylake-H", 0, 0 },
101 { HDA_INTEL_CFLK, "Intel Coffelake", 0, 0 },
102 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 },
103 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 },
104 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 },
105 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 },
106 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 },
107 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 },
108 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 },
109 { HDA_INTEL_PCH, "Intel Ibex Peak", 0, 0 },
110 { HDA_INTEL_PCH2, "Intel Ibex Peak", 0, 0 },
111 { HDA_INTEL_SCH, "Intel SCH", 0, 0 },
112 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI },
113 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI },
114 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 },
115 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 },
116 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 },
117 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 },
118 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 },
119 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 },
120 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 },
121 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 },
122 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT },
123 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT },
124 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT },
125 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT },
126 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 },
127 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 },
128 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 },
129 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 },
130 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 },
131 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 },
132 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 },
133 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 },
134 { HDA_NVIDIA_0BE2, "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI },
135 { HDA_NVIDIA_0BE3, "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI },
136 { HDA_NVIDIA_0BE4, "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI },
137 { HDA_NVIDIA_GT100, "NVIDIA GT100", 0, HDAC_QUIRK_MSI },
138 { HDA_NVIDIA_GT104, "NVIDIA GT104", 0, HDAC_QUIRK_MSI },
139 { HDA_NVIDIA_GT106, "NVIDIA GT106", 0, HDAC_QUIRK_MSI },
140 { HDA_NVIDIA_GT108, "NVIDIA GT108", 0, HDAC_QUIRK_MSI },
141 { HDA_NVIDIA_GT116, "NVIDIA GT116", 0, HDAC_QUIRK_MSI },
142 { HDA_NVIDIA_GF119, "NVIDIA GF119", 0, 0 },
143 { HDA_NVIDIA_GF110_1, "NVIDIA GF110", 0, HDAC_QUIRK_MSI },
144 { HDA_NVIDIA_GF110_2, "NVIDIA GF110", 0, HDAC_QUIRK_MSI },
145 { HDA_ATI_SB450, "ATI SB450", 0, 0 },
146 { HDA_ATI_SB600, "ATI SB600", 0, 0 },
147 { HDA_ATI_RS600, "ATI RS600", 0, 0 },
148 { HDA_ATI_RS690, "ATI RS690", 0, 0 },
149 { HDA_ATI_RS780, "ATI RS780", 0, 0 },
150 { HDA_ATI_R600, "ATI R600", 0, 0 },
151 { HDA_ATI_RV610, "ATI RV610", 0, 0 },
152 { HDA_ATI_RV620, "ATI RV620", 0, 0 },
153 { HDA_ATI_RV630, "ATI RV630", 0, 0 },
154 { HDA_ATI_RV635, "ATI RV635", 0, 0 },
155 { HDA_ATI_RV710, "ATI RV710", 0, 0 },
156 { HDA_ATI_RV730, "ATI RV730", 0, 0 },
157 { HDA_ATI_RV740, "ATI RV740", 0, 0 },
158 { HDA_ATI_RV770, "ATI RV770", 0, 0 },
159 { HDA_ATI_RV810, "ATI RV810", 0, 0 },
160 { HDA_ATI_RV830, "ATI RV830", 0, 0 },
161 { HDA_ATI_RV840, "ATI RV840", 0, 0 },
162 { HDA_ATI_RV870, "ATI RV870", 0, 0 },
163 { HDA_ATI_RV910, "ATI RV910", 0, 0 },
164 { HDA_ATI_RV930, "ATI RV930", 0, 0 },
165 { HDA_ATI_RV940, "ATI RV940", 0, 0 },
166 { HDA_ATI_RV970, "ATI RV970", 0, 0 },
167 { HDA_ATI_R1000, "ATI R1000", 0, 0 },
168 { HDA_AMD_HUDSON2, "AMD Hudson-2", 0, 0 },
169 { HDA_RDC_M3010, "RDC M3010", 0, 0 },
170 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 },
171 { HDA_SIS_966, "SiS 966", 0, 0 },
172 { HDA_ULI_M5461, "ULI M5461", 0, 0 },
174 { HDA_INTEL_ALL, "Intel", 0, 0 },
175 { HDA_NVIDIA_ALL, "NVIDIA", 0, 0 },
176 { HDA_ATI_ALL, "ATI", 0, 0 },
177 { HDA_AMD_ALL, "AMD", 0, 0 },
178 { HDA_VIA_ALL, "VIA", 0, 0 },
179 { HDA_SIS_ALL, "SiS", 0, 0 },
180 { HDA_ULI_ALL, "ULI", 0, 0 },
183 static const struct {
188 } hdac_pcie_snoop[] = {
189 { INTEL_VENDORID, 0x00, 0x00, 0x00 },
190 { ATI_VENDORID, 0x42, 0xf8, 0x02 },
191 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
194 /****************************************************************************
195 * Function prototypes
196 ****************************************************************************/
197 static void hdac_intr_handler(void *);
198 static int hdac_reset(struct hdac_softc *, int);
199 static int hdac_get_capabilities(struct hdac_softc *);
200 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
201 static int hdac_dma_alloc(struct hdac_softc *,
202 struct hdac_dma *, bus_size_t);
203 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
204 static int hdac_mem_alloc(struct hdac_softc *);
205 static void hdac_mem_free(struct hdac_softc *);
206 static int hdac_irq_alloc(struct hdac_softc *);
207 static void hdac_irq_free(struct hdac_softc *);
208 static void hdac_corb_init(struct hdac_softc *);
209 static void hdac_rirb_init(struct hdac_softc *);
210 static void hdac_corb_start(struct hdac_softc *);
211 static void hdac_rirb_start(struct hdac_softc *);
213 static void hdac_attach2(void *);
215 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t);
217 static int hdac_probe(device_t);
218 static int hdac_attach(device_t);
219 static int hdac_detach(device_t);
220 static int hdac_suspend(device_t);
221 static int hdac_resume(device_t);
223 static int hdac_rirb_flush(struct hdac_softc *sc);
224 static int hdac_unsolq_flush(struct hdac_softc *sc);
226 #define hdac_command(a1, a2, a3) \
227 hdac_send_command(a1, a3, a2)
229 /* This function surely going to make its way into upper level someday. */
231 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
233 const char *res = NULL;
234 int i = 0, j, k, len, inv;
236 if (resource_string_value(device_get_name(sc->dev),
237 device_get_unit(sc->dev), "config", &res) != 0)
239 if (!(res != NULL && strlen(res) > 0))
242 device_printf(sc->dev, "Config options:");
245 while (res[i] != '\0' &&
246 (res[i] == ',' || isspace(res[i]) != 0))
248 if (res[i] == '\0') {
255 while (res[j] != '\0' &&
256 !(res[j] == ',' || isspace(res[j]) != 0))
259 if (len > 2 && strncmp(res + i, "no", 2) == 0)
263 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) {
264 if (strncmp(res + i + inv,
265 hdac_quirks_tab[k].key, len - inv) != 0)
267 if (len - inv != strlen(hdac_quirks_tab[k].key))
270 printf(" %s%s", (inv != 0) ? "no" : "",
271 hdac_quirks_tab[k].key);
274 *on |= hdac_quirks_tab[k].value;
275 *on &= ~hdac_quirks_tab[k].value;
276 } else if (inv != 0) {
277 *off |= hdac_quirks_tab[k].value;
278 *off &= ~hdac_quirks_tab[k].value;
286 /****************************************************************************
287 * void hdac_intr_handler(void *)
289 * Interrupt handler. Processes interrupts received from the hdac.
290 ****************************************************************************/
292 hdac_intr_handler(void *context)
294 struct hdac_softc *sc;
300 sc = (struct hdac_softc *)context;
303 /* Do we have anything to do? */
304 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
305 if ((intsts & HDAC_INTSTS_GIS) == 0) {
310 /* Was this a controller interrupt? */
311 if (intsts & HDAC_INTSTS_CIS) {
312 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
313 /* Get as many responses that we can */
314 while (rirbsts & HDAC_RIRBSTS_RINTFL) {
315 HDAC_WRITE_1(&sc->mem,
316 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
318 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
320 if (sc->unsolq_rp != sc->unsolq_wp)
321 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
324 if (intsts & HDAC_INTSTS_SIS_MASK) {
325 for (i = 0; i < sc->num_ss; i++) {
326 if ((intsts & (1 << i)) == 0)
328 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS,
329 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
330 if ((dev = sc->streams[i].dev) != NULL) {
331 HDAC_STREAM_INTR(dev,
332 sc->streams[i].dir, sc->streams[i].stream);
337 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts);
342 hdac_poll_callback(void *arg)
344 struct hdac_softc *sc = arg;
350 if (sc->polling == 0) {
354 callout_reset(&sc->poll_callout, sc->poll_ival,
355 hdac_poll_callback, sc);
358 hdac_intr_handler(sc);
361 /****************************************************************************
362 * int hdac_reset(hdac_softc *, int)
364 * Reset the hdac to a quiescent and known state.
365 ****************************************************************************/
367 hdac_reset(struct hdac_softc *sc, int wakeup)
373 * Stop all Streams DMA engine
375 for (i = 0; i < sc->num_iss; i++)
376 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
377 for (i = 0; i < sc->num_oss; i++)
378 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
379 for (i = 0; i < sc->num_bss; i++)
380 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
383 * Stop Control DMA engines.
385 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
386 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
389 * Reset DMA position buffer.
391 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
392 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
395 * Reset the controller. The reset must remain asserted for
396 * a minimum of 100us.
398 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
399 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
402 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
403 if (!(gctl & HDAC_GCTL_CRST))
407 if (gctl & HDAC_GCTL_CRST) {
408 device_printf(sc->dev, "Unable to put hdac in reset\n");
412 /* If wakeup is not requested - leave the controller in reset state. */
417 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
418 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
421 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
422 if (gctl & HDAC_GCTL_CRST)
426 if (!(gctl & HDAC_GCTL_CRST)) {
427 device_printf(sc->dev, "Device stuck in reset\n");
432 * Wait for codecs to finish their own reset sequence. The delay here
433 * should be of 250us but for some reasons, it's not enough on my
434 * computer. Let's use twice as much as necessary to make sure that
435 * it's reset properly.
443 /****************************************************************************
444 * int hdac_get_capabilities(struct hdac_softc *);
446 * Retreive the general capabilities of the hdac;
447 * Number of Input Streams
448 * Number of Output Streams
449 * Number of bidirectional Streams
451 * CORB and RIRB sizes
452 ****************************************************************************/
454 hdac_get_capabilities(struct hdac_softc *sc)
457 uint8_t corbsize, rirbsize;
459 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
460 sc->num_iss = HDAC_GCAP_ISS(gcap);
461 sc->num_oss = HDAC_GCAP_OSS(gcap);
462 sc->num_bss = HDAC_GCAP_BSS(gcap);
463 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss;
464 sc->num_sdo = HDAC_GCAP_NSDO(gcap);
465 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0;
466 if (sc->quirks_on & HDAC_QUIRK_64BIT)
467 sc->support_64bit = 1;
468 else if (sc->quirks_off & HDAC_QUIRK_64BIT)
469 sc->support_64bit = 0;
471 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
472 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
473 HDAC_CORBSIZE_CORBSZCAP_256)
475 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
476 HDAC_CORBSIZE_CORBSZCAP_16)
478 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
479 HDAC_CORBSIZE_CORBSZCAP_2)
482 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
487 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
488 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
489 HDAC_RIRBSIZE_RIRBSZCAP_256)
491 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
492 HDAC_RIRBSIZE_RIRBSZCAP_16)
494 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
495 HDAC_RIRBSIZE_RIRBSZCAP_2)
498 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
504 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, "
505 "NSDO %d%s, CORB %d, RIRB %d\n",
506 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo,
507 sc->support_64bit ? ", 64bit" : "",
508 sc->corb_size, sc->rirb_size);
515 /****************************************************************************
518 * This function is called by bus_dmamap_load when the mapping has been
519 * established. We just record the physical address of the mapping into
520 * the struct hdac_dma passed in.
521 ****************************************************************************/
523 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
525 struct hdac_dma *dma;
528 dma = (struct hdac_dma *)callback_arg;
529 dma->dma_paddr = segs[0].ds_addr;
534 /****************************************************************************
537 * This function allocate and setup a dma region (struct hdac_dma).
538 * It must be freed by a corresponding hdac_dma_free.
539 ****************************************************************************/
541 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
546 roundsz = roundup2(size, HDA_DMA_ALIGNMENT);
547 bzero(dma, sizeof(*dma));
552 result = bus_dma_tag_create(
553 bus_get_dma_tag(sc->dev), /* parent */
554 HDA_DMA_ALIGNMENT, /* alignment */
556 (sc->support_64bit) ? BUS_SPACE_MAXADDR :
557 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
558 BUS_SPACE_MAXADDR, /* highaddr */
560 NULL, /* fistfuncarg */
561 roundsz, /* maxsize */
563 roundsz, /* maxsegsz */
566 NULL, /* lockfuncarg */
567 &dma->dma_tag); /* dmat */
569 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
571 goto hdac_dma_alloc_fail;
575 * Allocate DMA memory
577 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
578 BUS_DMA_NOWAIT | BUS_DMA_ZERO |
579 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
582 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
584 goto hdac_dma_alloc_fail;
587 dma->dma_size = roundsz;
592 result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
593 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
594 if (result != 0 || dma->dma_paddr == 0) {
597 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
599 goto hdac_dma_alloc_fail;
603 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
604 __func__, (uintmax_t)size, (uintmax_t)roundsz);
610 hdac_dma_free(sc, dma);
616 /****************************************************************************
617 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
619 * Free a struct dhac_dma that has been previously allocated via the
620 * hdac_dma_alloc function.
621 ****************************************************************************/
623 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
625 if (dma->dma_paddr != 0) {
628 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
629 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
631 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
634 if (dma->dma_vaddr != NULL) {
635 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
636 dma->dma_vaddr = NULL;
638 if (dma->dma_tag != NULL) {
639 bus_dma_tag_destroy(dma->dma_tag);
645 /****************************************************************************
646 * int hdac_mem_alloc(struct hdac_softc *)
648 * Allocate all the bus resources necessary to speak with the physical
650 ****************************************************************************/
652 hdac_mem_alloc(struct hdac_softc *sc)
654 struct hdac_mem *mem;
657 mem->mem_rid = PCIR_BAR(0);
658 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
659 &mem->mem_rid, RF_ACTIVE);
660 if (mem->mem_res == NULL) {
661 device_printf(sc->dev,
662 "%s: Unable to allocate memory resource\n", __func__);
665 mem->mem_tag = rman_get_bustag(mem->mem_res);
666 mem->mem_handle = rman_get_bushandle(mem->mem_res);
671 /****************************************************************************
672 * void hdac_mem_free(struct hdac_softc *)
674 * Free up resources previously allocated by hdac_mem_alloc.
675 ****************************************************************************/
677 hdac_mem_free(struct hdac_softc *sc)
679 struct hdac_mem *mem;
682 if (mem->mem_res != NULL)
683 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
688 /****************************************************************************
689 * int hdac_irq_alloc(struct hdac_softc *)
691 * Allocate and setup the resources necessary for interrupt handling.
692 ****************************************************************************/
694 hdac_irq_alloc(struct hdac_softc *sc)
696 struct hdac_irq *irq;
702 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 &&
703 (result = pci_msi_count(sc->dev)) == 1 &&
704 pci_alloc_msi(sc->dev, &result) == 0)
707 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
708 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
709 if (irq->irq_res == NULL) {
710 device_printf(sc->dev, "%s: Unable to allocate irq\n",
712 goto hdac_irq_alloc_fail;
714 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV,
715 NULL, hdac_intr_handler, sc, &irq->irq_handle);
717 device_printf(sc->dev,
718 "%s: Unable to setup interrupt handler (%x)\n",
720 goto hdac_irq_alloc_fail;
731 /****************************************************************************
732 * void hdac_irq_free(struct hdac_softc *)
734 * Free up resources previously allocated by hdac_irq_alloc.
735 ****************************************************************************/
737 hdac_irq_free(struct hdac_softc *sc)
739 struct hdac_irq *irq;
742 if (irq->irq_res != NULL && irq->irq_handle != NULL)
743 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
744 if (irq->irq_res != NULL)
745 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
747 if (irq->irq_rid == 0x1)
748 pci_release_msi(sc->dev);
749 irq->irq_handle = NULL;
754 /****************************************************************************
755 * void hdac_corb_init(struct hdac_softc *)
757 * Initialize the corb registers for operations but do not start it up yet.
758 * The CORB engine must not be running when this function is called.
759 ****************************************************************************/
761 hdac_corb_init(struct hdac_softc *sc)
766 /* Setup the CORB size. */
767 switch (sc->corb_size) {
769 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
772 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
775 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
778 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
780 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
782 /* Setup the CORB Address in the hdac */
783 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
784 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
785 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
787 /* Set the WP and RP */
789 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
790 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
792 * The HDA specification indicates that the CORBRPRST bit will always
793 * read as zero. Unfortunately, it seems that at least the 82801G
794 * doesn't reset the bit to zero, which stalls the corb engine.
795 * manually reset the bit to zero before continuing.
797 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
799 /* Enable CORB error reporting */
801 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
805 /****************************************************************************
806 * void hdac_rirb_init(struct hdac_softc *)
808 * Initialize the rirb registers for operations but do not start it up yet.
809 * The RIRB engine must not be running when this function is called.
810 ****************************************************************************/
812 hdac_rirb_init(struct hdac_softc *sc)
817 /* Setup the RIRB size. */
818 switch (sc->rirb_size) {
820 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
823 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
826 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
829 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
831 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
833 /* Setup the RIRB Address in the hdac */
834 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
835 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
836 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
838 /* Setup the WP and RP */
840 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
842 /* Setup the interrupt threshold */
843 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
845 /* Enable Overrun and response received reporting */
847 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
848 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
850 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
855 * Make sure that the Host CPU cache doesn't contain any dirty
856 * cache lines that falls in the rirb. If I understood correctly, it
857 * should be sufficient to do this only once as the rirb is purely
858 * read-only from now on.
860 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
861 BUS_DMASYNC_PREREAD);
865 /****************************************************************************
866 * void hdac_corb_start(hdac_softc *)
868 * Startup the corb DMA engine
869 ****************************************************************************/
871 hdac_corb_start(struct hdac_softc *sc)
875 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
876 corbctl |= HDAC_CORBCTL_CORBRUN;
877 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
880 /****************************************************************************
881 * void hdac_rirb_start(hdac_softc *)
883 * Startup the rirb DMA engine
884 ****************************************************************************/
886 hdac_rirb_start(struct hdac_softc *sc)
890 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
891 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
892 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
896 hdac_rirb_flush(struct hdac_softc *sc)
898 struct hdac_rirb *rirb_base, *rirb;
904 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
905 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
907 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
908 BUS_DMASYNC_POSTREAD);
912 while (sc->rirb_rp != rirbwp) {
914 sc->rirb_rp %= sc->rirb_size;
915 rirb = &rirb_base[sc->rirb_rp];
916 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
917 resp = rirb->response;
918 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
919 sc->unsolq[sc->unsolq_wp++] = resp;
920 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
921 sc->unsolq[sc->unsolq_wp++] = cad;
922 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
923 } else if (sc->codecs[cad].pending <= 0) {
924 device_printf(sc->dev, "Unexpected unsolicited "
925 "response from address %d: %08x\n", cad, resp);
927 sc->codecs[cad].response = resp;
928 sc->codecs[cad].pending--;
936 hdac_unsolq_flush(struct hdac_softc *sc)
943 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
944 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
945 while (sc->unsolq_rp != sc->unsolq_wp) {
946 resp = sc->unsolq[sc->unsolq_rp++];
947 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
948 cad = sc->unsolq[sc->unsolq_rp++];
949 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
950 if ((child = sc->codecs[cad].dev) != NULL)
951 HDAC_UNSOL_INTR(child, resp);
954 sc->unsolq_st = HDAC_UNSOLQ_READY;
960 /****************************************************************************
961 * uint32_t hdac_command_sendone_internal
963 * Wrapper function that sends only one command to a given codec
964 ****************************************************************************/
966 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb)
971 if (!hdac_lockowned(sc))
972 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
973 verb &= ~HDA_CMD_CAD_MASK;
974 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT;
975 sc->codecs[cad].response = HDA_INVALID;
977 sc->codecs[cad].pending++;
979 sc->corb_wp %= sc->corb_size;
980 corb = (uint32_t *)sc->corb_dma.dma_vaddr;
982 bus_dmamap_sync(sc->corb_dma.dma_tag,
983 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
985 corb[sc->corb_wp] = verb;
987 bus_dmamap_sync(sc->corb_dma.dma_tag,
988 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
990 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
994 if (hdac_rirb_flush(sc) == 0)
996 } while (sc->codecs[cad].pending != 0 && --timeout);
998 if (sc->codecs[cad].pending != 0) {
999 device_printf(sc->dev, "Command timeout on address %d\n", cad);
1000 sc->codecs[cad].pending = 0;
1003 if (sc->unsolq_rp != sc->unsolq_wp)
1004 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
1005 return (sc->codecs[cad].response);
1008 /****************************************************************************
1010 ****************************************************************************/
1012 /****************************************************************************
1013 * int hdac_probe(device_t)
1015 * Probe for the presence of an hdac. If none is found, check for a generic
1016 * match using the subclass of the device.
1017 ****************************************************************************/
1019 hdac_probe(device_t dev)
1023 uint16_t class, subclass;
1026 model = (uint32_t)pci_get_device(dev) << 16;
1027 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1028 class = pci_get_class(dev);
1029 subclass = pci_get_subclass(dev);
1031 bzero(desc, sizeof(desc));
1033 for (i = 0; i < nitems(hdac_devices); i++) {
1034 if (hdac_devices[i].model == model) {
1035 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
1036 result = BUS_PROBE_DEFAULT;
1039 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1040 class == PCIC_MULTIMEDIA &&
1041 subclass == PCIS_MULTIMEDIA_HDA) {
1042 snprintf(desc, sizeof(desc),
1044 hdac_devices[i].desc, pci_get_device(dev));
1045 result = BUS_PROBE_GENERIC;
1049 if (result == ENXIO && class == PCIC_MULTIMEDIA &&
1050 subclass == PCIS_MULTIMEDIA_HDA) {
1051 snprintf(desc, sizeof(desc), "Generic (0x%08x)", model);
1052 result = BUS_PROBE_GENERIC;
1054 if (result != ENXIO) {
1055 strlcat(desc, " HDA Controller", sizeof(desc));
1056 device_set_desc_copy(dev, desc);
1063 hdac_unsolq_task(void *context, int pending)
1065 struct hdac_softc *sc;
1067 sc = (struct hdac_softc *)context;
1070 hdac_unsolq_flush(sc);
1074 /****************************************************************************
1075 * int hdac_attach(device_t)
1077 * Attach the device into the kernel. Interrupts usually won't be enabled
1078 * when this function is called. Setup everything that doesn't require
1079 * interrupts and defer probing of codecs until interrupts are enabled.
1080 ****************************************************************************/
1082 hdac_attach(device_t dev)
1084 struct hdac_softc *sc;
1088 uint16_t class, subclass;
1092 sc = device_get_softc(dev);
1094 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n",
1095 pci_get_subvendor(dev), pci_get_subdevice(dev));
1096 device_printf(dev, "HDA Driver Revision: %s\n",
1100 model = (uint32_t)pci_get_device(dev) << 16;
1101 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1102 class = pci_get_class(dev);
1103 subclass = pci_get_subclass(dev);
1105 for (i = 0; i < nitems(hdac_devices); i++) {
1106 if (hdac_devices[i].model == model) {
1110 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1111 class == PCIC_MULTIMEDIA &&
1112 subclass == PCIS_MULTIMEDIA_HDA) {
1118 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex");
1120 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
1121 callout_init(&sc->poll_callout, 1);
1122 for (i = 0; i < HDAC_CODEC_MAX; i++)
1123 sc->codecs[i].dev = NULL;
1125 sc->quirks_on = hdac_devices[devid].quirks_on;
1126 sc->quirks_off = hdac_devices[devid].quirks_off;
1131 if (resource_int_value(device_get_name(dev),
1132 device_get_unit(dev), "msi", &i) == 0) {
1134 sc->quirks_off |= HDAC_QUIRK_MSI;
1136 sc->quirks_on |= HDAC_QUIRK_MSI;
1137 sc->quirks_off |= ~HDAC_QUIRK_MSI;
1140 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off);
1142 device_printf(sc->dev,
1143 "Config options: on=0x%08x off=0x%08x\n",
1144 sc->quirks_on, sc->quirks_off);
1147 if (resource_int_value(device_get_name(dev),
1148 device_get_unit(dev), "polling", &i) == 0 && i != 0)
1153 pci_enable_busmaster(dev);
1155 vendor = pci_get_vendor(dev);
1156 if (vendor == INTEL_VENDORID) {
1158 v = pci_read_config(dev, 0x44, 1);
1159 pci_write_config(dev, 0x44, v & 0xf8, 1);
1161 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
1162 pci_read_config(dev, 0x44, 1));
1166 #if defined(__i386__) || defined(__amd64__)
1167 sc->flags |= HDAC_F_DMA_NOCACHE;
1169 if (resource_int_value(device_get_name(dev),
1170 device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
1172 sc->flags &= ~HDAC_F_DMA_NOCACHE;
1175 * Try to enable PCIe snoop to avoid messing around with
1176 * uncacheable DMA attribute. Since PCIe snoop register
1177 * config is pretty much vendor specific, there are no
1178 * general solutions on how to enable it, forcing us (even
1179 * Microsoft) to enable uncacheable or write combined DMA
1182 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
1184 for (i = 0; i < nitems(hdac_pcie_snoop); i++) {
1185 if (hdac_pcie_snoop[i].vendor != vendor)
1187 sc->flags &= ~HDAC_F_DMA_NOCACHE;
1188 if (hdac_pcie_snoop[i].reg == 0x00)
1190 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
1191 if ((v & hdac_pcie_snoop[i].enable) ==
1192 hdac_pcie_snoop[i].enable)
1194 v &= hdac_pcie_snoop[i].mask;
1195 v |= hdac_pcie_snoop[i].enable;
1196 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
1197 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
1198 if ((v & hdac_pcie_snoop[i].enable) !=
1199 hdac_pcie_snoop[i].enable) {
1202 "WARNING: Failed to enable PCIe "
1205 #if defined(__i386__) || defined(__amd64__)
1206 sc->flags |= HDAC_F_DMA_NOCACHE;
1211 #if defined(__i386__) || defined(__amd64__)
1216 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
1217 (sc->flags & HDAC_F_DMA_NOCACHE) ?
1218 "Uncacheable" : "PCIe snoop", vendor);
1221 /* Allocate resources */
1222 result = hdac_mem_alloc(sc);
1224 goto hdac_attach_fail;
1225 result = hdac_irq_alloc(sc);
1227 goto hdac_attach_fail;
1229 /* Get Capabilities */
1230 result = hdac_get_capabilities(sc);
1232 goto hdac_attach_fail;
1234 /* Allocate CORB, RIRB, POS and BDLs dma memory */
1235 result = hdac_dma_alloc(sc, &sc->corb_dma,
1236 sc->corb_size * sizeof(uint32_t));
1238 goto hdac_attach_fail;
1239 result = hdac_dma_alloc(sc, &sc->rirb_dma,
1240 sc->rirb_size * sizeof(struct hdac_rirb));
1242 goto hdac_attach_fail;
1243 sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss,
1244 M_HDAC, M_ZERO | M_WAITOK);
1245 for (i = 0; i < sc->num_ss; i++) {
1246 result = hdac_dma_alloc(sc, &sc->streams[i].bdl,
1247 sizeof(struct hdac_bdle) * HDA_BDL_MAX);
1249 goto hdac_attach_fail;
1251 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) {
1252 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) {
1254 device_printf(dev, "Failed to "
1255 "allocate DMA pos buffer "
1259 uint64_t addr = sc->pos_dma.dma_paddr;
1261 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32);
1262 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
1263 (addr & HDAC_DPLBASE_DPLBASE_MASK) |
1264 HDAC_DPLBASE_DPLBASE_DMAPBE);
1268 result = bus_dma_tag_create(
1269 bus_get_dma_tag(sc->dev), /* parent */
1270 HDA_DMA_ALIGNMENT, /* alignment */
1272 (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1273 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1274 BUS_SPACE_MAXADDR, /* highaddr */
1275 NULL, /* filtfunc */
1276 NULL, /* fistfuncarg */
1277 HDA_BUFSZ_MAX, /* maxsize */
1279 HDA_BUFSZ_MAX, /* maxsegsz */
1281 NULL, /* lockfunc */
1282 NULL, /* lockfuncarg */
1283 &sc->chan_dmat); /* dmat */
1285 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
1287 goto hdac_attach_fail;
1290 /* Quiesce everything */
1292 device_printf(dev, "Reset controller...\n");
1296 /* Initialize the CORB and RIRB */
1300 /* Defer remaining of initialization until interrupts are enabled */
1301 sc->intrhook.ich_func = hdac_attach2;
1302 sc->intrhook.ich_arg = (void *)sc;
1303 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
1304 sc->intrhook.ich_func = NULL;
1305 hdac_attach2((void *)sc);
1312 for (i = 0; i < sc->num_ss; i++)
1313 hdac_dma_free(sc, &sc->streams[i].bdl);
1314 free(sc->streams, M_HDAC);
1315 hdac_dma_free(sc, &sc->rirb_dma);
1316 hdac_dma_free(sc, &sc->corb_dma);
1318 snd_mtxfree(sc->lock);
1324 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
1326 struct hdac_softc *sc;
1329 int devcount, i, err, val;
1331 dev = oidp->oid_arg1;
1332 sc = device_get_softc(dev);
1336 err = sysctl_handle_int(oidp, &val, 0, req);
1337 if (err != 0 || req->newptr == NULL || val == 0)
1340 /* XXX: Temporary. For debugging. */
1344 } else if (val == 101) {
1349 if ((err = device_get_children(dev, &devlist, &devcount)) != 0)
1352 for (i = 0; i < devcount; i++)
1353 HDAC_PINDUMP(devlist[i]);
1355 free(devlist, M_TEMP);
1360 hdac_mdata_rate(uint16_t fmt)
1362 static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 };
1365 if (fmt & (1 << 14))
1369 rate *= ((fmt >> 11) & 0x07) + 1;
1370 rate /= ((fmt >> 8) & 0x07) + 1;
1371 bits = mbits[(fmt >> 4) & 0x03];
1372 bits *= (fmt & 0x0f) + 1;
1373 return (rate * bits);
1377 hdac_bdata_rate(uint16_t fmt, int output)
1379 static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 };
1383 rate *= ((fmt >> 11) & 0x07) + 1;
1384 bits = bbits[(fmt >> 4) & 0x03];
1385 bits *= (fmt & 0x0f) + 1;
1387 bits = ((bits + 7) & ~0x07) + 10;
1388 return (rate * bits);
1392 hdac_poll_reinit(struct hdac_softc *sc)
1394 int i, pollticks, min = 1000000;
1395 struct hdac_stream *s;
1397 if (sc->polling == 0)
1399 if (sc->unsol_registered > 0)
1401 for (i = 0; i < sc->num_ss; i++) {
1402 s = &sc->streams[i];
1403 if (s->running == 0)
1405 pollticks = ((uint64_t)hz * s->blksz) /
1406 (hdac_mdata_rate(s->format) / 8);
1410 if (pollticks < 1) {
1412 device_printf(sc->dev,
1413 "poll interval < 1 tick !\n");
1417 if (min > pollticks)
1421 device_printf(sc->dev,
1422 "poll interval %d -> %d ticks\n",
1423 sc->poll_ival, min);
1425 sc->poll_ival = min;
1427 callout_stop(&sc->poll_callout);
1429 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc);
1433 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
1435 struct hdac_softc *sc;
1440 dev = oidp->oid_arg1;
1441 sc = device_get_softc(dev);
1447 err = sysctl_handle_int(oidp, &val, 0, req);
1449 if (err != 0 || req->newptr == NULL)
1451 if (val < 0 || val > 1)
1455 if (val != sc->polling) {
1457 callout_stop(&sc->poll_callout);
1459 callout_drain(&sc->poll_callout);
1462 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1463 ctl |= HDAC_INTCTL_GIE;
1464 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1466 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1467 ctl &= ~HDAC_INTCTL_GIE;
1468 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1470 hdac_poll_reinit(sc);
1479 hdac_attach2(void *arg)
1481 struct hdac_softc *sc;
1483 uint32_t vendorid, revisionid;
1487 sc = (struct hdac_softc *)arg;
1491 /* Remove ourselves from the config hooks */
1492 if (sc->intrhook.ich_func != NULL) {
1493 config_intrhook_disestablish(&sc->intrhook);
1494 sc->intrhook.ich_func = NULL;
1498 device_printf(sc->dev, "Starting CORB Engine...\n");
1500 hdac_corb_start(sc);
1502 device_printf(sc->dev, "Starting RIRB Engine...\n");
1504 hdac_rirb_start(sc);
1506 device_printf(sc->dev,
1507 "Enabling controller interrupt...\n");
1509 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1511 if (sc->polling == 0) {
1512 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
1513 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1518 device_printf(sc->dev, "Scanning HDA codecs ...\n");
1520 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1522 for (i = 0; i < HDAC_CODEC_MAX; i++) {
1523 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1525 device_printf(sc->dev,
1526 "Found CODEC at address %d\n", i);
1529 vendorid = hdac_send_command(sc, i,
1530 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID));
1531 revisionid = hdac_send_command(sc, i,
1532 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID));
1534 if (vendorid == HDA_INVALID &&
1535 revisionid == HDA_INVALID) {
1536 device_printf(sc->dev,
1537 "CODEC is not responding!\n");
1540 sc->codecs[i].vendor_id =
1541 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1542 sc->codecs[i].device_id =
1543 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1544 sc->codecs[i].revision_id =
1545 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1546 sc->codecs[i].stepping_id =
1547 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1548 child = device_add_child(sc->dev, "hdacc", -1);
1549 if (child == NULL) {
1550 device_printf(sc->dev,
1551 "Failed to add CODEC device\n");
1554 device_set_ivars(child, (void *)(intptr_t)i);
1555 sc->codecs[i].dev = child;
1558 bus_generic_attach(sc->dev);
1560 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1561 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1562 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1563 sysctl_hdac_pindump, "I", "Dump pin states/data");
1564 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1565 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1566 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1567 sysctl_hdac_polling, "I", "Enable polling mode");
1570 /****************************************************************************
1571 * int hdac_suspend(device_t)
1573 * Suspend and power down HDA bus and codecs.
1574 ****************************************************************************/
1576 hdac_suspend(device_t dev)
1578 struct hdac_softc *sc = device_get_softc(dev);
1581 device_printf(dev, "Suspend...\n");
1583 bus_generic_suspend(dev);
1587 device_printf(dev, "Reset controller...\n");
1589 callout_stop(&sc->poll_callout);
1592 callout_drain(&sc->poll_callout);
1593 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1595 device_printf(dev, "Suspend done\n");
1600 /****************************************************************************
1601 * int hdac_resume(device_t)
1603 * Powerup and restore HDA bus and codecs state.
1604 ****************************************************************************/
1606 hdac_resume(device_t dev)
1608 struct hdac_softc *sc = device_get_softc(dev);
1612 device_printf(dev, "Resume...\n");
1616 /* Quiesce everything */
1618 device_printf(dev, "Reset controller...\n");
1622 /* Initialize the CORB and RIRB */
1627 device_printf(dev, "Starting CORB Engine...\n");
1629 hdac_corb_start(sc);
1631 device_printf(dev, "Starting RIRB Engine...\n");
1633 hdac_rirb_start(sc);
1635 device_printf(dev, "Enabling controller interrupt...\n");
1637 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1639 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1641 hdac_poll_reinit(sc);
1644 error = bus_generic_resume(dev);
1646 device_printf(dev, "Resume done\n");
1651 /****************************************************************************
1652 * int hdac_detach(device_t)
1654 * Detach and free up resources utilized by the hdac device.
1655 ****************************************************************************/
1657 hdac_detach(device_t dev)
1659 struct hdac_softc *sc = device_get_softc(dev);
1661 int cad, i, devcount, error;
1663 if ((error = device_get_children(dev, &devlist, &devcount)) != 0)
1665 for (i = 0; i < devcount; i++) {
1666 cad = (intptr_t)device_get_ivars(devlist[i]);
1667 if ((error = device_delete_child(dev, devlist[i])) != 0) {
1668 free(devlist, M_TEMP);
1671 sc->codecs[cad].dev = NULL;
1673 free(devlist, M_TEMP);
1678 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1681 for (i = 0; i < sc->num_ss; i++)
1682 hdac_dma_free(sc, &sc->streams[i].bdl);
1683 free(sc->streams, M_HDAC);
1684 hdac_dma_free(sc, &sc->pos_dma);
1685 hdac_dma_free(sc, &sc->rirb_dma);
1686 hdac_dma_free(sc, &sc->corb_dma);
1687 if (sc->chan_dmat != NULL) {
1688 bus_dma_tag_destroy(sc->chan_dmat);
1689 sc->chan_dmat = NULL;
1692 snd_mtxfree(sc->lock);
1696 static bus_dma_tag_t
1697 hdac_get_dma_tag(device_t dev, device_t child)
1699 struct hdac_softc *sc = device_get_softc(dev);
1701 return (sc->chan_dmat);
1705 hdac_print_child(device_t dev, device_t child)
1709 retval = bus_print_child_header(dev, child);
1710 retval += printf(" at cad %d",
1711 (int)(intptr_t)device_get_ivars(child));
1712 retval += bus_print_child_footer(dev, child);
1718 hdac_child_location_str(device_t dev, device_t child, char *buf,
1722 snprintf(buf, buflen, "cad=%d",
1723 (int)(intptr_t)device_get_ivars(child));
1728 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
1731 struct hdac_softc *sc = device_get_softc(dev);
1732 nid_t cad = (uintptr_t)device_get_ivars(child);
1734 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x "
1736 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id,
1737 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id);
1742 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1744 struct hdac_softc *sc = device_get_softc(dev);
1745 nid_t cad = (uintptr_t)device_get_ivars(child);
1748 case HDA_IVAR_CODEC_ID:
1751 case HDA_IVAR_VENDOR_ID:
1752 *result = sc->codecs[cad].vendor_id;
1754 case HDA_IVAR_DEVICE_ID:
1755 *result = sc->codecs[cad].device_id;
1757 case HDA_IVAR_REVISION_ID:
1758 *result = sc->codecs[cad].revision_id;
1760 case HDA_IVAR_STEPPING_ID:
1761 *result = sc->codecs[cad].stepping_id;
1763 case HDA_IVAR_SUBVENDOR_ID:
1764 *result = pci_get_subvendor(dev);
1766 case HDA_IVAR_SUBDEVICE_ID:
1767 *result = pci_get_subdevice(dev);
1769 case HDA_IVAR_DMA_NOCACHE:
1770 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0;
1772 case HDA_IVAR_STRIPES_MASK:
1773 *result = (1 << (1 << sc->num_sdo)) - 1;
1782 hdac_get_mtx(device_t dev, device_t child)
1784 struct hdac_softc *sc = device_get_softc(dev);
1790 hdac_codec_command(device_t dev, device_t child, uint32_t verb)
1793 return (hdac_send_command(device_get_softc(dev),
1794 (intptr_t)device_get_ivars(child), verb));
1798 hdac_find_stream(struct hdac_softc *sc, int dir, int stream)
1803 /* Allocate ISS/BSS first. */
1805 for (i = 0; i < sc->num_iss; i++) {
1806 if (sc->streams[i].stream == stream) {
1812 for (i = 0; i < sc->num_oss; i++) {
1813 if (sc->streams[i + sc->num_iss].stream == stream) {
1814 ss = i + sc->num_iss;
1819 /* Fallback to BSS. */
1821 for (i = 0; i < sc->num_bss; i++) {
1822 if (sc->streams[i + sc->num_iss + sc->num_oss].stream
1824 ss = i + sc->num_iss + sc->num_oss;
1833 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe,
1836 struct hdac_softc *sc = device_get_softc(dev);
1837 nid_t cad = (uintptr_t)device_get_ivars(child);
1838 int stream, ss, bw, maxbw, prevbw;
1840 /* Look for empty stream. */
1841 ss = hdac_find_stream(sc, dir, 0);
1843 /* Return if found nothing. */
1847 /* Check bus bandwidth. */
1848 bw = hdac_bdata_rate(format, dir);
1850 bw *= 1 << (sc->num_sdo - stripe);
1851 prevbw = sc->sdo_bw_used;
1852 maxbw = 48000 * 960 * (1 << sc->num_sdo);
1854 prevbw = sc->codecs[cad].sdi_bw_used;
1855 maxbw = 48000 * 464;
1858 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n",
1859 (bw + prevbw) / 1000, maxbw / 1000,
1860 bw + prevbw > maxbw ? " -- OVERFLOW!" : "");
1862 if (bw + prevbw > maxbw)
1865 sc->sdo_bw_used += bw;
1867 sc->codecs[cad].sdi_bw_used += bw;
1869 /* Allocate stream number */
1870 if (ss >= sc->num_iss + sc->num_oss)
1871 stream = 15 - (ss - sc->num_iss + sc->num_oss);
1872 else if (ss >= sc->num_iss)
1873 stream = ss - sc->num_iss + 1;
1877 sc->streams[ss].dev = child;
1878 sc->streams[ss].dir = dir;
1879 sc->streams[ss].stream = stream;
1880 sc->streams[ss].bw = bw;
1881 sc->streams[ss].format = format;
1882 sc->streams[ss].stripe = stripe;
1883 if (dmapos != NULL) {
1884 if (sc->pos_dma.dma_vaddr != NULL)
1885 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8);
1893 hdac_stream_free(device_t dev, device_t child, int dir, int stream)
1895 struct hdac_softc *sc = device_get_softc(dev);
1896 nid_t cad = (uintptr_t)device_get_ivars(child);
1899 ss = hdac_find_stream(sc, dir, stream);
1901 ("Free for not allocated stream (%d/%d)\n", dir, stream));
1903 sc->sdo_bw_used -= sc->streams[ss].bw;
1905 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw;
1906 sc->streams[ss].stream = 0;
1907 sc->streams[ss].dev = NULL;
1911 hdac_stream_start(device_t dev, device_t child,
1912 int dir, int stream, bus_addr_t buf, int blksz, int blkcnt)
1914 struct hdac_softc *sc = device_get_softc(dev);
1915 struct hdac_bdle *bdle;
1920 ss = hdac_find_stream(sc, dir, stream);
1922 ("Start for not allocated stream (%d/%d)\n", dir, stream));
1924 addr = (uint64_t)buf;
1925 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr;
1926 for (i = 0; i < blkcnt; i++, bdle++) {
1927 bdle->addrl = (uint32_t)addr;
1928 bdle->addrh = (uint32_t)(addr >> 32);
1935 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt);
1936 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1);
1937 addr = sc->streams[ss].bdl.dma_paddr;
1938 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr);
1939 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
1941 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2);
1943 ctl |= HDAC_SDCTL2_DIR;
1945 ctl &= ~HDAC_SDCTL2_DIR;
1946 ctl &= ~HDAC_SDCTL2_STRM_MASK;
1947 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT;
1948 ctl &= ~HDAC_SDCTL2_STRIPE_MASK;
1949 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT;
1950 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl);
1952 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format);
1954 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1956 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1958 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS,
1959 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS);
1960 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1961 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1963 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1965 sc->streams[ss].blksz = blksz;
1966 sc->streams[ss].running = 1;
1967 hdac_poll_reinit(sc);
1972 hdac_stream_stop(device_t dev, device_t child, int dir, int stream)
1974 struct hdac_softc *sc = device_get_softc(dev);
1978 ss = hdac_find_stream(sc, dir, stream);
1980 ("Stop for not allocated stream (%d/%d)\n", dir, stream));
1983 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1984 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1986 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1988 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1990 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1992 sc->streams[ss].running = 0;
1993 hdac_poll_reinit(sc);
1997 hdac_stream_reset(device_t dev, device_t child, int dir, int stream)
1999 struct hdac_softc *sc = device_get_softc(dev);
2005 ss = hdac_find_stream(sc, dir, stream);
2007 ("Reset for not allocated stream (%d/%d)\n", dir, stream));
2010 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2011 ctl |= HDAC_SDCTL_SRST;
2012 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2014 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2015 if (ctl & HDAC_SDCTL_SRST)
2019 if (!(ctl & HDAC_SDCTL_SRST))
2020 device_printf(dev, "Reset setting timeout\n");
2021 ctl &= ~HDAC_SDCTL_SRST;
2022 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2025 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2026 if (!(ctl & HDAC_SDCTL_SRST))
2030 if (ctl & HDAC_SDCTL_SRST)
2031 device_printf(dev, "Reset timeout!\n");
2035 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream)
2037 struct hdac_softc *sc = device_get_softc(dev);
2040 ss = hdac_find_stream(sc, dir, stream);
2042 ("Reset for not allocated stream (%d/%d)\n", dir, stream));
2045 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB));
2049 hdac_unsol_alloc(device_t dev, device_t child, int tag)
2051 struct hdac_softc *sc = device_get_softc(dev);
2053 sc->unsol_registered++;
2054 hdac_poll_reinit(sc);
2059 hdac_unsol_free(device_t dev, device_t child, int tag)
2061 struct hdac_softc *sc = device_get_softc(dev);
2063 sc->unsol_registered--;
2064 hdac_poll_reinit(sc);
2067 static device_method_t hdac_methods[] = {
2068 /* device interface */
2069 DEVMETHOD(device_probe, hdac_probe),
2070 DEVMETHOD(device_attach, hdac_attach),
2071 DEVMETHOD(device_detach, hdac_detach),
2072 DEVMETHOD(device_suspend, hdac_suspend),
2073 DEVMETHOD(device_resume, hdac_resume),
2075 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag),
2076 DEVMETHOD(bus_print_child, hdac_print_child),
2077 DEVMETHOD(bus_child_location_str, hdac_child_location_str),
2078 DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method),
2079 DEVMETHOD(bus_read_ivar, hdac_read_ivar),
2080 DEVMETHOD(hdac_get_mtx, hdac_get_mtx),
2081 DEVMETHOD(hdac_codec_command, hdac_codec_command),
2082 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc),
2083 DEVMETHOD(hdac_stream_free, hdac_stream_free),
2084 DEVMETHOD(hdac_stream_start, hdac_stream_start),
2085 DEVMETHOD(hdac_stream_stop, hdac_stream_stop),
2086 DEVMETHOD(hdac_stream_reset, hdac_stream_reset),
2087 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr),
2088 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc),
2089 DEVMETHOD(hdac_unsol_free, hdac_unsol_free),
2093 static driver_t hdac_driver = {
2096 sizeof(struct hdac_softc),
2099 static devclass_t hdac_devclass;
2101 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL);