2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _HDAC_PRIVATE_H_
30 #define _HDAC_PRIVATE_H_
33 /****************************************************************************
34 * Miscellaneous defines
35 ****************************************************************************/
36 #define HDAC_DMA_ALIGNMENT 128
37 #define HDAC_CODEC_MAX 16
39 #define HDAC_MTX_NAME "hdac driver mutex"
41 /****************************************************************************
43 ****************************************************************************/
44 #define HDAC_READ_1(mem, offset) \
45 bus_space_read_1((mem)->mem_tag, (mem)->mem_handle, (offset))
46 #define HDAC_READ_2(mem, offset) \
47 bus_space_read_2((mem)->mem_tag, (mem)->mem_handle, (offset))
48 #define HDAC_READ_4(mem, offset) \
49 bus_space_read_4((mem)->mem_tag, (mem)->mem_handle, (offset))
50 #define HDAC_WRITE_1(mem, offset, value) \
51 bus_space_write_1((mem)->mem_tag, (mem)->mem_handle, (offset), (value))
52 #define HDAC_WRITE_2(mem, offset, value) \
53 bus_space_write_2((mem)->mem_tag, (mem)->mem_handle, (offset), (value))
54 #define HDAC_WRITE_4(mem, offset, value) \
55 bus_space_write_4((mem)->mem_tag, (mem)->mem_handle, (offset), (value))
57 #define HDAC_ISDCTL(sc, n) (_HDAC_ISDCTL((n), (sc)->num_iss, (sc)->num_oss))
58 #define HDAC_ISDSTS(sc, n) (_HDAC_ISDSTS((n), (sc)->num_iss, (sc)->num_oss))
59 #define HDAC_ISDPICB(sc, n) (_HDAC_ISDPICB((n), (sc)->num_iss, (sc)->num_oss))
60 #define HDAC_ISDCBL(sc, n) (_HDAC_ISDCBL((n), (sc)->num_iss, (sc)->num_oss))
61 #define HDAC_ISDLVI(sc, n) (_HDAC_ISDLVI((n), (sc)->num_iss, (sc)->num_oss))
62 #define HDAC_ISDFIFOD(sc, n) (_HDAC_ISDFIFOD((n), (sc)->num_iss, (sc)->num_oss))
63 #define HDAC_ISDFMT(sc, n) (_HDAC_ISDFMT((n), (sc)->num_iss, (sc)->num_oss))
64 #define HDAC_ISDBDPL(sc, n) (_HDAC_ISDBDPL((n), (sc)->num_iss, (sc)->num_oss))
65 #define HDAC_ISDBDPU(sc, n) (_HDAC_ISDBDPU((n), (sc)->num_iss, (sc)->num_oss))
67 #define HDAC_OSDCTL(sc, n) (_HDAC_OSDCTL((n), (sc)->num_iss, (sc)->num_oss))
68 #define HDAC_OSDSTS(sc, n) (_HDAC_OSDSTS((n), (sc)->num_iss, (sc)->num_oss))
69 #define HDAC_OSDPICB(sc, n) (_HDAC_OSDPICB((n), (sc)->num_iss, (sc)->num_oss))
70 #define HDAC_OSDCBL(sc, n) (_HDAC_OSDCBL((n), (sc)->num_iss, (sc)->num_oss))
71 #define HDAC_OSDLVI(sc, n) (_HDAC_OSDLVI((n), (sc)->num_iss, (sc)->num_oss))
72 #define HDAC_OSDFIFOD(sc, n) (_HDAC_OSDFIFOD((n), (sc)->num_iss, (sc)->num_oss))
73 #define HDAC_OSDBDPL(sc, n) (_HDAC_OSDBDPL((n), (sc)->num_iss, (sc)->num_oss))
74 #define HDAC_OSDBDPU(sc, n) (_HDAC_OSDBDPU((n), (sc)->num_iss, (sc)->num_oss))
76 #define HDAC_BSDCTL(sc, n) (_HDAC_BSDCTL((n), (sc)->num_iss, (sc)->num_oss))
77 #define HDAC_BSDSTS(sc, n) (_HDAC_BSDSTS((n), (sc)->num_iss, (sc)->num_oss))
78 #define HDAC_BSDPICB(sc, n) (_HDAC_BSDPICB((n), (sc)->num_iss, (sc)->num_oss))
79 #define HDAC_BSDCBL(sc, n) (_HDAC_BSDCBL((n), (sc)->num_iss, (sc)->num_oss))
80 #define HDAC_BSDLVI(sc, n) (_HDAC_BSDLVI((n), (sc)->num_iss, (sc)->num_oss))
81 #define HDAC_BSDFIFOD(sc, n) (_HDAC_BSDFIFOD((n), (sc)->num_iss, (sc)->num_oss))
82 #define HDAC_BSDBDPL(sc, n) (_HDAC_BSDBDPL((n), (sc)->num_iss, (sc)->num_oss))
83 #define HDAC_BSDBDPU(sc, n) (_HDAC_BSDBDPU((n), (sc)->num_iss, (sc)->num_oss))
86 /****************************************************************************
87 * Custom hdac malloc type
88 ****************************************************************************/
89 MALLOC_DECLARE(M_HDAC);
91 /****************************************************************************
94 * Holds the resources necessary to describe the physical memory associated
96 ****************************************************************************/
98 struct resource *mem_res;
100 bus_space_tag_t mem_tag;
101 bus_space_handle_t mem_handle;
104 /****************************************************************************
107 * Holds the resources necessary to describe the irq associated with the
109 ****************************************************************************/
111 struct resource *irq_res;
116 /****************************************************************************
119 * This structure is used to hold all the information to manage the dma
121 ****************************************************************************/
123 bus_dma_tag_t dma_tag;
124 bus_dmamap_t dma_map;
125 bus_addr_t dma_paddr;
130 /****************************************************************************
133 * Hold a response from a verb sent to a codec received via the rirb.
134 ****************************************************************************/
137 uint32_t response_ex;
140 #define HDAC_RIRB_RESPONSE_EX_SDATA_IN_MASK 0x0000000f
141 #define HDAC_RIRB_RESPONSE_EX_SDATA_IN_OFFSET 0
142 #define HDAC_RIRB_RESPONSE_EX_UNSOLICITED 0x00000010
144 #define HDAC_RIRB_RESPONSE_EX_SDATA_IN(response_ex) \
145 (((response_ex) & HDAC_RIRB_RESPONSE_EX_SDATA_IN_MASK) >> \
146 HDAC_RIRB_RESPONSE_EX_SDATA_IN_OFFSET)
148 /****************************************************************************
149 * struct hdac_command_list
151 * This structure holds the list of verbs that are to be sent to the codec
152 * via the corb and the responses received via the rirb. It's allocated by
153 * the codec driver and is owned by it.
154 ****************************************************************************/
155 struct hdac_command_list {
165 volatile uint32_t addrl;
166 volatile uint32_t addrh;
167 volatile uint32_t len;
168 volatile uint32_t ioc;
171 #define HDA_MAX_CONNS 32
172 #define HDA_MAX_NAMELEN 32
185 nid_t conns[HDA_MAX_CONNS];
186 u_char connsenable[HDA_MAX_CONNS];
187 char name[HDA_MAX_NAMELEN];
188 struct hdac_devinfo *devinfo;
193 uint32_t supp_stream_formats;
194 uint32_t supp_pcm_size_rate;
206 struct hdac_audio_ctl {
207 struct hdac_widget *widget, *childwidget;
209 int index, dir, ndir;
210 int mute, step, size, offset;
211 int left, right, forcemute;
213 uint32_t ossmask, possmask;
216 /* Association is a group of pins bound for some special function. */
217 struct hdac_audio_as {
231 struct hdac_pcm_devinfo {
233 struct hdac_devinfo *devinfo;
237 u_char left[SOUND_MIXER_NRDEVICES];
238 u_char right[SOUND_MIXER_NRDEVICES];
244 /****************************************************************************
245 * struct hdac_devinfo
247 * Holds all the parameters of a given codec function group. This is stored
248 * in the ivar of each child of the hdac bus
249 ****************************************************************************/
250 struct hdac_devinfo {
253 nid_t startnode, endnode;
255 struct hdac_codec *codec;
256 struct hdac_widget *widget;
261 uint32_t supp_stream_formats;
262 uint32_t supp_pcm_size_rate;
264 struct hdac_audio_ctl *ctl;
265 struct hdac_audio_as *as;
268 struct hdac_pcm_devinfo *devs;
271 /* XXX undefined: modem, hdmi. */
275 #define HDAC_CHN_RUNNING 0x00000001
276 #define HDAC_CHN_SUSPEND 0x00000002
280 struct pcm_channel *c;
281 struct pcmchan_caps caps;
282 struct hdac_devinfo *devinfo;
283 struct hdac_pcm_devinfo *pdevinfo;
284 struct hdac_dma bdl_dma;
285 uint32_t spd, fmt, fmtlist[16], pcmrates[16];
286 uint32_t supp_stream_formats, supp_pcm_size_rate;
287 uint32_t ptr, prevptr, blkcnt, blksz;
298 /****************************************************************************
301 ****************************************************************************/
304 int responses_received;
310 struct hdac_command_list *commands;
311 struct hdac_softc *sc;
312 struct hdac_devinfo *fgs;
316 /****************************************************************************
319 * This structure holds the current state of the hdac driver.
320 ****************************************************************************/
322 #define HDAC_F_DMA_NOCACHE 0x00000001
323 #define HDAC_F_MSI 0x00000002
330 struct intr_config_hook intrhook;
334 uint32_t pci_subvendor;
338 struct hdac_chan *chans;
348 struct hdac_dma corb_dma;
352 struct hdac_dma rirb_dma;
355 struct hdac_dma pos_dma;
357 bus_dma_tag_t chan_dmat;
365 struct callout poll_hda;
366 struct callout poll_hdac;
367 struct callout poll_jack;
369 struct task unsolq_task;
371 #define HDAC_UNSOLQ_MAX 64
372 #define HDAC_UNSOLQ_READY 0
373 #define HDAC_UNSOLQ_BUSY 1
377 uint32_t unsolq[HDAC_UNSOLQ_MAX];
379 struct hdac_codec *codecs[HDAC_CODEC_MAX];
382 /****************************************************************************
383 * struct hdac_command flags
384 ****************************************************************************/
385 #define HDAC_COMMAND_FLAG_WAITOK 0x0000
386 #define HDAC_COMMAND_FLAG_NOWAIT 0x0001