2 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #define PCI_VENDOR_XILINX 0x10ee
30 #define PCI_DEVICE_XILINX_HDSPE 0x3fc6 /* AIO, MADI, AES, RayDAT */
31 #define PCI_CLASS_REVISION 0x08
32 #define PCI_REVISION_AIO 212
33 #define PCI_REVISION_RAYDAT 211
39 #define HDSPE_OUT_ENABLE_BASE 512
40 #define HDSPE_IN_ENABLE_BASE 768
41 #define HDSPE_MIXER_BASE 32768
42 #define HDSPE_MAX_GAIN 32768
45 #define HDSPE_PAGE_ADDR_BUF_OUT 8192
46 #define HDSPE_PAGE_ADDR_BUF_IN (HDSPE_PAGE_ADDR_BUF_OUT + 64 * 16 * 4)
47 #define HDSPE_BUF_POSITION_MASK 0x000FFC0
50 #define HDSPE_FREQ_0 (1 << 6)
51 #define HDSPE_FREQ_1 (1 << 7)
52 #define HDSPE_FREQ_DOUBLE (1 << 8)
53 #define HDSPE_FREQ_QUAD (1 << 31)
55 #define HDSPE_FREQ_32000 HDSPE_FREQ_0
56 #define HDSPE_FREQ_44100 HDSPE_FREQ_1
57 #define HDSPE_FREQ_48000 (HDSPE_FREQ_0 | HDSPE_FREQ_1)
58 #define HDSPE_FREQ_MASK (HDSPE_FREQ_0 | HDSPE_FREQ_1 | \
59 HDSPE_FREQ_DOUBLE | HDSPE_FREQ_QUAD)
60 #define HDSPE_FREQ_MASK_DEFAULT HDSPE_FREQ_48000
61 #define HDSPE_FREQ_REG 256
62 #define HDSPE_FREQ_AIO 104857600000000ULL
64 #define HDSPE_SPEED_DEFAULT 48000
67 #define HDSPE_LAT_0 (1 << 1)
68 #define HDSPE_LAT_1 (1 << 2)
69 #define HDSPE_LAT_2 (1 << 3)
70 #define HDSPE_LAT_MASK (HDSPE_LAT_0 | HDSPE_LAT_1 | HDSPE_LAT_2)
71 #define HDSPE_LAT_BYTES_MAX (4096 * 4)
72 #define HDSPE_LAT_BYTES_MIN (32 * 4)
73 #define hdspe_encode_latency(x) (((x)<<1) & HDSPE_LAT_MASK)
76 #define HDSP_ADGain0 (1 << 25)
77 #define HDSP_ADGain1 (1 << 26)
78 #define HDSP_DAGain0 (1 << 27)
79 #define HDSP_DAGain1 (1 << 28)
80 #define HDSP_PhoneGain0 (1 << 29)
81 #define HDSP_PhoneGain1 (1 << 30)
83 #define HDSP_ADGainMask (HDSP_ADGain0 | HDSP_ADGain1)
84 #define HDSP_ADGainMinus10dBV (HDSP_ADGainMask)
85 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
86 #define HDSP_ADGainLowGain 0
88 #define HDSP_DAGainMask (HDSP_DAGain0 | HDSP_DAGain1)
89 #define HDSP_DAGainHighGain (HDSP_DAGainMask)
90 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
91 #define HDSP_DAGainMinus10dBV 0
93 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
94 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
95 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
96 #define HDSP_PhoneGainMinus12dB 0
98 #define HDSPM_statusRegister 0
99 #define HDSPM_statusRegister2 192
102 #define HDSPE_SETTINGS_REG 0
103 #define HDSPE_CONTROL_REG 64
104 #define HDSPE_STATUS_REG 0
105 #define HDSPE_ENABLE (1 << 0)
106 #define HDSPM_CLOCK_MODE_MASTER (1 << 4)
109 #define HDSPE_AUDIO_IRQ_PENDING (1 << 0)
110 #define HDSPE_AUDIO_INT_ENABLE (1 << 5)
111 #define HDSPE_INTERRUPT_ACK 96
114 #define HDSPE_MAX_SLOTS 64 /* Mono channels */
115 #define HDSPE_MAX_CHANS (HDSPE_MAX_SLOTS / 2) /* Stereo pairs */
117 #define HDSPE_CHANBUF_SAMPLES (16 * 1024)
118 #define HDSPE_CHANBUF_SIZE (4 * HDSPE_CHANBUF_SAMPLES)
119 #define HDSPE_DMASEGSIZE (HDSPE_CHANBUF_SIZE * HDSPE_MAX_SLOTS)
121 struct hdspe_channel {
129 static MALLOC_DEFINE(M_HDSPE, "hdspe", "hdspe audio");
131 /* Channel registers */
133 struct snd_dbuf *buffer;
134 struct pcm_channel *channel;
135 struct sc_pcminfo *parent;
137 /* Channel information */
153 /* PCM device private data */
156 uint32_t (*ih) (struct sc_pcminfo *scp);
158 struct sc_chinfo chan[HDSPE_MAX_CHANS];
160 struct hdspe_channel *hc;
163 /* HDSPe device private data */
168 uint32_t ctrl_register;
169 uint32_t settings_register;
172 /* Control/Status register */
176 bus_space_handle_t csh;
178 struct resource *irq;
183 /* Play/Record DMA buffers */
193 #define hdspe_read_1(sc, regno) \
194 bus_space_read_1((sc)->cst, (sc)->csh, (regno))
195 #define hdspe_read_2(sc, regno) \
196 bus_space_read_2((sc)->cst, (sc)->csh, (regno))
197 #define hdspe_read_4(sc, regno) \
198 bus_space_read_4((sc)->cst, (sc)->csh, (regno))
200 #define hdspe_write_1(sc, regno, data) \
201 bus_space_write_1((sc)->cst, (sc)->csh, (regno), (data))
202 #define hdspe_write_2(sc, regno, data) \
203 bus_space_write_2((sc)->cst, (sc)->csh, (regno), (data))
204 #define hdspe_write_4(sc, regno, data) \
205 bus_space_write_4((sc)->cst, (sc)->csh, (regno), (data))