2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp>
5 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
30 #ifdef HAVE_KERNEL_OPTION_HEADERS
34 #include <dev/sound/pcm/sound.h>
35 #include <dev/sound/pcm/ac97.h>
36 #include <dev/sound/pci/ich.h>
38 #include <dev/pci/pcireg.h>
39 #include <dev/pci/pcivar.h>
41 SND_DECLARE_FILE("$FreeBSD$");
43 /* -------------------------------------------------------------------- */
45 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */
46 #define ICH_DTBL_LENGTH 32
47 #define ICH_DEFAULT_BUFSZ 16384
48 #define ICH_MAX_BUFSZ 65536
49 #define ICH_MIN_BUFSZ 4096
50 #define ICH_DEFAULT_BLKCNT 2
51 #define ICH_MAX_BLKCNT 32
52 #define ICH_MIN_BLKCNT 2
53 #define ICH_MIN_BLKSZ 64
55 #define INTEL_VENDORID 0x8086
56 #define SIS_VENDORID 0x1039
57 #define NVIDIA_VENDORID 0x10de
58 #define AMD_VENDORID 0x1022
60 #define INTEL_82440MX 0x7195
61 #define INTEL_82801AA 0x2415
62 #define INTEL_82801AB 0x2425
63 #define INTEL_82801BA 0x2445
64 #define INTEL_82801CA 0x2485
65 #define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */
66 #define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */
67 #define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */
68 #define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */
69 #define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */
70 #define SIS_7012 0x7012 /* SiS 7012 needs special handling */
71 #define NVIDIA_NFORCE 0x01b1
72 #define NVIDIA_NFORCE2 0x006a
73 #define NVIDIA_NFORCE2_400 0x008a
74 #define NVIDIA_NFORCE3 0x00da
75 #define NVIDIA_NFORCE3_250 0x00ea
76 #define NVIDIA_NFORCE4 0x0059
77 #define NVIDIA_NFORCE_410_MCP 0x026b
78 #define NVIDIA_NFORCE4_MCP 0x003a
79 #define AMD_768 0x7445
80 #define AMD_8111 0x746d
82 #define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock)
83 #define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock)
84 #define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock)
87 #define ICH_DEBUG(stmt) do { \
91 #define ICH_DEBUG(...)
94 #define ICH_CALIBRATE_DONE (1 << 0)
95 #define ICH_IGNORE_PCR (1 << 1)
96 #define ICH_IGNORE_RESET (1 << 2)
97 #define ICH_FIXED_RATE (1 << 3)
98 #define ICH_DMA_NOCACHE (1 << 4)
99 #define ICH_HIGH_LATENCY (1 << 5)
101 static const struct ich_type {
105 #define PROBE_LOW 0x01
108 { INTEL_VENDORID, INTEL_82440MX, 0,
110 { INTEL_VENDORID, INTEL_82801AA, 0,
111 "Intel ICH (82801AA)" },
112 { INTEL_VENDORID, INTEL_82801AB, 0,
113 "Intel ICH (82801AB)" },
114 { INTEL_VENDORID, INTEL_82801BA, 0,
115 "Intel ICH2 (82801BA)" },
116 { INTEL_VENDORID, INTEL_82801CA, 0,
117 "Intel ICH3 (82801CA)" },
118 { INTEL_VENDORID, INTEL_82801DB, PROBE_LOW,
119 "Intel ICH4 (82801DB)" },
120 { INTEL_VENDORID, INTEL_82801EB, PROBE_LOW,
121 "Intel ICH5 (82801EB)" },
122 { INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW,
124 { INTEL_VENDORID, INTEL_82801FB, PROBE_LOW,
125 "Intel ICH6 (82801FB)" },
126 { INTEL_VENDORID, INTEL_82801GB, PROBE_LOW,
127 "Intel ICH7 (82801GB)" },
128 { SIS_VENDORID, SIS_7012, 0,
130 { NVIDIA_VENDORID, NVIDIA_NFORCE, 0,
132 { NVIDIA_VENDORID, NVIDIA_NFORCE2, 0,
134 { NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0,
135 "nVidia nForce2 400" },
136 { NVIDIA_VENDORID, NVIDIA_NFORCE3, 0,
138 { NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0,
139 "nVidia nForce3 250" },
140 { NVIDIA_VENDORID, NVIDIA_NFORCE4, 0,
142 { NVIDIA_VENDORID, NVIDIA_NFORCE_410_MCP, 0,
143 "nVidia nForce 410 MCP" },
144 { NVIDIA_VENDORID, NVIDIA_NFORCE4_MCP, 0,
145 "nVidia nForce 4 MCP" },
146 { AMD_VENDORID, AMD_768, 0,
148 { AMD_VENDORID, AMD_8111, 0,
152 /* buffer descriptor */
154 volatile uint32_t buffer;
155 volatile uint32_t length;
160 /* channel registers */
162 uint32_t num:8, run:1, run_save:1;
163 uint32_t blksz, blkcnt, spd;
164 uint32_t regbase, spdreg;
168 struct snd_dbuf *buffer;
169 struct pcm_channel *channel;
170 struct sc_info *parent;
172 struct ich_desc *dtbl;
173 bus_addr_t desc_addr;
176 /* device private data */
179 int hasvra, hasvrm, hasmic;
180 unsigned int chnum, bufsz, blkcnt;
181 int sample_size, swap_reg;
183 struct resource *nambar, *nabmbar, *irq;
184 int regtype, nambarid, nabmbarid, irqid;
185 bus_space_tag_t nambart, nabmbart;
186 bus_space_handle_t nambarh, nabmbarh;
187 bus_dma_tag_t dmat, chan_dmat;
191 struct ac97_info *codec;
192 struct sc_chinfo ch[3];
194 struct ich_desc *dtbl;
195 unsigned int dtbl_size;
196 bus_addr_t desc_addr;
197 struct intr_config_hook intrhook;
201 struct mtx *ich_lock;
204 /* -------------------------------------------------------------------- */
206 static uint32_t ich_fmt[] = {
207 SND_FORMAT(AFMT_S16_LE, 2, 0),
210 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0};
211 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0};
213 /* -------------------------------------------------------------------- */
215 static __inline uint32_t
216 ich_rd(struct sc_info *sc, int regno, int size)
220 return (bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno));
222 return (bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno));
224 return (bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno));
231 ich_wr(struct sc_info *sc, int regno, uint32_t data, int size)
235 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data);
238 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data);
241 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data);
248 ich_waitcd(void *devinfo)
250 struct sc_info *sc = (struct sc_info *)devinfo;
254 for (i = 0; i < ICH_TIMEOUT; i++) {
255 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1);
256 if ((data & 0x01) == 0)
260 if ((sc->flags & ICH_IGNORE_PCR) != 0)
262 device_printf(sc->dev, "CODEC semaphore timeout\n");
267 ich_rdcd(kobj_t obj, void *devinfo, int regno)
269 struct sc_info *sc = (struct sc_info *)devinfo;
274 return (bus_space_read_2(sc->nambart, sc->nambarh, regno));
278 ich_wrcd(kobj_t obj, void *devinfo, int regno, uint32_t data)
280 struct sc_info *sc = (struct sc_info *)devinfo;
284 bus_space_write_2(sc->nambart, sc->nambarh, regno, data);
289 static kobj_method_t ich_ac97_methods[] = {
290 KOBJMETHOD(ac97_read, ich_rdcd),
291 KOBJMETHOD(ac97_write, ich_wrcd),
294 AC97_DECLARE(ich_ac97);
296 /* -------------------------------------------------------------------- */
297 /* common routines */
300 ich_filldtbl(struct sc_chinfo *ch)
302 struct sc_info *sc = ch->parent;
306 base = sndbuf_getbufaddr(ch->buffer);
307 if ((ch->blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->buffer))
308 ch->blksz = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt;
309 if ((sndbuf_getblksz(ch->buffer) != ch->blksz ||
310 sndbuf_getblkcnt(ch->buffer) != ch->blkcnt) &&
311 sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz) != 0)
312 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
313 __func__, ch->blksz, ch->blkcnt);
314 ch->blksz = sndbuf_getblksz(ch->buffer);
316 for (i = 0; i < ICH_DTBL_LENGTH; i++) {
317 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt));
318 ch->dtbl[i].length = ICH_BDC_IOC
319 | (ch->blksz / ch->parent->sample_size);
324 ich_resetchan(struct sc_info *sc, int num)
329 regbase = ICH_REG_PO_BASE;
331 regbase = ICH_REG_PI_BASE;
333 regbase = ICH_REG_MC_BASE;
337 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1);
339 /* This may result in no sound output on NForce 2 MBs, see PR 73987 */
342 (void)ich_rd(sc, regbase + ICH_REG_X_CR, 1);
344 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
345 for (i = 0; i < ICH_TIMEOUT; i++) {
346 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1);
352 if (sc->flags & ICH_IGNORE_RESET)
355 else if (sc->vendor == NVIDIA_VENDORID) {
356 sc->flags |= ICH_IGNORE_RESET;
357 device_printf(sc->dev, "ignoring reset failure!\n");
362 device_printf(sc->dev, "cannot reset channel %d\n", num);
366 /* -------------------------------------------------------------------- */
367 /* channel interface */
370 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
372 struct sc_info *sc = devinfo;
373 struct sc_chinfo *ch;
384 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH);
385 ch->desc_addr = sc->desc_addr +
386 (ch->num * ICH_DTBL_LENGTH * sizeof(struct ich_desc));
387 ch->blkcnt = sc->blkcnt;
388 ch->blksz = sc->bufsz / ch->blkcnt;
392 KASSERT(dir == PCMDIR_PLAY, ("wrong direction"));
393 ch->regbase = ICH_REG_PO_BASE;
394 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_FDACRATE : 0;
395 ch->imask = ICH_GLOB_STA_POINT;
399 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
400 ch->regbase = ICH_REG_PI_BASE;
401 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_LADCRATE : 0;
402 ch->imask = ICH_GLOB_STA_PIINT;
406 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
407 ch->regbase = ICH_REG_MC_BASE;
408 ch->spdreg = (sc->hasvrm) ? AC97_REGEXT_MADCRATE : 0;
409 ch->imask = ICH_GLOB_STA_MINT;
416 if (sc->flags & ICH_FIXED_RATE)
420 if (sndbuf_alloc(ch->buffer, sc->chan_dmat,
421 ((sc->flags & ICH_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
426 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4);
433 ichchan_setformat(kobj_t obj, void *data, uint32_t format)
437 struct sc_chinfo *ch = data;
438 struct sc_info *sc = ch->parent;
439 if (!(sc->flags & ICH_CALIBRATE_DONE))
440 device_printf(sc->dev,
441 "WARNING: %s() called before calibration!\n",
449 ichchan_setspeed(kobj_t obj, void *data, uint32_t speed)
451 struct sc_chinfo *ch = data;
452 struct sc_info *sc = ch->parent;
455 if (!(sc->flags & ICH_CALIBRATE_DONE))
456 device_printf(sc->dev,
457 "WARNING: %s() called before calibration!\n",
465 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000)
466 sc->ac97rate = 48000;
467 ac97rate = sc->ac97rate;
469 r = (speed * 48000) / ac97rate;
471 * Cast the return value of ac97_setrate() to uint64 so that
472 * the math don't overflow into the negative range.
474 ch->spd = ((uint64_t)ac97_setrate(sc->codec, ch->spdreg, r) *
483 ichchan_setblocksize(kobj_t obj, void *data, uint32_t blocksize)
485 struct sc_chinfo *ch = data;
486 struct sc_info *sc = ch->parent;
489 if (!(sc->flags & ICH_CALIBRATE_DONE))
490 device_printf(sc->dev,
491 "WARNING: %s() called before calibration!\n",
495 if (sc->flags & ICH_HIGH_LATENCY)
496 blocksize = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt;
498 if (blocksize < ICH_MIN_BLKSZ)
499 blocksize = ICH_MIN_BLKSZ;
500 blocksize &= ~(ICH_MIN_BLKSZ - 1);
501 ch->blksz = blocksize;
504 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1);
511 ichchan_trigger(kobj_t obj, void *data, int go)
513 struct sc_chinfo *ch = data;
514 struct sc_info *sc = ch->parent;
517 if (!(sc->flags & ICH_CALIBRATE_DONE))
518 device_printf(sc->dev,
519 "WARNING: %s() called before calibration!\n",
527 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4);
528 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1);
534 ich_resetchan(sc, ch->num);
545 ichchan_getptr(kobj_t obj, void *data)
547 struct sc_chinfo *ch = data;
548 struct sc_info *sc = ch->parent;
552 if (!(sc->flags & ICH_CALIBRATE_DONE))
553 device_printf(sc->dev,
554 "WARNING: %s() called before calibration!\n",
559 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt;
562 pos = ch->civ * ch->blksz;
567 static struct pcmchan_caps *
568 ichchan_getcaps(kobj_t obj, void *data)
570 struct sc_chinfo *ch = data;
573 struct sc_info *sc = ch->parent;
575 if (!(sc->flags & ICH_CALIBRATE_DONE))
576 device_printf(ch->parent->dev,
577 "WARNING: %s() called before calibration!\n",
581 return ((ch->spdreg) ? &ich_vrcaps : &ich_caps);
584 static kobj_method_t ichchan_methods[] = {
585 KOBJMETHOD(channel_init, ichchan_init),
586 KOBJMETHOD(channel_setformat, ichchan_setformat),
587 KOBJMETHOD(channel_setspeed, ichchan_setspeed),
588 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize),
589 KOBJMETHOD(channel_trigger, ichchan_trigger),
590 KOBJMETHOD(channel_getptr, ichchan_getptr),
591 KOBJMETHOD(channel_getcaps, ichchan_getcaps),
594 CHANNEL_DECLARE(ichchan);
596 /* -------------------------------------------------------------------- */
597 /* The interrupt handler */
602 struct sc_info *sc = (struct sc_info *)p;
603 struct sc_chinfo *ch;
604 uint32_t cbi, lbi, lvi, st, gs;
610 if (!(sc->flags & ICH_CALIBRATE_DONE))
611 device_printf(sc->dev,
612 "WARNING: %s() called before calibration!\n",
616 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK;
617 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) {
618 /* Clear resume interrupt(s) - nothing doing with them */
619 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4);
621 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES);
623 for (i = 0; i < 3; i++) {
625 if ((ch->imask & gs) == 0)
628 st = ich_rd(sc, ch->regbase +
629 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR),
631 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI;
632 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) {
633 /* block complete - update buffer */
636 chn_intr(ch->channel);
639 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1);
640 cbi = ch->civ % ch->blkcnt;
642 cbi = ch->blkcnt - 1;
645 lbi = lvi % ch->blkcnt;
649 lvi += cbi + ch->blkcnt - lbi;
650 lvi %= ICH_DTBL_LENGTH;
651 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1);
654 /* clear status bit */
655 ich_wr(sc, ch->regbase +
656 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR),
661 device_printf(sc->dev,
662 "Unhandled interrupt, gs_intr = %x\n", gs);
666 /* ------------------------------------------------------------------------- */
667 /* Sysctl to control ac97 speed (some boards appear to end up using
668 * XTAL_IN rather than BIT_CLK for link timing).
672 ich_initsys(struct sc_info* sc)
674 /* XXX: this should move to a device specific sysctl "dev.pcm.X.yyy"
675 via device_get_sysctl_*() as discussed on multimedia@ in msg-id
676 <861wujij2q.fsf@xps.des.no> */
677 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev),
678 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
679 OID_AUTO, "ac97rate", CTLFLAG_RW,
680 &sc->ac97rate, 48000,
681 "AC97 link rate (default = 48000)");
687 ich_setstatus(struct sc_info *sc)
689 char status[SND_STATUSLEN];
691 snprintf(status, SND_STATUSLEN,
692 "at io 0x%jx, 0x%jx irq %jd bufsz %u %s",
693 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar),
694 rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich));
696 if (bootverbose && (sc->flags & ICH_DMA_NOCACHE))
697 device_printf(sc->dev,
698 "PCI Master abort workaround enabled\n");
700 pcm_setstatus(sc->dev, status);
703 /* -------------------------------------------------------------------- */
704 /* Calibrate card to determine the clock source. The source maybe a
705 * function of the ac97 codec initialization code (to be investigated).
709 ich_calibrate(void *arg)
712 struct sc_chinfo *ch;
713 struct timeval t1, t2;
715 uint32_t wait_us, actual_48k_rate, oblkcnt;
717 sc = (struct sc_info *)arg;
721 if (sc->intrhook.ich_func != NULL) {
722 config_intrhook_disestablish(&sc->intrhook);
723 sc->intrhook.ich_func = NULL;
727 * Grab audio from input for fixed interval and compare how
728 * much we actually get with what we expect. Interval needs
729 * to be sufficiently short that no interrupts are
733 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction"));
735 oblkcnt = ch->blkcnt;
737 sc->flags |= ICH_CALIBRATE_DONE;
739 ichchan_setblocksize(0, ch, sndbuf_getmaxsize(ch->buffer) >> 1);
741 sc->flags &= ~ICH_CALIBRATE_DONE;
744 * our data format is stereo, 16 bit so each sample is 4 bytes.
745 * assuming we get 48000 samples per second, we get 192000 bytes/sec.
746 * we're going to start recording with interrupts disabled and measure
747 * the time taken for one block to complete. we know the block size,
748 * we know the time in microseconds, we calculate the sample rate:
750 * actual_rate [bps] = bytes / (time [s] * 4)
751 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4)
752 * actual_rate [Hz] = (bytes * 250000) / time [us]
756 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
758 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4);
762 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1);
767 if (t2.tv_sec - t1.tv_sec > 1)
769 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
770 } while (nciv == ociv);
773 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1);
777 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
778 ch->blkcnt = oblkcnt;
780 /* turn time delta into us */
781 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec;
784 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us);
785 sc->flags |= ICH_CALIBRATE_DONE;
791 /* Just in case the timecounter screwed. It is possible, really. */
793 actual_48k_rate = ((uint64_t)ch->blksz * 250000) / wait_us;
795 actual_48k_rate = 48000;
797 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) {
798 sc->ac97rate = actual_48k_rate;
800 sc->ac97rate = 48000;
803 if (bootverbose || sc->ac97rate != 48000) {
804 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate);
805 if (sc->ac97rate != actual_48k_rate)
806 printf(", will use %d Hz", sc->ac97rate);
809 sc->flags |= ICH_CALIBRATE_DONE;
817 /* -------------------------------------------------------------------- */
818 /* Probe and attach the card */
821 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
823 struct sc_info *sc = (struct sc_info *)arg;
824 sc->desc_addr = segs->ds_addr;
829 ich_init(struct sc_info *sc)
833 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4);
835 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4);
837 if ((stat & ICH_GLOB_STA_PCR) == 0) {
838 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */
839 if (sc->vendor == INTEL_VENDORID && (
840 sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB ||
841 sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB ||
842 sc->devid == INTEL_82801GB)) {
843 sc->flags |= ICH_IGNORE_PCR;
844 device_printf(sc->dev, "primary codec not ready!\n");
849 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4);
851 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4);
854 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1))
856 if (sc->hasmic && ich_resetchan(sc, 2))
863 ich_pci_probe(device_t dev)
866 uint16_t devid, vendor;
868 vendor = pci_get_vendor(dev);
869 devid = pci_get_device(dev);
870 for (i = 0; i < sizeof(ich_devs)/sizeof(ich_devs[0]); i++) {
871 if (vendor == ich_devs[i].vendor &&
872 devid == ich_devs[i].devid) {
873 device_set_desc(dev, ich_devs[i].name);
874 /* allow a better driver to override us */
875 if ((ich_devs[i].options & PROBE_LOW) != 0)
876 return (BUS_PROBE_LOW_PRIORITY);
877 return (BUS_PROBE_DEFAULT);
884 ich_pci_attach(device_t dev)
888 uint16_t devid, vendor;
892 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
893 sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "snd_ich softc");
896 vendor = sc->vendor = pci_get_vendor(dev);
897 devid = sc->devid = pci_get_device(dev);
898 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev);
900 * The SiS 7012 register set isn't quite like the standard ich.
901 * There really should be a general "quirks" mechanism.
903 if (vendor == SIS_VENDORID && devid == SIS_7012) {
912 * Intel 440MX Errata #36
913 * - AC97 Soft Audio and Soft Modem Master Abort Errata
915 * http://www.intel.com/design/chipsets/specupdt/245051.htm
917 if (vendor == INTEL_VENDORID && devid == INTEL_82440MX)
918 sc->flags |= ICH_DMA_NOCACHE;
921 * Enable bus master. On ich4/5 this may prevent the detection of
922 * the primary codec becoming ready in ich_init().
924 pci_enable_busmaster(dev);
927 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as
928 * read-only. Need to enable "legacy support", by poking into
929 * pci config space. The driver should use MMBAR and MBBAR,
930 * but doing so will mess things up here. ich4 has enough new
931 * features it warrants it's own driver.
933 if (vendor == INTEL_VENDORID && (devid == INTEL_82801DB ||
934 devid == INTEL_82801EB || devid == INTEL_6300ESB ||
935 devid == INTEL_82801FB || devid == INTEL_82801GB)) {
936 sc->nambarid = PCIR_MMBAR;
937 sc->nabmbarid = PCIR_MBBAR;
938 sc->regtype = SYS_RES_MEMORY;
939 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1);
941 sc->nambarid = PCIR_NAMBAR;
942 sc->nabmbarid = PCIR_NABMBAR;
943 sc->regtype = SYS_RES_IOPORT;
946 sc->nambar = bus_alloc_resource_any(dev, sc->regtype,
947 &sc->nambarid, RF_ACTIVE);
948 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype,
949 &sc->nabmbarid, RF_ACTIVE);
951 if (!sc->nambar || !sc->nabmbar) {
952 device_printf(dev, "unable to map IO port space\n");
956 sc->nambart = rman_get_bustag(sc->nambar);
957 sc->nambarh = rman_get_bushandle(sc->nambar);
958 sc->nabmbart = rman_get_bustag(sc->nabmbar);
959 sc->nabmbarh = rman_get_bushandle(sc->nabmbar);
961 sc->bufsz = pcm_getbuffersize(dev,
962 ICH_MIN_BUFSZ, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ);
964 if (resource_int_value(device_get_name(dev),
965 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
966 sc->blkcnt = sc->bufsz / i;
968 while (sc->blkcnt >> i)
970 sc->blkcnt = 1 << (i - 1);
971 if (sc->blkcnt < ICH_MIN_BLKCNT)
972 sc->blkcnt = ICH_MIN_BLKCNT;
973 else if (sc->blkcnt > ICH_MAX_BLKCNT)
974 sc->blkcnt = ICH_MAX_BLKCNT;
976 sc->blkcnt = ICH_DEFAULT_BLKCNT;
978 if (resource_int_value(device_get_name(dev),
979 device_get_unit(dev), "highlatency", &i) == 0 && i != 0) {
980 sc->flags |= ICH_HIGH_LATENCY;
981 sc->blkcnt = ICH_MIN_BLKCNT;
984 if (resource_int_value(device_get_name(dev),
985 device_get_unit(dev), "fixedrate", &i) == 0 && i != 0)
986 sc->flags |= ICH_FIXED_RATE;
988 if (resource_int_value(device_get_name(dev),
989 device_get_unit(dev), "micchannel_enabled", &i) == 0 && i != 0)
993 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
994 RF_ACTIVE | RF_SHAREABLE);
995 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr,
997 device_printf(dev, "unable to map interrupt\n");
1002 device_printf(dev, "unable to initialize the card\n");
1006 sc->codec = AC97_CREATE(dev, sc, ich_ac97);
1007 if (sc->codec == NULL)
1011 * Turn on inverted external amplifier sense flags for few
1015 case 0x202f161f: /* Gateway 7326GZ */
1016 case 0x203a161f: /* Gateway 4028GZ */
1017 case 0x203e161f: /* Gateway 3520GZ/M210 */
1018 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */
1019 case 0x8144104d: /* Sony VAIO PCG-TR* */
1020 case 0x8197104d: /* Sony S1XP */
1021 case 0x81c0104d: /* Sony VAIO type T */
1022 case 0x81c5104d: /* Sony VAIO VGN B1VP/B1XP */
1023 case 0x3089103c: /* Compaq Presario B3800 */
1024 case 0x309a103c: /* HP Compaq nx4300 */
1025 case 0x82131033: /* NEC VersaPro VJ10F/BH */
1026 case 0x82be1033: /* NEC VersaPro VJ12F/CH */
1027 ac97_setflags(sc->codec, ac97_getflags(sc->codec) | AC97_F_EAPD_INV);
1033 mixer_init(dev, ac97_getmixerclass(), sc->codec);
1035 /* check and set VRA function */
1036 extcaps = ac97_getextcaps(sc->codec);
1037 sc->hasvra = extcaps & AC97_EXTCAP_VRA;
1038 sc->hasvrm = extcaps & AC97_EXTCAP_VRM;
1039 sc->hasmic = (sc->hasmic != 0 &&
1040 (ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL)) ? 1 : 0;
1041 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
1043 sc->dtbl_size = sizeof(struct ich_desc) * ICH_DTBL_LENGTH *
1044 ((sc->hasmic) ? 3 : 2);
1047 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1048 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1049 sc->dtbl_size, 1, 0x3ffff, 0, NULL, NULL, &sc->dmat) != 0) {
1050 device_printf(dev, "unable to create dma tag\n");
1054 /* PCM channel tag */
1055 if (bus_dma_tag_create(bus_get_dma_tag(dev), ICH_MIN_BLKSZ, 0,
1056 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1057 sc->bufsz, 1, 0x3ffff, 0, NULL, NULL, &sc->chan_dmat) != 0) {
1058 device_printf(dev, "unable to create dma tag\n");
1062 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT |
1063 ((sc->flags & ICH_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
1067 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sc->dtbl_size,
1071 if (pcm_register(dev, sc, 1, (sc->hasmic) ? 2 : 1))
1074 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */
1075 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */
1077 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */
1079 if (sc->flags & ICH_FIXED_RATE) {
1080 sc->flags |= ICH_CALIBRATE_DONE;
1085 sc->intrhook.ich_func = ich_calibrate;
1086 sc->intrhook.ich_arg = sc;
1088 config_intrhook_establish(&sc->intrhook) != 0) {
1089 sc->intrhook.ich_func = NULL;
1098 ac97_destroy(sc->codec);
1100 bus_teardown_intr(dev, sc->irq, sc->ih);
1102 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1104 bus_release_resource(dev, sc->regtype,
1105 sc->nambarid, sc->nambar);
1107 bus_release_resource(dev, sc->regtype,
1108 sc->nabmbarid, sc->nabmbar);
1110 bus_dmamap_unload(sc->dmat, sc->dtmap);
1112 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap);
1114 bus_dma_tag_destroy(sc->chan_dmat);
1116 bus_dma_tag_destroy(sc->dmat);
1118 snd_mtxfree(sc->ich_lock);
1124 ich_pci_detach(device_t dev)
1129 r = pcm_unregister(dev);
1132 sc = pcm_getdevinfo(dev);
1134 bus_teardown_intr(dev, sc->irq, sc->ih);
1135 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1136 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar);
1137 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar);
1138 bus_dmamap_unload(sc->dmat, sc->dtmap);
1139 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap);
1140 bus_dma_tag_destroy(sc->chan_dmat);
1141 bus_dma_tag_destroy(sc->dmat);
1142 snd_mtxfree(sc->ich_lock);
1148 ich_pci_codec_reset(struct sc_info *sc)
1153 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4);
1154 control &= ~(ICH_GLOB_CTL_SHUT);
1155 control |= (control & ICH_GLOB_CTL_COLD) ?
1156 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD;
1157 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4);
1159 for (i = 500000; i; i--) {
1160 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR)
1161 break; /* or ICH_SCR? */
1166 printf("%s: time out\n", __func__);
1170 ich_pci_suspend(device_t dev)
1175 sc = pcm_getdevinfo(dev);
1177 for (i = 0 ; i < 3; i++) {
1178 sc->ch[i].run_save = sc->ch[i].run;
1179 if (sc->ch[i].run) {
1181 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT);
1190 ich_pci_resume(device_t dev)
1195 sc = pcm_getdevinfo(dev);
1198 /* Reinit audio device */
1199 if (ich_init(sc) == -1) {
1200 device_printf(dev, "unable to reinitialize the card\n");
1205 ich_pci_codec_reset(sc);
1207 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
1208 if (mixer_reinit(dev) == -1) {
1209 device_printf(dev, "unable to reinitialize the mixer\n");
1212 /* Re-start DMA engines */
1213 for (i = 0 ; i < 3; i++) {
1214 struct sc_chinfo *ch = &sc->ch[i];
1215 if (sc->ch[i].run_save) {
1216 ichchan_setblocksize(0, ch, ch->blksz);
1217 ichchan_setspeed(0, ch, ch->spd);
1218 ichchan_trigger(0, ch, PCMTRIG_START);
1224 static device_method_t ich_methods[] = {
1225 /* Device interface */
1226 DEVMETHOD(device_probe, ich_pci_probe),
1227 DEVMETHOD(device_attach, ich_pci_attach),
1228 DEVMETHOD(device_detach, ich_pci_detach),
1229 DEVMETHOD(device_suspend, ich_pci_suspend),
1230 DEVMETHOD(device_resume, ich_pci_resume),
1234 static driver_t ich_driver = {
1240 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0);
1241 MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1242 MODULE_VERSION(snd_ich, 1);