2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2000-2004 Taku YAMAMOTO <taku@tackymt.homeip.net>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * maestro.c,v 1.23.2.1 2003/10/03 18:21:38 taku Exp
34 * Part of this code (especially in many magic numbers) was heavily inspired
35 * by the Linux driver originally written by
36 * Alan Cox <alan.cox@linux.org>, modified heavily by
37 * Zach Brown <zab@zabbo.net>.
39 * busdma()-ize and buffer size reduction were suggested by
40 * Cameron Grant <cg@freebsd.org>.
41 * Also he showed me the way to use busdma() suite.
43 * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
45 * Munehiro Matsuda <haro@tk.kubota.co.jp>,
46 * who brought patches based on the Linux driver with some simplification.
48 * Hardware volume controller was implemented by
49 * John Baldwin <jhb@freebsd.org>.
52 #ifdef HAVE_KERNEL_OPTION_HEADERS
56 #include <dev/sound/pcm/sound.h>
57 #include <dev/sound/pcm/ac97.h>
58 #include <dev/pci/pcireg.h>
59 #include <dev/pci/pcivar.h>
61 #include <dev/sound/pci/maestro_reg.h>
63 SND_DECLARE_FILE("$FreeBSD$");
66 * PCI IDs of supported chips:
68 * MAESTRO-1 0x01001285
69 * MAESTRO-2 0x1968125d
70 * MAESTRO-2E 0x1978125d
73 #define MAESTRO_1_PCI_ID 0x01001285
74 #define MAESTRO_2_PCI_ID 0x1968125d
75 #define MAESTRO_2E_PCI_ID 0x1978125d
77 #define NEC_SUBID1 0x80581033 /* Taken from Linux driver */
78 #define NEC_SUBID2 0x803c1033 /* NEC VersaProNX VA26D */
81 # if AGG_MAXPLAYCH > 4
83 # define AGG_MAXPLAYCH 4
86 # define AGG_MAXPLAYCH 4
89 #define AGG_DEFAULT_BUFSZ 0x4000 /* 0x1000, but gets underflows */
92 #define PCIR_BAR(x) (PCIR_MAPS + (x) * 4)
95 /* -----------------------------
100 struct agg_info *parent;
102 /* FreeBSD newpcm related */
103 struct pcm_channel *channel;
104 struct snd_dbuf *buffer;
108 bus_addr_t phys; /* channel buffer physical address */
109 bus_addr_t base; /* channel buffer segment base */
110 u_int32_t blklen; /* DMA block length in WORDs */
111 u_int32_t buflen; /* channel buffer length in WORDs */
115 unsigned qs16 : 1; /* quantum size is 16bit */
116 unsigned us : 1; /* in unsigned format */
121 struct agg_info *parent;
123 /* FreeBSD newpcm related */
124 struct pcm_channel *channel;
125 struct snd_dbuf *buffer;
129 bus_addr_t phys; /* channel buffer physical address */
130 bus_addr_t base; /* channel buffer segment base */
131 u_int32_t blklen; /* DMA block length in WORDs */
132 u_int32_t buflen; /* channel buffer length in WORDs */
137 int16_t *src; /* stereo peer buffer */
138 int16_t *sink; /* channel buffer pointer */
139 volatile u_int32_t hwptr; /* ready point in 16bit sample */
143 /* FreeBSD newbus related */
146 /* I wonder whether bus_space_* are in common in *BSD... */
147 struct resource *reg;
150 bus_space_handle_t sh;
152 struct resource *irq;
156 bus_dma_tag_t buf_dmat;
157 bus_dma_tag_t stat_dmat;
159 /* FreeBSD SMPng related */
160 struct mtx lock; /* mutual exclusion */
161 /* FreeBSD newpcm related */
162 struct ac97_info *codec;
165 bus_dmamap_t stat_map;
166 u_int8_t *stat; /* status buffer pointer */
167 bus_addr_t phys; /* status buffer physical address */
168 unsigned int bufsz; /* channel buffer size in bytes */
170 volatile u_int active;
171 struct agg_chinfo pch[AGG_MAXPLAYCH];
172 struct agg_rchinfo rch;
173 volatile u_int8_t curpwr; /* current power status: D[0-3] */
176 /* -----------------------------
179 static unsigned int powerstate_active = PCI_POWERSTATE_D1;
180 #ifdef MAESTRO_AGGRESSIVE_POWERSAVE
181 static unsigned int powerstate_idle = PCI_POWERSTATE_D2;
183 static unsigned int powerstate_idle = PCI_POWERSTATE_D1;
185 static unsigned int powerstate_init = PCI_POWERSTATE_D2;
187 /* XXX: this should move to a device specific sysctl dev.pcm.X.debug.Y via
188 device_get_sysctl_*() as discussed on multimedia@ in msg-id
189 <861wujij2q.fsf@xps.des.no> */
190 static SYSCTL_NODE(_debug, OID_AUTO, maestro, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
192 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_active, CTLFLAG_RW,
193 &powerstate_active, 0, "The Dx power state when active (0-1)");
194 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_idle, CTLFLAG_RW,
195 &powerstate_idle, 0, "The Dx power state when idle (0-2)");
196 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_init, CTLFLAG_RW,
198 "The Dx power state prior to the first use (0-2)");
200 /* -----------------------------
204 static void agg_sleep(struct agg_info*, const char *wmesg, int msec);
207 static __inline u_int32_t agg_rd(struct agg_info*, int, int size);
208 static __inline void agg_wr(struct agg_info*, int, u_int32_t data,
211 static int agg_rdcodec(struct agg_info*, int);
212 static int agg_wrcodec(struct agg_info*, int, u_int32_t);
214 static void ringbus_setdest(struct agg_info*, int, int);
216 static u_int16_t wp_rdreg(struct agg_info*, u_int16_t);
217 static void wp_wrreg(struct agg_info*, u_int16_t, u_int16_t);
218 static u_int16_t wp_rdapu(struct agg_info*, unsigned, u_int16_t);
219 static void wp_wrapu(struct agg_info*, unsigned, u_int16_t, u_int16_t);
220 static void wp_settimer(struct agg_info*, u_int);
221 static void wp_starttimer(struct agg_info*);
222 static void wp_stoptimer(struct agg_info*);
225 static u_int16_t wc_rdreg(struct agg_info*, u_int16_t);
227 static void wc_wrreg(struct agg_info*, u_int16_t, u_int16_t);
229 static u_int16_t wc_rdchctl(struct agg_info*, int);
231 static void wc_wrchctl(struct agg_info*, int, u_int16_t);
233 static void agg_stopclock(struct agg_info*, int part, int st);
235 static void agg_initcodec(struct agg_info*);
236 static void agg_init(struct agg_info*);
237 static void agg_power(struct agg_info*, int);
239 static void aggch_start_dac(struct agg_chinfo*);
240 static void aggch_stop_dac(struct agg_chinfo*);
241 static void aggch_start_adc(struct agg_rchinfo*);
242 static void aggch_stop_adc(struct agg_rchinfo*);
243 static void aggch_feed_adc_stereo(struct agg_rchinfo*);
244 static void aggch_feed_adc_mono(struct agg_rchinfo*);
246 #ifdef AGG_JITTER_CORRECTION
247 static void suppress_jitter(struct agg_chinfo*);
248 static void suppress_rec_jitter(struct agg_rchinfo*);
251 static void set_timer(struct agg_info*);
253 static void agg_intr(void *);
254 static int agg_probe(device_t);
255 static int agg_attach(device_t);
256 static int agg_detach(device_t);
257 static int agg_suspend(device_t);
258 static int agg_resume(device_t);
259 static int agg_shutdown(device_t);
261 static void *dma_malloc(bus_dma_tag_t, u_int32_t, bus_addr_t*,
263 static void dma_free(bus_dma_tag_t, void *, bus_dmamap_t);
265 /* -----------------------------
270 #define agg_lock(sc) snd_mtxlock(&((sc)->lock))
271 #define agg_unlock(sc) snd_mtxunlock(&((sc)->lock))
274 agg_sleep(struct agg_info *sc, const char *wmesg, int msec)
278 timo = msec * hz / 1000;
281 msleep(sc, &sc->lock, PWAIT, wmesg, timo);
287 static __inline u_int32_t
288 agg_rd(struct agg_info *sc, int regno, int size)
292 return bus_space_read_1(sc->st, sc->sh, regno);
294 return bus_space_read_2(sc->st, sc->sh, regno);
296 return bus_space_read_4(sc->st, sc->sh, regno);
298 return ~(u_int32_t)0;
303 #define AGG_RD(sc, regno, size) \
304 bus_space_read_##size( \
305 ((struct agg_info*)(sc))->st, \
306 ((struct agg_info*)(sc))->sh, (regno))
310 agg_wr(struct agg_info *sc, int regno, u_int32_t data, int size)
314 bus_space_write_1(sc->st, sc->sh, regno, data);
317 bus_space_write_2(sc->st, sc->sh, regno, data);
320 bus_space_write_4(sc->st, sc->sh, regno, data);
326 #define AGG_WR(sc, regno, data, size) \
327 bus_space_write_##size( \
328 ((struct agg_info*)(sc))->st, \
329 ((struct agg_info*)(sc))->sh, (regno), (data))
331 /* -------------------------------------------------------------------- */
336 agg_codec_wait4idle(struct agg_info *ess)
340 while (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK) {
343 DELAY(2); /* 20.8us / 13 */
349 agg_rdcodec(struct agg_info *ess, int regno)
353 /* We have to wait for a SAFE time to write addr/data */
354 if (agg_codec_wait4idle(ess)) {
355 /* Timed out. No read performed. */
356 device_printf(ess->dev, "agg_rdcodec() PROGLESS timed out.\n");
360 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_READ | regno, 1);
361 /*DELAY(21); * AC97 cycle = 20.8usec */
363 /* Wait for data retrieve */
364 if (!agg_codec_wait4idle(ess)) {
365 ret = AGG_RD(ess, PORT_CODEC_REG, 2);
367 /* Timed out. No read performed. */
368 device_printf(ess->dev, "agg_rdcodec() RW_DONE timed out.\n");
376 agg_wrcodec(struct agg_info *ess, int regno, u_int32_t data)
378 /* We have to wait for a SAFE time to write addr/data */
379 if (agg_codec_wait4idle(ess)) {
380 /* Timed out. Abort writing. */
381 device_printf(ess->dev, "agg_wrcodec() PROGLESS timed out.\n");
385 AGG_WR(ess, PORT_CODEC_REG, data, 2);
386 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_WRITE | regno, 1);
388 /* Wait for write completion */
389 if (agg_codec_wait4idle(ess)) {
391 device_printf(ess->dev, "agg_wrcodec() RW_DONE timed out.\n");
399 ringbus_setdest(struct agg_info *ess, int src, int dest)
403 data = AGG_RD(ess, PORT_RINGBUS_CTRL, 4);
404 data &= ~(0xfU << src);
405 data |= (0xfU & dest) << src;
406 AGG_WR(ess, PORT_RINGBUS_CTRL, data, 4);
409 /* -------------------------------------------------------------------- */
414 wp_rdreg(struct agg_info *ess, u_int16_t reg)
416 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
417 return AGG_RD(ess, PORT_DSP_DATA, 2);
421 wp_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
423 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
424 AGG_WR(ess, PORT_DSP_DATA, data, 2);
428 wp_wait_data(struct agg_info *ess, u_int16_t data)
432 while (AGG_RD(ess, PORT_DSP_DATA, 2) != data) {
436 AGG_WR(ess, PORT_DSP_DATA, data, 2);
443 wp_rdapu(struct agg_info *ess, unsigned ch, u_int16_t reg)
445 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
446 if (wp_wait_data(ess, reg | (ch << 4)) != 0)
447 device_printf(ess->dev, "wp_rdapu() indexing timed out.\n");
448 return wp_rdreg(ess, WPREG_DATA_PORT);
452 wp_wrapu(struct agg_info *ess, unsigned ch, u_int16_t reg, u_int16_t data)
454 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
455 if (wp_wait_data(ess, reg | (ch << 4)) == 0) {
456 wp_wrreg(ess, WPREG_DATA_PORT, data);
457 if (wp_wait_data(ess, data) != 0)
458 device_printf(ess->dev,
459 "wp_wrapu() write timed out.\n");
461 device_printf(ess->dev, "wp_wrapu() indexing timed out.\n");
466 apu_setparam(struct agg_info *ess, int apuch,
467 u_int32_t wpwa, u_int16_t size, int16_t pan, u_int dv)
469 wp_wrapu(ess, apuch, APUREG_WAVESPACE, (wpwa >> 8) & APU_64KPAGE_MASK);
470 wp_wrapu(ess, apuch, APUREG_CURPTR, wpwa);
471 wp_wrapu(ess, apuch, APUREG_ENDPTR, wpwa + size);
472 wp_wrapu(ess, apuch, APUREG_LOOPLEN, size);
473 wp_wrapu(ess, apuch, APUREG_ROUTING, 0);
474 wp_wrapu(ess, apuch, APUREG_AMPLITUDE, 0xf000);
475 wp_wrapu(ess, apuch, APUREG_POSITION, 0x8f00
476 | (APU_RADIUS_MASK & (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT))
477 | (APU_PAN_MASK & ((pan + PAN_FRONT) << APU_PAN_SHIFT)));
478 wp_wrapu(ess, apuch, APUREG_FREQ_LOBYTE,
479 APU_plus6dB | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT));
480 wp_wrapu(ess, apuch, APUREG_FREQ_HIWORD, dv >> 8);
484 wp_settimer(struct agg_info *ess, u_int divide)
488 RANGE(divide, 2, 32 << 7);
490 for (; divide > 32; divide >>= 1) {
495 for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1)
498 wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
499 wp_wrreg(ess, WPREG_TIMER_FREQ, 0x9000 |
500 (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1));
501 wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
505 wp_starttimer(struct agg_info *ess)
507 AGG_WR(ess, PORT_INT_STAT, 1, 2);
508 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_INT_ENABLED
509 | AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
510 wp_wrreg(ess, WPREG_TIMER_START, 1);
514 wp_stoptimer(struct agg_info *ess)
516 AGG_WR(ess, PORT_HOSTINT_CTRL, ~HOSTINT_CTRL_DSOUND_INT_ENABLED
517 & AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
518 AGG_WR(ess, PORT_INT_STAT, 1, 2);
519 wp_wrreg(ess, WPREG_TIMER_START, 0);
522 /* -------------------------------------------------------------------- */
528 wc_rdreg(struct agg_info *ess, u_int16_t reg)
530 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
531 return AGG_RD(ess, PORT_WAVCACHE_DATA, 2);
536 wc_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
538 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
539 AGG_WR(ess, PORT_WAVCACHE_DATA, data, 2);
544 wc_rdchctl(struct agg_info *ess, int ch)
546 return wc_rdreg(ess, ch << 3);
551 wc_wrchctl(struct agg_info *ess, int ch, u_int16_t data)
553 wc_wrreg(ess, ch << 3, data);
556 /* -------------------------------------------------------------------- */
558 /* Power management */
560 agg_stopclock(struct agg_info *ess, int part, int st)
564 data = pci_read_config(ess->dev, CONF_ACPI_STOPCLOCK, 4);
566 if (st == PCI_POWERSTATE_D1)
567 data &= ~(1 << part);
570 if (st == PCI_POWERSTATE_D1 || st == PCI_POWERSTATE_D2)
571 data |= (0x10000 << part);
573 data &= ~(0x10000 << part);
574 pci_write_config(ess->dev, CONF_ACPI_STOPCLOCK, data, 4);
578 /* -----------------------------
583 agg_initcodec(struct agg_info* ess)
587 if (AGG_RD(ess, PORT_RINGBUS_CTRL, 4) & RINGBUS_CTRL_ACLINK_ENABLED) {
588 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
589 DELAY(104); /* 20.8us * (4 + 1) */
591 /* XXX - 2nd codec should be looked at. */
592 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_AC97_SWRESET, 4);
594 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
597 if (agg_rdcodec(ess, 0) < 0) {
598 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
601 /* Try cold reset. */
602 device_printf(ess->dev, "will perform cold reset.\n");
603 data = AGG_RD(ess, PORT_GPIO_DIR, 2);
604 if (pci_read_config(ess->dev, 0x58, 2) & 1)
606 data |= 0x009 & ~AGG_RD(ess, PORT_GPIO_DATA, 2);
607 AGG_WR(ess, PORT_GPIO_MASK, 0xff6, 2);
608 AGG_WR(ess, PORT_GPIO_DIR, data | 0x009, 2);
609 AGG_WR(ess, PORT_GPIO_DATA, 0x000, 2);
611 AGG_WR(ess, PORT_GPIO_DATA, 0x001, 2);
613 AGG_WR(ess, PORT_GPIO_DATA, 0x009, 2);
614 agg_sleep(ess, "agginicd", 500);
615 AGG_WR(ess, PORT_GPIO_DIR, data, 2);
616 DELAY(84); /* 20.8us * 4 */
617 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
623 agg_init(struct agg_info* ess)
627 /* Setup PCI config registers. */
629 /* Disable all legacy emulations. */
630 data = pci_read_config(ess->dev, CONF_LEGACY, 2);
631 data |= LEGACY_DISABLED;
632 pci_write_config(ess->dev, CONF_LEGACY, data, 2);
634 /* Disconnect from CHI. (Makes Dell inspiron 7500 work?)
635 * Enable posted write.
636 * Prefer PCI timing rather than that of ISA.
638 data = pci_read_config(ess->dev, CONF_MAESTRO, 4);
640 data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING;
641 data &= ~MAESTRO_SWAP_LR;
642 pci_write_config(ess->dev, CONF_MAESTRO, data, 4);
644 /* Turn off unused parts if necessary. */
645 /* consult CONF_MAESTRO. */
646 if (data & MAESTRO_SPDIF)
647 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D2);
649 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D1);
650 if (data & MAESTRO_HWVOL)
651 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D3);
653 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D1);
655 /* parts that never be used */
656 agg_stopclock(ess, ACPI_PART_978, PCI_POWERSTATE_D1);
657 agg_stopclock(ess, ACPI_PART_DAA, PCI_POWERSTATE_D1);
658 agg_stopclock(ess, ACPI_PART_GPIO, PCI_POWERSTATE_D1);
659 agg_stopclock(ess, ACPI_PART_SB, PCI_POWERSTATE_D1);
660 agg_stopclock(ess, ACPI_PART_FM, PCI_POWERSTATE_D1);
661 agg_stopclock(ess, ACPI_PART_MIDI, PCI_POWERSTATE_D1);
662 agg_stopclock(ess, ACPI_PART_GAME_PORT, PCI_POWERSTATE_D1);
664 /* parts that will be used only when play/recording */
665 agg_stopclock(ess, ACPI_PART_WP, PCI_POWERSTATE_D2);
667 /* parts that should always be turned on */
668 agg_stopclock(ess, ACPI_PART_CODEC_CLOCK, PCI_POWERSTATE_D3);
669 agg_stopclock(ess, ACPI_PART_GLUE, PCI_POWERSTATE_D3);
670 agg_stopclock(ess, ACPI_PART_PCI_IF, PCI_POWERSTATE_D3);
671 agg_stopclock(ess, ACPI_PART_RINGBUS, PCI_POWERSTATE_D3);
673 /* Reset direct sound. */
674 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_SOFT_RESET, 2);
676 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
678 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_RESET, 2);
680 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
683 /* Enable hardware volume control interruption. */
684 if (data & MAESTRO_HWVOL) /* XXX - why not use device flags? */
685 AGG_WR(ess, PORT_HOSTINT_CTRL,HOSTINT_CTRL_HWVOL_ENABLED, 2);
687 /* Setup Wave Processor. */
689 /* Enable WaveCache, set DMA base address. */
690 wp_wrreg(ess, WPREG_WAVE_ROMRAM,
691 WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED);
692 wp_wrreg(ess, WPREG_CRAM_DATA, 0);
694 AGG_WR(ess, PORT_WAVCACHE_CTRL,
695 WAVCACHE_ENABLED | WAVCACHE_WTSIZE_2MB | WAVCACHE_SGC_32_47, 2);
697 for (data = WAVCACHE_PCMBAR; data < WAVCACHE_PCMBAR + 4; data++)
698 wc_wrreg(ess, data, ess->phys >> WAVCACHE_BASEADDR_SHIFT);
700 /* Setup Codec/Ringbus. */
702 AGG_WR(ess, PORT_RINGBUS_CTRL,
703 RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED, 4);
705 wp_wrreg(ess, 0x08, 0xB004);
706 wp_wrreg(ess, 0x09, 0x001B);
707 wp_wrreg(ess, 0x0A, 0x8000);
708 wp_wrreg(ess, 0x0B, 0x3F37);
709 wp_wrreg(ess, WPREG_BASE, 0x8598); /* Parallel I/O */
710 wp_wrreg(ess, WPREG_BASE + 1, 0x7632);
711 ringbus_setdest(ess, RINGBUS_SRC_ADC,
712 RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN);
713 ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
714 RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC);
716 /* Enable S/PDIF if necessary. */
717 if (pci_read_config(ess->dev, CONF_MAESTRO, 4) & MAESTRO_SPDIF)
718 /* XXX - why not use device flags? */
719 AGG_WR(ess, PORT_RINGBUS_CTRL_B, RINGBUS_CTRL_SPDIF |
720 AGG_RD(ess, PORT_RINGBUS_CTRL_B, 1), 1);
722 /* Setup ASSP. Needed for Dell Inspiron 7500? */
723 AGG_WR(ess, PORT_ASSP_CTRL_B, 0x00, 1);
724 AGG_WR(ess, PORT_ASSP_CTRL_A, 0x03, 1);
725 AGG_WR(ess, PORT_ASSP_CTRL_C, 0x00, 1);
729 * There seems to be speciality with NEC systems.
731 switch (pci_get_subvendor(ess->dev)
732 | (pci_get_subdevice(ess->dev) << 16)) {
735 /* Matthew Braithwaite <matt@braithwaite.net> reported that
736 * NEC Versa LX doesn't need GPIO operation. */
737 AGG_WR(ess, PORT_GPIO_MASK, 0x9ff, 2);
738 AGG_WR(ess, PORT_GPIO_DIR,
739 AGG_RD(ess, PORT_GPIO_DIR, 2) | 0x600, 2);
740 AGG_WR(ess, PORT_GPIO_DATA, 0x200, 2);
745 /* Deals power state transition. Must be called with softc->lock held. */
747 agg_power(struct agg_info *ess, int status)
751 lastpwr = ess->curpwr;
752 if (lastpwr == status)
756 case PCI_POWERSTATE_D0:
757 case PCI_POWERSTATE_D1:
759 case PCI_POWERSTATE_D2:
760 pci_set_powerstate(ess->dev, status);
761 /* Turn on PCM-related parts. */
762 agg_wrcodec(ess, AC97_REG_POWER, 0);
765 if ((agg_rdcodec(ess, AC97_REG_POWER) & 3) != 3)
766 device_printf(ess->dev,
767 "warning: codec not ready.\n");
769 AGG_WR(ess, PORT_RINGBUS_CTRL,
770 (AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
771 & ~RINGBUS_CTRL_ACLINK_ENABLED)
772 | RINGBUS_CTRL_RINGBUS_ENABLED, 4);
774 AGG_WR(ess, PORT_RINGBUS_CTRL,
775 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
776 | RINGBUS_CTRL_ACLINK_ENABLED, 4);
778 case PCI_POWERSTATE_D3:
780 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
784 case PCI_POWERSTATE_D0:
785 case PCI_POWERSTATE_D1:
786 pci_set_powerstate(ess->dev, status);
790 case PCI_POWERSTATE_D2:
792 case PCI_POWERSTATE_D3:
794 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
798 case PCI_POWERSTATE_D0:
799 case PCI_POWERSTATE_D1:
800 /* Turn off PCM-related parts. */
801 AGG_WR(ess, PORT_RINGBUS_CTRL,
802 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
803 & ~RINGBUS_CTRL_RINGBUS_ENABLED, 4);
805 agg_wrcodec(ess, AC97_REG_POWER, 0x300);
809 pci_set_powerstate(ess->dev, status);
811 case PCI_POWERSTATE_D3:
812 /* Entirely power down. */
813 agg_wrcodec(ess, AC97_REG_POWER, 0xdf00);
815 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
817 if (lastpwr != PCI_POWERSTATE_D2)
819 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
820 AGG_WR(ess, PORT_HOSTINT_STAT, 0xff, 1);
821 pci_set_powerstate(ess->dev, status);
824 /* Invalid power state; let it ignored. */
829 ess->curpwr = status;
832 /* -------------------------------------------------------------------- */
834 /* Channel controller. */
837 aggch_start_dac(struct agg_chinfo *ch)
841 u_int16_t size, apuch, wtbar, wcreg, aputype;
846 wpwa = (ch->phys - ch->base) >> 1;
847 wtbar = 0xc & (wpwa >> WPWA_WTBAR_SHIFT(2));
848 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
850 apuch = (ch->num << 1) | 32;
851 pan = PAN_RIGHT - PAN_FRONT;
854 wcreg |= WAVCACHE_CHCTL_STEREO;
856 aputype = APUTYPE_16BITSTEREO;
861 aputype = APUTYPE_8BITSTEREO;
865 aputype = APUTYPE_16BITLINEAR;
867 aputype = APUTYPE_8BITLINEAR;
872 wcreg |= WAVCACHE_CHCTL_U8;
875 wtbar = (wtbar >> 1) + 4;
877 dv = (((speed % 48000) << 16) + 24000) / 48000
878 + ((speed / 48000) << 16);
880 agg_lock(ch->parent);
881 agg_power(ch->parent, powerstate_active);
883 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar,
884 ch->base >> WAVCACHE_BASEADDR_SHIFT);
885 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 1,
886 ch->base >> WAVCACHE_BASEADDR_SHIFT);
888 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 2,
889 ch->base >> WAVCACHE_BASEADDR_SHIFT);
890 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 3,
891 ch->base >> WAVCACHE_BASEADDR_SHIFT);
893 wc_wrchctl(ch->parent, apuch, wcreg);
894 wc_wrchctl(ch->parent, apuch + 1, wcreg);
896 apu_setparam(ch->parent, apuch, wpwa, size, pan, dv);
899 wpwa |= (WPWA_STEREO >> 1);
900 apu_setparam(ch->parent, apuch + 1, wpwa, size, -pan, dv);
903 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
904 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
905 wp_wrapu(ch->parent, apuch + 1, APUREG_APUTYPE,
906 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
909 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
910 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
913 /* to mark that this channel is ready for intr. */
914 ch->parent->active |= (1 << ch->num);
916 set_timer(ch->parent);
917 wp_starttimer(ch->parent);
918 agg_unlock(ch->parent);
922 aggch_stop_dac(struct agg_chinfo *ch)
924 agg_lock(ch->parent);
926 /* to mark that this channel no longer needs further intrs. */
927 ch->parent->active &= ~(1 << ch->num);
929 wp_wrapu(ch->parent, (ch->num << 1) | 32, APUREG_APUTYPE,
930 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
931 wp_wrapu(ch->parent, (ch->num << 1) | 33, APUREG_APUTYPE,
932 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
934 if (ch->parent->active) {
935 set_timer(ch->parent);
936 wp_starttimer(ch->parent);
938 wp_stoptimer(ch->parent);
939 agg_power(ch->parent, powerstate_idle);
941 agg_unlock(ch->parent);
945 aggch_start_adc(struct agg_rchinfo *ch)
947 bus_addr_t wpwa, wpwa2;
948 u_int16_t wcreg, wcreg2;
952 /* speed > 48000 not cared */
953 dv = ((ch->speed << 16) + 24000) / 48000;
955 /* RATECONV doesn't seem to like dv == 0x10000. */
960 wpwa = (ch->srcphys - ch->base) >> 1;
961 wpwa2 = (ch->srcphys + ch->parent->bufsz/2 - ch->base) >> 1;
962 wcreg = (ch->srcphys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
963 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
964 pan = PAN_LEFT - PAN_FRONT;
966 wpwa = (ch->phys - ch->base) >> 1;
967 wpwa2 = (ch->srcphys - ch->base) >> 1;
968 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
969 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
973 agg_lock(ch->parent);
976 agg_power(ch->parent, powerstate_active);
978 /* Invalidate WaveCache. */
979 wc_wrchctl(ch->parent, 0, wcreg | WAVCACHE_CHCTL_STEREO);
980 wc_wrchctl(ch->parent, 1, wcreg | WAVCACHE_CHCTL_STEREO);
981 wc_wrchctl(ch->parent, 2, wcreg2 | WAVCACHE_CHCTL_STEREO);
982 wc_wrchctl(ch->parent, 3, wcreg2 | WAVCACHE_CHCTL_STEREO);
984 /* Load APU registers. */
985 /* APU #0 : Sample rate converter for left/center. */
986 apu_setparam(ch->parent, 0, WPWA_USE_SYSMEM | wpwa,
987 ch->buflen >> ch->stereo, 0, dv);
988 wp_wrapu(ch->parent, 0, APUREG_AMPLITUDE, 0);
989 wp_wrapu(ch->parent, 0, APUREG_ROUTING, 2 << APU_DATASRC_A_SHIFT);
991 /* APU #1 : Sample rate converter for right. */
992 apu_setparam(ch->parent, 1, WPWA_USE_SYSMEM | wpwa2,
993 ch->buflen >> ch->stereo, 0, dv);
994 wp_wrapu(ch->parent, 1, APUREG_AMPLITUDE, 0);
995 wp_wrapu(ch->parent, 1, APUREG_ROUTING, 3 << APU_DATASRC_A_SHIFT);
997 /* APU #2 : Input mixer for left. */
998 apu_setparam(ch->parent, 2, WPWA_USE_SYSMEM | 0,
999 ch->parent->bufsz >> 2, pan, 0x10000);
1000 wp_wrapu(ch->parent, 2, APUREG_AMPLITUDE, 0);
1001 wp_wrapu(ch->parent, 2, APUREG_EFFECT_GAIN, 0xf0);
1002 wp_wrapu(ch->parent, 2, APUREG_ROUTING, 0x15 << APU_DATASRC_A_SHIFT);
1004 /* APU #3 : Input mixer for right. */
1005 apu_setparam(ch->parent, 3, WPWA_USE_SYSMEM | (ch->parent->bufsz >> 2),
1006 ch->parent->bufsz >> 2, -pan, 0x10000);
1007 wp_wrapu(ch->parent, 3, APUREG_AMPLITUDE, 0);
1008 wp_wrapu(ch->parent, 3, APUREG_EFFECT_GAIN, 0xf0);
1009 wp_wrapu(ch->parent, 3, APUREG_ROUTING, 0x14 << APU_DATASRC_A_SHIFT);
1011 /* to mark this channel ready for intr. */
1012 ch->parent->active |= (1 << ch->parent->playchns);
1016 wp_wrapu(ch->parent, 0, APUREG_APUTYPE,
1017 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1018 wp_wrapu(ch->parent, 1, APUREG_APUTYPE,
1019 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1020 wp_wrapu(ch->parent, 2, APUREG_APUTYPE,
1021 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1022 wp_wrapu(ch->parent, 3, APUREG_APUTYPE,
1023 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1026 set_timer(ch->parent);
1027 wp_starttimer(ch->parent);
1028 agg_unlock(ch->parent);
1032 aggch_stop_adc(struct agg_rchinfo *ch)
1036 agg_lock(ch->parent);
1038 /* to mark that this channel no longer needs further intrs. */
1039 ch->parent->active &= ~(1 << ch->parent->playchns);
1041 for (apuch = 0; apuch < 4; apuch++)
1042 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
1043 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1045 if (ch->parent->active) {
1046 set_timer(ch->parent);
1047 wp_starttimer(ch->parent);
1049 wp_stoptimer(ch->parent);
1050 agg_power(ch->parent, powerstate_idle);
1052 agg_unlock(ch->parent);
1056 * Feed from L/R channel of ADC to destination with stereo interleaving.
1057 * This function expects n not overwrapping the buffer boundary.
1058 * Note that n is measured in sample unit.
1060 * XXX - this function works in 16bit stereo format only.
1063 interleave(int16_t *l, int16_t *r, int16_t *p, unsigned n)
1067 for (end = l + n; l < end; ) {
1074 aggch_feed_adc_stereo(struct agg_rchinfo *ch)
1079 agg_lock(ch->parent);
1080 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1081 agg_unlock(ch->parent);
1082 cur -= 0xffff & ((ch->srcphys - ch->base) >> 1);
1084 src2 = ch->src + ch->parent->bufsz/4;
1087 interleave(ch->src + last, src2 + last,
1088 ch->sink + 2*last, ch->buflen/2 - last);
1089 interleave(ch->src, src2,
1091 } else if (cur > last)
1092 interleave(ch->src + last, src2 + last,
1093 ch->sink + 2*last, cur - last);
1098 * Feed from R channel of ADC and mixdown to destination L/center.
1099 * This function expects n not overwrapping the buffer boundary.
1100 * Note that n is measured in sample unit.
1102 * XXX - this function works in 16bit monoral format only.
1105 mixdown(int16_t *src, int16_t *dest, unsigned n)
1109 for (end = dest + n; dest < end; dest++)
1110 *dest = (int16_t)(((int)*dest - (int)*src++) / 2);
1114 aggch_feed_adc_mono(struct agg_rchinfo *ch)
1118 agg_lock(ch->parent);
1119 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1120 agg_unlock(ch->parent);
1121 cur -= 0xffff & ((ch->phys - ch->base) >> 1);
1125 mixdown(ch->src + last, ch->sink + last, ch->buflen - last);
1126 mixdown(ch->src, ch->sink, cur);
1127 } else if (cur > last)
1128 mixdown(ch->src + last, ch->sink + last, cur - last);
1132 #ifdef AGG_JITTER_CORRECTION
1134 * Stereo jitter suppressor.
1135 * Sometimes playback pointers differ in stereo-paired channels.
1136 * Calling this routine within intr fixes the problem.
1139 suppress_jitter(struct agg_chinfo *ch)
1142 int cp1, cp2, diff /*, halfsize*/ ;
1144 /*halfsize = (ch->qs16? ch->buflen >> 2 : ch->buflen >> 1);*/
1145 cp1 = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1146 cp2 = wp_rdapu(ch->parent, (ch->num << 1) | 33, APUREG_CURPTR);
1148 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1149 if (diff > 1 /* && diff < halfsize*/ )
1150 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1156 suppress_rec_jitter(struct agg_rchinfo *ch)
1158 int cp1, cp2, diff /*, halfsize*/ ;
1160 /*halfsize = (ch->stereo? ch->buflen >> 2 : ch->buflen >> 1);*/
1161 cp1 = (ch->stereo? ch->parent->bufsz >> 2 : ch->parent->bufsz >> 1)
1162 + wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1163 cp2 = wp_rdapu(ch->parent, 1, APUREG_CURPTR);
1165 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1166 if (diff > 1 /* && diff < halfsize*/ )
1167 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1173 calc_timer_div(struct agg_chinfo *ch)
1180 printf("snd_maestro: pch[%d].speed == 0, which shouldn't\n",
1185 return (48000 * (ch->blklen << (!ch->qs16 + !ch->stereo))
1186 + speed - 1) / speed;
1190 calc_timer_div_rch(struct agg_rchinfo *ch)
1197 printf("snd_maestro: rch.speed == 0, which shouldn't\n");
1201 return (48000 * (ch->blklen << (!ch->stereo))
1202 + speed - 1) / speed;
1206 set_timer(struct agg_info *ess)
1209 u_int dv = 32 << 7, newdv;
1211 for (i = 0; i < ess->playchns; i++)
1212 if ((ess->active & (1 << i)) &&
1213 (dv > (newdv = calc_timer_div(ess->pch + i))))
1215 if ((ess->active & (1 << i)) &&
1216 (dv > (newdv = calc_timer_div_rch(&ess->rch))))
1219 wp_settimer(ess, dv);
1222 /* -----------------------------
1226 /* AC97 mixer interface. */
1229 agg_ac97_init(kobj_t obj, void *sc)
1231 struct agg_info *ess = sc;
1233 return (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK)? 0 : 1;
1237 agg_ac97_read(kobj_t obj, void *sc, int regno)
1239 struct agg_info *ess = sc;
1242 /* XXX sound locking violation: agg_lock(ess); */
1243 ret = agg_rdcodec(ess, regno);
1244 /* agg_unlock(ess); */
1249 agg_ac97_write(kobj_t obj, void *sc, int regno, u_int32_t data)
1251 struct agg_info *ess = sc;
1254 /* XXX sound locking violation: agg_lock(ess); */
1255 ret = agg_wrcodec(ess, regno, data);
1256 /* agg_unlock(ess); */
1260 static kobj_method_t agg_ac97_methods[] = {
1261 KOBJMETHOD(ac97_init, agg_ac97_init),
1262 KOBJMETHOD(ac97_read, agg_ac97_read),
1263 KOBJMETHOD(ac97_write, agg_ac97_write),
1266 AC97_DECLARE(agg_ac97);
1268 /* -------------------------------------------------------------------- */
1270 /* Playback channel. */
1273 aggpch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
1274 struct pcm_channel *c, int dir)
1276 struct agg_info *ess = devinfo;
1277 struct agg_chinfo *ch;
1278 bus_addr_t physaddr;
1281 KASSERT((dir == PCMDIR_PLAY),
1282 ("aggpch_init() called for RECORDING channel!"));
1283 ch = ess->pch + ess->playchns;
1288 ch->num = ess->playchns;
1290 p = dma_malloc(ess->buf_dmat, ess->bufsz, &physaddr, &ch->map);
1293 ch->phys = physaddr;
1294 ch->base = physaddr & ((~(bus_addr_t)0) << WAVCACHE_BASEADDR_SHIFT);
1296 sndbuf_setup(b, p, ess->bufsz);
1297 ch->blklen = sndbuf_getblksz(b) / 2;
1298 ch->buflen = sndbuf_getsize(b) / 2;
1305 adjust_pchbase(struct agg_chinfo *chans, u_int n, u_int size)
1307 struct agg_chinfo *pchs[AGG_MAXPLAYCH];
1311 /* sort pchs by phys address */
1312 for (i = 0; i < n; i++) {
1313 for (j = 0; j < i; j++)
1314 if (chans[i].phys < pchs[j]->phys) {
1315 for (k = i; k > j; k--)
1316 pchs[k] = pchs[k - 1];
1319 pchs[j] = chans + i;
1322 /* use new base register if next buffer can not be addressed
1323 via current base. */
1324 #define BASE_SHIFT (WPWA_WTBAR_SHIFT(2) + 2 + 1)
1325 base = pchs[0]->base;
1326 for (k = 1, i = 1; i < n; i++) {
1327 if (pchs[i]->phys + size - base >= 1 << BASE_SHIFT)
1328 /* not addressable: assign new base */
1329 base = (pchs[i]->base -= k++ << BASE_SHIFT);
1331 pchs[i]->base = base;
1336 printf("Total of %d bases are assigned.\n", k);
1337 for (i = 0; i < n; i++) {
1338 printf("ch.%d: phys 0x%llx, wpwa 0x%llx\n",
1339 i, (long long)chans[i].phys,
1340 (long long)(chans[i].phys -
1341 chans[i].base) >> 1);
1347 aggpch_free(kobj_t obj, void *data)
1349 struct agg_chinfo *ch = data;
1350 struct agg_info *ess = ch->parent;
1352 /* free up buffer - called after channel stopped */
1353 dma_free(ess->buf_dmat, sndbuf_getbuf(ch->buffer), ch->map);
1355 /* return 0 if ok */
1360 aggpch_setformat(kobj_t obj, void *data, u_int32_t format)
1362 struct agg_chinfo *ch = data;
1364 if (format & AFMT_BIGENDIAN || format & AFMT_U16_LE)
1366 ch->stereo = ch->qs16 = ch->us = 0;
1367 if (AFMT_CHANNEL(format) > 1)
1370 if (format & AFMT_U8 || format & AFMT_S8) {
1371 if (format & AFMT_U8)
1379 aggpch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1382 ((struct agg_chinfo*)data)->speed = speed;
1388 aggpch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1390 struct agg_chinfo *ch = data;
1393 /* try to keep at least 20msec DMA space */
1394 blkcnt = (ch->speed << (ch->stereo + ch->qs16)) / (50 * blocksize);
1395 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1397 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1398 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1399 blkcnt = sndbuf_getblkcnt(ch->buffer);
1400 blocksize = sndbuf_getblksz(ch->buffer);
1402 sndbuf_setblkcnt(ch->buffer, blkcnt);
1403 sndbuf_setblksz(ch->buffer, blocksize);
1406 ch->blklen = blocksize / 2;
1407 ch->buflen = blkcnt * blocksize / 2;
1412 aggpch_trigger(kobj_t obj, void *data, int go)
1414 struct agg_chinfo *ch = data;
1417 case PCMTRIG_EMLDMAWR:
1420 aggch_start_dac(ch);
1431 aggpch_getptr(kobj_t obj, void *data)
1433 struct agg_chinfo *ch = data;
1436 agg_lock(ch->parent);
1437 cp = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1438 agg_unlock(ch->parent);
1440 return ch->qs16 && ch->stereo
1441 ? (cp << 2) - ((0xffff << 2) & (ch->phys - ch->base))
1442 : (cp << 1) - ((0xffff << 1) & (ch->phys - ch->base));
1445 static struct pcmchan_caps *
1446 aggpch_getcaps(kobj_t obj, void *data)
1448 static u_int32_t playfmt[] = {
1449 SND_FORMAT(AFMT_U8, 1, 0),
1450 SND_FORMAT(AFMT_U8, 2, 0),
1451 SND_FORMAT(AFMT_S8, 1, 0),
1452 SND_FORMAT(AFMT_S8, 2, 0),
1453 SND_FORMAT(AFMT_S16_LE, 1, 0),
1454 SND_FORMAT(AFMT_S16_LE, 2, 0),
1457 static struct pcmchan_caps playcaps = {8000, 48000, playfmt, 0};
1462 static kobj_method_t aggpch_methods[] = {
1463 KOBJMETHOD(channel_init, aggpch_init),
1464 KOBJMETHOD(channel_free, aggpch_free),
1465 KOBJMETHOD(channel_setformat, aggpch_setformat),
1466 KOBJMETHOD(channel_setspeed, aggpch_setspeed),
1467 KOBJMETHOD(channel_setblocksize, aggpch_setblocksize),
1468 KOBJMETHOD(channel_trigger, aggpch_trigger),
1469 KOBJMETHOD(channel_getptr, aggpch_getptr),
1470 KOBJMETHOD(channel_getcaps, aggpch_getcaps),
1473 CHANNEL_DECLARE(aggpch);
1475 /* -------------------------------------------------------------------- */
1477 /* Recording channel. */
1480 aggrch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
1481 struct pcm_channel *c, int dir)
1483 struct agg_info *ess = devinfo;
1484 struct agg_rchinfo *ch;
1487 KASSERT((dir == PCMDIR_REC),
1488 ("aggrch_init() called for PLAYBACK channel!"));
1495 /* Uses the bottom-half of the status buffer. */
1496 p = ess->stat + ess->bufsz;
1497 ch->phys = ess->phys + ess->bufsz;
1498 ch->base = ess->phys;
1499 ch->src = (int16_t *)(p + ess->bufsz);
1500 ch->srcphys = ch->phys + ess->bufsz;
1501 ch->sink = (int16_t *)p;
1503 sndbuf_setup(b, p, ess->bufsz);
1504 ch->blklen = sndbuf_getblksz(b) / 2;
1505 ch->buflen = sndbuf_getsize(b) / 2;
1511 aggrch_setformat(kobj_t obj, void *data, u_int32_t format)
1513 struct agg_rchinfo *ch = data;
1515 if (!(format & AFMT_S16_LE))
1517 if (AFMT_CHANNEL(format) > 1)
1525 aggrch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1528 ((struct agg_rchinfo*)data)->speed = speed;
1534 aggrch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1536 struct agg_rchinfo *ch = data;
1539 /* try to keep at least 20msec DMA space */
1540 blkcnt = (ch->speed << ch->stereo) / (25 * blocksize);
1541 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1543 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1544 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1545 blkcnt = sndbuf_getblkcnt(ch->buffer);
1546 blocksize = sndbuf_getblksz(ch->buffer);
1548 sndbuf_setblkcnt(ch->buffer, blkcnt);
1549 sndbuf_setblksz(ch->buffer, blocksize);
1552 ch->blklen = blocksize / 2;
1553 ch->buflen = blkcnt * blocksize / 2;
1558 aggrch_trigger(kobj_t obj, void *sc, int go)
1560 struct agg_rchinfo *ch = sc;
1563 case PCMTRIG_EMLDMARD:
1565 aggch_feed_adc_stereo(ch);
1567 aggch_feed_adc_mono(ch);
1570 aggch_start_adc(ch);
1581 aggrch_getptr(kobj_t obj, void *sc)
1583 struct agg_rchinfo *ch = sc;
1585 return ch->stereo? ch->hwptr << 2 : ch->hwptr << 1;
1588 static struct pcmchan_caps *
1589 aggrch_getcaps(kobj_t obj, void *sc)
1591 static u_int32_t recfmt[] = {
1592 SND_FORMAT(AFMT_S16_LE, 1, 0),
1593 SND_FORMAT(AFMT_S16_LE, 2, 0),
1596 static struct pcmchan_caps reccaps = {8000, 48000, recfmt, 0};
1601 static kobj_method_t aggrch_methods[] = {
1602 KOBJMETHOD(channel_init, aggrch_init),
1603 /* channel_free: no-op */
1604 KOBJMETHOD(channel_setformat, aggrch_setformat),
1605 KOBJMETHOD(channel_setspeed, aggrch_setspeed),
1606 KOBJMETHOD(channel_setblocksize, aggrch_setblocksize),
1607 KOBJMETHOD(channel_trigger, aggrch_trigger),
1608 KOBJMETHOD(channel_getptr, aggrch_getptr),
1609 KOBJMETHOD(channel_getcaps, aggrch_getcaps),
1612 CHANNEL_DECLARE(aggrch);
1614 /* -----------------------------
1621 struct agg_info* ess = sc;
1622 register u_int8_t status;
1626 status = AGG_RD(ess, PORT_HOSTINT_STAT, 1);
1630 /* Acknowledge intr. */
1631 AGG_WR(ess, PORT_HOSTINT_STAT, status, 1);
1633 if (status & HOSTINT_STAT_DSOUND) {
1634 #ifdef AGG_JITTER_CORRECTION
1637 if (ess->curpwr <= PCI_POWERSTATE_D1) {
1638 AGG_WR(ess, PORT_INT_STAT, 1, 2);
1639 #ifdef AGG_JITTER_CORRECTION
1640 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1641 if (ess->active & m)
1642 suppress_jitter(ess->pch + i);
1644 if (ess->active & m)
1645 suppress_rec_jitter(&ess->rch);
1648 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1649 if (ess->active & m) {
1650 if (ess->curpwr <= PCI_POWERSTATE_D1)
1651 chn_intr(ess->pch[i].channel);
1658 if ((ess->active & m)
1659 && ess->curpwr <= PCI_POWERSTATE_D1)
1660 chn_intr(ess->rch.channel);
1662 #ifdef AGG_JITTER_CORRECTION
1668 if (status & HOSTINT_STAT_HWVOL) {
1669 register u_int8_t event;
1672 event = AGG_RD(ess, PORT_HWVOL_MASTER, 1);
1673 AGG_WR(ess, PORT_HWVOL_MASTER, HWVOL_NOP, 1);
1678 mixer_hwvol_step(ess->dev, 1, 1);
1681 mixer_hwvol_step(ess->dev, -1, -1);
1686 if (event & HWVOL_MUTE) {
1687 mixer_hwvol_mute(ess->dev);
1690 device_printf(ess->dev,
1691 "%s: unknown HWVOL event 0x%x\n",
1692 device_get_nameunit(ess->dev), event);
1698 setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1700 bus_addr_t *phys = arg;
1702 *phys = error? 0 : segs->ds_addr;
1705 printf("setmap (%lx, %lx), nseg=%d, error=%d\n",
1706 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
1712 dma_malloc(bus_dma_tag_t dmat, u_int32_t sz, bus_addr_t *phys,
1717 if (bus_dmamem_alloc(dmat, &buf, BUS_DMA_NOWAIT, map))
1719 if (bus_dmamap_load(dmat, *map, buf, sz, setmap, phys,
1720 BUS_DMA_NOWAIT) != 0 || *phys == 0) {
1721 bus_dmamem_free(dmat, buf, *map);
1728 dma_free(bus_dma_tag_t dmat, void *buf, bus_dmamap_t map)
1730 bus_dmamap_unload(dmat, map);
1731 bus_dmamem_free(dmat, buf, map);
1735 agg_probe(device_t dev)
1739 switch (pci_get_devid(dev)) {
1740 case MAESTRO_1_PCI_ID:
1741 s = "ESS Technology Maestro-1";
1744 case MAESTRO_2_PCI_ID:
1745 s = "ESS Technology Maestro-2";
1748 case MAESTRO_2E_PCI_ID:
1749 s = "ESS Technology Maestro-2E";
1753 if (s != NULL && pci_get_class(dev) == PCIC_MULTIMEDIA) {
1754 device_set_desc(dev, s);
1755 return BUS_PROBE_DEFAULT;
1761 agg_attach(device_t dev)
1763 struct agg_info *ess = NULL;
1765 int regid = PCIR_BAR(0);
1766 struct resource *reg = NULL;
1767 struct ac97_info *codec = NULL;
1769 struct resource *irq = NULL;
1771 char status[SND_STATUSLEN];
1774 ess = malloc(sizeof(*ess), M_DEVBUF, M_WAITOK | M_ZERO);
1777 mtx_init(&ess->lock, device_get_desc(dev), "snd_maestro softc",
1778 MTX_DEF | MTX_RECURSE);
1780 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
1781 "dac", &dacn) == 0) {
1784 else if (dacn > AGG_MAXPLAYCH)
1785 dacn = AGG_MAXPLAYCH;
1787 dacn = AGG_MAXPLAYCH;
1789 ess->bufsz = pcm_getbuffersize(dev, 4096, AGG_DEFAULT_BUFSZ, 65536);
1790 if (bus_dma_tag_create(/*parent*/ bus_get_dma_tag(dev),
1791 /*align */ 4, 1 << (16+1),
1792 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1793 /*filter*/ NULL, NULL,
1794 /*size */ ess->bufsz, 1, 0x3ffff,
1796 /*lock */ NULL, NULL,
1797 &ess->buf_dmat) != 0) {
1798 device_printf(dev, "unable to create dma tag\n");
1803 if (bus_dma_tag_create(/*parent*/ bus_get_dma_tag(dev),
1804 /*align */ 1 << WAVCACHE_BASEADDR_SHIFT,
1806 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1807 /*filter*/ NULL, NULL,
1808 /*size */ 3*ess->bufsz, 1, 0x3ffff,
1810 /*lock */ NULL, NULL,
1811 &ess->stat_dmat) != 0) {
1812 device_printf(dev, "unable to create dma tag\n");
1817 /* Allocate the room for brain-damaging status buffer. */
1818 ess->stat = dma_malloc(ess->stat_dmat, 3*ess->bufsz, &ess->phys,
1820 if (ess->stat == NULL) {
1821 device_printf(dev, "cannot allocate status buffer\n");
1826 device_printf(dev, "Maestro status/record buffer: %#llx\n",
1827 (long long)ess->phys);
1829 /* State D0-uninitialized. */
1830 ess->curpwr = PCI_POWERSTATE_D3;
1831 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1833 pci_enable_busmaster(dev);
1835 /* Allocate resources. */
1836 reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, ®id, RF_ACTIVE);
1840 ess->st = rman_get_bustag(reg);
1841 ess->sh = rman_get_bushandle(reg);
1843 device_printf(dev, "unable to map register space\n");
1847 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqid,
1848 RF_ACTIVE | RF_SHAREABLE);
1853 device_printf(dev, "unable to map interrupt\n");
1858 /* Setup resources. */
1859 if (snd_setup_intr(dev, irq, INTR_MPSAFE, agg_intr, ess, &ih)) {
1860 device_printf(dev, "unable to setup interrupt\n");
1866 /* Transition from D0-uninitialized to D0. */
1868 agg_power(ess, PCI_POWERSTATE_D0);
1869 if (agg_rdcodec(ess, 0) == 0x80) {
1870 /* XXX - TODO: PT101 */
1872 device_printf(dev, "PT101 codec detected!\n");
1877 codec = AC97_CREATE(dev, ess, agg_ac97);
1878 if (codec == NULL) {
1879 device_printf(dev, "failed to create AC97 codec softc!\n");
1883 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) {
1884 device_printf(dev, "mixer initialization failed!\n");
1890 ret = pcm_register(dev, ess, dacn, 1);
1894 mixer_hwvol_init(dev);
1896 agg_power(ess, powerstate_init);
1898 for (data = 0; data < dacn; data++)
1899 pcm_addchan(dev, PCMDIR_PLAY, &aggpch_class, ess);
1900 pcm_addchan(dev, PCMDIR_REC, &aggrch_class, ess);
1901 adjust_pchbase(ess->pch, ess->playchns, ess->bufsz);
1903 snprintf(status, SND_STATUSLEN,
1904 "port 0x%jx-0x%jx irq %jd at device %d.%d on pci%d",
1905 rman_get_start(reg), rman_get_end(reg), rman_get_start(irq),
1906 pci_get_slot(dev), pci_get_function(dev), pci_get_bus(dev));
1907 pcm_setstatus(dev, status);
1913 ac97_destroy(codec);
1915 bus_teardown_intr(dev, irq, ih);
1917 bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
1919 bus_release_resource(dev, SYS_RES_IOPORT, regid, reg);
1921 if (ess->stat != NULL)
1922 dma_free(ess->stat_dmat, ess->stat, ess->stat_map);
1923 if (ess->stat_dmat != NULL)
1924 bus_dma_tag_destroy(ess->stat_dmat);
1925 if (ess->buf_dmat != NULL)
1926 bus_dma_tag_destroy(ess->buf_dmat);
1927 mtx_destroy(&ess->lock);
1928 free(ess, M_DEVBUF);
1935 agg_detach(device_t dev)
1937 struct agg_info *ess = pcm_getdevinfo(dev);
1941 icr = AGG_RD(ess, PORT_HOSTINT_CTRL, 2);
1942 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
1946 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1952 r = pcm_unregister(dev);
1954 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1959 agg_power(ess, PCI_POWERSTATE_D3);
1962 bus_teardown_intr(dev, ess->irq, ess->ih);
1963 bus_release_resource(dev, SYS_RES_IRQ, ess->irqid, ess->irq);
1964 bus_release_resource(dev, SYS_RES_IOPORT, ess->regid, ess->reg);
1965 dma_free(ess->stat_dmat, ess->stat, ess->stat_map);
1966 bus_dma_tag_destroy(ess->stat_dmat);
1967 bus_dma_tag_destroy(ess->buf_dmat);
1968 mtx_destroy(&ess->lock);
1969 free(ess, M_DEVBUF);
1974 agg_suspend(device_t dev)
1976 struct agg_info *ess = pcm_getdevinfo(dev);
1978 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
1980 agg_power(ess, PCI_POWERSTATE_D3);
1987 agg_resume(device_t dev)
1990 struct agg_info *ess = pcm_getdevinfo(dev);
1992 for (i = 0; i < ess->playchns; i++)
1993 if (ess->active & (1 << i))
1994 aggch_start_dac(ess->pch + i);
1995 if (ess->active & (1 << i))
1996 aggch_start_adc(&ess->rch);
2000 agg_power(ess, powerstate_init);
2003 if (mixer_reinit(dev)) {
2004 device_printf(dev, "unable to reinitialize the mixer\n");
2012 agg_shutdown(device_t dev)
2014 struct agg_info *ess = pcm_getdevinfo(dev);
2017 agg_power(ess, PCI_POWERSTATE_D3);
2023 static device_method_t agg_methods[] = {
2024 DEVMETHOD(device_probe, agg_probe),
2025 DEVMETHOD(device_attach, agg_attach),
2026 DEVMETHOD(device_detach, agg_detach),
2027 DEVMETHOD(device_suspend, agg_suspend),
2028 DEVMETHOD(device_resume, agg_resume),
2029 DEVMETHOD(device_shutdown, agg_shutdown),
2033 static driver_t agg_driver = {
2039 /*static devclass_t pcm_devclass;*/
2041 DRIVER_MODULE(snd_maestro, pci, agg_driver, pcm_devclass, 0, 0);
2042 MODULE_DEPEND(snd_maestro, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2043 MODULE_VERSION(snd_maestro, 1);