2 * Copyright (c) 2000-2004 Taku YAMAMOTO <taku@tackymt.homeip.net>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * maestro.c,v 1.23.2.1 2003/10/03 18:21:38 taku Exp
32 * Part of this code (especially in many magic numbers) was heavily inspired
33 * by the Linux driver originally written by
34 * Alan Cox <alan.cox@linux.org>, modified heavily by
35 * Zach Brown <zab@zabbo.net>.
37 * busdma()-ize and buffer size reduction were suggested by
38 * Cameron Grant <cg@freebsd.org>.
39 * Also he showed me the way to use busdma() suite.
41 * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
43 * Munehiro Matsuda <haro@tk.kubota.co.jp>,
44 * who brought patches based on the Linux driver with some simplification.
46 * Hardware volume controller was implemented by
47 * John Baldwin <jhb@freebsd.org>.
50 #ifdef HAVE_KERNEL_OPTION_HEADERS
54 #include <dev/sound/pcm/sound.h>
55 #include <dev/sound/pcm/ac97.h>
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pcivar.h>
59 #include <dev/sound/pci/maestro_reg.h>
61 SND_DECLARE_FILE("$FreeBSD$");
64 * PCI IDs of supported chips:
66 * MAESTRO-1 0x01001285
67 * MAESTRO-2 0x1968125d
68 * MAESTRO-2E 0x1978125d
71 #define MAESTRO_1_PCI_ID 0x01001285
72 #define MAESTRO_2_PCI_ID 0x1968125d
73 #define MAESTRO_2E_PCI_ID 0x1978125d
75 #define NEC_SUBID1 0x80581033 /* Taken from Linux driver */
76 #define NEC_SUBID2 0x803c1033 /* NEC VersaProNX VA26D */
79 # if AGG_MAXPLAYCH > 4
81 # define AGG_MAXPLAYCH 4
84 # define AGG_MAXPLAYCH 4
87 #define AGG_DEFAULT_BUFSZ 0x4000 /* 0x1000, but gets underflows */
91 #define PCIR_BAR(x) (PCIR_MAPS + (x) * 4)
95 /* -----------------------------
100 struct agg_info *parent;
102 /* FreeBSD newpcm related */
103 struct pcm_channel *channel;
104 struct snd_dbuf *buffer;
108 bus_addr_t phys; /* channel buffer physical address */
109 bus_addr_t base; /* channel buffer segment base */
110 u_int32_t blklen; /* DMA block length in WORDs */
111 u_int32_t buflen; /* channel buffer length in WORDs */
115 unsigned qs16 : 1; /* quantum size is 16bit */
116 unsigned us : 1; /* in unsigned format */
121 struct agg_info *parent;
123 /* FreeBSD newpcm related */
124 struct pcm_channel *channel;
125 struct snd_dbuf *buffer;
129 bus_addr_t phys; /* channel buffer physical address */
130 bus_addr_t base; /* channel buffer segment base */
131 u_int32_t blklen; /* DMA block length in WORDs */
132 u_int32_t buflen; /* channel buffer length in WORDs */
137 int16_t *src; /* stereo peer buffer */
138 int16_t *sink; /* channel buffer pointer */
139 volatile u_int32_t hwptr; /* ready point in 16bit sample */
143 /* FreeBSD newbus related */
146 /* I wonder whether bus_space_* are in common in *BSD... */
147 struct resource *reg;
150 bus_space_handle_t sh;
152 struct resource *irq;
156 bus_dma_tag_t buf_dmat;
157 bus_dma_tag_t stat_dmat;
159 /* FreeBSD SMPng related */
160 struct mtx lock; /* mutual exclusion */
161 /* FreeBSD newpcm related */
162 struct ac97_info *codec;
165 bus_dmamap_t stat_map;
166 u_int8_t *stat; /* status buffer pointer */
167 bus_addr_t phys; /* status buffer physical address */
168 unsigned int bufsz; /* channel buffer size in bytes */
170 volatile u_int active;
171 struct agg_chinfo pch[AGG_MAXPLAYCH];
172 struct agg_rchinfo rch;
173 volatile u_int8_t curpwr; /* current power status: D[0-3] */
177 /* -----------------------------
180 static unsigned int powerstate_active = PCI_POWERSTATE_D1;
181 #ifdef MAESTRO_AGGRESSIVE_POWERSAVE
182 static unsigned int powerstate_idle = PCI_POWERSTATE_D2;
184 static unsigned int powerstate_idle = PCI_POWERSTATE_D1;
186 static unsigned int powerstate_init = PCI_POWERSTATE_D2;
188 /* XXX: this should move to a device specific sysctl dev.pcm.X.debug.Y via
189 device_get_sysctl_*() as discussed on multimedia@ in msg-id
190 <861wujij2q.fsf@xps.des.no> */
191 static SYSCTL_NODE(_debug, OID_AUTO, maestro, CTLFLAG_RD, 0, "");
192 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_active, CTLFLAG_RW,
193 &powerstate_active, 0, "The Dx power state when active (0-1)");
194 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_idle, CTLFLAG_RW,
195 &powerstate_idle, 0, "The Dx power state when idle (0-2)");
196 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_init, CTLFLAG_RW,
198 "The Dx power state prior to the first use (0-2)");
201 /* -----------------------------
205 static void agg_sleep(struct agg_info*, const char *wmesg, int msec);
208 static __inline u_int32_t agg_rd(struct agg_info*, int, int size);
209 static __inline void agg_wr(struct agg_info*, int, u_int32_t data,
212 static int agg_rdcodec(struct agg_info*, int);
213 static int agg_wrcodec(struct agg_info*, int, u_int32_t);
215 static void ringbus_setdest(struct agg_info*, int, int);
217 static u_int16_t wp_rdreg(struct agg_info*, u_int16_t);
218 static void wp_wrreg(struct agg_info*, u_int16_t, u_int16_t);
219 static u_int16_t wp_rdapu(struct agg_info*, unsigned, u_int16_t);
220 static void wp_wrapu(struct agg_info*, unsigned, u_int16_t, u_int16_t);
221 static void wp_settimer(struct agg_info*, u_int);
222 static void wp_starttimer(struct agg_info*);
223 static void wp_stoptimer(struct agg_info*);
226 static u_int16_t wc_rdreg(struct agg_info*, u_int16_t);
228 static void wc_wrreg(struct agg_info*, u_int16_t, u_int16_t);
230 static u_int16_t wc_rdchctl(struct agg_info*, int);
232 static void wc_wrchctl(struct agg_info*, int, u_int16_t);
234 static void agg_stopclock(struct agg_info*, int part, int st);
236 static void agg_initcodec(struct agg_info*);
237 static void agg_init(struct agg_info*);
238 static void agg_power(struct agg_info*, int);
240 static void aggch_start_dac(struct agg_chinfo*);
241 static void aggch_stop_dac(struct agg_chinfo*);
242 static void aggch_start_adc(struct agg_rchinfo*);
243 static void aggch_stop_adc(struct agg_rchinfo*);
244 static void aggch_feed_adc_stereo(struct agg_rchinfo*);
245 static void aggch_feed_adc_mono(struct agg_rchinfo*);
247 #ifdef AGG_JITTER_CORRECTION
248 static void suppress_jitter(struct agg_chinfo*);
249 static void suppress_rec_jitter(struct agg_rchinfo*);
252 static void set_timer(struct agg_info*);
254 static void agg_intr(void *);
255 static int agg_probe(device_t);
256 static int agg_attach(device_t);
257 static int agg_detach(device_t);
258 static int agg_suspend(device_t);
259 static int agg_resume(device_t);
260 static int agg_shutdown(device_t);
262 static void *dma_malloc(bus_dma_tag_t, u_int32_t, bus_addr_t*,
264 static void dma_free(bus_dma_tag_t, void *, bus_dmamap_t);
267 /* -----------------------------
272 #define agg_lock(sc) snd_mtxlock(&((sc)->lock))
273 #define agg_unlock(sc) snd_mtxunlock(&((sc)->lock))
276 agg_sleep(struct agg_info *sc, const char *wmesg, int msec)
280 timo = msec * hz / 1000;
283 msleep(sc, &sc->lock, PWAIT, wmesg, timo);
290 static __inline u_int32_t
291 agg_rd(struct agg_info *sc, int regno, int size)
295 return bus_space_read_1(sc->st, sc->sh, regno);
297 return bus_space_read_2(sc->st, sc->sh, regno);
299 return bus_space_read_4(sc->st, sc->sh, regno);
301 return ~(u_int32_t)0;
306 #define AGG_RD(sc, regno, size) \
307 bus_space_read_##size( \
308 ((struct agg_info*)(sc))->st, \
309 ((struct agg_info*)(sc))->sh, (regno))
313 agg_wr(struct agg_info *sc, int regno, u_int32_t data, int size)
317 bus_space_write_1(sc->st, sc->sh, regno, data);
320 bus_space_write_2(sc->st, sc->sh, regno, data);
323 bus_space_write_4(sc->st, sc->sh, regno, data);
329 #define AGG_WR(sc, regno, data, size) \
330 bus_space_write_##size( \
331 ((struct agg_info*)(sc))->st, \
332 ((struct agg_info*)(sc))->sh, (regno), (data))
334 /* -------------------------------------------------------------------- */
339 agg_codec_wait4idle(struct agg_info *ess)
343 while (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK) {
346 DELAY(2); /* 20.8us / 13 */
353 agg_rdcodec(struct agg_info *ess, int regno)
357 /* We have to wait for a SAFE time to write addr/data */
358 if (agg_codec_wait4idle(ess)) {
359 /* Timed out. No read performed. */
360 device_printf(ess->dev, "agg_rdcodec() PROGLESS timed out.\n");
364 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_READ | regno, 1);
365 /*DELAY(21); * AC97 cycle = 20.8usec */
367 /* Wait for data retrieve */
368 if (!agg_codec_wait4idle(ess)) {
369 ret = AGG_RD(ess, PORT_CODEC_REG, 2);
371 /* Timed out. No read performed. */
372 device_printf(ess->dev, "agg_rdcodec() RW_DONE timed out.\n");
380 agg_wrcodec(struct agg_info *ess, int regno, u_int32_t data)
382 /* We have to wait for a SAFE time to write addr/data */
383 if (agg_codec_wait4idle(ess)) {
384 /* Timed out. Abort writing. */
385 device_printf(ess->dev, "agg_wrcodec() PROGLESS timed out.\n");
389 AGG_WR(ess, PORT_CODEC_REG, data, 2);
390 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_WRITE | regno, 1);
392 /* Wait for write completion */
393 if (agg_codec_wait4idle(ess)) {
395 device_printf(ess->dev, "agg_wrcodec() RW_DONE timed out.\n");
403 ringbus_setdest(struct agg_info *ess, int src, int dest)
407 data = AGG_RD(ess, PORT_RINGBUS_CTRL, 4);
408 data &= ~(0xfU << src);
409 data |= (0xfU & dest) << src;
410 AGG_WR(ess, PORT_RINGBUS_CTRL, data, 4);
413 /* -------------------------------------------------------------------- */
418 wp_rdreg(struct agg_info *ess, u_int16_t reg)
420 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
421 return AGG_RD(ess, PORT_DSP_DATA, 2);
425 wp_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
427 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
428 AGG_WR(ess, PORT_DSP_DATA, data, 2);
432 wp_wait_data(struct agg_info *ess, u_int16_t data)
436 while (AGG_RD(ess, PORT_DSP_DATA, 2) != data) {
440 AGG_WR(ess, PORT_DSP_DATA, data, 2);
447 wp_rdapu(struct agg_info *ess, unsigned ch, u_int16_t reg)
449 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
450 if (wp_wait_data(ess, reg | (ch << 4)) != 0)
451 device_printf(ess->dev, "wp_rdapu() indexing timed out.\n");
452 return wp_rdreg(ess, WPREG_DATA_PORT);
456 wp_wrapu(struct agg_info *ess, unsigned ch, u_int16_t reg, u_int16_t data)
458 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
459 if (wp_wait_data(ess, reg | (ch << 4)) == 0) {
460 wp_wrreg(ess, WPREG_DATA_PORT, data);
461 if (wp_wait_data(ess, data) != 0)
462 device_printf(ess->dev,
463 "wp_wrapu() write timed out.\n");
465 device_printf(ess->dev, "wp_wrapu() indexing timed out.\n");
470 apu_setparam(struct agg_info *ess, int apuch,
471 u_int32_t wpwa, u_int16_t size, int16_t pan, u_int dv)
473 wp_wrapu(ess, apuch, APUREG_WAVESPACE, (wpwa >> 8) & APU_64KPAGE_MASK);
474 wp_wrapu(ess, apuch, APUREG_CURPTR, wpwa);
475 wp_wrapu(ess, apuch, APUREG_ENDPTR, wpwa + size);
476 wp_wrapu(ess, apuch, APUREG_LOOPLEN, size);
477 wp_wrapu(ess, apuch, APUREG_ROUTING, 0);
478 wp_wrapu(ess, apuch, APUREG_AMPLITUDE, 0xf000);
479 wp_wrapu(ess, apuch, APUREG_POSITION, 0x8f00
480 | (APU_RADIUS_MASK & (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT))
481 | (APU_PAN_MASK & ((pan + PAN_FRONT) << APU_PAN_SHIFT)));
482 wp_wrapu(ess, apuch, APUREG_FREQ_LOBYTE,
483 APU_plus6dB | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT));
484 wp_wrapu(ess, apuch, APUREG_FREQ_HIWORD, dv >> 8);
488 wp_settimer(struct agg_info *ess, u_int divide)
492 RANGE(divide, 2, 32 << 7);
494 for (; divide > 32; divide >>= 1) {
499 for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1)
502 wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
503 wp_wrreg(ess, WPREG_TIMER_FREQ, 0x9000 |
504 (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1));
505 wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
509 wp_starttimer(struct agg_info *ess)
511 AGG_WR(ess, PORT_INT_STAT, 1, 2);
512 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_INT_ENABLED
513 | AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
514 wp_wrreg(ess, WPREG_TIMER_START, 1);
518 wp_stoptimer(struct agg_info *ess)
520 AGG_WR(ess, PORT_HOSTINT_CTRL, ~HOSTINT_CTRL_DSOUND_INT_ENABLED
521 & AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
522 AGG_WR(ess, PORT_INT_STAT, 1, 2);
523 wp_wrreg(ess, WPREG_TIMER_START, 0);
526 /* -------------------------------------------------------------------- */
532 wc_rdreg(struct agg_info *ess, u_int16_t reg)
534 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
535 return AGG_RD(ess, PORT_WAVCACHE_DATA, 2);
540 wc_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
542 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
543 AGG_WR(ess, PORT_WAVCACHE_DATA, data, 2);
548 wc_rdchctl(struct agg_info *ess, int ch)
550 return wc_rdreg(ess, ch << 3);
555 wc_wrchctl(struct agg_info *ess, int ch, u_int16_t data)
557 wc_wrreg(ess, ch << 3, data);
560 /* -------------------------------------------------------------------- */
562 /* Power management */
564 agg_stopclock(struct agg_info *ess, int part, int st)
568 data = pci_read_config(ess->dev, CONF_ACPI_STOPCLOCK, 4);
570 if (st == PCI_POWERSTATE_D1)
571 data &= ~(1 << part);
574 if (st == PCI_POWERSTATE_D1 || st == PCI_POWERSTATE_D2)
575 data |= (0x10000 << part);
577 data &= ~(0x10000 << part);
578 pci_write_config(ess->dev, CONF_ACPI_STOPCLOCK, data, 4);
583 /* -----------------------------
588 agg_initcodec(struct agg_info* ess)
592 if (AGG_RD(ess, PORT_RINGBUS_CTRL, 4) & RINGBUS_CTRL_ACLINK_ENABLED) {
593 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
594 DELAY(104); /* 20.8us * (4 + 1) */
596 /* XXX - 2nd codec should be looked at. */
597 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_AC97_SWRESET, 4);
599 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
602 if (agg_rdcodec(ess, 0) < 0) {
603 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
606 /* Try cold reset. */
607 device_printf(ess->dev, "will perform cold reset.\n");
608 data = AGG_RD(ess, PORT_GPIO_DIR, 2);
609 if (pci_read_config(ess->dev, 0x58, 2) & 1)
611 data |= 0x009 & ~AGG_RD(ess, PORT_GPIO_DATA, 2);
612 AGG_WR(ess, PORT_GPIO_MASK, 0xff6, 2);
613 AGG_WR(ess, PORT_GPIO_DIR, data | 0x009, 2);
614 AGG_WR(ess, PORT_GPIO_DATA, 0x000, 2);
616 AGG_WR(ess, PORT_GPIO_DATA, 0x001, 2);
618 AGG_WR(ess, PORT_GPIO_DATA, 0x009, 2);
619 agg_sleep(ess, "agginicd", 500);
620 AGG_WR(ess, PORT_GPIO_DIR, data, 2);
621 DELAY(84); /* 20.8us * 4 */
622 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
628 agg_init(struct agg_info* ess)
632 /* Setup PCI config registers. */
634 /* Disable all legacy emulations. */
635 data = pci_read_config(ess->dev, CONF_LEGACY, 2);
636 data |= LEGACY_DISABLED;
637 pci_write_config(ess->dev, CONF_LEGACY, data, 2);
639 /* Disconnect from CHI. (Makes Dell inspiron 7500 work?)
640 * Enable posted write.
641 * Prefer PCI timing rather than that of ISA.
643 data = pci_read_config(ess->dev, CONF_MAESTRO, 4);
645 data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING;
646 data &= ~MAESTRO_SWAP_LR;
647 pci_write_config(ess->dev, CONF_MAESTRO, data, 4);
649 /* Turn off unused parts if necessary. */
650 /* consult CONF_MAESTRO. */
651 if (data & MAESTRO_SPDIF)
652 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D2);
654 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D1);
655 if (data & MAESTRO_HWVOL)
656 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D3);
658 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D1);
660 /* parts that never be used */
661 agg_stopclock(ess, ACPI_PART_978, PCI_POWERSTATE_D1);
662 agg_stopclock(ess, ACPI_PART_DAA, PCI_POWERSTATE_D1);
663 agg_stopclock(ess, ACPI_PART_GPIO, PCI_POWERSTATE_D1);
664 agg_stopclock(ess, ACPI_PART_SB, PCI_POWERSTATE_D1);
665 agg_stopclock(ess, ACPI_PART_FM, PCI_POWERSTATE_D1);
666 agg_stopclock(ess, ACPI_PART_MIDI, PCI_POWERSTATE_D1);
667 agg_stopclock(ess, ACPI_PART_GAME_PORT, PCI_POWERSTATE_D1);
669 /* parts that will be used only when play/recording */
670 agg_stopclock(ess, ACPI_PART_WP, PCI_POWERSTATE_D2);
672 /* parts that should always be turned on */
673 agg_stopclock(ess, ACPI_PART_CODEC_CLOCK, PCI_POWERSTATE_D3);
674 agg_stopclock(ess, ACPI_PART_GLUE, PCI_POWERSTATE_D3);
675 agg_stopclock(ess, ACPI_PART_PCI_IF, PCI_POWERSTATE_D3);
676 agg_stopclock(ess, ACPI_PART_RINGBUS, PCI_POWERSTATE_D3);
678 /* Reset direct sound. */
679 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_SOFT_RESET, 2);
681 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
683 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_RESET, 2);
685 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
688 /* Enable hardware volume control interruption. */
689 if (data & MAESTRO_HWVOL) /* XXX - why not use device flags? */
690 AGG_WR(ess, PORT_HOSTINT_CTRL,HOSTINT_CTRL_HWVOL_ENABLED, 2);
692 /* Setup Wave Processor. */
694 /* Enable WaveCache, set DMA base address. */
695 wp_wrreg(ess, WPREG_WAVE_ROMRAM,
696 WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED);
697 wp_wrreg(ess, WPREG_CRAM_DATA, 0);
699 AGG_WR(ess, PORT_WAVCACHE_CTRL,
700 WAVCACHE_ENABLED | WAVCACHE_WTSIZE_2MB | WAVCACHE_SGC_32_47, 2);
702 for (data = WAVCACHE_PCMBAR; data < WAVCACHE_PCMBAR + 4; data++)
703 wc_wrreg(ess, data, ess->phys >> WAVCACHE_BASEADDR_SHIFT);
705 /* Setup Codec/Ringbus. */
707 AGG_WR(ess, PORT_RINGBUS_CTRL,
708 RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED, 4);
710 wp_wrreg(ess, 0x08, 0xB004);
711 wp_wrreg(ess, 0x09, 0x001B);
712 wp_wrreg(ess, 0x0A, 0x8000);
713 wp_wrreg(ess, 0x0B, 0x3F37);
714 wp_wrreg(ess, WPREG_BASE, 0x8598); /* Parallel I/O */
715 wp_wrreg(ess, WPREG_BASE + 1, 0x7632);
716 ringbus_setdest(ess, RINGBUS_SRC_ADC,
717 RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN);
718 ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
719 RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC);
721 /* Enable S/PDIF if necessary. */
722 if (pci_read_config(ess->dev, CONF_MAESTRO, 4) & MAESTRO_SPDIF)
723 /* XXX - why not use device flags? */
724 AGG_WR(ess, PORT_RINGBUS_CTRL_B, RINGBUS_CTRL_SPDIF |
725 AGG_RD(ess, PORT_RINGBUS_CTRL_B, 1), 1);
727 /* Setup ASSP. Needed for Dell Inspiron 7500? */
728 AGG_WR(ess, PORT_ASSP_CTRL_B, 0x00, 1);
729 AGG_WR(ess, PORT_ASSP_CTRL_A, 0x03, 1);
730 AGG_WR(ess, PORT_ASSP_CTRL_C, 0x00, 1);
734 * There seems to be speciality with NEC systems.
736 switch (pci_get_subvendor(ess->dev)
737 | (pci_get_subdevice(ess->dev) << 16)) {
740 /* Matthew Braithwaite <matt@braithwaite.net> reported that
741 * NEC Versa LX doesn't need GPIO operation. */
742 AGG_WR(ess, PORT_GPIO_MASK, 0x9ff, 2);
743 AGG_WR(ess, PORT_GPIO_DIR,
744 AGG_RD(ess, PORT_GPIO_DIR, 2) | 0x600, 2);
745 AGG_WR(ess, PORT_GPIO_DATA, 0x200, 2);
750 /* Deals power state transition. Must be called with softc->lock held. */
752 agg_power(struct agg_info *ess, int status)
756 lastpwr = ess->curpwr;
757 if (lastpwr == status)
761 case PCI_POWERSTATE_D0:
762 case PCI_POWERSTATE_D1:
764 case PCI_POWERSTATE_D2:
765 pci_set_powerstate(ess->dev, status);
766 /* Turn on PCM-related parts. */
767 agg_wrcodec(ess, AC97_REG_POWER, 0);
770 if ((agg_rdcodec(ess, AC97_REG_POWER) & 3) != 3)
771 device_printf(ess->dev,
772 "warning: codec not ready.\n");
774 AGG_WR(ess, PORT_RINGBUS_CTRL,
775 (AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
776 & ~RINGBUS_CTRL_ACLINK_ENABLED)
777 | RINGBUS_CTRL_RINGBUS_ENABLED, 4);
779 AGG_WR(ess, PORT_RINGBUS_CTRL,
780 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
781 | RINGBUS_CTRL_ACLINK_ENABLED, 4);
783 case PCI_POWERSTATE_D3:
785 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
789 case PCI_POWERSTATE_D0:
790 case PCI_POWERSTATE_D1:
791 pci_set_powerstate(ess->dev, status);
795 case PCI_POWERSTATE_D2:
797 case PCI_POWERSTATE_D3:
799 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
803 case PCI_POWERSTATE_D0:
804 case PCI_POWERSTATE_D1:
805 /* Turn off PCM-related parts. */
806 AGG_WR(ess, PORT_RINGBUS_CTRL,
807 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
808 & ~RINGBUS_CTRL_RINGBUS_ENABLED, 4);
810 agg_wrcodec(ess, AC97_REG_POWER, 0x300);
814 pci_set_powerstate(ess->dev, status);
816 case PCI_POWERSTATE_D3:
817 /* Entirely power down. */
818 agg_wrcodec(ess, AC97_REG_POWER, 0xdf00);
820 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
822 if (lastpwr != PCI_POWERSTATE_D2)
824 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
825 AGG_WR(ess, PORT_HOSTINT_STAT, 0xff, 1);
826 pci_set_powerstate(ess->dev, status);
829 /* Invalid power state; let it ignored. */
834 ess->curpwr = status;
837 /* -------------------------------------------------------------------- */
839 /* Channel controller. */
842 aggch_start_dac(struct agg_chinfo *ch)
846 u_int16_t size, apuch, wtbar, wcreg, aputype;
851 wpwa = (ch->phys - ch->base) >> 1;
852 wtbar = 0xc & (wpwa >> WPWA_WTBAR_SHIFT(2));
853 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
855 apuch = (ch->num << 1) | 32;
856 pan = PAN_RIGHT - PAN_FRONT;
859 wcreg |= WAVCACHE_CHCTL_STEREO;
861 aputype = APUTYPE_16BITSTEREO;
866 aputype = APUTYPE_8BITSTEREO;
870 aputype = APUTYPE_16BITLINEAR;
872 aputype = APUTYPE_8BITLINEAR;
877 wcreg |= WAVCACHE_CHCTL_U8;
880 wtbar = (wtbar >> 1) + 4;
882 dv = (((speed % 48000) << 16) + 24000) / 48000
883 + ((speed / 48000) << 16);
885 agg_lock(ch->parent);
886 agg_power(ch->parent, powerstate_active);
888 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar,
889 ch->base >> WAVCACHE_BASEADDR_SHIFT);
890 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 1,
891 ch->base >> WAVCACHE_BASEADDR_SHIFT);
893 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 2,
894 ch->base >> WAVCACHE_BASEADDR_SHIFT);
895 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 3,
896 ch->base >> WAVCACHE_BASEADDR_SHIFT);
898 wc_wrchctl(ch->parent, apuch, wcreg);
899 wc_wrchctl(ch->parent, apuch + 1, wcreg);
901 apu_setparam(ch->parent, apuch, wpwa, size, pan, dv);
904 wpwa |= (WPWA_STEREO >> 1);
905 apu_setparam(ch->parent, apuch + 1, wpwa, size, -pan, dv);
908 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
909 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
910 wp_wrapu(ch->parent, apuch + 1, APUREG_APUTYPE,
911 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
914 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
915 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
918 /* to mark that this channel is ready for intr. */
919 ch->parent->active |= (1 << ch->num);
921 set_timer(ch->parent);
922 wp_starttimer(ch->parent);
923 agg_unlock(ch->parent);
927 aggch_stop_dac(struct agg_chinfo *ch)
929 agg_lock(ch->parent);
931 /* to mark that this channel no longer needs further intrs. */
932 ch->parent->active &= ~(1 << ch->num);
934 wp_wrapu(ch->parent, (ch->num << 1) | 32, APUREG_APUTYPE,
935 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
936 wp_wrapu(ch->parent, (ch->num << 1) | 33, APUREG_APUTYPE,
937 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
939 if (ch->parent->active) {
940 set_timer(ch->parent);
941 wp_starttimer(ch->parent);
943 wp_stoptimer(ch->parent);
944 agg_power(ch->parent, powerstate_idle);
946 agg_unlock(ch->parent);
950 aggch_start_adc(struct agg_rchinfo *ch)
952 bus_addr_t wpwa, wpwa2;
953 u_int16_t wcreg, wcreg2;
957 /* speed > 48000 not cared */
958 dv = ((ch->speed << 16) + 24000) / 48000;
960 /* RATECONV doesn't seem to like dv == 0x10000. */
965 wpwa = (ch->srcphys - ch->base) >> 1;
966 wpwa2 = (ch->srcphys + ch->parent->bufsz/2 - ch->base) >> 1;
967 wcreg = (ch->srcphys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
968 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
969 pan = PAN_LEFT - PAN_FRONT;
971 wpwa = (ch->phys - ch->base) >> 1;
972 wpwa2 = (ch->srcphys - ch->base) >> 1;
973 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
974 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
978 agg_lock(ch->parent);
981 agg_power(ch->parent, powerstate_active);
983 /* Invalidate WaveCache. */
984 wc_wrchctl(ch->parent, 0, wcreg | WAVCACHE_CHCTL_STEREO);
985 wc_wrchctl(ch->parent, 1, wcreg | WAVCACHE_CHCTL_STEREO);
986 wc_wrchctl(ch->parent, 2, wcreg2 | WAVCACHE_CHCTL_STEREO);
987 wc_wrchctl(ch->parent, 3, wcreg2 | WAVCACHE_CHCTL_STEREO);
989 /* Load APU registers. */
990 /* APU #0 : Sample rate converter for left/center. */
991 apu_setparam(ch->parent, 0, WPWA_USE_SYSMEM | wpwa,
992 ch->buflen >> ch->stereo, 0, dv);
993 wp_wrapu(ch->parent, 0, APUREG_AMPLITUDE, 0);
994 wp_wrapu(ch->parent, 0, APUREG_ROUTING, 2 << APU_DATASRC_A_SHIFT);
996 /* APU #1 : Sample rate converter for right. */
997 apu_setparam(ch->parent, 1, WPWA_USE_SYSMEM | wpwa2,
998 ch->buflen >> ch->stereo, 0, dv);
999 wp_wrapu(ch->parent, 1, APUREG_AMPLITUDE, 0);
1000 wp_wrapu(ch->parent, 1, APUREG_ROUTING, 3 << APU_DATASRC_A_SHIFT);
1002 /* APU #2 : Input mixer for left. */
1003 apu_setparam(ch->parent, 2, WPWA_USE_SYSMEM | 0,
1004 ch->parent->bufsz >> 2, pan, 0x10000);
1005 wp_wrapu(ch->parent, 2, APUREG_AMPLITUDE, 0);
1006 wp_wrapu(ch->parent, 2, APUREG_EFFECT_GAIN, 0xf0);
1007 wp_wrapu(ch->parent, 2, APUREG_ROUTING, 0x15 << APU_DATASRC_A_SHIFT);
1009 /* APU #3 : Input mixer for right. */
1010 apu_setparam(ch->parent, 3, WPWA_USE_SYSMEM | (ch->parent->bufsz >> 2),
1011 ch->parent->bufsz >> 2, -pan, 0x10000);
1012 wp_wrapu(ch->parent, 3, APUREG_AMPLITUDE, 0);
1013 wp_wrapu(ch->parent, 3, APUREG_EFFECT_GAIN, 0xf0);
1014 wp_wrapu(ch->parent, 3, APUREG_ROUTING, 0x14 << APU_DATASRC_A_SHIFT);
1016 /* to mark this channel ready for intr. */
1017 ch->parent->active |= (1 << ch->parent->playchns);
1021 wp_wrapu(ch->parent, 0, APUREG_APUTYPE,
1022 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1023 wp_wrapu(ch->parent, 1, APUREG_APUTYPE,
1024 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1025 wp_wrapu(ch->parent, 2, APUREG_APUTYPE,
1026 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1027 wp_wrapu(ch->parent, 3, APUREG_APUTYPE,
1028 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1031 set_timer(ch->parent);
1032 wp_starttimer(ch->parent);
1033 agg_unlock(ch->parent);
1037 aggch_stop_adc(struct agg_rchinfo *ch)
1041 agg_lock(ch->parent);
1043 /* to mark that this channel no longer needs further intrs. */
1044 ch->parent->active &= ~(1 << ch->parent->playchns);
1046 for (apuch = 0; apuch < 4; apuch++)
1047 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
1048 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1050 if (ch->parent->active) {
1051 set_timer(ch->parent);
1052 wp_starttimer(ch->parent);
1054 wp_stoptimer(ch->parent);
1055 agg_power(ch->parent, powerstate_idle);
1057 agg_unlock(ch->parent);
1061 * Feed from L/R channel of ADC to destination with stereo interleaving.
1062 * This function expects n not overwrapping the buffer boundary.
1063 * Note that n is measured in sample unit.
1065 * XXX - this function works in 16bit stereo format only.
1068 interleave(int16_t *l, int16_t *r, int16_t *p, unsigned n)
1072 for (end = l + n; l < end; ) {
1079 aggch_feed_adc_stereo(struct agg_rchinfo *ch)
1084 agg_lock(ch->parent);
1085 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1086 agg_unlock(ch->parent);
1087 cur -= 0xffff & ((ch->srcphys - ch->base) >> 1);
1089 src2 = ch->src + ch->parent->bufsz/4;
1092 interleave(ch->src + last, src2 + last,
1093 ch->sink + 2*last, ch->buflen/2 - last);
1094 interleave(ch->src, src2,
1096 } else if (cur > last)
1097 interleave(ch->src + last, src2 + last,
1098 ch->sink + 2*last, cur - last);
1103 * Feed from R channel of ADC and mixdown to destination L/center.
1104 * This function expects n not overwrapping the buffer boundary.
1105 * Note that n is measured in sample unit.
1107 * XXX - this function works in 16bit monoral format only.
1110 mixdown(int16_t *src, int16_t *dest, unsigned n)
1114 for (end = dest + n; dest < end; dest++)
1115 *dest = (int16_t)(((int)*dest - (int)*src++) / 2);
1119 aggch_feed_adc_mono(struct agg_rchinfo *ch)
1123 agg_lock(ch->parent);
1124 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1125 agg_unlock(ch->parent);
1126 cur -= 0xffff & ((ch->phys - ch->base) >> 1);
1130 mixdown(ch->src + last, ch->sink + last, ch->buflen - last);
1131 mixdown(ch->src, ch->sink, cur);
1132 } else if (cur > last)
1133 mixdown(ch->src + last, ch->sink + last, cur - last);
1137 #ifdef AGG_JITTER_CORRECTION
1139 * Stereo jitter suppressor.
1140 * Sometimes playback pointers differ in stereo-paired channels.
1141 * Calling this routine within intr fixes the problem.
1144 suppress_jitter(struct agg_chinfo *ch)
1147 int cp1, cp2, diff /*, halfsize*/ ;
1149 /*halfsize = (ch->qs16? ch->buflen >> 2 : ch->buflen >> 1);*/
1150 cp1 = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1151 cp2 = wp_rdapu(ch->parent, (ch->num << 1) | 33, APUREG_CURPTR);
1153 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1154 if (diff > 1 /* && diff < halfsize*/ )
1155 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1161 suppress_rec_jitter(struct agg_rchinfo *ch)
1163 int cp1, cp2, diff /*, halfsize*/ ;
1165 /*halfsize = (ch->stereo? ch->buflen >> 2 : ch->buflen >> 1);*/
1166 cp1 = (ch->stereo? ch->parent->bufsz >> 2 : ch->parent->bufsz >> 1)
1167 + wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1168 cp2 = wp_rdapu(ch->parent, 1, APUREG_CURPTR);
1170 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1171 if (diff > 1 /* && diff < halfsize*/ )
1172 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1178 calc_timer_div(struct agg_chinfo *ch)
1185 printf("snd_maestro: pch[%d].speed == 0, which shouldn't\n",
1190 return (48000 * (ch->blklen << (!ch->qs16 + !ch->stereo))
1191 + speed - 1) / speed;
1195 calc_timer_div_rch(struct agg_rchinfo *ch)
1202 printf("snd_maestro: rch.speed == 0, which shouldn't\n");
1206 return (48000 * (ch->blklen << (!ch->stereo))
1207 + speed - 1) / speed;
1211 set_timer(struct agg_info *ess)
1214 u_int dv = 32 << 7, newdv;
1216 for (i = 0; i < ess->playchns; i++)
1217 if ((ess->active & (1 << i)) &&
1218 (dv > (newdv = calc_timer_div(ess->pch + i))))
1220 if ((ess->active & (1 << i)) &&
1221 (dv > (newdv = calc_timer_div_rch(&ess->rch))))
1224 wp_settimer(ess, dv);
1228 /* -----------------------------
1232 /* AC97 mixer interface. */
1235 agg_ac97_init(kobj_t obj, void *sc)
1237 struct agg_info *ess = sc;
1239 return (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK)? 0 : 1;
1243 agg_ac97_read(kobj_t obj, void *sc, int regno)
1245 struct agg_info *ess = sc;
1248 /* XXX sound locking violation: agg_lock(ess); */
1249 ret = agg_rdcodec(ess, regno);
1250 /* agg_unlock(ess); */
1255 agg_ac97_write(kobj_t obj, void *sc, int regno, u_int32_t data)
1257 struct agg_info *ess = sc;
1260 /* XXX sound locking violation: agg_lock(ess); */
1261 ret = agg_wrcodec(ess, regno, data);
1262 /* agg_unlock(ess); */
1267 static kobj_method_t agg_ac97_methods[] = {
1268 KOBJMETHOD(ac97_init, agg_ac97_init),
1269 KOBJMETHOD(ac97_read, agg_ac97_read),
1270 KOBJMETHOD(ac97_write, agg_ac97_write),
1273 AC97_DECLARE(agg_ac97);
1276 /* -------------------------------------------------------------------- */
1278 /* Playback channel. */
1281 aggpch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
1282 struct pcm_channel *c, int dir)
1284 struct agg_info *ess = devinfo;
1285 struct agg_chinfo *ch;
1286 bus_addr_t physaddr;
1289 KASSERT((dir == PCMDIR_PLAY),
1290 ("aggpch_init() called for RECORDING channel!"));
1291 ch = ess->pch + ess->playchns;
1296 ch->num = ess->playchns;
1298 p = dma_malloc(ess->buf_dmat, ess->bufsz, &physaddr, &ch->map);
1301 ch->phys = physaddr;
1302 ch->base = physaddr & ((~(bus_addr_t)0) << WAVCACHE_BASEADDR_SHIFT);
1304 sndbuf_setup(b, p, ess->bufsz);
1305 ch->blklen = sndbuf_getblksz(b) / 2;
1306 ch->buflen = sndbuf_getsize(b) / 2;
1313 adjust_pchbase(struct agg_chinfo *chans, u_int n, u_int size)
1315 struct agg_chinfo *pchs[AGG_MAXPLAYCH];
1319 /* sort pchs by phys address */
1320 for (i = 0; i < n; i++) {
1321 for (j = 0; j < i; j++)
1322 if (chans[i].phys < pchs[j]->phys) {
1323 for (k = i; k > j; k--)
1324 pchs[k] = pchs[k - 1];
1327 pchs[j] = chans + i;
1330 /* use new base register if next buffer can not be addressed
1331 via current base. */
1332 #define BASE_SHIFT (WPWA_WTBAR_SHIFT(2) + 2 + 1)
1333 base = pchs[0]->base;
1334 for (k = 1, i = 1; i < n; i++) {
1335 if (pchs[i]->phys + size - base >= 1 << BASE_SHIFT)
1336 /* not addressable: assign new base */
1337 base = (pchs[i]->base -= k++ << BASE_SHIFT);
1339 pchs[i]->base = base;
1344 printf("Total of %d bases are assigned.\n", k);
1345 for (i = 0; i < n; i++) {
1346 printf("ch.%d: phys 0x%llx, wpwa 0x%llx\n",
1347 i, (long long)chans[i].phys,
1348 (long long)(chans[i].phys -
1349 chans[i].base) >> 1);
1355 aggpch_free(kobj_t obj, void *data)
1357 struct agg_chinfo *ch = data;
1358 struct agg_info *ess = ch->parent;
1360 /* free up buffer - called after channel stopped */
1361 dma_free(ess->buf_dmat, sndbuf_getbuf(ch->buffer), ch->map);
1363 /* return 0 if ok */
1368 aggpch_setformat(kobj_t obj, void *data, u_int32_t format)
1370 struct agg_chinfo *ch = data;
1372 if (format & AFMT_BIGENDIAN || format & AFMT_U16_LE)
1374 ch->stereo = ch->qs16 = ch->us = 0;
1375 if (AFMT_CHANNEL(format) > 1)
1378 if (format & AFMT_U8 || format & AFMT_S8) {
1379 if (format & AFMT_U8)
1387 aggpch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1390 ((struct agg_chinfo*)data)->speed = speed;
1396 aggpch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1398 struct agg_chinfo *ch = data;
1401 /* try to keep at least 20msec DMA space */
1402 blkcnt = (ch->speed << (ch->stereo + ch->qs16)) / (50 * blocksize);
1403 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1405 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1406 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1407 blkcnt = sndbuf_getblkcnt(ch->buffer);
1408 blocksize = sndbuf_getblksz(ch->buffer);
1410 sndbuf_setblkcnt(ch->buffer, blkcnt);
1411 sndbuf_setblksz(ch->buffer, blocksize);
1414 ch->blklen = blocksize / 2;
1415 ch->buflen = blkcnt * blocksize / 2;
1420 aggpch_trigger(kobj_t obj, void *data, int go)
1422 struct agg_chinfo *ch = data;
1425 case PCMTRIG_EMLDMAWR:
1428 aggch_start_dac(ch);
1439 aggpch_getptr(kobj_t obj, void *data)
1441 struct agg_chinfo *ch = data;
1444 agg_lock(ch->parent);
1445 cp = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1446 agg_unlock(ch->parent);
1448 return ch->qs16 && ch->stereo
1449 ? (cp << 2) - ((0xffff << 2) & (ch->phys - ch->base))
1450 : (cp << 1) - ((0xffff << 1) & (ch->phys - ch->base));
1453 static struct pcmchan_caps *
1454 aggpch_getcaps(kobj_t obj, void *data)
1456 static u_int32_t playfmt[] = {
1457 SND_FORMAT(AFMT_U8, 1, 0),
1458 SND_FORMAT(AFMT_U8, 2, 0),
1459 SND_FORMAT(AFMT_S8, 1, 0),
1460 SND_FORMAT(AFMT_S8, 2, 0),
1461 SND_FORMAT(AFMT_S16_LE, 1, 0),
1462 SND_FORMAT(AFMT_S16_LE, 2, 0),
1465 static struct pcmchan_caps playcaps = {8000, 48000, playfmt, 0};
1471 static kobj_method_t aggpch_methods[] = {
1472 KOBJMETHOD(channel_init, aggpch_init),
1473 KOBJMETHOD(channel_free, aggpch_free),
1474 KOBJMETHOD(channel_setformat, aggpch_setformat),
1475 KOBJMETHOD(channel_setspeed, aggpch_setspeed),
1476 KOBJMETHOD(channel_setblocksize, aggpch_setblocksize),
1477 KOBJMETHOD(channel_trigger, aggpch_trigger),
1478 KOBJMETHOD(channel_getptr, aggpch_getptr),
1479 KOBJMETHOD(channel_getcaps, aggpch_getcaps),
1482 CHANNEL_DECLARE(aggpch);
1485 /* -------------------------------------------------------------------- */
1487 /* Recording channel. */
1490 aggrch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
1491 struct pcm_channel *c, int dir)
1493 struct agg_info *ess = devinfo;
1494 struct agg_rchinfo *ch;
1497 KASSERT((dir == PCMDIR_REC),
1498 ("aggrch_init() called for PLAYBACK channel!"));
1505 /* Uses the bottom-half of the status buffer. */
1506 p = ess->stat + ess->bufsz;
1507 ch->phys = ess->phys + ess->bufsz;
1508 ch->base = ess->phys;
1509 ch->src = (int16_t *)(p + ess->bufsz);
1510 ch->srcphys = ch->phys + ess->bufsz;
1511 ch->sink = (int16_t *)p;
1513 sndbuf_setup(b, p, ess->bufsz);
1514 ch->blklen = sndbuf_getblksz(b) / 2;
1515 ch->buflen = sndbuf_getsize(b) / 2;
1521 aggrch_setformat(kobj_t obj, void *data, u_int32_t format)
1523 struct agg_rchinfo *ch = data;
1525 if (!(format & AFMT_S16_LE))
1527 if (AFMT_CHANNEL(format) > 1)
1535 aggrch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1538 ((struct agg_rchinfo*)data)->speed = speed;
1544 aggrch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1546 struct agg_rchinfo *ch = data;
1549 /* try to keep at least 20msec DMA space */
1550 blkcnt = (ch->speed << ch->stereo) / (25 * blocksize);
1551 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1553 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1554 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1555 blkcnt = sndbuf_getblkcnt(ch->buffer);
1556 blocksize = sndbuf_getblksz(ch->buffer);
1558 sndbuf_setblkcnt(ch->buffer, blkcnt);
1559 sndbuf_setblksz(ch->buffer, blocksize);
1562 ch->blklen = blocksize / 2;
1563 ch->buflen = blkcnt * blocksize / 2;
1568 aggrch_trigger(kobj_t obj, void *sc, int go)
1570 struct agg_rchinfo *ch = sc;
1573 case PCMTRIG_EMLDMARD:
1575 aggch_feed_adc_stereo(ch);
1577 aggch_feed_adc_mono(ch);
1580 aggch_start_adc(ch);
1591 aggrch_getptr(kobj_t obj, void *sc)
1593 struct agg_rchinfo *ch = sc;
1595 return ch->stereo? ch->hwptr << 2 : ch->hwptr << 1;
1598 static struct pcmchan_caps *
1599 aggrch_getcaps(kobj_t obj, void *sc)
1601 static u_int32_t recfmt[] = {
1602 SND_FORMAT(AFMT_S16_LE, 1, 0),
1603 SND_FORMAT(AFMT_S16_LE, 2, 0),
1606 static struct pcmchan_caps reccaps = {8000, 48000, recfmt, 0};
1611 static kobj_method_t aggrch_methods[] = {
1612 KOBJMETHOD(channel_init, aggrch_init),
1613 /* channel_free: no-op */
1614 KOBJMETHOD(channel_setformat, aggrch_setformat),
1615 KOBJMETHOD(channel_setspeed, aggrch_setspeed),
1616 KOBJMETHOD(channel_setblocksize, aggrch_setblocksize),
1617 KOBJMETHOD(channel_trigger, aggrch_trigger),
1618 KOBJMETHOD(channel_getptr, aggrch_getptr),
1619 KOBJMETHOD(channel_getcaps, aggrch_getcaps),
1622 CHANNEL_DECLARE(aggrch);
1625 /* -----------------------------
1632 struct agg_info* ess = sc;
1633 register u_int8_t status;
1637 status = AGG_RD(ess, PORT_HOSTINT_STAT, 1);
1641 /* Acknowledge intr. */
1642 AGG_WR(ess, PORT_HOSTINT_STAT, status, 1);
1644 if (status & HOSTINT_STAT_DSOUND) {
1645 #ifdef AGG_JITTER_CORRECTION
1648 if (ess->curpwr <= PCI_POWERSTATE_D1) {
1649 AGG_WR(ess, PORT_INT_STAT, 1, 2);
1650 #ifdef AGG_JITTER_CORRECTION
1651 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1652 if (ess->active & m)
1653 suppress_jitter(ess->pch + i);
1655 if (ess->active & m)
1656 suppress_rec_jitter(&ess->rch);
1659 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1660 if (ess->active & m) {
1661 if (ess->curpwr <= PCI_POWERSTATE_D1)
1662 chn_intr(ess->pch[i].channel);
1669 if ((ess->active & m)
1670 && ess->curpwr <= PCI_POWERSTATE_D1)
1671 chn_intr(ess->rch.channel);
1673 #ifdef AGG_JITTER_CORRECTION
1679 if (status & HOSTINT_STAT_HWVOL) {
1680 register u_int8_t event;
1683 event = AGG_RD(ess, PORT_HWVOL_MASTER, 1);
1684 AGG_WR(ess, PORT_HWVOL_MASTER, HWVOL_NOP, 1);
1689 mixer_hwvol_step(ess->dev, 1, 1);
1692 mixer_hwvol_step(ess->dev, -1, -1);
1697 if (event & HWVOL_MUTE) {
1698 mixer_hwvol_mute(ess->dev);
1701 device_printf(ess->dev,
1702 "%s: unknown HWVOL event 0x%x\n",
1703 device_get_nameunit(ess->dev), event);
1709 setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1711 bus_addr_t *phys = arg;
1713 *phys = error? 0 : segs->ds_addr;
1716 printf("setmap (%lx, %lx), nseg=%d, error=%d\n",
1717 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
1723 dma_malloc(bus_dma_tag_t dmat, u_int32_t sz, bus_addr_t *phys,
1728 if (bus_dmamem_alloc(dmat, &buf, BUS_DMA_NOWAIT, map))
1730 if (bus_dmamap_load(dmat, *map, buf, sz, setmap, phys, 0) != 0 ||
1732 bus_dmamem_free(dmat, buf, *map);
1739 dma_free(bus_dma_tag_t dmat, void *buf, bus_dmamap_t map)
1741 bus_dmamap_unload(dmat, map);
1742 bus_dmamem_free(dmat, buf, map);
1746 agg_probe(device_t dev)
1750 switch (pci_get_devid(dev)) {
1751 case MAESTRO_1_PCI_ID:
1752 s = "ESS Technology Maestro-1";
1755 case MAESTRO_2_PCI_ID:
1756 s = "ESS Technology Maestro-2";
1759 case MAESTRO_2E_PCI_ID:
1760 s = "ESS Technology Maestro-2E";
1764 if (s != NULL && pci_get_class(dev) == PCIC_MULTIMEDIA) {
1765 device_set_desc(dev, s);
1766 return BUS_PROBE_DEFAULT;
1772 agg_attach(device_t dev)
1774 struct agg_info *ess = NULL;
1776 int regid = PCIR_BAR(0);
1777 struct resource *reg = NULL;
1778 struct ac97_info *codec = NULL;
1780 struct resource *irq = NULL;
1782 char status[SND_STATUSLEN];
1785 ess = malloc(sizeof(*ess), M_DEVBUF, M_WAITOK | M_ZERO);
1788 mtx_init(&ess->lock, device_get_desc(dev), "snd_maestro softc",
1789 MTX_DEF | MTX_RECURSE);
1790 if (!mtx_initialized(&ess->lock)) {
1791 device_printf(dev, "failed to create a mutex.\n");
1796 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
1797 "dac", &dacn) == 0) {
1800 else if (dacn > AGG_MAXPLAYCH)
1801 dacn = AGG_MAXPLAYCH;
1803 dacn = AGG_MAXPLAYCH;
1805 ess->bufsz = pcm_getbuffersize(dev, 4096, AGG_DEFAULT_BUFSZ, 65536);
1806 if (bus_dma_tag_create(/*parent*/ bus_get_dma_tag(dev),
1807 /*align */ 4, 1 << (16+1),
1808 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1809 /*filter*/ NULL, NULL,
1810 /*size */ ess->bufsz, 1, 0x3ffff,
1812 /*lock */ busdma_lock_mutex, &Giant,
1813 &ess->buf_dmat) != 0) {
1814 device_printf(dev, "unable to create dma tag\n");
1819 if (bus_dma_tag_create(/*parent*/ bus_get_dma_tag(dev),
1820 /*align */ 1 << WAVCACHE_BASEADDR_SHIFT,
1822 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1823 /*filter*/ NULL, NULL,
1824 /*size */ 3*ess->bufsz, 1, 0x3ffff,
1826 /*lock */ busdma_lock_mutex, &Giant,
1827 &ess->stat_dmat) != 0) {
1828 device_printf(dev, "unable to create dma tag\n");
1833 /* Allocate the room for brain-damaging status buffer. */
1834 ess->stat = dma_malloc(ess->stat_dmat, 3*ess->bufsz, &ess->phys,
1836 if (ess->stat == NULL) {
1837 device_printf(dev, "cannot allocate status buffer\n");
1842 device_printf(dev, "Maestro status/record buffer: %#llx\n",
1843 (long long)ess->phys);
1845 /* State D0-uninitialized. */
1846 ess->curpwr = PCI_POWERSTATE_D3;
1847 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1849 pci_enable_busmaster(dev);
1851 /* Allocate resources. */
1852 reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, ®id, RF_ACTIVE);
1856 ess->st = rman_get_bustag(reg);
1857 ess->sh = rman_get_bushandle(reg);
1859 device_printf(dev, "unable to map register space\n");
1863 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqid,
1864 RF_ACTIVE | RF_SHAREABLE);
1869 device_printf(dev, "unable to map interrupt\n");
1874 /* Setup resources. */
1875 if (snd_setup_intr(dev, irq, INTR_MPSAFE, agg_intr, ess, &ih)) {
1876 device_printf(dev, "unable to setup interrupt\n");
1882 /* Transition from D0-uninitialized to D0. */
1884 agg_power(ess, PCI_POWERSTATE_D0);
1885 if (agg_rdcodec(ess, 0) == 0x80) {
1886 /* XXX - TODO: PT101 */
1888 device_printf(dev, "PT101 codec detected!\n");
1893 codec = AC97_CREATE(dev, ess, agg_ac97);
1894 if (codec == NULL) {
1895 device_printf(dev, "failed to create AC97 codec softc!\n");
1899 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) {
1900 device_printf(dev, "mixer initialization failed!\n");
1906 ret = pcm_register(dev, ess, dacn, 1);
1910 mixer_hwvol_init(dev);
1912 agg_power(ess, powerstate_init);
1914 for (data = 0; data < dacn; data++)
1915 pcm_addchan(dev, PCMDIR_PLAY, &aggpch_class, ess);
1916 pcm_addchan(dev, PCMDIR_REC, &aggrch_class, ess);
1917 adjust_pchbase(ess->pch, ess->playchns, ess->bufsz);
1919 snprintf(status, SND_STATUSLEN,
1920 "port 0x%jx-0x%jx irq %jd at device %d.%d on pci%d",
1921 rman_get_start(reg), rman_get_end(reg), rman_get_start(irq),
1922 pci_get_slot(dev), pci_get_function(dev), pci_get_bus(dev));
1923 pcm_setstatus(dev, status);
1929 ac97_destroy(codec);
1931 bus_teardown_intr(dev, irq, ih);
1933 bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
1935 bus_release_resource(dev, SYS_RES_IOPORT, regid, reg);
1937 if (ess->stat != NULL)
1938 dma_free(ess->stat_dmat, ess->stat, ess->stat_map);
1939 if (ess->stat_dmat != NULL)
1940 bus_dma_tag_destroy(ess->stat_dmat);
1941 if (ess->buf_dmat != NULL)
1942 bus_dma_tag_destroy(ess->buf_dmat);
1943 if (mtx_initialized(&ess->lock))
1944 mtx_destroy(&ess->lock);
1945 free(ess, M_DEVBUF);
1952 agg_detach(device_t dev)
1954 struct agg_info *ess = pcm_getdevinfo(dev);
1958 icr = AGG_RD(ess, PORT_HOSTINT_CTRL, 2);
1959 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
1963 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1969 r = pcm_unregister(dev);
1971 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1976 agg_power(ess, PCI_POWERSTATE_D3);
1979 bus_teardown_intr(dev, ess->irq, ess->ih);
1980 bus_release_resource(dev, SYS_RES_IRQ, ess->irqid, ess->irq);
1981 bus_release_resource(dev, SYS_RES_IOPORT, ess->regid, ess->reg);
1982 dma_free(ess->stat_dmat, ess->stat, ess->stat_map);
1983 bus_dma_tag_destroy(ess->stat_dmat);
1984 bus_dma_tag_destroy(ess->buf_dmat);
1985 mtx_destroy(&ess->lock);
1986 free(ess, M_DEVBUF);
1991 agg_suspend(device_t dev)
1993 struct agg_info *ess = pcm_getdevinfo(dev);
1995 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
1997 agg_power(ess, PCI_POWERSTATE_D3);
2004 agg_resume(device_t dev)
2007 struct agg_info *ess = pcm_getdevinfo(dev);
2009 for (i = 0; i < ess->playchns; i++)
2010 if (ess->active & (1 << i))
2011 aggch_start_dac(ess->pch + i);
2012 if (ess->active & (1 << i))
2013 aggch_start_adc(&ess->rch);
2017 agg_power(ess, powerstate_init);
2020 if (mixer_reinit(dev)) {
2021 device_printf(dev, "unable to reinitialize the mixer\n");
2029 agg_shutdown(device_t dev)
2031 struct agg_info *ess = pcm_getdevinfo(dev);
2034 agg_power(ess, PCI_POWERSTATE_D3);
2041 static device_method_t agg_methods[] = {
2042 DEVMETHOD(device_probe, agg_probe),
2043 DEVMETHOD(device_attach, agg_attach),
2044 DEVMETHOD(device_detach, agg_detach),
2045 DEVMETHOD(device_suspend, agg_suspend),
2046 DEVMETHOD(device_resume, agg_resume),
2047 DEVMETHOD(device_shutdown, agg_shutdown),
2052 static driver_t agg_driver = {
2058 /*static devclass_t pcm_devclass;*/
2060 DRIVER_MODULE(snd_maestro, pci, agg_driver, pcm_devclass, 0, 0);
2061 MODULE_DEPEND(snd_maestro, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2062 MODULE_VERSION(snd_maestro, 1);