2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2001 Scott Long <scottl@freebsd.org>
5 * Copyright (c) 2001 Darrell Anderson <anderson@cs.duke.edu>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Maestro-3/Allegro FreeBSD pcm sound driver
33 * executive status summary:
34 * (+) /dev/dsp multiple concurrent play channels.
35 * (+) /dev/dsp config (speed, mono/stereo, 8/16 bit).
36 * (+) /dev/mixer sets left/right volumes.
37 * (+) /dev/dsp recording works. Tested successfully with the cdrom channel
38 * (+) apm suspend/resume works, and works properly!.
39 * (-) hardware volme controls don't work =-(
40 * (-) setblocksize() does nothing.
42 * The real credit goes to:
44 * Zach Brown for his Linux driver core and helpful technical comments.
45 * <zab@zabbo.net>, http://www.zabbo.net/maestro3
47 * Cameron Grant created the pcm framework used here nearly verbatim.
48 * <cg@freebsd.org>, https://people.freebsd.org/~cg/template.c
50 * Taku YAMAMOTO for his Maestro-1/2 FreeBSD driver and sanity reference.
51 * <taku@cent.saitama-u.ac.jp>
53 * ESS docs explained a few magic registers and numbers.
54 * http://virgo.caltech.edu/~dmoore/maestro3.pdf.gz
57 #ifdef HAVE_KERNEL_OPTION_HEADERS
61 #include <dev/sound/pcm/sound.h>
62 #include <dev/sound/pcm/ac97.h>
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
69 #include <dev/sound/pci/allegro_reg.h>
70 #include <dev/sound/pci/allegro_code.h>
72 SND_DECLARE_FILE("$FreeBSD$");
74 /* -------------------------------------------------------------------- */
76 enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1};
77 #ifndef M3_DEBUG_LEVEL
78 #define M3_DEBUG_LEVEL NONE
80 #define M3_DEBUG(level, _msg) {if ((level) <= M3_DEBUG_LEVEL) {printf _msg;}}
82 /* -------------------------------------------------------------------- */
88 static struct m3_card_type {
89 u_int32_t pci_id; int which; int delay1; int delay2; char *name;
91 { 0x1988125d, ESS_ALLEGRO_1, 50, 800, "ESS Technology Allegro-1" },
92 { 0x1998125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" },
93 { 0x199a125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" },
97 #define M3_BUFSIZE_MIN 4096
98 #define M3_BUFSIZE_MAX 65536
99 #define M3_BUFSIZE_DEFAULT 4096
100 #define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */
102 #define M3_MAXADDR ((1 << 27) - 1)
103 #define M3_DEFAULT_VOL 0x6800
110 struct snd_dbuf *buffer;
111 struct pcm_channel *channel;
112 struct sc_info *parent;
124 struct snd_dbuf *buffer;
125 struct pcm_channel *channel;
126 struct sc_info *parent;
143 bus_space_handle_t sh;
144 bus_dma_tag_t parent_dmat;
146 struct resource *reg;
147 struct resource *irq;
153 struct sc_pchinfo pch[M3_PCHANS];
154 struct sc_rchinfo rch[M3_RCHANS];
164 #define M3_LOCK(_sc) snd_mtxlock((_sc)->sc_lock)
165 #define M3_UNLOCK(_sc) snd_mtxunlock((_sc)->sc_lock)
166 #define M3_LOCK_ASSERT(_sc) snd_mtxassert((_sc)->sc_lock)
168 /* -------------------------------------------------------------------- */
170 /* play channel interface */
171 static void *m3_pchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int);
172 static int m3_pchan_free(kobj_t, void *);
173 static int m3_pchan_setformat(kobj_t, void *, u_int32_t);
174 static u_int32_t m3_pchan_setspeed(kobj_t, void *, u_int32_t);
175 static u_int32_t m3_pchan_setblocksize(kobj_t, void *, u_int32_t);
176 static int m3_pchan_trigger(kobj_t, void *, int);
177 static int m3_pchan_trigger_locked(kobj_t, void *, int);
178 static u_int32_t m3_pchan_getptr_internal(struct sc_pchinfo *);
179 static u_int32_t m3_pchan_getptr(kobj_t, void *);
180 static struct pcmchan_caps *m3_pchan_getcaps(kobj_t, void *);
182 /* record channel interface */
183 static void *m3_rchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int);
184 static int m3_rchan_free(kobj_t, void *);
185 static int m3_rchan_setformat(kobj_t, void *, u_int32_t);
186 static u_int32_t m3_rchan_setspeed(kobj_t, void *, u_int32_t);
187 static u_int32_t m3_rchan_setblocksize(kobj_t, void *, u_int32_t);
188 static int m3_rchan_trigger(kobj_t, void *, int);
189 static int m3_rchan_trigger_locked(kobj_t, void *, int);
190 static u_int32_t m3_rchan_getptr_internal(struct sc_rchinfo *);
191 static u_int32_t m3_rchan_getptr(kobj_t, void *);
192 static struct pcmchan_caps *m3_rchan_getcaps(kobj_t, void *);
194 static int m3_chan_active(struct sc_info *);
196 /* talk to the codec - called from ac97.c */
197 static u_int32_t m3_initcd(kobj_t, void *);
198 static int m3_rdcd(kobj_t, void *, int);
199 static int m3_wrcd(kobj_t, void *, int, u_int32_t);
202 static void m3_intr(void *);
203 static int m3_power(struct sc_info *, int);
204 static int m3_init(struct sc_info *);
205 static int m3_uninit(struct sc_info *);
206 static u_int8_t m3_assp_halt(struct sc_info *);
207 static void m3_config(struct sc_info *);
208 static void m3_amp_enable(struct sc_info *);
209 static void m3_enable_ints(struct sc_info *);
210 static void m3_codec_reset(struct sc_info *);
212 /* -------------------------------------------------------------------- */
213 /* Codec descriptor */
214 static kobj_method_t m3_codec_methods[] = {
215 KOBJMETHOD(ac97_init, m3_initcd),
216 KOBJMETHOD(ac97_read, m3_rdcd),
217 KOBJMETHOD(ac97_write, m3_wrcd),
220 AC97_DECLARE(m3_codec);
222 /* -------------------------------------------------------------------- */
223 /* channel descriptors */
225 static u_int32_t m3_playfmt[] = {
226 SND_FORMAT(AFMT_U8, 1, 0),
227 SND_FORMAT(AFMT_U8, 2, 0),
228 SND_FORMAT(AFMT_S16_LE, 1, 0),
229 SND_FORMAT(AFMT_S16_LE, 2, 0),
232 static struct pcmchan_caps m3_playcaps = {8000, 48000, m3_playfmt, 0};
234 static kobj_method_t m3_pch_methods[] = {
235 KOBJMETHOD(channel_init, m3_pchan_init),
236 KOBJMETHOD(channel_setformat, m3_pchan_setformat),
237 KOBJMETHOD(channel_setspeed, m3_pchan_setspeed),
238 KOBJMETHOD(channel_setblocksize, m3_pchan_setblocksize),
239 KOBJMETHOD(channel_trigger, m3_pchan_trigger),
240 KOBJMETHOD(channel_getptr, m3_pchan_getptr),
241 KOBJMETHOD(channel_getcaps, m3_pchan_getcaps),
242 KOBJMETHOD(channel_free, m3_pchan_free),
245 CHANNEL_DECLARE(m3_pch);
247 static u_int32_t m3_recfmt[] = {
248 SND_FORMAT(AFMT_U8, 1, 0),
249 SND_FORMAT(AFMT_U8, 2, 0),
250 SND_FORMAT(AFMT_S16_LE, 1, 0),
251 SND_FORMAT(AFMT_S16_LE, 2, 0),
254 static struct pcmchan_caps m3_reccaps = {8000, 48000, m3_recfmt, 0};
256 static kobj_method_t m3_rch_methods[] = {
257 KOBJMETHOD(channel_init, m3_rchan_init),
258 KOBJMETHOD(channel_setformat, m3_rchan_setformat),
259 KOBJMETHOD(channel_setspeed, m3_rchan_setspeed),
260 KOBJMETHOD(channel_setblocksize, m3_rchan_setblocksize),
261 KOBJMETHOD(channel_trigger, m3_rchan_trigger),
262 KOBJMETHOD(channel_getptr, m3_rchan_getptr),
263 KOBJMETHOD(channel_getcaps, m3_rchan_getcaps),
264 KOBJMETHOD(channel_free, m3_rchan_free),
267 CHANNEL_DECLARE(m3_rch);
269 /* -------------------------------------------------------------------- */
270 /* some i/o convenience functions */
272 #define m3_rd_1(sc, regno) bus_space_read_1(sc->st, sc->sh, regno)
273 #define m3_rd_2(sc, regno) bus_space_read_2(sc->st, sc->sh, regno)
274 #define m3_rd_4(sc, regno) bus_space_read_4(sc->st, sc->sh, regno)
275 #define m3_wr_1(sc, regno, data) bus_space_write_1(sc->st, sc->sh, regno, data)
276 #define m3_wr_2(sc, regno, data) bus_space_write_2(sc->st, sc->sh, regno, data)
277 #define m3_wr_4(sc, regno, data) bus_space_write_4(sc->st, sc->sh, regno, data)
278 #define m3_rd_assp_code(sc, index) \
279 m3_rd_assp(sc, MEMTYPE_INTERNAL_CODE, index)
280 #define m3_wr_assp_code(sc, index, data) \
281 m3_wr_assp(sc, MEMTYPE_INTERNAL_CODE, index, data)
282 #define m3_rd_assp_data(sc, index) \
283 m3_rd_assp(sc, MEMTYPE_INTERNAL_DATA, index)
284 #define m3_wr_assp_data(sc, index, data) \
285 m3_wr_assp(sc, MEMTYPE_INTERNAL_DATA, index, data)
287 static __inline u_int16_t
288 m3_rd_assp(struct sc_info *sc, u_int16_t region, u_int16_t index)
290 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
291 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
292 return m3_rd_2(sc, DSP_PORT_MEMORY_DATA);
296 m3_wr_assp(struct sc_info *sc, u_int16_t region, u_int16_t index,
299 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
300 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
301 m3_wr_2(sc, DSP_PORT_MEMORY_DATA, data);
305 m3_wait(struct sc_info *sc)
309 for (i=0 ; i<20 ; i++) {
310 if ((m3_rd_1(sc, CODEC_STATUS) & 1) == 0) {
318 /* -------------------------------------------------------------------- */
322 m3_initcd(kobj_t kobj, void *devinfo)
324 struct sc_info *sc = (struct sc_info *)devinfo;
327 M3_DEBUG(CALL, ("m3_initcd\n"));
331 data = m3_rd_1(sc, CODEC_COMMAND);
332 return ((data & 0x1) ? 0 : 1);
336 m3_rdcd(kobj_t kobj, void *devinfo, int regno)
338 struct sc_info *sc = (struct sc_info *)devinfo;
342 device_printf(sc->dev, "m3_rdcd timed out.\n");
345 m3_wr_1(sc, CODEC_COMMAND, (regno & 0x7f) | 0x80);
346 DELAY(50); /* ac97 cycle = 20.8 usec */
348 device_printf(sc->dev, "m3_rdcd timed out.\n");
351 data = m3_rd_2(sc, CODEC_DATA);
356 m3_wrcd(kobj_t kobj, void *devinfo, int regno, u_int32_t data)
358 struct sc_info *sc = (struct sc_info *)devinfo;
360 device_printf(sc->dev, "m3_wrcd timed out.\n");
363 m3_wr_2(sc, CODEC_DATA, data);
364 m3_wr_1(sc, CODEC_COMMAND, regno & 0x7f);
365 DELAY(50); /* ac97 cycle = 20.8 usec */
369 /* -------------------------------------------------------------------- */
370 /* play channel interface */
372 #define LO(x) (((x) & 0x0000ffff) )
373 #define HI(x) (((x) & 0xffff0000) >> 16)
376 m3_pchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
378 struct sc_info *sc = devinfo;
379 struct sc_pchinfo *ch;
380 u_int32_t bus_addr, i;
381 int idx, data_bytes, dac_data;
382 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
387 {CDATA_LEFT_VOLUME, M3_DEFAULT_VOL},
388 {CDATA_RIGHT_VOLUME, M3_DEFAULT_VOL},
389 {SRC3_DIRECTION_OFFSET, 0} ,
390 {SRC3_DIRECTION_OFFSET + 3, 0x0000},
391 {SRC3_DIRECTION_OFFSET + 4, 0},
392 {SRC3_DIRECTION_OFFSET + 5, 0},
393 {SRC3_DIRECTION_OFFSET + 6, 0},
394 {SRC3_DIRECTION_OFFSET + 7, 0},
395 {SRC3_DIRECTION_OFFSET + 8, 0},
396 {SRC3_DIRECTION_OFFSET + 9, 0},
397 {SRC3_DIRECTION_OFFSET + 10, 0x8000},
398 {SRC3_DIRECTION_OFFSET + 11, 0xFF00},
399 {SRC3_DIRECTION_OFFSET + 13, 0},
400 {SRC3_DIRECTION_OFFSET + 14, 0},
401 {SRC3_DIRECTION_OFFSET + 15, 0},
402 {SRC3_DIRECTION_OFFSET + 16, 8},
403 {SRC3_DIRECTION_OFFSET + 17, 50*2},
404 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1},
405 {SRC3_DIRECTION_OFFSET + 20, 0},
406 {SRC3_DIRECTION_OFFSET + 21, 0}
410 idx = sc->pch_cnt; /* dac instance number, no active reuse! */
411 M3_DEBUG(CHANGE, ("m3_pchan_init(dac=%d)\n", idx));
413 if (dir != PCMDIR_PLAY) {
415 device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n");
419 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) +
420 (MINISRC_IN_BUFFER_SIZE & ~1) +
421 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255;
422 dac_data = 0x1100 + (data_bytes * idx);
424 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
425 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
426 dsp_in_buf = dac_data + (MINISRC_TMP_BUFFER_SIZE/2);
427 dsp_out_buf = dsp_in_buf + (dsp_in_size/2) + 1;
431 ch->dac_data = dac_data;
432 if (ch->dac_data + data_bytes/2 >= 0x1c00) {
434 device_printf(sc->dev, "m3_pchan_init: revb mem exhausted\n");
441 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
442 ch->spd = DSP_DEFAULT_SPEED;
443 M3_UNLOCK(sc); /* XXX */
444 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
445 device_printf(sc->dev, "m3_pchan_init chn_allocbuf failed\n");
449 ch->bufsize = sndbuf_getsize(ch->buffer);
451 /* host dma buffer pointers */
452 bus_addr = sndbuf_getbufaddr(ch->buffer);
454 device_printf(sc->dev, "m3_pchan_init unaligned bus_addr\n");
455 bus_addr = (bus_addr + 4) & ~3;
457 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
458 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
459 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1L,
460 LO(bus_addr + ch->bufsize));
461 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1H,
462 HI(bus_addr + ch->bufsize));
463 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL,
465 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH,
469 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
470 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_END_PLUS_1,
471 dsp_in_buf + dsp_in_size/2);
472 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
473 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
474 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
475 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_END_PLUS_1,
476 dsp_out_buf + dsp_out_size/2);
477 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
478 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
480 /* some per client initializers */
481 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 12,
482 ch->dac_data + 40 + 8);
483 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 19,
484 0x400 + MINISRC_COEF_LOC);
485 /* enable or disable low pass filter? (0xff if rate> 45000) */
486 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 22, 0);
487 /* tell it which way dma is going? */
488 m3_wr_assp_data(sc, ch->dac_data + CDATA_DMA_CONTROL,
489 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR +
490 DMAC_BLOCKF_SELECTOR);
492 /* set an armload of static initializers */
493 for(i = 0 ; i < (sizeof(pv) / sizeof(pv[0])) ; i++) {
494 m3_wr_assp_data(sc, ch->dac_data + pv[i].addr, pv[i].val);
497 /* put us in the packed task lists */
498 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
499 (sc->pch_cnt + sc->rch_cnt),
500 ch->dac_data >> DP_SHIFT_COUNT);
501 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
502 ch->dac_data >> DP_SHIFT_COUNT);
503 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + sc->pch_cnt,
504 ch->dac_data >> DP_SHIFT_COUNT);
506 /* gotta start before stop */
507 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_START);
508 /* silence noise on load */
509 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_STOP);
518 m3_pchan_free(kobj_t kobj, void *chdata)
520 struct sc_pchinfo *ch = chdata;
521 struct sc_info *sc = ch->parent;
524 M3_DEBUG(CHANGE, ("m3_pchan_free(dac=%d)\n", ch->dac_idx));
527 * should remove this exact instance from the packed lists, but all
528 * are released at once (and in a stopped state) so this is ok.
530 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
531 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
532 m3_wr_assp_data(sc, KDATA_DMA_XFER0 +
533 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
534 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + (sc->pch_cnt-1), 0);
542 m3_pchan_setformat(kobj_t kobj, void *chdata, u_int32_t format)
544 struct sc_pchinfo *ch = chdata;
545 struct sc_info *sc = ch->parent;
550 ("m3_pchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
552 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit",
553 (AFMT_CHANNEL(format) > 1) ? "STEREO":"MONO"));
556 data = (AFMT_CHANNEL(format) > 1)? 0 : 1;
557 m3_wr_assp_data(sc, ch->dac_data + SRC3_MODE_OFFSET, data);
560 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0;
561 m3_wr_assp_data(sc, ch->dac_data + SRC3_WORD_LENGTH_OFFSET, data);
570 m3_pchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed)
572 struct sc_pchinfo *ch = chdata;
573 struct sc_info *sc = ch->parent;
577 M3_DEBUG(CHANGE, ("m3_pchan_setspeed(dac=%d, speed=%d)\n",
578 ch->dac_idx, speed));
580 if ((freq = ((speed << 15) + 24000) / 48000) != 0) {
584 m3_wr_assp_data(sc, ch->dac_data + CDATA_FREQUENCY, freq);
588 /* return closest possible speed */
593 m3_pchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize)
595 struct sc_pchinfo *ch = chdata;
597 M3_DEBUG(CHANGE, ("m3_pchan_setblocksize(dac=%d, blocksize=%d)\n",
598 ch->dac_idx, blocksize));
600 return (sndbuf_getblksz(ch->buffer));
604 m3_pchan_trigger(kobj_t kobj, void *chdata, int go)
606 struct sc_pchinfo *ch = chdata;
607 struct sc_info *sc = ch->parent;
610 if (!PCMTRIG_COMMON(go))
614 ret = m3_pchan_trigger_locked(kobj, chdata, go);
621 m3_chan_active(struct sc_info *sc)
627 for (i = 0; i < sc->pch_cnt; i++)
628 ret += sc->pch[i].active;
630 for (i = 0; i < sc->rch_cnt; i++)
631 ret += sc->rch[i].active;
637 m3_pchan_trigger_locked(kobj_t kobj, void *chdata, int go)
639 struct sc_pchinfo *ch = chdata;
640 struct sc_info *sc = ch->parent;
644 M3_DEBUG(go == PCMTRIG_START ? CHANGE :
645 go == PCMTRIG_STOP ? CHANGE :
646 go == PCMTRIG_ABORT ? CHANGE :
648 ("m3_pchan_trigger(dac=%d, go=0x%x{%s})\n", ch->dac_idx, go,
649 go == PCMTRIG_START ? "PCMTRIG_START" :
650 go == PCMTRIG_STOP ? "PCMTRIG_STOP" :
651 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore"));
661 sc->pch_active_cnt++;
663 /*[[inc_timer_users]]*/
664 if (m3_chan_active(sc) == 1) {
665 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240);
666 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240);
667 data = m3_rd_2(sc, HOST_INT_CTRL);
668 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
671 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 1);
672 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER,
678 if (ch->active == 0) {
682 sc->pch_active_cnt--;
684 /* XXX should the channel be drained? */
685 /*[[dec_timer_users]]*/
686 if (m3_chan_active(sc) == 0) {
687 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0);
688 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0);
689 data = m3_rd_2(sc, HOST_INT_CTRL);
690 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);
693 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 0);
694 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER,
698 case PCMTRIG_EMLDMAWR:
699 /* got play irq, transfer next buffer - ignore if using dma */
700 case PCMTRIG_EMLDMARD:
701 /* got rec irq, transfer next buffer - ignore if using dma */
709 m3_pchan_getptr_internal(struct sc_pchinfo *ch)
711 struct sc_info *sc = ch->parent;
712 u_int32_t hi, lo, bus_base, bus_crnt;
714 bus_base = sndbuf_getbufaddr(ch->buffer);
715 hi = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH);
716 lo = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL);
717 bus_crnt = lo | (hi << 16);
719 M3_DEBUG(CALL, ("m3_pchan_getptr(dac=%d) result=%d\n",
720 ch->dac_idx, bus_crnt - bus_base));
722 return (bus_crnt - bus_base); /* current byte offset of channel */
726 m3_pchan_getptr(kobj_t kobj, void *chdata)
728 struct sc_pchinfo *ch = chdata;
729 struct sc_info *sc = ch->parent;
739 static struct pcmchan_caps *
740 m3_pchan_getcaps(kobj_t kobj, void *chdata)
742 struct sc_pchinfo *ch = chdata;
744 M3_DEBUG(CALL, ("m3_pchan_getcaps(dac=%d)\n", ch->dac_idx));
749 /* -------------------------------------------------------------------- */
750 /* rec channel interface */
753 m3_rchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
755 struct sc_info *sc = devinfo;
756 struct sc_rchinfo *ch;
757 u_int32_t bus_addr, i;
759 int idx, data_bytes, adc_data;
760 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
765 {CDATA_LEFT_VOLUME, M3_DEFAULT_VOL},
766 {CDATA_RIGHT_VOLUME, M3_DEFAULT_VOL},
767 {SRC3_DIRECTION_OFFSET, 1},
768 {SRC3_DIRECTION_OFFSET + 3, 0x0000},
769 {SRC3_DIRECTION_OFFSET + 4, 0},
770 {SRC3_DIRECTION_OFFSET + 5, 0},
771 {SRC3_DIRECTION_OFFSET + 6, 0},
772 {SRC3_DIRECTION_OFFSET + 7, 0},
773 {SRC3_DIRECTION_OFFSET + 8, 0},
774 {SRC3_DIRECTION_OFFSET + 9, 0},
775 {SRC3_DIRECTION_OFFSET + 10, 0x8000},
776 {SRC3_DIRECTION_OFFSET + 11, 0xFF00},
777 {SRC3_DIRECTION_OFFSET + 13, 0},
778 {SRC3_DIRECTION_OFFSET + 14, 0},
779 {SRC3_DIRECTION_OFFSET + 15, 0},
780 {SRC3_DIRECTION_OFFSET + 16, 50},
781 {SRC3_DIRECTION_OFFSET + 17, 8},
782 {SRC3_DIRECTION_OFFSET + 18, 0},
783 {SRC3_DIRECTION_OFFSET + 19, 0},
784 {SRC3_DIRECTION_OFFSET + 20, 0},
785 {SRC3_DIRECTION_OFFSET + 21, 0},
786 {SRC3_DIRECTION_OFFSET + 22, 0xff}
790 idx = sc->rch_cnt; /* adc instance number, no active reuse! */
791 M3_DEBUG(CHANGE, ("m3_rchan_init(adc=%d)\n", idx));
793 if (dir != PCMDIR_REC) {
795 device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n");
799 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) +
800 (MINISRC_IN_BUFFER_SIZE & ~1) +
801 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255;
802 adc_data = 0x1100 + (data_bytes * idx) + data_bytes/2;
803 dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2);
804 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
805 dsp_in_buf = adc_data + (MINISRC_TMP_BUFFER_SIZE / 2);
806 dsp_out_buf = dsp_in_buf + (dsp_in_size / 2) + 1;
810 ch->adc_data = adc_data;
811 if (ch->adc_data + data_bytes/2 >= 0x1c00) {
813 device_printf(sc->dev, "m3_rchan_init: revb mem exhausted\n");
820 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
821 ch->spd = DSP_DEFAULT_SPEED;
822 M3_UNLOCK(sc); /* XXX */
823 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
824 device_printf(sc->dev, "m3_rchan_init chn_allocbuf failed\n");
828 ch->bufsize = sndbuf_getsize(ch->buffer);
830 /* host dma buffer pointers */
831 bus_addr = sndbuf_getbufaddr(ch->buffer);
833 device_printf(sc->dev, "m3_rchan_init unaligned bus_addr\n");
834 bus_addr = (bus_addr + 4) & ~3;
836 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
837 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
838 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1L,
839 LO(bus_addr + ch->bufsize));
840 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1H,
841 HI(bus_addr + ch->bufsize));
842 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL,
844 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH,
848 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
849 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_END_PLUS_1,
850 dsp_in_buf + dsp_in_size/2);
851 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
852 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
853 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
854 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_END_PLUS_1,
855 dsp_out_buf + dsp_out_size/2);
856 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
857 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
859 /* some per client initializers */
860 m3_wr_assp_data(sc, ch->adc_data + SRC3_DIRECTION_OFFSET + 12,
861 ch->adc_data + 40 + 8);
862 m3_wr_assp_data(sc, ch->adc_data + CDATA_DMA_CONTROL,
863 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
864 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
866 /* set an armload of static initializers */
867 for(i = 0 ; i < (sizeof(rv) / sizeof(rv[0])) ; i++) {
868 m3_wr_assp_data(sc, ch->adc_data + rv[i].addr, rv[i].val);
871 /* put us in the packed task lists */
872 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
873 (sc->pch_cnt + sc->rch_cnt),
874 ch->adc_data >> DP_SHIFT_COUNT);
875 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
876 ch->adc_data >> DP_SHIFT_COUNT);
877 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + sc->rch_cnt,
878 ch->adc_data >> DP_SHIFT_COUNT);
880 /* gotta start before stop */
881 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_START);
883 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_STOP);
892 m3_rchan_free(kobj_t kobj, void *chdata)
894 struct sc_rchinfo *ch = chdata;
895 struct sc_info *sc = ch->parent;
898 M3_DEBUG(CHANGE, ("m3_rchan_free(adc=%d)\n", ch->adc_idx));
901 * should remove this exact instance from the packed lists, but all
902 * are released at once (and in a stopped state) so this is ok.
904 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
905 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
906 m3_wr_assp_data(sc, KDATA_DMA_XFER0 +
907 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
908 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + (sc->rch_cnt - 1), 0);
916 m3_rchan_setformat(kobj_t kobj, void *chdata, u_int32_t format)
918 struct sc_rchinfo *ch = chdata;
919 struct sc_info *sc = ch->parent;
924 ("m3_rchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
926 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit",
927 (AFMT_CHANNEL(format) > 1) ? "STEREO":"MONO"));
930 data = (AFMT_CHANNEL(format) > 1) ? 0 : 1;
931 m3_wr_assp_data(sc, ch->adc_data + SRC3_MODE_OFFSET, data);
934 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0;
935 m3_wr_assp_data(sc, ch->adc_data + SRC3_WORD_LENGTH_OFFSET, data);
943 m3_rchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed)
945 struct sc_rchinfo *ch = chdata;
946 struct sc_info *sc = ch->parent;
950 M3_DEBUG(CHANGE, ("m3_rchan_setspeed(adc=%d, speed=%d)\n",
951 ch->adc_idx, speed));
953 if ((freq = ((speed << 15) + 24000) / 48000) != 0) {
957 m3_wr_assp_data(sc, ch->adc_data + CDATA_FREQUENCY, freq);
961 /* return closest possible speed */
966 m3_rchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize)
968 struct sc_rchinfo *ch = chdata;
970 M3_DEBUG(CHANGE, ("m3_rchan_setblocksize(adc=%d, blocksize=%d)\n",
971 ch->adc_idx, blocksize));
973 return (sndbuf_getblksz(ch->buffer));
977 m3_rchan_trigger(kobj_t kobj, void *chdata, int go)
979 struct sc_rchinfo *ch = chdata;
980 struct sc_info *sc = ch->parent;
983 if (!PCMTRIG_COMMON(go))
987 ret = m3_rchan_trigger_locked(kobj, chdata, go);
994 m3_rchan_trigger_locked(kobj_t kobj, void *chdata, int go)
996 struct sc_rchinfo *ch = chdata;
997 struct sc_info *sc = ch->parent;
1001 M3_DEBUG(go == PCMTRIG_START ? CHANGE :
1002 go == PCMTRIG_STOP ? CHANGE :
1003 go == PCMTRIG_ABORT ? CHANGE :
1005 ("m3_rchan_trigger(adc=%d, go=0x%x{%s})\n", ch->adc_idx, go,
1006 go == PCMTRIG_START ? "PCMTRIG_START" :
1007 go == PCMTRIG_STOP ? "PCMTRIG_STOP" :
1008 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore"));
1019 /*[[inc_timer_users]]*/
1020 if (m3_chan_active(sc) == 1) {
1021 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240);
1022 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240);
1023 data = m3_rd_2(sc, HOST_INT_CTRL);
1024 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
1027 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 1);
1028 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 1);
1033 if (ch->active == 0) {
1038 /*[[dec_timer_users]]*/
1039 if (m3_chan_active(sc) == 0) {
1040 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0);
1041 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0);
1042 data = m3_rd_2(sc, HOST_INT_CTRL);
1043 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);
1046 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 0);
1047 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 0);
1050 case PCMTRIG_EMLDMAWR:
1051 /* got play irq, transfer next buffer - ignore if using dma */
1052 case PCMTRIG_EMLDMARD:
1053 /* got rec irq, transfer next buffer - ignore if using dma */
1061 m3_rchan_getptr_internal(struct sc_rchinfo *ch)
1063 struct sc_info *sc = ch->parent;
1064 u_int32_t hi, lo, bus_base, bus_crnt;
1066 bus_base = sndbuf_getbufaddr(ch->buffer);
1067 hi = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH);
1068 lo = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL);
1069 bus_crnt = lo | (hi << 16);
1071 M3_DEBUG(CALL, ("m3_rchan_getptr(adc=%d) result=%d\n",
1072 ch->adc_idx, bus_crnt - bus_base));
1074 return (bus_crnt - bus_base); /* current byte offset of channel */
1078 m3_rchan_getptr(kobj_t kobj, void *chdata)
1080 struct sc_rchinfo *ch = chdata;
1081 struct sc_info *sc = ch->parent;
1091 static struct pcmchan_caps *
1092 m3_rchan_getcaps(kobj_t kobj, void *chdata)
1094 struct sc_rchinfo *ch = chdata;
1096 M3_DEBUG(CALL, ("m3_rchan_getcaps(adc=%d)\n", ch->adc_idx));
1101 /* -------------------------------------------------------------------- */
1102 /* The interrupt handler */
1107 struct sc_info *sc = (struct sc_info *)p;
1108 struct sc_pchinfo *pch;
1109 struct sc_rchinfo *rch;
1110 u_int32_t status, ctl, i, delta;
1112 M3_DEBUG(INTR, ("m3_intr\n"));
1115 status = m3_rd_1(sc, HOST_INT_STATUS);
1121 m3_wr_1(sc, HOST_INT_STATUS, 0xff); /* ack the int? */
1123 if (status & HV_INT_PENDING) {
1126 event = m3_rd_1(sc, HW_VOL_COUNTER_MASTER);
1129 mixer_hwvol_mute(sc->dev);
1132 mixer_hwvol_step(sc->dev, 1, 1);
1135 mixer_hwvol_step(sc->dev, -1, -1);
1140 device_printf(sc->dev, "Unknown HWVOL event\n");
1142 m3_wr_1(sc, HW_VOL_COUNTER_MASTER, 0x88);
1146 if (status & ASSP_INT_PENDING) {
1147 ctl = m3_rd_1(sc, ASSP_CONTROL_B);
1148 if (!(ctl & STOP_ASSP_CLOCK)) {
1149 ctl = m3_rd_1(sc, ASSP_HOST_INT_STATUS);
1150 if (ctl & DSP2HOST_REQ_TIMER) {
1151 m3_wr_1(sc, ASSP_HOST_INT_STATUS,
1152 DSP2HOST_REQ_TIMER);
1153 /*[[ess_update_ptr]]*/
1154 goto m3_handle_channel_intr;
1159 goto m3_handle_channel_intr_out;
1161 m3_handle_channel_intr:
1162 for (i=0 ; i<sc->pch_cnt ; i++) {
1165 pch->ptr = m3_pchan_getptr_internal(pch);
1166 delta = pch->bufsize + pch->ptr - pch->prevptr;
1167 delta %= pch->bufsize;
1168 if (delta < sndbuf_getblksz(pch->buffer))
1170 pch->prevptr = pch->ptr;
1172 chn_intr(pch->channel);
1176 for (i=0 ; i<sc->rch_cnt ; i++) {
1179 rch->ptr = m3_rchan_getptr_internal(rch);
1180 delta = rch->bufsize + rch->ptr - rch->prevptr;
1181 delta %= rch->bufsize;
1182 if (delta < sndbuf_getblksz(rch->buffer))
1184 rch->prevptr = rch->ptr;
1186 chn_intr(rch->channel);
1191 m3_handle_channel_intr_out:
1195 /* -------------------------------------------------------------------- */
1199 m3_power(struct sc_info *sc, int state)
1203 M3_DEBUG(CHANGE, ("m3_power(%d)\n", state));
1206 data = pci_read_config(sc->dev, 0x34, 1);
1207 if (pci_read_config(sc->dev, data, 1) == 1) {
1208 pci_write_config(sc->dev, data + 4, state, 1);
1215 m3_init(struct sc_info *sc)
1217 u_int32_t data, i, size;
1218 u_int8_t reset_state;
1221 M3_DEBUG(CHANGE, ("m3_init\n"));
1223 /* diable legacy emulations. */
1224 data = pci_read_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, 2);
1225 data |= DISABLE_LEGACY;
1226 pci_write_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, data, 2);
1230 reset_state = m3_assp_halt(sc);
1234 /* [m3_assp_init] */
1235 /* zero kernel data */
1236 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1237 for(i = 0 ; i < size / 2 ; i++) {
1238 m3_wr_assp_data(sc, KDATA_BASE_ADDR + i, 0);
1240 /* zero mixer data? */
1241 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1242 for(i = 0 ; i < size / 2 ; i++) {
1243 m3_wr_assp_data(sc, KDATA_BASE_ADDR2 + i, 0);
1245 /* init dma pointer */
1246 m3_wr_assp_data(sc, KDATA_CURRENT_DMA,
1248 /* write kernel into code memory */
1249 size = sizeof(gaw_kernel_vect_code);
1250 for(i = 0 ; i < size / 2; i++) {
1251 m3_wr_assp_code(sc, REV_B_CODE_MEMORY_BEGIN + i,
1252 gaw_kernel_vect_code[i]);
1255 * We only have this one client and we know that 0x400 is free in
1256 * our kernel's mem map, so lets just drop it there. It seems that
1257 * the minisrc doesn't need vectors, so we won't bother with them..
1259 size = sizeof(gaw_minisrc_code_0400);
1260 for(i = 0 ; i < size / 2; i++) {
1261 m3_wr_assp_code(sc, 0x400 + i, gaw_minisrc_code_0400[i]);
1263 /* write the coefficients for the low pass filter? */
1264 size = sizeof(minisrc_lpf);
1265 for(i = 0; i < size / 2 ; i++) {
1266 m3_wr_assp_code(sc,0x400 + MINISRC_COEF_LOC + i,
1269 m3_wr_assp_code(sc, 0x400 + MINISRC_COEF_LOC + size, 0x8000);
1270 /* the minisrc is the only thing on our task list */
1271 m3_wr_assp_data(sc, KDATA_TASK0, 0x400);
1272 /* init the mixer number */
1273 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 0);
1274 /* extreme kernel master volume */
1275 m3_wr_assp_data(sc, KDATA_DAC_LEFT_VOLUME, M3_DEFAULT_VOL);
1276 m3_wr_assp_data(sc, KDATA_DAC_RIGHT_VOLUME, M3_DEFAULT_VOL);
1280 /* [m3_assp_client_init] (only one client at index 0) */
1281 for (i=0x1100 ; i<0x1c00 ; i++) {
1282 m3_wr_assp_data(sc, i, 0); /* zero entire dac/adc area */
1285 /* [m3_assp_continue] */
1286 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
1292 m3_uninit(struct sc_info *sc)
1294 M3_DEBUG(CHANGE, ("m3_uninit\n"));
1298 /* -------------------------------------------------------------------- */
1299 /* Probe and attach the card */
1302 m3_pci_probe(device_t dev)
1304 struct m3_card_type *card;
1306 M3_DEBUG(CALL, ("m3_pci_probe(0x%x)\n", pci_get_devid(dev)));
1308 for (card = m3_card_types ; card->pci_id ; card++) {
1309 if (pci_get_devid(dev) == card->pci_id) {
1310 device_set_desc(dev, card->name);
1311 return BUS_PROBE_DEFAULT;
1318 m3_pci_attach(device_t dev)
1321 struct ac97_info *codec = NULL;
1322 char status[SND_STATUSLEN];
1323 struct m3_card_type *card;
1324 int i, len, dacn, adcn;
1326 M3_DEBUG(CALL, ("m3_pci_attach\n"));
1328 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
1330 sc->type = pci_get_devid(dev);
1331 sc->sc_lock = snd_mtxcreate(device_get_nameunit(dev),
1332 "snd_maestro3 softc");
1333 for (card = m3_card_types ; card->pci_id ; card++) {
1334 if (sc->type == card->pci_id) {
1335 sc->which = card->which;
1336 sc->delay1 = card->delay1;
1337 sc->delay2 = card->delay2;
1342 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
1346 else if (i > M3_PCHANS)
1355 pci_enable_busmaster(dev);
1357 sc->regid = PCIR_BAR(0);
1358 sc->regtype = SYS_RES_MEMORY;
1359 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
1362 sc->regtype = SYS_RES_IOPORT;
1363 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
1367 device_printf(dev, "unable to allocate register space\n");
1370 sc->st = rman_get_bustag(sc->reg);
1371 sc->sh = rman_get_bushandle(sc->reg);
1374 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
1375 RF_ACTIVE | RF_SHAREABLE);
1377 device_printf(dev, "unable to allocate interrupt\n");
1381 if (snd_setup_intr(dev, sc->irq, INTR_MPSAFE, m3_intr, sc, &sc->ih)) {
1382 device_printf(dev, "unable to setup interrupt\n");
1386 sc->bufsz = pcm_getbuffersize(dev, M3_BUFSIZE_MIN, M3_BUFSIZE_DEFAULT,
1389 if (bus_dma_tag_create(
1390 bus_get_dma_tag(dev), /* parent */
1391 2, 0, /* alignment, boundary */
1392 M3_MAXADDR, /* lowaddr */
1393 BUS_SPACE_MAXADDR, /* highaddr */
1394 NULL, NULL, /* filtfunc, filtfuncarg */
1395 sc->bufsz, /* maxsize */
1397 0x3ffff, /* maxsegz */
1399 NULL, /* lockfunc */
1400 NULL, /* lockfuncarg */
1401 &sc->parent_dmat) != 0) {
1402 device_printf(dev, "unable to create dma tag\n");
1407 m3_power(sc, 0); /* power up */
1412 device_printf(dev, "unable to initialize the card\n");
1416 /* create/init mixer */
1417 codec = AC97_CREATE(dev, sc, m3_codec);
1418 if (codec == NULL) {
1419 device_printf(dev, "ac97_create error\n");
1422 if (mixer_init(dev, ac97_getmixerclass(), codec)) {
1423 device_printf(dev, "mixer_init error\n");
1429 if (pcm_register(dev, sc, dacn, adcn)) {
1430 device_printf(dev, "pcm_register error\n");
1433 for (i=0 ; i<dacn ; i++) {
1434 if (pcm_addchan(dev, PCMDIR_PLAY, &m3_pch_class, sc)) {
1435 device_printf(dev, "pcm_addchan (play) error\n");
1439 for (i=0 ; i<adcn ; i++) {
1440 if (pcm_addchan(dev, PCMDIR_REC, &m3_rch_class, sc)) {
1441 device_printf(dev, "pcm_addchan (rec) error\n");
1445 snprintf(status, SND_STATUSLEN, "at %s 0x%jx irq %jd %s",
1446 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
1447 rman_get_start(sc->reg), rman_get_start(sc->irq),
1448 PCM_KLDSTRING(snd_maestro3));
1449 if (pcm_setstatus(dev, status)) {
1450 device_printf(dev, "attach: pcm_setstatus error\n");
1454 mixer_hwvol_init(dev);
1456 /* Create the buffer for saving the card state during suspend */
1457 len = sizeof(u_int16_t) * (REV_B_CODE_MEMORY_LENGTH +
1458 REV_B_DATA_MEMORY_LENGTH);
1459 sc->savemem = (u_int16_t*)malloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1465 ac97_destroy(codec);
1467 bus_teardown_intr(dev, sc->irq, sc->ih);
1469 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1471 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1472 if (sc->parent_dmat)
1473 bus_dma_tag_destroy(sc->parent_dmat);
1475 snd_mtxfree(sc->sc_lock);
1481 m3_pci_detach(device_t dev)
1483 struct sc_info *sc = pcm_getdevinfo(dev);
1486 M3_DEBUG(CALL, ("m3_pci_detach\n"));
1488 if ((r = pcm_unregister(dev)) != 0) {
1493 m3_uninit(sc); /* shutdown chip */
1494 m3_power(sc, 3); /* power off */
1497 bus_teardown_intr(dev, sc->irq, sc->ih);
1498 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1499 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1500 bus_dma_tag_destroy(sc->parent_dmat);
1502 free(sc->savemem, M_DEVBUF);
1503 snd_mtxfree(sc->sc_lock);
1509 m3_pci_suspend(device_t dev)
1511 struct sc_info *sc = pcm_getdevinfo(dev);
1514 M3_DEBUG(CHANGE, ("m3_pci_suspend\n"));
1517 for (i=0 ; i<sc->pch_cnt ; i++) {
1518 if (sc->pch[i].active) {
1519 m3_pchan_trigger_locked(NULL, &sc->pch[i],
1523 for (i=0 ; i<sc->rch_cnt ; i++) {
1524 if (sc->rch[i].active) {
1525 m3_rchan_trigger_locked(NULL, &sc->rch[i],
1529 DELAY(10 * 1000); /* give things a chance to stop */
1531 /* Disable interrupts */
1532 m3_wr_2(sc, HOST_INT_CTRL, 0);
1533 m3_wr_1(sc, ASSP_CONTROL_C, 0);
1537 /* Save the state of the ASSP */
1538 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
1539 sc->savemem[index++] = m3_rd_assp_code(sc, i);
1540 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++)
1541 sc->savemem[index++] = m3_rd_assp_data(sc, i);
1543 /* Power down the card to D3 state */
1551 m3_pci_resume(device_t dev)
1553 struct sc_info *sc = pcm_getdevinfo(dev);
1555 u_int8_t reset_state;
1557 M3_DEBUG(CHANGE, ("m3_pci_resume\n"));
1560 /* Power the card back to D0 */
1565 reset_state = m3_assp_halt(sc);
1569 /* Restore the ASSP state */
1570 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
1571 m3_wr_assp_code(sc, i, sc->savemem[index++]);
1572 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++)
1573 m3_wr_assp_data(sc, i, sc->savemem[index++]);
1575 /* Restart the DMA engine */
1576 m3_wr_assp_data(sc, KDATA_DMA_ACTIVE, 0);
1578 /* [m3_assp_continue] */
1579 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
1585 M3_UNLOCK(sc); /* XXX */
1586 if (mixer_reinit(dev) == -1) {
1587 device_printf(dev, "unable to reinitialize the mixer\n");
1592 /* Turn the channels back on */
1593 for (i=0 ; i<sc->pch_cnt ; i++) {
1594 if (sc->pch[i].active) {
1595 m3_pchan_trigger_locked(NULL, &sc->pch[i],
1599 for (i=0 ; i<sc->rch_cnt ; i++) {
1600 if (sc->rch[i].active) {
1601 m3_rchan_trigger_locked(NULL, &sc->rch[i],
1611 m3_pci_shutdown(device_t dev)
1613 struct sc_info *sc = pcm_getdevinfo(dev);
1615 M3_DEBUG(CALL, ("m3_pci_shutdown\n"));
1618 m3_power(sc, 3); /* power off */
1625 m3_assp_halt(struct sc_info *sc)
1627 u_int8_t data, reset_state;
1631 data = m3_rd_1(sc, DSP_PORT_CONTROL_REG_B);
1632 reset_state = data & ~REGB_STOP_CLOCK; /* remember for continue */
1634 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state & ~REGB_ENABLE_RESET);
1635 DELAY(10 * 1000); /* necessary? */
1641 m3_config(struct sc_info *sc)
1643 u_int32_t data, hv_cfg;
1650 * The volume buttons can be wired up via two different sets of pins.
1651 * This presents a problem since we can't tell which way it's
1652 * configured. Allow the user to set a hint in order to twiddle
1655 if (resource_int_value(device_get_name(sc->dev),
1656 device_get_unit(sc->dev),
1657 "hwvol_config", &hint) == 0)
1658 hv_cfg = (hint > 0) ? HV_BUTTON_FROM_GD : 0;
1660 hv_cfg = HV_BUTTON_FROM_GD;
1663 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1664 data &= ~HV_BUTTON_FROM_GD;
1665 data |= REDUCED_DEBOUNCE | HV_CTRL_ENABLE | hv_cfg;
1666 data |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
1667 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1669 m3_wr_1(sc, ASSP_CONTROL_B, RESET_ASSP);
1670 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1671 data &= ~INT_CLK_SELECT;
1672 if (sc->which == ESS_MAESTRO3) {
1673 data &= ~INT_CLK_MULT_ENABLE;
1674 data |= INT_CLK_SRC_NOT_PCI;
1676 data &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2);
1677 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1679 if (sc->which == ESS_ALLEGRO_1) {
1680 data = pci_read_config(sc->dev, PCI_USER_CONFIG, 4);
1681 data |= IN_CLK_12MHZ_SELECT;
1682 pci_write_config(sc->dev, PCI_USER_CONFIG, data, 4);
1685 data = m3_rd_1(sc, ASSP_CONTROL_A);
1686 data &= ~(DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
1687 data |= ASSP_CLK_49MHZ_SELECT; /*XXX assumes 49MHZ dsp XXX*/
1688 data |= ASSP_0_WS_ENABLE;
1689 m3_wr_1(sc, ASSP_CONTROL_A, data);
1691 m3_wr_1(sc, ASSP_CONTROL_B, RUN_ASSP);
1695 m3_enable_ints(struct sc_info *sc)
1699 m3_wr_2(sc, HOST_INT_CTRL, ASSP_INT_ENABLE | HV_INT_ENABLE);
1700 data = m3_rd_1(sc, ASSP_CONTROL_C);
1701 m3_wr_1(sc, ASSP_CONTROL_C, data | ASSP_HOST_INT_ENABLE);
1705 m3_amp_enable(struct sc_info *sc)
1707 u_int32_t gpo, polarity_port, polarity;
1712 switch (sc->which) {
1714 polarity_port = 0x1800;
1717 polarity_port = 0x1100;
1720 panic("bad sc->which");
1722 gpo = (polarity_port >> 8) & 0x0f;
1723 polarity = polarity_port >> 12;
1724 polarity = !polarity; /* enable */
1725 polarity = polarity << gpo;
1727 m3_wr_2(sc, GPIO_MASK, ~gpo);
1728 data = m3_rd_2(sc, GPIO_DIRECTION);
1729 m3_wr_2(sc, GPIO_DIRECTION, data | gpo);
1730 data = GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity;
1731 m3_wr_2(sc, GPIO_DATA, data);
1732 m3_wr_2(sc, GPIO_MASK, ~0);
1736 m3_codec_reset(struct sc_info *sc)
1738 u_int16_t data, dir;
1743 data = m3_rd_2(sc, GPIO_DIRECTION);
1744 dir = data | 0x10; /* assuming pci bus master? */
1746 /* [[remote_codec_config]] */
1747 data = m3_rd_2(sc, RING_BUS_CTRL_B);
1748 m3_wr_2(sc, RING_BUS_CTRL_B, data & ~SECOND_CODEC_ID_MASK);
1749 data = m3_rd_2(sc, SDO_OUT_DEST_CTRL);
1750 m3_wr_2(sc, SDO_OUT_DEST_CTRL, data & ~COMMAND_ADDR_OUT);
1751 data = m3_rd_2(sc, SDO_IN_DEST_CTRL);
1752 m3_wr_2(sc, SDO_IN_DEST_CTRL, data & ~STATUS_ADDR_IN);
1754 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE);
1757 m3_wr_2(sc, GPIO_DIRECTION, dir & ~GPO_PRIMARY_AC97);
1758 m3_wr_2(sc, GPIO_MASK, ~GPO_PRIMARY_AC97);
1759 m3_wr_2(sc, GPIO_DATA, 0);
1760 m3_wr_2(sc, GPIO_DIRECTION, dir | GPO_PRIMARY_AC97);
1761 DELAY(sc->delay1 * 1000); /*delay1 (ALLEGRO:50, MAESTRO3:20)*/
1762 m3_wr_2(sc, GPIO_DATA, GPO_PRIMARY_AC97);
1764 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE |
1765 SERIAL_AC_LINK_ENABLE);
1766 m3_wr_2(sc, GPIO_MASK, ~0);
1767 DELAY(sc->delay2 * 1000); /*delay2 (ALLEGRO:800, MAESTRO3:500)*/
1769 /* [[try read vendor]] */
1770 data = m3_rdcd(NULL, sc, 0x7c);
1771 if ((data == 0) || (data == 0xffff)) {
1774 device_printf(sc->dev, "Codec reset failed\n");
1777 device_printf(sc->dev, "Codec reset retry\n");
1782 static device_method_t m3_methods[] = {
1783 DEVMETHOD(device_probe, m3_pci_probe),
1784 DEVMETHOD(device_attach, m3_pci_attach),
1785 DEVMETHOD(device_detach, m3_pci_detach),
1786 DEVMETHOD(device_suspend, m3_pci_suspend),
1787 DEVMETHOD(device_resume, m3_pci_resume),
1788 DEVMETHOD(device_shutdown, m3_pci_shutdown),
1792 static driver_t m3_driver = {
1798 DRIVER_MODULE(snd_maestro3, pci, m3_driver, pcm_devclass, 0, 0);
1799 MODULE_DEPEND(snd_maestro3, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1800 MODULE_VERSION(snd_maestro3, 1);