2 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
27 #include <dev/sound/pcm/sound.h>
28 #include <dev/sound/pcm/ac97.h>
29 #include <dev/sound/pci/t4dwave.h>
31 #include <dev/pci/pcireg.h>
32 #include <dev/pci/pcivar.h>
34 SND_DECLARE_FILE("$FreeBSD$");
36 /* -------------------------------------------------------------------- */
38 #define TDX_PCI_ID 0x20001023
39 #define TNX_PCI_ID 0x20011023
40 #define ALI_PCI_ID 0x545110b9
41 #define SPA_PCI_ID 0x70181039
43 #define TR_DEFAULT_BUFSZ 0x1000
44 #define TR_TIMEOUT_CDC 0xffff
45 #define TR_MAXPLAYCH 4
47 * Though, it's not clearly documented in trident datasheet, trident
48 * audio cards can't handle DMA addresses located above 1GB. The LBA
49 * (loop begin address) register which holds DMA base address is 32bits
51 * But the MSB 2bits are used for other purposes(I guess it is really
52 * bad idea). This effectivly limits the DMA address space up to 1GB.
54 #define TR_MAXADDR ((1 << 30) - 1)
59 /* channel registers */
61 u_int32_t cso, alpha, fms, fmc, ec;
65 u_int32_t gvsel, pan, vol, ctrl;
66 u_int32_t active:1, was_active:1;
68 struct snd_dbuf *buffer;
69 struct pcm_channel *channel;
70 struct tr_info *parent;
75 u_int32_t active:1, was_active:1;
76 struct snd_dbuf *buffer;
77 struct pcm_channel *channel;
78 struct tr_info *parent;
81 /* device private data */
87 bus_space_handle_t sh;
88 bus_dma_tag_t parent_dmat;
90 struct resource *reg, *irq;
91 int regtype, regid, irqid;
99 struct tr_chinfo chinfo[TR_MAXPLAYCH];
100 struct tr_rchinfo recchinfo;
103 /* -------------------------------------------------------------------- */
105 static u_int32_t tr_recfmt[] = {
107 AFMT_STEREO | AFMT_U8,
109 AFMT_STEREO | AFMT_S8,
111 AFMT_STEREO | AFMT_S16_LE,
113 AFMT_STEREO | AFMT_U16_LE,
116 static struct pcmchan_caps tr_reccaps = {4000, 48000, tr_recfmt, 0};
118 static u_int32_t tr_playfmt[] = {
120 AFMT_STEREO | AFMT_U8,
122 AFMT_STEREO | AFMT_S8,
124 AFMT_STEREO | AFMT_S16_LE,
126 AFMT_STEREO | AFMT_U16_LE,
129 static struct pcmchan_caps tr_playcaps = {4000, 48000, tr_playfmt, 0};
131 /* -------------------------------------------------------------------- */
136 tr_rd(struct tr_info *tr, int regno, int size)
140 return bus_space_read_1(tr->st, tr->sh, regno);
142 return bus_space_read_2(tr->st, tr->sh, regno);
144 return bus_space_read_4(tr->st, tr->sh, regno);
151 tr_wr(struct tr_info *tr, int regno, u_int32_t data, int size)
155 bus_space_write_1(tr->st, tr->sh, regno, data);
158 bus_space_write_2(tr->st, tr->sh, regno, data);
161 bus_space_write_4(tr->st, tr->sh, regno, data);
166 /* -------------------------------------------------------------------- */
170 tr_rdcd(kobj_t obj, void *devinfo, int regno)
172 struct tr_info *tr = (struct tr_info *)devinfo;
177 treg=SPA_REG_CODECRD;
182 treg=TDX_REG_CODECWR;
184 treg=TDX_REG_CODECRD;
188 treg=TDX_REG_CODECRD;
192 treg=(regno & 0x100)? TNX_REG_CODEC2RD : TNX_REG_CODEC1RD;
196 printf("!!! tr_rdcd defaulted !!!\n");
203 snd_mtxlock(tr->lock);
204 if (tr->type == ALI_PCI_ID) {
205 u_int32_t chk1, chk2;
207 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
208 j = tr_rd(tr, treg, 4);
210 chk1 = tr_rd(tr, 0xc8, 4);
211 chk2 = tr_rd(tr, 0xc8, 4);
212 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2);
214 chk2 = tr_rd(tr, 0xc8, 4);
217 if (tr->type != ALI_PCI_ID || i > 0) {
218 tr_wr(tr, treg, regno | trw, 4);
220 for (i=TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
221 j=tr_rd(tr, treg, 4);
223 snd_mtxunlock(tr->lock);
224 if (i == 0) printf("codec timeout during read of register %x\n", regno);
225 return (j >> TR_CDC_DATA) & 0xffff;
229 tr_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
231 struct tr_info *tr = (struct tr_info *)devinfo;
236 treg=SPA_REG_CODECWR;
241 treg=TDX_REG_CODECWR;
245 treg=TNX_REG_CODECWR;
246 trw=TNX_CDC_RWSTAT | ((regno & 0x100)? TNX_CDC_SEC : 0);
249 printf("!!! tr_wrcd defaulted !!!");
257 printf("tr_wrcd: reg %x was %x", regno, tr_rdcd(devinfo, regno));
260 snd_mtxlock(tr->lock);
261 if (tr->type == ALI_PCI_ID) {
263 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
264 j = tr_rd(tr, treg, 4);
266 u_int32_t chk1, chk2;
267 chk1 = tr_rd(tr, 0xc8, 4);
268 chk2 = tr_rd(tr, 0xc8, 4);
269 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2);
271 chk2 = tr_rd(tr, 0xc8, 4);
274 if (tr->type != ALI_PCI_ID || i > 0) {
275 for (i=TR_TIMEOUT_CDC; (i>0) && (j & trw); i--)
276 j=tr_rd(tr, treg, 4);
277 if (tr->type == ALI_PCI_ID && tr->rev > 0x01)
279 tr_wr(tr, treg, (data << TR_CDC_DATA) | regno | trw, 4);
282 printf(" - wrote %x, now %x\n", data, tr_rdcd(devinfo, regno));
284 snd_mtxunlock(tr->lock);
285 if (i==0) printf("codec timeout writing %x, data %x\n", regno, data);
286 return (i > 0)? 0 : -1;
289 static kobj_method_t tr_ac97_methods[] = {
290 KOBJMETHOD(ac97_read, tr_rdcd),
291 KOBJMETHOD(ac97_write, tr_wrcd),
294 AC97_DECLARE(tr_ac97);
296 /* -------------------------------------------------------------------- */
297 /* playback channel interrupts */
301 tr_testint(struct tr_chinfo *ch)
303 struct tr_info *tr = ch->parent;
306 bank = (ch->index & 0x20) ? 1 : 0;
307 chan = ch->index & 0x1f;
308 return tr_rd(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 4) & (1 << chan);
313 tr_clrint(struct tr_chinfo *ch)
315 struct tr_info *tr = ch->parent;
318 bank = (ch->index & 0x20) ? 1 : 0;
319 chan = ch->index & 0x1f;
320 tr_wr(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 1 << chan, 4);
324 tr_enaint(struct tr_chinfo *ch, int enable)
326 struct tr_info *tr = ch->parent;
330 snd_mtxlock(tr->lock);
331 bank = (ch->index & 0x20) ? 1 : 0;
332 chan = ch->index & 0x1f;
333 reg = bank? TR_REG_INTENB : TR_REG_INTENA;
335 i = tr_rd(tr, reg, 4);
337 i |= (enable? 1 : 0) << chan;
340 tr_wr(tr, reg, i, 4);
341 snd_mtxunlock(tr->lock);
344 /* playback channels */
347 tr_selch(struct tr_chinfo *ch)
349 struct tr_info *tr = ch->parent;
352 i = tr_rd(tr, TR_REG_CIR, 4);
354 i |= ch->index & 0x3f;
355 tr_wr(tr, TR_REG_CIR, i, 4);
359 tr_startch(struct tr_chinfo *ch)
361 struct tr_info *tr = ch->parent;
364 bank = (ch->index & 0x20) ? 1 : 0;
365 chan = ch->index & 0x1f;
366 tr_wr(tr, bank? TR_REG_STARTB : TR_REG_STARTA, 1 << chan, 4);
370 tr_stopch(struct tr_chinfo *ch)
372 struct tr_info *tr = ch->parent;
375 bank = (ch->index & 0x20) ? 1 : 0;
376 chan = ch->index & 0x1f;
377 tr_wr(tr, bank? TR_REG_STOPB : TR_REG_STOPA, 1 << chan, 4);
381 tr_wrch(struct tr_chinfo *ch)
383 struct tr_info *tr = ch->parent;
384 u_int32_t cr[TR_CHN_REGS], i;
386 ch->gvsel &= 0x00000001;
387 ch->fmc &= 0x00000003;
388 ch->fms &= 0x0000000f;
389 ch->ctrl &= 0x0000000f;
390 ch->pan &= 0x0000007f;
391 ch->rvol &= 0x0000007f;
392 ch->cvol &= 0x0000007f;
393 ch->vol &= 0x000000ff;
394 ch->ec &= 0x00000fff;
395 ch->alpha &= 0x00000fff;
396 ch->delta &= 0x0000ffff;
397 ch->lba &= 0x3fffffff;
400 cr[3]=(ch->fmc<<14) | (ch->rvol<<7) | (ch->cvol);
401 cr[4]=(ch->gvsel<<31) | (ch->pan<<24) | (ch->vol<<16) | (ch->ctrl<<12) | (ch->ec);
407 ch->cso &= 0x0000ffff;
408 ch->eso &= 0x0000ffff;
409 cr[0]=(ch->cso<<16) | (ch->alpha<<4) | (ch->fms);
410 cr[2]=(ch->eso<<16) | (ch->delta);
413 ch->cso &= 0x00ffffff;
414 ch->eso &= 0x00ffffff;
415 cr[0]=((ch->delta & 0xff)<<24) | (ch->cso);
416 cr[2]=((ch->delta>>8)<<24) | (ch->eso);
417 cr[3]|=(ch->alpha<<20) | (ch->fms<<16) | (ch->fmc<<14);
420 snd_mtxlock(tr->lock);
422 for (i=0; i<TR_CHN_REGS; i++)
423 tr_wr(tr, TR_REG_CHNBASE+(i<<2), cr[i], 4);
424 snd_mtxunlock(tr->lock);
428 tr_rdch(struct tr_chinfo *ch)
430 struct tr_info *tr = ch->parent;
433 snd_mtxlock(tr->lock);
436 cr[i]=tr_rd(tr, TR_REG_CHNBASE+(i<<2), 4);
437 snd_mtxunlock(tr->lock);
440 ch->lba= (cr[1] & 0x3fffffff);
441 ch->fmc= (cr[3] & 0x0000c000) >> 14;
442 ch->rvol= (cr[3] & 0x00003f80) >> 7;
443 ch->cvol= (cr[3] & 0x0000007f);
444 ch->gvsel= (cr[4] & 0x80000000) >> 31;
445 ch->pan= (cr[4] & 0x7f000000) >> 24;
446 ch->vol= (cr[4] & 0x00ff0000) >> 16;
447 ch->ctrl= (cr[4] & 0x0000f000) >> 12;
448 ch->ec= (cr[4] & 0x00000fff);
453 ch->cso= (cr[0] & 0xffff0000) >> 16;
454 ch->alpha= (cr[0] & 0x0000fff0) >> 4;
455 ch->fms= (cr[0] & 0x0000000f);
456 ch->eso= (cr[2] & 0xffff0000) >> 16;
457 ch->delta= (cr[2] & 0x0000ffff);
460 ch->cso= (cr[0] & 0x00ffffff);
461 ch->eso= (cr[2] & 0x00ffffff);
462 ch->delta= ((cr[2] & 0xff000000) >> 16) | ((cr[0] & 0xff000000) >> 24);
463 ch->alpha= (cr[3] & 0xfff00000) >> 20;
464 ch->fms= (cr[3] & 0x000f0000) >> 16;
470 tr_fmttobits(u_int32_t fmt)
475 bits |= (fmt & AFMT_SIGNED)? 0x2 : 0;
476 bits |= (fmt & AFMT_STEREO)? 0x4 : 0;
477 bits |= (fmt & AFMT_16BIT)? 0x8 : 0;
482 /* -------------------------------------------------------------------- */
483 /* channel interface */
486 trpchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
488 struct tr_info *tr = devinfo;
489 struct tr_chinfo *ch;
491 KASSERT(dir == PCMDIR_PLAY, ("trpchan_init: bad direction"));
492 ch = &tr->chinfo[tr->playchns];
493 ch->index = tr->playchns++;
497 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0)
504 trpchan_setformat(kobj_t obj, void *data, u_int32_t format)
506 struct tr_chinfo *ch = data;
508 ch->ctrl = tr_fmttobits(format) | 0x01;
514 trpchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
516 struct tr_chinfo *ch = data;
518 ch->delta = (speed << 12) / 48000;
519 return (ch->delta * 48000) >> 12;
523 trpchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
525 struct tr_chinfo *ch = data;
527 sndbuf_resize(ch->buffer, 2, blocksize);
532 trpchan_trigger(kobj_t obj, void *data, int go)
534 struct tr_chinfo *ch = data;
536 if (!PCMTRIG_COMMON(go))
539 if (go == PCMTRIG_START) {
544 ch->lba = sndbuf_getbufaddr(ch->buffer);
546 ch->eso = (sndbuf_getsize(ch->buffer) / sndbuf_getbps(ch->buffer)) - 1;
547 ch->rvol = ch->cvol = 0x7f;
565 trpchan_getptr(kobj_t obj, void *data)
567 struct tr_chinfo *ch = data;
570 return ch->cso * sndbuf_getbps(ch->buffer);
573 static struct pcmchan_caps *
574 trpchan_getcaps(kobj_t obj, void *data)
579 static kobj_method_t trpchan_methods[] = {
580 KOBJMETHOD(channel_init, trpchan_init),
581 KOBJMETHOD(channel_setformat, trpchan_setformat),
582 KOBJMETHOD(channel_setspeed, trpchan_setspeed),
583 KOBJMETHOD(channel_setblocksize, trpchan_setblocksize),
584 KOBJMETHOD(channel_trigger, trpchan_trigger),
585 KOBJMETHOD(channel_getptr, trpchan_getptr),
586 KOBJMETHOD(channel_getcaps, trpchan_getcaps),
589 CHANNEL_DECLARE(trpchan);
591 /* -------------------------------------------------------------------- */
592 /* rec channel interface */
595 trrchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
597 struct tr_info *tr = devinfo;
598 struct tr_rchinfo *ch;
600 KASSERT(dir == PCMDIR_REC, ("trrchan_init: bad direction"));
605 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0)
612 trrchan_setformat(kobj_t obj, void *data, u_int32_t format)
614 struct tr_rchinfo *ch = data;
615 struct tr_info *tr = ch->parent;
618 bits = tr_fmttobits(format);
619 /* set # of samples between interrupts */
620 i = (sndbuf_runsz(ch->buffer) >> ((bits & 0x08)? 1 : 0)) - 1;
621 tr_wr(tr, TR_REG_SBBL, i | (i << 16), 4);
622 /* set sample format */
623 i = 0x18 | (bits << 4);
624 tr_wr(tr, TR_REG_SBCTRL, i, 1);
631 trrchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
633 struct tr_rchinfo *ch = data;
634 struct tr_info *tr = ch->parent;
637 ch->delta = (48000 << 12) / speed;
638 tr_wr(tr, TR_REG_SBDELTA, ch->delta, 2);
640 /* return closest possible speed */
641 return (48000 << 12) / ch->delta;
645 trrchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
647 struct tr_rchinfo *ch = data;
649 sndbuf_resize(ch->buffer, 2, blocksize);
655 trrchan_trigger(kobj_t obj, void *data, int go)
657 struct tr_rchinfo *ch = data;
658 struct tr_info *tr = ch->parent;
661 if (!PCMTRIG_COMMON(go))
664 if (go == PCMTRIG_START) {
665 /* set up dma mode regs */
666 tr_wr(tr, TR_REG_DMAR15, 0, 1);
667 i = tr_rd(tr, TR_REG_DMAR11, 1) & 0x03;
668 tr_wr(tr, TR_REG_DMAR11, i | 0x54, 1);
669 /* set up base address */
670 tr_wr(tr, TR_REG_DMAR0, sndbuf_getbufaddr(ch->buffer), 4);
671 /* set up buffer size */
672 i = tr_rd(tr, TR_REG_DMAR4, 4) & ~0x00ffffff;
673 tr_wr(tr, TR_REG_DMAR4, i | (sndbuf_runsz(ch->buffer) - 1), 4);
675 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) | 1, 1);
678 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) & ~7, 1);
687 trrchan_getptr(kobj_t obj, void *data)
689 struct tr_rchinfo *ch = data;
690 struct tr_info *tr = ch->parent;
692 /* return current byte offset of channel */
693 return tr_rd(tr, TR_REG_DMAR0, 4) - sndbuf_getbufaddr(ch->buffer);
696 static struct pcmchan_caps *
697 trrchan_getcaps(kobj_t obj, void *data)
702 static kobj_method_t trrchan_methods[] = {
703 KOBJMETHOD(channel_init, trrchan_init),
704 KOBJMETHOD(channel_setformat, trrchan_setformat),
705 KOBJMETHOD(channel_setspeed, trrchan_setspeed),
706 KOBJMETHOD(channel_setblocksize, trrchan_setblocksize),
707 KOBJMETHOD(channel_trigger, trrchan_trigger),
708 KOBJMETHOD(channel_getptr, trrchan_getptr),
709 KOBJMETHOD(channel_getcaps, trrchan_getcaps),
712 CHANNEL_DECLARE(trrchan);
714 /* -------------------------------------------------------------------- */
715 /* The interrupt handler */
720 struct tr_info *tr = (struct tr_info *)p;
721 struct tr_chinfo *ch;
722 u_int32_t active, mask, bufhalf, chnum, intsrc;
725 intsrc = tr_rd(tr, TR_REG_MISCINT, 4);
726 if (intsrc & TR_INT_ADDR) {
730 active = tr_rd(tr, (chnum < 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, 4);
731 bufhalf = tr_rd(tr, (chnum < 32)? TR_REG_CSPF_A : TR_REG_CSPF_B, 4);
735 tmp = (bufhalf & mask)? 1 : 0;
736 if (chnum < tr->playchns) {
737 ch = &tr->chinfo[chnum];
738 /* printf("%d @ %d, ", chnum, trpchan_getptr(NULL, ch)); */
739 if (ch->bufhalf != tmp) {
740 chn_intr(ch->channel);
747 } while (chnum & 31);
751 tr_wr(tr, (chnum <= 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, active, 4);
754 if (intsrc & TR_INT_SB) {
755 chn_intr(tr->recchinfo.channel);
756 tr_rd(tr, TR_REG_SBR9, 1);
757 tr_rd(tr, TR_REG_SBR10, 1);
761 /* -------------------------------------------------------------------- */
764 * Probe and attach the card
768 tr_init(struct tr_info *tr)
772 tr_wr(tr, SPA_REG_GPIO, 0, 4);
773 tr_wr(tr, SPA_REG_CODECST, SPA_RST_OFF, 4);
776 tr_wr(tr, TDX_REG_CODECST, TDX_CDC_ON, 4);
779 tr_wr(tr, TNX_REG_CODECST, TNX_CDC_ON, 4);
783 tr_wr(tr, TR_REG_CIR, TR_CIR_MIDENA | TR_CIR_ADDRENA, 4);
788 tr_pci_probe(device_t dev)
790 switch (pci_get_devid(dev)) {
792 device_set_desc(dev, "SiS 7018");
793 return BUS_PROBE_DEFAULT;
795 device_set_desc(dev, "Acer Labs M5451");
796 return BUS_PROBE_DEFAULT;
798 device_set_desc(dev, "Trident 4DWave DX");
799 return BUS_PROBE_DEFAULT;
801 device_set_desc(dev, "Trident 4DWave NX");
802 return BUS_PROBE_DEFAULT;
809 tr_pci_attach(device_t dev)
813 struct ac97_info *codec = 0;
815 char status[SND_STATUSLEN];
817 tr = malloc(sizeof(*tr), M_DEVBUF, M_WAITOK | M_ZERO);
818 tr->type = pci_get_devid(dev);
819 tr->rev = pci_get_revid(dev);
820 tr->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_t4dwave softc");
822 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
826 else if (i > TR_MAXPLAYCH)
841 data = pci_read_config(dev, PCIR_COMMAND, 2);
842 data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
843 pci_write_config(dev, PCIR_COMMAND, data, 2);
844 data = pci_read_config(dev, PCIR_COMMAND, 2);
846 tr->regid = PCIR_BAR(0);
847 tr->regtype = SYS_RES_IOPORT;
848 tr->reg = bus_alloc_resource_any(dev, tr->regtype, &tr->regid,
851 tr->st = rman_get_bustag(tr->reg);
852 tr->sh = rman_get_bushandle(tr->reg);
854 device_printf(dev, "unable to map register space\n");
858 tr->bufsz = pcm_getbuffersize(dev, 4096, TR_DEFAULT_BUFSZ, 65536);
860 if (tr_init(tr) == -1) {
861 device_printf(dev, "unable to initialize the card\n");
866 codec = AC97_CREATE(dev, tr, tr_ac97);
867 if (codec == NULL) goto bad;
868 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad;
871 tr->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &tr->irqid,
872 RF_ACTIVE | RF_SHAREABLE);
873 if (!tr->irq || snd_setup_intr(dev, tr->irq, 0, tr_intr, tr, &tr->ih)) {
874 device_printf(dev, "unable to map interrupt\n");
878 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
880 /*lowaddr*/TR_MAXADDR,
881 /*highaddr*/BUS_SPACE_MAXADDR,
882 /*filter*/NULL, /*filterarg*/NULL,
883 /*maxsize*/tr->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
884 /*flags*/0, /*lockfunc*/busdma_lock_mutex,
885 /*lockarg*/&Giant, &tr->parent_dmat) != 0) {
886 device_printf(dev, "unable to create dma tag\n");
890 snprintf(status, 64, "at io 0x%lx irq %ld %s",
891 rman_get_start(tr->reg), rman_get_start(tr->irq),PCM_KLDSTRING(snd_t4dwave));
893 if (pcm_register(dev, tr, dacn, 1))
895 pcm_addchan(dev, PCMDIR_REC, &trrchan_class, tr);
896 for (i = 0; i < dacn; i++)
897 pcm_addchan(dev, PCMDIR_PLAY, &trpchan_class, tr);
898 pcm_setstatus(dev, status);
903 if (codec) ac97_destroy(codec);
904 if (tr->reg) bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);
905 if (tr->ih) bus_teardown_intr(dev, tr->irq, tr->ih);
906 if (tr->irq) bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq);
907 if (tr->parent_dmat) bus_dma_tag_destroy(tr->parent_dmat);
908 if (tr->lock) snd_mtxfree(tr->lock);
914 tr_pci_detach(device_t dev)
919 r = pcm_unregister(dev);
923 tr = pcm_getdevinfo(dev);
924 bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);
925 bus_teardown_intr(dev, tr->irq, tr->ih);
926 bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq);
927 bus_dma_tag_destroy(tr->parent_dmat);
928 snd_mtxfree(tr->lock);
935 tr_pci_suspend(device_t dev)
940 tr = pcm_getdevinfo(dev);
942 for (i = 0; i < tr->playchns; i++) {
943 tr->chinfo[i].was_active = tr->chinfo[i].active;
944 if (tr->chinfo[i].active) {
945 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_STOP);
949 tr->recchinfo.was_active = tr->recchinfo.active;
950 if (tr->recchinfo.active) {
951 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_STOP);
958 tr_pci_resume(device_t dev)
963 tr = pcm_getdevinfo(dev);
965 if (tr_init(tr) == -1) {
966 device_printf(dev, "unable to initialize the card\n");
970 if (mixer_reinit(dev) == -1) {
971 device_printf(dev, "unable to initialize the mixer\n");
975 for (i = 0; i < tr->playchns; i++) {
976 if (tr->chinfo[i].was_active) {
977 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_START);
981 if (tr->recchinfo.was_active) {
982 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_START);
988 static device_method_t tr_methods[] = {
989 /* Device interface */
990 DEVMETHOD(device_probe, tr_pci_probe),
991 DEVMETHOD(device_attach, tr_pci_attach),
992 DEVMETHOD(device_detach, tr_pci_detach),
993 DEVMETHOD(device_suspend, tr_pci_suspend),
994 DEVMETHOD(device_resume, tr_pci_resume),
998 static driver_t tr_driver = {
1004 DRIVER_MODULE(snd_t4dwave, pci, tr_driver, pcm_devclass, 0, 0);
1005 MODULE_DEPEND(snd_t4dwave, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1006 MODULE_VERSION(snd_t4dwave, 1);