2 * Copyright (c) 1996 John Hay.
3 * Copyright (c) 1996 SDL Communications, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * $Id: if_sr.c,v 1.15 1998/06/21 14:53:12 bde Exp $
34 * Programming assumptions and other issues.
36 * Only a 16K window will be used.
38 * The descriptors of a DMA channel will fit in a 16K memory window.
40 * The buffers of a transmit DMA channel will fit in a 16K memory window.
42 * When interface is going up, handshaking is set and it is only cleared
43 * when the interface is down'ed.
45 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
46 * internal/external clock, etc.....
60 #error Device 'sr' requires sppp.
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/kernel.h>
66 #include <sys/malloc.h>
68 #include <sys/sockio.h>
69 #include <sys/socket.h>
72 #include <net/if_sppp.h>
78 #include <machine/md_var.h>
80 #include <i386/isa/if_srregs.h>
81 #include <i386/isa/ic/hd64570.h>
82 #include <i386/isa/isa_device.h>
84 /* #define USE_MODEMCK */
90 #define PPP_HEADER_LEN 4
93 * These macros are used to hide the difference between the way the
94 * ISA N2 cards and the PCI N2 cards access the Hitachi 64570 SCA.
96 #define SRC_GET8(base,off) (*hc->src_get8)(base,(u_int)&off)
97 #define SRC_GET16(base,off) (*hc->src_get16)(base,(u_int)&off)
98 #define SRC_PUT8(base,off,d) (*hc->src_put8)(base,(u_int)&off,d)
99 #define SRC_PUT16(base,off,d) (*hc->src_put16)(base,(u_int)&off,d)
102 * These macros enable/disable the DPRAM and select the correct
105 #define SRC_GET_WIN(addr) ((addr >> SRC_WIN_SHFT) & SR_PG_MSK)
107 #define SRC_SET_ON(iobase) outb(iobase+SR_PCR, \
108 SR_PCR_MEM_WIN | inb(iobase+SR_PCR))
109 #define SRC_SET_MEM(iobase,win) outb(iobase+SR_PSR, SRC_GET_WIN(win) | \
110 (inb(iobase+SR_PSR) & ~SR_PG_MSK))
111 #define SRC_SET_OFF(iobase) outb(iobase+SR_PCR, \
112 ~SR_PCR_MEM_WIN & inb(iobase+SR_PCR))
115 * Define the hardware (card information) structure needed to keep
116 * track of the device itself... There is only one per card.
119 struct sr_hardc *next; /* PCI card linkage */
120 struct sr_softc *sc; /* software channels */
121 int cunit; /* card w/in system */
123 u_short iobase; /* I/O Base Address */
125 int numports; /* # of ports on cd */
127 u_int memsize; /* DPRAM size: bytes */
129 vm_offset_t sca_base;
130 vm_offset_t mem_pstart; /* start of buffer */
131 caddr_t mem_start; /* start of DP RAM */
132 caddr_t mem_end; /* end of DP RAM */
135 sca_regs *sca; /* register array */
138 * We vectorize the following functions to allow re-use between the
139 * ISA card's needs and those of the PCI card.
141 void (*src_put8)(u_int base, u_int off, u_int val);
142 void (*src_put16)(u_int base, u_int off, u_int val);
143 u_int (*src_get8)(u_int base, u_int off);
144 u_int (*src_get16)(u_int base, u_int off);
147 static int next_sc_unit = 0;
148 static int sr_watcher = 0;
149 static struct sr_hardc sr_hardc[NSR];
150 static struct sr_hardc *sr_hardc_pci;
153 * Define the software interface for the card... There is one for
154 * every channel (port).
157 struct sppp ifsppp; /* PPP service w/in system */
158 struct sr_hardc *hc; /* card-level information */
160 int unit; /* With regard to all sr devices */
161 int subunit; /* With regard to this card */
163 int attached; /* attached to FR or PPP */
164 int protocol; /* FR or PPP */
165 #define N2_USE_FRP 2 /* Frame Relay Protocol */
166 #define N2_USE_PPP 1 /* Point-to-Point Protocol */
169 u_int txdesc; /* DPRAM offset */
170 u_int txstart;/* DPRAM offset */
171 u_int txend; /* DPRAM offset */
172 u_int txtail; /* # of 1st free gran */
173 u_int txmax; /* # of free grans */
174 u_int txeda; /* err descr addr */
175 } block[SR_TX_BLOCKS];
177 char xmit_busy; /* Transmitter is busy */
178 char txb_inuse; /* # of tx grans in use */
179 u_int txb_new; /* ndx to new buffer */
180 u_int txb_next_tx; /* ndx to next gran rdy tx */
182 u_int rxdesc; /* DPRAM offset */
183 u_int rxstart; /* DPRAM offset */
184 u_int rxend; /* DPRAM offset */
185 u_int rxhind; /* ndx to the hd of rx bufrs */
186 u_int rxmax; /* # of avail grans */
188 u_int clk_cfg; /* Clock configuration */
190 int scachan; /* channel # on card */
194 * List of valid interrupt numbers for the N2 ISA card.
196 static int sr_irqtable[16] = {
215 static int srprobe(struct isa_device *id);
216 static int srattach_isa(struct isa_device *id);
218 struct isa_driver srdriver = {srprobe, srattach_isa, "src"};
221 * Baud Rate table for Sync Mode.
222 * Each entry consists of 3 elements:
223 * Baud Rate (x100) , TMC, BR
225 * Baud Rate = FCLK / TMC / 2^BR
226 * Baud table for Crystal freq. of 9.8304 Mhz
230 int target; /* target rate/100 */
231 int tmc_reg; /* TMC register value */
232 int br_reg; /* BR (BaudRateClk) selector */
234 /* Baudx100 TMC BR */
255 int sr_test_speed[] = {
261 SR_MCR_ETC0, /* ISA channel 0 */
262 SR_MCR_ETC1, /* ISA channel 1 */
263 SR_FECR_ETC0, /* PCI channel 0 */
264 SR_FECR_ETC1 /* PCI channel 1 */
268 struct sr_hardc *srattach_pci(int unit, vm_offset_t plx_vaddr,
269 vm_offset_t sca_vaddr);
270 void srintr_hc(struct sr_hardc *hc);
272 static int srattach(struct sr_hardc *hc);
273 static ointhand2_t srintr;
274 static void sr_xmit(struct sr_softc *sc);
275 static void srstart(struct ifnet *ifp);
276 static int srioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
277 static void srwatchdog(struct ifnet *ifp);
278 static int sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat);
279 static void sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len);
280 static void sr_eat_packet(struct sr_softc *sc, int single);
281 static void sr_get_packets(struct sr_softc *sc);
283 static void sr_up(struct sr_softc *sc);
284 static void sr_down(struct sr_softc *sc);
285 static void src_init(struct sr_hardc *hc);
286 static void sr_init_sca(struct sr_hardc *hc);
287 static void sr_init_msci(struct sr_softc *sc);
288 static void sr_init_rx_dmac(struct sr_softc *sc);
289 static void sr_init_tx_dmac(struct sr_softc *sc);
290 static void sr_dmac_intr(struct sr_hardc *hc, u_char isr);
291 static void sr_msci_intr(struct sr_hardc *hc, u_char isr);
292 static void sr_timer_intr(struct sr_hardc *hc, u_char isr);
293 static void sr_modemck(void *x);
295 static u_int src_get8_io(u_int base, u_int off);
296 static u_int src_get16_io(u_int base, u_int off);
297 static void src_put8_io(u_int base, u_int off, u_int val);
298 static void src_put16_io(u_int base, u_int off, u_int val);
299 static u_int src_get8_mem(u_int base, u_int off);
300 static u_int src_get16_mem(u_int base, u_int off);
301 static void src_put8_mem(u_int base, u_int off, u_int val);
302 static void src_put16_mem(u_int base, u_int off, u_int val);
305 extern void fr_detach(struct ifnet *);
306 extern int fr_attach(struct ifnet *);
307 extern int fr_ioctl(struct ifnet *, int, caddr_t);
308 extern void fr_flush(struct ifnet *);
309 extern int fr_input(struct ifnet *, struct mbuf *);
310 extern struct mbuf *fr_dequeue(struct ifnet *);
314 * I/O for ISA N2 card(s)
316 #define SRC_REG(iobase,y) ((((y) & 0xf) + (((y) & 0xf0) << 6) + \
320 src_get8_io(u_int base, u_int off)
322 return inb(SRC_REG(base, off));
326 src_get16_io(u_int base, u_int off)
328 return inw(SRC_REG(base, off));
332 src_put8_io(u_int base, u_int off, u_int val)
334 outb(SRC_REG(base, off), val);
338 src_put16_io(u_int base, u_int off, u_int val)
340 outw(SRC_REG(base, off), val);
344 * I/O for PCI N2 card(s)
346 #define SRC_PCI_SCA_REG(y) ((y & 2) ? ((y & 0xfd) + 0x100) : y)
349 src_get8_mem(u_int base, u_int off)
351 return *((u_char *)(base + SRC_PCI_SCA_REG(off)));
355 src_get16_mem(u_int base, u_int off)
357 return *((u_short *)(base + SRC_PCI_SCA_REG(off)));
361 src_put8_mem(u_int base, u_int off, u_int val)
363 *((u_char *)(base + SRC_PCI_SCA_REG(off))) = (u_char)val;
367 src_put16_mem(u_int base, u_int off, u_int val)
369 *((u_short *)(base + SRC_PCI_SCA_REG(off))) = (u_short)val;
373 * Probe for an ISA card. If it is there, size its memory. Then get the
374 * rest of its information and fill it in.
377 srprobe(struct isa_device *id)
379 struct sr_hardc *hc = &sr_hardc[id->id_unit];
387 * Now see if the card is realy there.
389 hc->cardtype = SR_CRD_N2;
392 * We have to fill these in early because the SRC_PUT* and SRC_GET*
395 hc->src_get8 = src_get8_io;
396 hc->src_get16 = src_get16_io;
397 hc->src_put8 = src_put8_io;
398 hc->src_put16 = src_put16_io;
401 port = id->id_iobase;
402 hc->numports = NCHAN; /* assumed # of channels on the card */
404 if (id->id_flags & SR_FLAGS_NCHAN_MSK)
405 hc->numports = id->id_flags & SR_FLAGS_NCHAN_MSK;
407 outb(port + SR_PCR, 0); /* turn off the card */
410 * Next, we'll test the Base Address Register to retension of
411 * data... ... seeing if we're *really* talking to an N2.
413 for (i = 0; i < 0x100; i++) {
414 outb(port + SR_BAR, i);
416 tmp = inb(port + SR_BAR);
418 printf("sr%d: probe failed BAR %x, %x.\n",
419 id->id_unit, i, tmp);
425 * Now see if we can see the SCA.
427 outb(port + SR_PCR, SR_PCR_SCARUN | inb(port + SR_PCR));
428 SRC_PUT8(port, sca->wcrl, 0);
429 SRC_PUT8(port, sca->wcrm, 0);
430 SRC_PUT8(port, sca->wcrh, 0);
431 SRC_PUT8(port, sca->pcr, 0);
432 SRC_PUT8(port, sca->msci[0].tmc, 0);
435 tmp = SRC_GET8(port, sca->msci[0].tmc);
437 printf("sr%d: Error reading SCA 0, %x\n", id->id_unit, tmp);
440 SRC_PUT8(port, sca->msci[0].tmc, 0x5A);
443 tmp = SRC_GET8(port, sca->msci[0].tmc);
445 printf("sr%d: Error reading SCA 0x5A, %x\n", id->id_unit, tmp);
448 SRC_PUT16(port, sca->dmac[0].cda, 0);
451 tmp = SRC_GET16(port, sca->dmac[0].cda);
453 printf("sr%d: Error reading SCA 0, %x\n", id->id_unit, tmp);
456 SRC_PUT16(port, sca->dmac[0].cda, 0x55AA);
459 tmp = SRC_GET16(port, sca->dmac[0].cda);
461 printf("sr%d: Error reading SCA 0x55AA, %x\n",
466 * OK, the board's interface registers seem to work. Now we'll see
467 * if the Dual-Ported RAM is fully accessible...
469 outb(port + SR_PCR, SR_PCR_EN_VPM | SR_PCR_ISA16);
470 outb(port + SR_PSR, SR_PSR_WIN_16K);
473 * Take the kernel "virtual" address supplied to us and convert
474 * it to a "real" address. Then program the card to use that.
476 mar = (kvtop(id->id_maddr) >> 16) & SR_PCR_16M_SEL;
477 outb(port + SR_PCR, mar | inb(port + SR_PCR));
478 mar = kvtop(id->id_maddr) >> 12;
479 outb(port + SR_BAR, mar);
480 outb(port + SR_PCR, inb(port + SR_PCR) | SR_PCR_MEM_WIN);
481 smem = (u_short *)id->id_maddr; /* DP RAM Address */
484 * Here we will perform the memory scan to size the device.
486 * This is done by marking each potential page with a magic number.
487 * We then loop through the pages looking for that magic number. As
488 * soon as we no longer see that magic number, we'll quit the scan,
489 * knowing that no more memory is present. This provides the number
490 * of pages present on the card.
492 * Note: We're sizing 16K memory granules.
494 for (i = 0; i <= SR_PSR_PG_SEL; i++) {
496 (inb(port + SR_PSR) & ~SR_PSR_PG_SEL) | i);
501 for (i = 0; i <= SR_PSR_PG_SEL; i++) {
503 (inb(port + SR_PSR) & ~SR_PSR_PG_SEL) | i);
505 if (*smem != 0xAA55) {
507 * If we have less than 64k of memory, give up. That
511 printf("sr%d: Bad mem page %d, mem %x, %x.\n",
512 id->id_unit, i, 0xAA55, *smem);
521 hc->memsize = i * SRC_WIN_SIZ;
522 hc->winmsk = SRC_WIN_MSK;
523 pgs = i; /* final count of 16K pages */
526 * This next loop erases the contents of that page in DPRAM
528 for (i = 0; i <= pgs; i++) {
530 (inb(port + SR_PSR) & ~SR_PSR_PG_SEL) | i);
531 bzero(smem, SRC_WIN_SIZ);
537 * We have a card here, fill in what we can.
539 id->id_msize = SRC_WIN_SIZ;
540 hc->iobase = id->id_iobase;
541 hc->sca_base = id->id_iobase;
542 hc->mem_start = id->id_maddr;
543 hc->mem_end = (id->id_maddr + id->id_msize) - 1;
545 hc->cunit = id->id_unit;
548 * Do a little sanity check.
550 if (sr_irqtable[ffs(id->id_irq) - 1] == 0)
551 printf("sr%d: Warning: illegal interrupt %d chosen.\n",
552 id->id_unit, ffs(id->id_irq) - 1);
555 * Bogus card configuration
557 if ((hc->numports > NCHAN) /* only 2 ports/card */
558 ||(hc->memsize > (512 * 1024))) /* no more than 256K */
561 return SRC_IO_SIZ; /* return the amount of IO addresses used. */
565 * srattach_isa and srattach_pci allocate memory for hardc, softc and
566 * data buffers. It also does any initialization that is bus specific.
567 * At the end they call the common srattach() function.
570 srattach_isa(struct isa_device *id)
573 struct sr_hardc *hc = &sr_hardc[id->id_unit];
575 outb(hc->iobase + SR_PCR, inb(hc->iobase + SR_PCR) | SR_PCR_SCARUN);
576 outb(hc->iobase + SR_PSR, inb(hc->iobase + SR_PSR) | SR_PSR_EN_SCA_DMA);
577 outb(hc->iobase + SR_MCR,
578 SR_MCR_DTR0 | SR_MCR_DTR1 | SR_MCR_TE0 | SR_MCR_TE1);
580 SRC_SET_ON(hc->iobase);
583 * Configure the card. Mem address, irq,
585 mar = (kvtop(id->id_maddr) >> 16) & SR_PCR_16M_SEL;
586 outb(hc->iobase + SR_PCR,
587 mar | (inb(hc->iobase + SR_PCR) & ~SR_PCR_16M_SEL));
588 mar = kvtop(id->id_maddr) >> 12;
589 outb(hc->iobase + SR_BAR, mar);
592 * Allocate the software interface table(s)
594 hc->sc = malloc(hc->numports * sizeof(struct sr_softc),
596 bzero(hc->sc, hc->numports * sizeof(struct sr_softc));
599 * Get the TX clock direction and configuration. The default is a
600 * single external clock which is used by RX and TX.
603 if (sr_test_speed[0] > 0)
604 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
605 else if (id->id_flags & SR_FLAGS_0_CLK_MSK)
607 (id->id_flags & SR_FLAGS_0_CLK_MSK)
608 >> SR_FLAGS_CLK_SHFT;
610 if (id->id_flags & SR_FLAGS_0_CLK_MSK)
612 (id->id_flags & SR_FLAGS_0_CLK_MSK)
613 >> SR_FLAGS_CLK_SHFT;
616 if (hc->numports == 2)
618 if (sr_test_speed[1] > 0)
619 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
622 if (id->id_flags & SR_FLAGS_1_CLK_MSK)
623 hc->sc[1].clk_cfg = (id->id_flags & SR_FLAGS_1_CLK_MSK)
624 >> (SR_FLAGS_CLK_SHFT + SR_FLAGS_CLK_CHAN_SHFT);
630 srattach_pci(int unit, vm_offset_t plx_vaddr, vm_offset_t sca_vaddr)
633 u_int fecr, *fecrp = (u_int *)(sca_vaddr + SR_FECR);
634 struct sr_hardc *hc, **hcp;
637 * Configure the PLX. This is magic. I'm doing it just like I'm told
641 * 0x00 - Map Range - Mem-mapped to locate anywhere
642 * 0x04 - Re-Map - PCI address decode enable
643 * 0x18 - Bus Region - 32-bit bus, ready enable
644 * 0x1c - Master Range - include all 16 MB
645 * 0x20 - Master RAM - Map SCA Base at 0
646 * 0x28 - Master Remap - direct master memory enable
647 * 0x68 - Interrupt - Enable interrupt (0 to disable)
649 * Note: This is "cargo cult" stuff. - jrc
651 *((u_int *)(plx_vaddr + 0x00)) = 0xfffff000;
652 *((u_int *)(plx_vaddr + 0x04)) = 1;
653 *((u_int *)(plx_vaddr + 0x18)) = 0x40030043;
654 *((u_int *)(plx_vaddr + 0x1c)) = 0xff000000;
655 *((u_int *)(plx_vaddr + 0x20)) = 0;
656 *((u_int *)(plx_vaddr + 0x28)) = 0xe9;
657 *((u_int *)(plx_vaddr + 0x68)) = 0x10900;
660 * Get info from card.
662 * Only look for the second port if the first exists. Too many things
663 * will break if we have only a second port.
668 if (((fecr & SR_FECR_ID0) >> SR_FE_ID0_SHFT) != SR_FE_ID_NONE) {
670 if (((fecr & SR_FECR_ID1) >> SR_FE_ID1_SHFT) != SR_FE_ID_NONE)
684 hc = malloc(sizeof(struct sr_hardc), M_DEVBUF, M_WAITOK);
686 bzero(hc, sizeof(struct sr_hardc));
688 hc->sc = malloc(numports * sizeof(struct sr_softc),
690 bzero(hc->sc, numports * sizeof(struct sr_softc));
692 hc->numports = numports;
694 hc->cardtype = SR_CRD_N2PCI;
695 hc->plx_base = (caddr_t)plx_vaddr;
696 hc->sca_base = sca_vaddr;
698 hc->src_put8 = src_put8_mem;
699 hc->src_put16 = src_put16_mem;
700 hc->src_get8 = src_get8_mem;
701 hc->src_get16 = src_get16_mem;
704 * Malloc area for tx and rx buffers. For now allocate SRC_WIN_SIZ
705 * (16k) for each buffer.
707 * Allocate the block below 16M because the N2pci card can only access
708 * 16M memory at a time.
710 * (We could actually allocate a contiguous block above the 16MB limit,
711 * but this would complicate card programming more than we want to
714 hc->memsize = 2 * hc->numports * SRC_WIN_SIZ;
715 hc->mem_start = contigmalloc(hc->memsize,
723 if (hc->mem_start == NULL) {
724 printf("src%d: pci: failed to allocate buffer space.\n", unit);
727 hc->winmsk = 0xffffffff;
728 hc->mem_end = (caddr_t)((u_int)hc->mem_start + hc->memsize);
729 hc->mem_pstart = kvtop(hc->mem_start);
730 bzero(hc->mem_start, hc->memsize);
732 for (pndx = 0; pndx < numports; pndx++) {
740 intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT;
744 intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT;
748 if (sr_test_speed[pndx] > 0)
749 sc->clk_cfg = SR_FLAGS_INT_CLK;
761 sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK;
765 sc->clk_cfg = SR_FLAGS_EXT_CLK;
770 *fecrp = SR_FECR_DTR0
781 * Register the ports on the adapter.
782 * Fill in the info for each port.
783 * Attach each port to sppp and bpf.
786 srattach(struct sr_hardc *hc)
788 struct sr_softc *sc = hc->sc;
790 int unit; /* index: channel w/in card */
793 * Report Card configuration information before we start configuring
794 * each channel on the card...
796 printf("src%d: %uK RAM (%d mempages) @ %08x-%08x, %u ports.\n",
797 hc->cunit, hc->memsize / 1024, hc->mempages,
798 (u_int)hc->mem_start, (u_int)hc->mem_end, hc->numports);
804 * Now configure each port on the card.
806 for (unit = 0; unit < hc->numports; sc++, unit++) {
809 sc->unit = next_sc_unit;
811 sc->scachan = unit % NCHAN;
817 ifp = &sc->ifsppp.pp_if;
819 ifp->if_unit = sc->unit;
821 ifp->if_mtu = PP_MTU;
822 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
823 ifp->if_ioctl = srioctl;
824 ifp->if_start = srstart;
825 ifp->if_watchdog = srwatchdog;
827 printf("sr%d: Adapter %d, port %d.\n",
828 sc->unit, hc->cunit, sc->subunit);
831 * Despite the fact that we want to allow both PPP *and*
832 * Frame Relay access to a channel, due to the architecture
833 * of the system, we'll have to do the attach here.
835 * At some point I'll defer the attach to the "up" call and
836 * have the attach/detach performed when the interface is
840 sc->protocol = N2_USE_PPP; /* default protocol */
843 sc->ifsppp.pp_flags = PP_KEEPALIVE;
844 sppp_attach((struct ifnet *)&sc->ifsppp);
850 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
855 SRC_SET_OFF(hc->iobase);
861 * N2 Interrupt Service Routine
863 * First figure out which SCA gave the interrupt.
865 * See if there is other interrupts pending.
866 * Repeat until there no interrupts remain.
873 hc = &sr_hardc[unit];
880 srintr_hc(struct sr_hardc *hc)
882 sca_regs *sca = hc->sca; /* MSCI register tree */
883 u_char isr0, isr1, isr2; /* interrupt statii captured */
886 printf("sr: srintr_hc(hc=%08x)\n", hc);
890 * Since multiple interfaces may share this interrupt, we must loop
891 * until no interrupts are still pending service.
895 * Read all three interrupt status registers from the N2
898 isr0 = SRC_GET8(hc->sca_base, sca->isr0);
899 isr1 = SRC_GET8(hc->sca_base, sca->isr1);
900 isr2 = SRC_GET8(hc->sca_base, sca->isr2);
903 * If all three registers returned 0, we've finished
904 * processing interrupts from this device, so we can quit
907 if ((isr0 | isr1 | isr2) == 0)
911 printf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n",
912 unit, isr0, isr1, isr2);
916 * Now we can dispatch the interrupts. Since we don't expect
917 * either MSCI or timer interrupts, we'll test for DMA
918 * interrupts first...
920 if (isr1) /* DMA-initiated interrupt */
921 sr_dmac_intr(hc, isr1);
923 if (isr0) /* serial part IRQ? */
924 sr_msci_intr(hc, isr0);
926 if (isr2) /* timer-initiated interrupt */
927 sr_timer_intr(hc, isr2);
932 * This will only start the transmitter. It is assumed that the data
934 * It is normally called from srstart() or sr_dmac_intr().
937 sr_xmit(struct sr_softc *sc)
939 u_short cda_value; /* starting descriptor */
940 u_short eda_value; /* ending descriptor */
942 struct ifnet *ifp; /* O/S Network Services */
943 dmac_channel *dmac; /* DMA channel registers */
946 printf("sr: sr_xmit( sc=%08x)\n", sc);
950 ifp = &sc->ifsppp.pp_if;
951 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
954 * Get the starting and ending addresses of the chain to be
955 * transmitted and pass these on to the DMA engine on-chip.
957 cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart;
958 cda_value &= 0x00ffff;
959 eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart;
960 eda_value &= 0x00ffff;
962 SRC_PUT16(hc->sca_base, dmac->cda, cda_value);
963 SRC_PUT16(hc->sca_base, dmac->eda, eda_value);
966 * Now we'll let the DMA status register know about this change
968 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
970 sc->xmit_busy = 1; /* mark transmitter busy */
973 printf("sr%d: XMIT cda=%04x, eda=%4x, rcda=%08lx\n",
974 sc->unit, cda_value, eda_value,
975 sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart);
978 sc->txb_next_tx++; /* update next transmit seq# */
980 if (sc->txb_next_tx == SR_TX_BLOCKS) /* handle wrap... */
984 * Finally, we'll set a timout (which will start srwatchdog())
985 * within the O/S network services layer...
987 ifp->if_timer = 2; /* Value in seconds. */
991 * This function will be called from the upper level when a user add a
992 * packet to be send, and from the interrupt handler after a finished
995 * NOTE: it should run at spl_imp().
997 * This function only place the data in the oncard buffers. It does not
998 * start the transmition. sr_xmit() does that.
1000 * Transmitter idle state is indicated by the IFF_OACTIVE flag.
1001 * The function that clears that should ensure that the transmitter
1002 * and its DMA is in a "good" idle state.
1005 srstart(struct ifnet *ifp)
1007 struct sr_softc *sc; /* channel control structure */
1008 struct sr_hardc *hc; /* card control/config block */
1009 int len; /* total length of a packet */
1010 int pkts; /* packets placed in DPRAM */
1011 int tlen; /* working length of pkt */
1013 struct mbuf *mtx; /* message buffer from O/S */
1014 u_char *txdata; /* buffer address in DPRAM */
1015 sca_descriptor *txdesc; /* working descriptor pointr */
1016 struct buf_block *blkp;
1019 printf("sr: srstart( ifp=%08x)\n", ifp);
1025 if ((ifp->if_flags & IFF_RUNNING) == 0)
1029 * It is OK to set the memory window outside the loop because all tx
1030 * buffers and descriptors are assumed to be in the same 16K window.
1033 SRC_SET_ON(hc->iobase);
1034 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
1038 * Loop to place packets into DPRAM.
1040 * We stay in this loop until there is nothing in
1041 * the TX queue left or the tx buffers are full.
1046 * See if we have space for more packets.
1048 if (sc->txb_inuse == SR_TX_BLOCKS) { /* out of space? */
1049 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */
1052 SRC_SET_OFF(hc->iobase);
1055 printf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n",
1056 sc->unit, sc->txb_inuse);
1061 * OK, the card can take more traffic. Let's see if there's any
1062 * pending from the system...
1065 * The architecture of the networking interface doesn't
1066 * actually call us like 'write()', providing an address. We get
1067 * started, a lot like a disk strategy routine, and we actually call
1068 * back out to the system to get traffic to send...
1071 * If we were gonna run through another layer, we would use a
1072 * dispatch table to select the service we're getting a packet
1075 switch (sc->protocol) {
1078 mtx = fr_dequeue(ifp);
1083 mtx = sppp_dequeue(ifp);
1088 SRC_SET_OFF(hc->iobase);
1092 * OK, we got a packet from the network services of the O/S. Now we
1093 * can move it into the DPRAM (under control of the descriptors) and
1097 i = 0; /* counts # of granules used */
1099 blkp = &sc->block[sc->txb_new]; /* address of free granule */
1100 txdesc = (sca_descriptor *)
1101 (hc->mem_start + (blkp->txdesc & hc->winmsk));
1103 txdata = (u_char *)(hc->mem_start
1104 + (blkp->txstart & hc->winmsk));
1107 * Now we'll try to install as many packets as possible into the
1108 * card's DP RAM buffers.
1110 for (;;) { /* perform actual copy of packet */
1111 len = mtx->m_pkthdr.len; /* length of message */
1114 printf("sr%d.srstart: mbuf @ %08lx, %d bytes\n",
1115 sc->unit, mtx, len);
1124 * We can perform a straight copy because the tranmit
1125 * buffers won't wrap.
1127 m_copydata(mtx, 0, len, txdata);
1130 * Now we know how big the message is gonna be. We must now
1131 * construct the descriptors to drive this message out...
1134 while (tlen > SR_BUF_SIZ) { /* loop for full granules */
1135 txdesc->stat = 0; /* reset bits */
1136 txdesc->len = SR_BUF_SIZ; /* size of granule */
1139 txdesc++; /* move to next dscr */
1140 txdata += SR_BUF_SIZ; /* adjust data addr */
1145 * This section handles the setting of the final piece of a
1148 txdesc->stat = SCA_DESC_EOM;
1153 * prepare for subsequent packets (if any)
1156 txdata += SR_BUF_SIZ; /* next mem granule */
1157 i++; /* count of granules */
1160 * OK, we've now placed the message into the DPRAM where it
1161 * can be transmitted. We'll now release the message memory
1162 * and update the statistics...
1165 ++sc->ifsppp.pp_if.if_opackets;
1168 * Check if we have space for another packet. XXX This is
1169 * hardcoded. A packet can't be larger than 3 buffers (3 x
1172 if ((i + 3) >= blkp->txmax) { /* enough remains? */
1174 printf("sr%d.srstart: i=%d (%d pkts); card full.\n",
1180 * We'll pull the next message to be sent (if any)
1182 switch (sc->protocol) {
1185 mtx = fr_dequeue(ifp);
1190 mtx = sppp_dequeue(ifp);
1193 if (!mtx) { /* no message? We're done! */
1195 printf("sr%d.srstart: pending=0, pkts=%d\n",
1202 blkp->txtail = i; /* record next free granule */
1205 * Mark the last descriptor, so that the SCA know where to stop.
1207 txdesc--; /* back up to last descriptor in list */
1208 txdesc->stat |= SCA_DESC_EOT; /* mark as end of list */
1211 * Now we'll reset the transmit granule's descriptor address so we
1212 * can record this in the structure and fire it off w/ the DMA
1213 * processor of the serial chip...
1215 txdesc = (sca_descriptor *)blkp->txdesc;
1216 blkp->txeda = (u_short)((u_int)&txdesc[i]);
1218 sc->txb_inuse++; /* update inuse status */
1219 sc->txb_new++; /* new traffic wuz added */
1221 if (sc->txb_new == SR_TX_BLOCKS)
1225 * If the tranmitter wasn't marked as "busy" we will force it to be
1228 if (sc->xmit_busy == 0) {
1231 printf("sr%d.srstart: called sr_xmit()\n", sc->unit);
1238 * Handle ioctl's at the device level, though we *will* call up
1242 static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0};
1246 srioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1248 int s, error, was_up, should_be_up;
1249 struct sppp *sp = (struct sppp *)ifp;
1250 struct sr_softc *sc = ifp->if_softc;
1253 printf("sr%d: srioctl(ifp=%08x, cmd=%08x, data=%08x)\n",
1254 ifp->if_unit, ifp, cmd, data);
1257 was_up = ifp->if_flags & IFF_RUNNING;
1259 if (cmd == SIOCSIFFLAGS) {
1261 * First, handle an apparent protocol switch
1264 if (was_up == 0)/* can only happen if DOWN */
1265 if (ifp->if_flags & IFF_LINK1)
1266 sc->protocol = N2_USE_FRP;
1268 sc->protocol = N2_USE_PPP;
1270 sc->protocol = N2_USE_PPP;
1271 ifp->if_flags &= ~IFF_LINK1;
1275 * Next we can handle minor protocol point(s)
1277 if (ifp->if_flags & IFF_LINK2)
1278 sp->pp_flags |= PP_CISCO;
1280 sp->pp_flags &= ~PP_CISCO;
1283 * Next, we'll allow the network service layer we've called process
1286 if ((sc->attached != 0)
1287 && (sc->attached != sc->protocol)) {
1288 switch (sc->attached) {
1297 sc->ifsppp.pp_flags &= ~PP_KEEPALIVE;
1302 if (sc->attached == 0) {
1303 switch (sc->protocol) {
1306 fr_attach(&sc->ifsppp.pp_if);
1311 sc->ifsppp.pp_flags |= PP_KEEPALIVE;
1312 sppp_attach(&sc->ifsppp.pp_if);
1315 * Shortcut the sppp tls/tlf actions to
1316 * up/down events since our lower layer is
1319 sc->ifsppp.pp_tls = sc->ifsppp.pp_up;
1320 sc->ifsppp.pp_tlf = sc->ifsppp.pp_down;
1323 sc->attached = sc->protocol;
1325 switch (sc->protocol) {
1328 error = fr_ioctl(ifp, cmd, data);
1333 error = sppp_ioctl(ifp, cmd, data);
1337 printf("sr%d: ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n",
1338 ifp->if_unit, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);
1344 if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) {
1346 if (bug_splats[sc->unit]++ < 2) {
1347 printf("sr(%d).if_addrlist = %08x\n",
1348 sc->unit, ifp->if_addrlist);
1349 printf("sr(%d).if_bpf = %08x\n",
1350 sc->unit, ifp->if_bpf);
1351 printf("sr(%d).if_init = %08x\n",
1352 sc->unit, ifp->if_init);
1353 printf("sr(%d).if_output = %08x\n",
1354 sc->unit, ifp->if_output);
1355 printf("sr(%d).if_start = %08x\n",
1356 sc->unit, ifp->if_start);
1357 printf("sr(%d).if_done = %08x\n",
1358 sc->unit, ifp->if_done);
1359 printf("sr(%d).if_ioctl = %08x\n",
1360 sc->unit, ifp->if_ioctl);
1361 printf("sr(%d).if_reset = %08x\n",
1362 sc->unit, ifp->if_reset);
1363 printf("sr(%d).if_watchdog = %08x\n",
1364 sc->unit, ifp->if_watchdog);
1371 should_be_up = ifp->if_flags & IFF_RUNNING;
1373 if (!was_up && should_be_up) {
1375 * Interface should be up -- start it.
1381 * XXX Clear the IFF_UP flag so that the link will only go
1382 * up after sppp lcp and ipcp negotiation.
1384 ifp->if_flags &= ~IFF_UP;
1385 } else if (was_up && !should_be_up) {
1387 * Interface should be down -- stop it.
1390 switch (sc->protocol) {
1404 if (bug_splats[sc->unit]++ < 2) {
1405 printf("sr(%d).if_addrlist = %08x\n",
1406 sc->unit, ifp->if_addrlist);
1407 printf("sr(%d).if_bpf = %08x\n",
1408 sc->unit, ifp->if_bpf);
1409 printf("sr(%d).if_init = %08x\n",
1410 sc->unit, ifp->if_init);
1411 printf("sr(%d).if_output = %08x\n",
1412 sc->unit, ifp->if_output);
1413 printf("sr(%d).if_start = %08x\n",
1414 sc->unit, ifp->if_start);
1415 printf("sr(%d).if_done = %08x\n",
1416 sc->unit, ifp->if_done);
1417 printf("sr(%d).if_ioctl = %08x\n",
1418 sc->unit, ifp->if_ioctl);
1419 printf("sr(%d).if_reset = %08x\n",
1420 sc->unit, ifp->if_reset);
1421 printf("sr(%d).if_watchdog = %08x\n",
1422 sc->unit, ifp->if_watchdog);
1430 * This is to catch lost tx interrupts.
1433 srwatchdog(struct ifnet *ifp)
1435 int got_st0, got_st1, got_st3, got_dsr;
1436 struct sr_softc *sc = ifp->if_softc;
1437 struct sr_hardc *hc = sc->hc;
1438 msci_channel *msci = &hc->sca->msci[sc->scachan];
1439 dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan];
1442 printf("srwatchdog(unit=%d)\n", unit);
1445 if (!(ifp->if_flags & IFF_RUNNING))
1448 ifp->if_oerrors++; /* update output error count */
1450 got_st0 = SRC_GET8(hc->sca_base, msci->st0);
1451 got_st1 = SRC_GET8(hc->sca_base, msci->st1);
1452 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
1453 got_dsr = SRC_GET8(hc->sca_base, dmac->dsr);
1456 if (ifp->if_flags & IFF_DEBUG)
1458 printf("sr%d: transmit failed, "
1459 "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n",
1461 got_st0, got_st1, got_st3, got_dsr);
1463 if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) {
1464 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT);
1465 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1466 SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN);
1469 ifp->if_flags &= ~IFF_OACTIVE;
1471 if (sc->txb_inuse && --sc->txb_inuse)
1474 srstart(ifp); /* restart transmitter */
1478 sr_up(struct sr_softc *sc)
1481 struct sr_hardc *hc = sc->hc;
1482 sca_regs *sca = hc->sca;
1483 msci_channel *msci = &sca->msci[sc->scachan];
1486 printf("sr_up(sc=%08x)\n", sc);
1490 * This section should really do the attach to the appropriate
1491 * system service, be it frame relay or PPP...
1493 if (sc->attached == 0) {
1494 switch (sc->protocol) {
1497 fr_attach(&sc->ifsppp.pp_if);
1502 sc->ifsppp.pp_flags |= PP_KEEPALIVE;
1503 sppp_attach(&sc->ifsppp.pp_if);
1506 * Shortcut the sppp tls/tlf actions to
1507 * up/down events since our lower layer is
1510 sc->ifsppp.pp_tls = sc->ifsppp.pp_up;
1511 sc->ifsppp.pp_tlf = sc->ifsppp.pp_down;
1514 sc->attached = sc->protocol;
1518 * Enable transmitter and receiver. Raise DTR and RTS. Enable
1521 * XXX What about using AUTO mode in msci->md0 ???
1523 SRC_PUT8(hc->sca_base, msci->ctl,
1524 SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS);
1526 if (sc->scachan == 0)
1527 switch (hc->cardtype) {
1529 outb(hc->iobase + SR_MCR,
1530 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR0));
1533 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1534 *fecrp &= ~SR_FECR_DTR0;
1538 switch (hc->cardtype) {
1540 outb(hc->iobase + SR_MCR,
1541 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR1));
1544 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1545 *fecrp &= ~SR_FECR_DTR1;
1549 if (sc->scachan == 0) {
1550 SRC_PUT8(hc->sca_base, sca->ier0,
1551 SRC_GET8(hc->sca_base, sca->ier0) | 0x000F);
1552 SRC_PUT8(hc->sca_base, sca->ier1,
1553 SRC_GET8(hc->sca_base, sca->ier1) | 0x000F);
1555 SRC_PUT8(hc->sca_base, sca->ier0,
1556 SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0);
1557 SRC_PUT8(hc->sca_base, sca->ier1,
1558 SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0);
1561 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE);
1562 inb(hc->iobase); /* XXX slow it down a bit. */
1563 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1566 if (sr_watcher == 0)
1572 sr_down(struct sr_softc *sc)
1575 struct sr_hardc *hc = sc->hc;
1576 sca_regs *sca = hc->sca;
1577 msci_channel *msci = &sca->msci[sc->scachan];
1580 printf("sr_down(sc=%08x)\n", sc);
1584 * Disable transmitter and receiver. Lower DTR and RTS. Disable
1587 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE);
1588 inb(hc->iobase); /* XXX slow it down a bit. */
1589 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE);
1591 SRC_PUT8(hc->sca_base, msci->ctl,
1592 SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS);
1594 if (sc->scachan == 0)
1595 switch (hc->cardtype) {
1597 outb(hc->iobase + SR_MCR,
1598 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR0));
1601 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1602 *fecrp |= SR_FECR_DTR0;
1606 switch (hc->cardtype) {
1608 outb(hc->iobase + SR_MCR,
1609 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR1));
1612 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1613 *fecrp |= SR_FECR_DTR1;
1617 if (sc->scachan == 0) {
1618 SRC_PUT8(hc->sca_base, sca->ier0,
1619 SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F);
1620 SRC_PUT8(hc->sca_base, sca->ier1,
1621 SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F);
1623 SRC_PUT8(hc->sca_base, sca->ier0,
1624 SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0);
1625 SRC_PUT8(hc->sca_base, sca->ier1,
1626 SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0);
1630 * This section does the detach from the currently configured net
1631 * service, be it frame relay or PPP...
1633 switch (sc->protocol) {
1636 fr_detach(&sc->ifsppp.pp_if);
1641 sppp_detach(&sc->ifsppp.pp_if);
1648 * Initialize the card, allocate memory for the sr_softc structures
1649 * and fill in the pointers.
1652 src_init(struct sr_hardc *hc)
1654 struct sr_softc *sc = hc->sc;
1662 printf("src_init(hc=%08x)\n", hc);
1665 chanmem = hc->memsize / hc->numports;
1668 for (x = 0; x < hc->numports; x++, sc++) {
1671 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1672 sc->block[blk].txdesc = next;
1673 bufmem = (16 * 1024) / SR_TX_BLOCKS;
1674 descneeded = bufmem / SR_BUF_SIZ;
1676 sc->block[blk].txstart = sc->block[blk].txdesc
1677 + ((((descneeded * sizeof(sca_descriptor))
1681 sc->block[blk].txend = next + bufmem;
1682 sc->block[blk].txmax =
1683 (sc->block[blk].txend - sc->block[blk].txstart)
1688 printf("sr%d: blk %d: txdesc %08x, txstart %08x\n",
1690 sc->block[blk].txdesc, sc->block[blk].txstart);
1695 bufmem = chanmem - (bufmem * SR_TX_BLOCKS);
1696 descneeded = bufmem / SR_BUF_SIZ;
1697 sc->rxstart = sc->rxdesc +
1698 ((((descneeded * sizeof(sca_descriptor)) /
1699 SR_BUF_SIZ) + 1) * SR_BUF_SIZ);
1700 sc->rxend = next + bufmem;
1701 sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ;
1707 * The things done here are channel independent.
1709 * Configure the sca waitstates.
1710 * Configure the global interrupt registers.
1711 * Enable master dma enable.
1714 sr_init_sca(struct sr_hardc *hc)
1716 sca_regs *sca = hc->sca;
1719 printf("sr_init_sca(hc=%08x)\n", hc);
1723 * Do the wait registers. Set everything to 0 wait states.
1725 SRC_PUT8(hc->sca_base, sca->pabr0, 0);
1726 SRC_PUT8(hc->sca_base, sca->pabr1, 0);
1727 SRC_PUT8(hc->sca_base, sca->wcrl, 0);
1728 SRC_PUT8(hc->sca_base, sca->wcrm, 0);
1729 SRC_PUT8(hc->sca_base, sca->wcrh, 0);
1732 * Configure the interrupt registers. Most are cleared until the
1733 * interface is configured.
1735 SRC_PUT8(hc->sca_base, sca->ier0, 0x00); /* MSCI interrupts. */
1736 SRC_PUT8(hc->sca_base, sca->ier1, 0x00); /* DMAC interrupts */
1737 SRC_PUT8(hc->sca_base, sca->ier2, 0x00); /* TIMER interrupts. */
1738 SRC_PUT8(hc->sca_base, sca->itcr, 0x00); /* Use ivr and no intr
1740 SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */
1741 SRC_PUT8(hc->sca_base, sca->imvr, 0x40);
1744 * Configure the timers. XXX Later
1748 * Set the DMA channel priority to rotate between all four channels.
1750 * Enable all dma channels.
1752 SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2);
1753 SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN);
1757 * Configure the msci
1759 * NOTE: The serial port configuration is hardcoded at the moment.
1762 sr_init_msci(struct sr_softc *sc)
1764 int portndx; /* on-board port number */
1765 u_int mcr_v; /* contents of modem control */
1766 u_int *fecrp; /* pointer for PCI's MCR i/o */
1767 struct sr_hardc *hc = sc->hc;
1768 msci_channel *msci = &hc->sca->msci[sc->scachan];
1769 #ifdef N2_TEST_SPEED
1770 int br_v; /* contents for BR divisor */
1771 int etcndx; /* index into ETC table */
1772 int fifo_v, gotspeed; /* final tabled speed found */
1773 int tmc_v; /* timer control register */
1774 int wanted; /* speed (bitrate) wanted... */
1775 struct rate_line *rtp;
1778 portndx = sc->scachan;
1781 printf("sr: sr_init_msci( sc=%08x)\n", sc);
1784 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET);
1785 SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 |
1787 SCA_MD0_CRC_ENABLE |
1789 SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK);
1790 SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ);
1793 * According to the manual I should give a reset after changing the
1796 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET);
1797 SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT |
1802 * XXX Later we will have to support different clock settings.
1804 switch (sc->clk_cfg) {
1807 printf("sr%: clk_cfg=%08x, selected default clock.\n",
1808 portndx, sc->clk_cfg);
1811 case SR_FLAGS_EXT_CLK:
1813 * For now all interfaces are programmed to use the RX clock
1818 printf("sr%d: External Clock Selected.\n", portndx);
1821 SRC_PUT8(hc->sca_base, msci->rxs, 0);
1822 SRC_PUT8(hc->sca_base, msci->txs, 0);
1825 case SR_FLAGS_EXT_SEP_CLK:
1827 printf("sr%d: Split Clocking Selected.\n", portndx);
1831 SRC_PUT8(hc->sca_base, msci->rxs, 0);
1832 SRC_PUT8(hc->sca_base, msci->txs, 0);
1834 SRC_PUT8(hc->sca_base, msci->rxs,
1835 SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1838 * We need to configure the internal bit clock for the
1839 * transmitter's channel...
1841 SRC_PUT8(hc->sca_base, msci->txs,
1842 SCA_TXS_CLK_RX | SCA_TXS_DIV1);
1846 case SR_FLAGS_INT_CLK:
1848 printf("sr%d: Internal Clocking selected.\n", portndx);
1852 * XXX I do need some code to set the baud rate here!
1854 #ifdef N2_TEST_SPEED
1855 switch (hc->cardtype) {
1857 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1863 mcr_v = inb(hc->iobase + SR_MCR);
1867 fifo_v = 0x10; /* stolen from Linux version */
1870 * search for appropriate speed in table, don't calc it:
1872 wanted = sr_test_speed[portndx];
1873 rtp = &n2_rates[0]; /* point to first table item */
1875 while ((rtp->target > 0) /* search table for speed */
1876 &&(rtp->target != wanted))
1880 * We've searched the table for a matching speed. If we've
1881 * found the correct rate line, we'll get the pre-calc'd
1882 * values for the TMC and baud rate divisor for subsequent
1885 if (rtp->target > 0) { /* use table-provided values */
1887 tmc_v = rtp->tmc_reg;
1889 } else { /* otherwise assume 1MBit comm rate */
1896 * Now we mask in the enable clock output for the MCR:
1898 mcr_v |= etc0vals[etcndx + portndx];
1901 * Now we'll program the registers with these speed- related
1904 SRC_PUT8(hc->sca_base, msci->tmc, tmc_v);
1905 SRC_PUT8(hc->sca_base, msci->trc0, fifo_v);
1906 SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v);
1907 SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v);
1909 switch (hc->cardtype) {
1915 outb(hc->iobase + SR_MCR, mcr_v);
1919 if (wanted != gotspeed)
1920 printf("sr%d: Speed wanted=%d, found=%d\n",
1923 printf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n",
1924 portndx, gotspeed, tmc_v, br_v);
1927 SRC_PUT8(hc->sca_base, msci->rxs,
1928 SCA_RXS_CLK_INT | SCA_RXS_DIV1);
1929 SRC_PUT8(hc->sca_base, msci->txs,
1930 SCA_TXS_CLK_INT | SCA_TXS_DIV1);
1932 SRC_PUT8(hc->sca_base, msci->tmc, 5);
1935 switch (hc->cardtype) {
1937 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1938 *fecrp |= SR_FECR_ETC0;
1942 mcr_v = inb(hc->iobase + SR_MCR);
1943 mcr_v |= SR_MCR_ETC0;
1944 outb(hc->iobase + SR_MCR, mcr_v);
1947 switch (hc->cardtype) {
1949 mcr_v = inb(hc->iobase + SR_MCR);
1950 mcr_v |= SR_MCR_ETC1;
1951 outb(hc->iobase + SR_MCR, mcr_v);
1954 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1955 *fecrp |= SR_FECR_ETC1;
1962 * XXX Disable all interrupts for now. I think if you are using the
1963 * dmac you don't use these interrupts.
1965 SRC_PUT8(hc->sca_base, msci->ie0, 0);
1966 SRC_PUT8(hc->sca_base, msci->ie1, 0x0C);
1967 SRC_PUT8(hc->sca_base, msci->ie2, 0);
1968 SRC_PUT8(hc->sca_base, msci->fie, 0);
1970 SRC_PUT8(hc->sca_base, msci->sa0, 0);
1971 SRC_PUT8(hc->sca_base, msci->sa1, 0);
1973 SRC_PUT8(hc->sca_base, msci->idl, 0x7E); /* set flags value */
1975 SRC_PUT8(hc->sca_base, msci->rrc, 0x0E);
1976 SRC_PUT8(hc->sca_base, msci->trc0, 0x10);
1977 SRC_PUT8(hc->sca_base, msci->trc1, 0x1F);
1981 * Configure the rx dma controller.
1984 sr_init_rx_dmac(struct sr_softc *sc)
1986 struct sr_hardc *hc;
1988 sca_descriptor *rxd;
1989 u_int cda_v, sarb_v, rxbuf, rxda, rxda_d;
1992 printf("sr_init_rx_dmac(sc=%08x)\n", sc);
1996 dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)];
1999 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2002 * This phase initializes the contents of the descriptor table
2003 * needed to construct a circular buffer...
2005 rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk));
2006 rxda_d = (u_int) hc->mem_start - (sc->rxdesc & ~hc->winmsk);
2008 for (rxbuf = sc->rxstart;
2010 rxbuf += SR_BUF_SIZ, rxd++) {
2012 * construct the circular chain...
2014 rxda = (u_int) & rxd[1] - rxda_d + hc->mem_pstart;
2015 rxd->cp = (u_short)(rxda & 0xffff);
2018 * set the on-card buffer address...
2020 rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff);
2021 rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff);
2023 rxd->len = 0; /* bytes resident w/in granule */
2024 rxd->stat = 0xff; /* The sca write here when finished */
2028 * heal the chain so that the last entry points to the first...
2031 rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
2034 * reset the reception handler's index...
2039 * We'll now configure the receiver's DMA logic...
2041 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA transfer */
2042 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
2044 /* XXX maybe also SCA_DMR_CNTE */
2045 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
2046 SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ);
2048 cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
2049 sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff);
2051 SRC_PUT16(hc->sca_base, dmac->cda, cda_v);
2052 SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v);
2054 rxd = (sca_descriptor *)sc->rxstart;
2056 SRC_PUT16(hc->sca_base, dmac->eda,
2057 (u_short)((u_int) & rxd[sc->rxmax - 1] & 0xffff));
2059 SRC_PUT8(hc->sca_base, dmac->dir, 0xF0);
2062 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); /* Enable DMA */
2066 * Configure the TX DMA descriptors.
2067 * Initialize the needed values and chain the descriptors.
2070 sr_init_tx_dmac(struct sr_softc *sc)
2073 u_int txbuf, txda, txda_d;
2074 struct sr_hardc *hc;
2075 sca_descriptor *txd;
2077 struct buf_block *blkp;
2082 printf("sr_init_tx_dmac(sc=%08x)\n", sc);
2086 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
2089 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
2092 * Initialize the array of descriptors for transmission
2094 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
2095 blkp = &sc->block[blk];
2096 txd = (sca_descriptor *)(hc->mem_start
2097 + (blkp->txdesc & hc->winmsk));
2098 txda_d = (u_int) hc->mem_start
2099 - (blkp->txdesc & ~hc->winmsk);
2102 txbuf = blkp->txstart;
2103 for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) {
2104 txda = (u_int) & txd[1] - txda_d + hc->mem_pstart;
2105 txd->cp = (u_short)(txda & 0xffff);
2107 txd->bp = (u_short)((txbuf + hc->mem_pstart)
2109 txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16)
2117 txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart)
2120 blkp->txtail = (u_int)txd - (u_int)hc->mem_start;
2123 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA */
2124 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
2125 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
2126 SRC_PUT8(hc->sca_base, dmac->dir,
2127 SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF);
2129 sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16;
2132 SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v);
2136 * Look through the descriptors to see if there is a complete packet
2137 * available. Stop if we get to where the sca is busy.
2139 * Return the length and status of the packet.
2140 * Return nonzero if there is a packet available.
2143 * It seems that we get the interrupt a bit early. The updateing of
2144 * descriptor values is not always completed when this is called.
2147 sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat)
2149 int granules; /* count of granules in pkt */
2151 struct sr_hardc *hc;
2152 sca_descriptor *rxdesc; /* current descriptor */
2153 sca_descriptor *endp; /* ending descriptor */
2154 sca_descriptor *cda; /* starting descriptor */
2156 hc = sc->hc; /* get card's information */
2159 * set up starting descriptor by pulling that info from the DMA half
2162 wki = DMAC_RXCH(sc->scachan);
2163 wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda);
2165 cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk));
2168 printf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n",
2173 * open the appropriate memory window and set our expectations...
2176 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2177 SRC_SET_ON(hc->iobase);
2179 rxdesc = (sca_descriptor *)
2180 (hc->mem_start + (sc->rxdesc & hc->winmsk));
2182 rxdesc = &rxdesc[sc->rxhind];
2183 endp = &endp[sc->rxmax];
2185 *len = 0; /* reset result total length */
2186 granules = 0; /* reset count of granules */
2189 * This loop will scan descriptors, but it *will* puke up if we wrap
2190 * around to our starting point...
2192 while (rxdesc != cda) {
2193 *len += rxdesc->len; /* increment result length */
2197 * If we hit a valid packet's completion we'll know we've
2198 * got a live one, and that we can deliver the packet.
2199 * Since we're only allowed to report a packet available,
2200 * somebody else does that...
2202 if (rxdesc->stat & SCA_DESC_EOM) { /* End Of Message */
2203 *rxstat = rxdesc->stat; /* return closing */
2205 printf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n",
2206 sc->unit, *len, *rxstat, granules);
2208 return 1; /* indicate success */
2211 * OK, this packet take up multiple granules. Move on to
2212 * the next descriptor so we can consider it...
2216 if (rxdesc == endp) /* recognize & act on wrap point */
2217 rxdesc = (sca_descriptor *)
2218 (hc->mem_start + (sc->rxdesc & hc->winmsk));
2222 * Nothing found in the DPRAM. Let the caller know...
2231 * Copy a packet from the on card memory into a provided mbuf.
2232 * Take into account that buffers wrap and that a packet may
2233 * be larger than a buffer.
2236 sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len)
2238 struct sr_hardc *hc;
2239 sca_descriptor *rxdesc;
2246 printf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n",
2252 rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ);
2253 rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ);
2255 rxdesc = (sca_descriptor *)
2256 (hc->mem_start + (sc->rxdesc & hc->winmsk));
2257 rxdesc = &rxdesc[sc->rxhind];
2260 * Using the count of bytes in the received packet, we decrement it
2261 * for each granule (controller by an SCA descriptor) to control the
2266 * tlen gets the length of *this* granule... ...which is
2267 * then copied to the target buffer.
2269 tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ;
2272 SRC_SET_MEM(hc->iobase, rxdata);
2274 bcopy(hc->mem_start + (rxdata & hc->winmsk),
2275 mtod(m, caddr_t) +off,
2282 * now, return to the descriptor's window in DPRAM and reset
2283 * the descriptor we've just suctioned...
2286 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2289 rxdesc->stat = 0xff;
2292 * Move on to the next granule. If we've any remaining
2293 * bytes to process we'll just continue in our loop...
2295 rxdata += SR_BUF_SIZ;
2298 if (rxdata == rxmax) { /* handle the wrap point */
2299 rxdata = sc->rxstart;
2300 rxdesc = (sca_descriptor *)
2301 (hc->mem_start + (sc->rxdesc & hc->winmsk));
2307 * If single is set, just eat a packet. Otherwise eat everything up to
2308 * where cda points. Update pointers to point to the next packet.
2310 * This handles "flushing" of a packet as received...
2312 * If the "single" parameter is zero, all pending reeceive traffic will
2313 * be flushed out of existence. A non-zero value will only drop the
2314 * *next* (currently) pending packet...
2317 sr_eat_packet(struct sr_softc *sc, int single)
2319 struct sr_hardc *hc;
2320 sca_descriptor *rxdesc; /* current descriptor being eval'd */
2321 sca_descriptor *endp; /* last descriptor in chain */
2322 sca_descriptor *cda; /* current start point */
2323 u_int loopcnt = 0; /* count of packets flushed ??? */
2324 u_char stat; /* captured status byte from descr */
2327 cda = (sca_descriptor *)(hc->mem_start +
2328 (SRC_GET16(hc->sca_base,
2329 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) &
2333 * loop until desc->stat == (0xff || EOM) Clear the status and
2334 * length in the descriptor. Increment the descriptor.
2337 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2339 rxdesc = (sca_descriptor *)
2340 (hc->mem_start + (sc->rxdesc & hc->winmsk));
2342 rxdesc = &rxdesc[sc->rxhind];
2343 endp = &endp[sc->rxmax];
2346 * allow loop, but abort it if we wrap completely...
2348 while (rxdesc != cda) {
2351 if (loopcnt > sc->rxmax) {
2352 printf("sr%d: eat pkt %d loop, cda %x, "
2353 "rxdesc %x, stat %x.\n",
2354 sc->unit, loopcnt, (u_int) cda, (u_int) rxdesc,
2358 stat = rxdesc->stat;
2361 rxdesc->stat = 0xff;
2366 if (rxdesc == endp) {
2367 rxdesc = (sca_descriptor *)
2368 (hc->mem_start + (sc->rxdesc & hc->winmsk));
2371 if (single && (stat == SCA_DESC_EOM))
2376 * Update the eda to the previous descriptor.
2378 rxdesc = (sca_descriptor *)sc->rxdesc;
2379 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax];
2381 SRC_PUT16(hc->sca_base,
2382 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2383 (u_short)((u_int)(rxdesc + hc->mem_pstart) & 0xffff));
2387 * While there is packets available in the rx buffer, read them out
2388 * into mbufs and ship them off.
2391 sr_get_packets(struct sr_softc *sc)
2393 u_char rxstat; /* acquired status byte */
2395 int pkts; /* count of packets found */
2396 int rxndx; /* rcv buffer index */
2397 int tries; /* settling time counter */
2398 u_int len; /* length of pending packet */
2399 struct sr_hardc *hc; /* card-level information */
2400 sca_descriptor *rxdesc; /* descriptor in memory */
2401 struct ifnet *ifp; /* network intf ctl table */
2402 struct mbuf *m = NULL; /* message buffer */
2405 printf("sr_get_packets(sc=%08x)\n", sc);
2409 ifp = &sc->ifsppp.pp_if;
2412 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2413 SRC_SET_ON(hc->iobase); /* enable shared memory */
2415 pkts = 0; /* reset count of found packets */
2418 * for each complete packet in the receiving pool, process each
2421 while (sr_packet_avail(sc, &len, &rxstat)) { /* packet pending? */
2423 * I have seen situations where we got the interrupt but the
2424 * status value wasn't deposited. This code should allow
2425 * the status byte's value to settle...
2430 while ((rxstat == 0x00ff)
2432 sr_packet_avail(sc, &len, &rxstat);
2435 printf("sr_packet_avail() returned len=%d, rxstat=%02ux\n",
2442 * OK, we've settled the incoming message status. We can now
2445 if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
2447 printf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n",
2448 sc->unit, rxstat, len);
2451 MGETHDR(m, M_DONTWAIT, MT_DATA);
2454 * eat (flush) packet if get mbuf fail!!
2456 sr_eat_packet(sc, 1);
2460 * construct control information for pass-off
2462 m->m_pkthdr.rcvif = ifp;
2463 m->m_pkthdr.len = m->m_len = len;
2465 MCLGET(m, M_DONTWAIT);
2466 if ((m->m_flags & M_EXT) == 0) {
2468 * We couldn't get a big enough
2469 * message packet, so we'll send the
2470 * packet to /dev/null...
2473 sr_eat_packet(sc, 1);
2478 * OK, we've got a good message buffer. Now we can
2479 * copy the received message into it
2481 sr_copy_rxbuf(m, sc, len); /* copy from DPRAM */
2493 printf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n",
2495 bp[0], bp[1], bp[2],
2496 bp[4], bp[5], bp[6]);
2501 * Pass off the message to PPP, connecting it it to
2504 switch (sc->protocol) {
2518 * Update the eda to the previous descriptor.
2520 i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ;
2521 sc->rxhind = (sc->rxhind + i) % sc->rxmax;
2523 rxdesc = (sca_descriptor *)sc->rxdesc;
2524 rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax;
2525 rxdesc = &rxdesc[rxndx];
2527 SRC_PUT16(hc->sca_base,
2528 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2529 (u_short)((u_int)(rxdesc + hc->mem_pstart)
2533 int got_st3, got_cda, got_eda;
2536 while((rxstat == 0xff) && --tries)
2537 sr_packet_avail(sc, &len, &rxstat);
2540 * It look like we get an interrupt early
2541 * sometimes and then the status is not
2544 if(tries && (tries != 5))
2548 * This chunk of code handles the error packets.
2549 * We'll log them for posterity...
2551 sr_eat_packet(sc, 1);
2555 got_st3 = SRC_GET8(hc->sca_base,
2556 hc->sca->msci[sc->scachan].st3);
2557 got_cda = SRC_GET16(hc->sca_base,
2558 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda);
2559 got_eda = SRC_GET16(hc->sca_base,
2560 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda);
2563 printf("sr%d: Receive error chan %d, "
2564 "stat %02x, msci st3 %02x,"
2565 "rxhind %d, cda %04x, eda %04x.\n",
2566 sc->unit, sc->scachan, rxstat,
2567 got_st3, sc->rxhind, got_cda, got_eda);
2573 printf("sr%d: sr_get_packets() found %d packet(s)\n",
2578 SRC_SET_OFF(hc->iobase);
2582 * All DMA interrupts come here.
2584 * Each channel has two interrupts.
2585 * Interrupt A for errors and Interrupt B for normal stuff like end
2586 * of transmit or receive dmas.
2589 sr_dmac_intr(struct sr_hardc *hc, u_char isr1)
2591 u_char dsr; /* contents of DMA Stat Reg */
2592 u_char dotxstart; /* enables for tranmit part */
2593 int mch; /* channel being processed */
2594 struct sr_softc *sc; /* channel's softc structure */
2595 sca_regs *sca = hc->sca;
2596 dmac_channel *dmac; /* dma structure of chip */
2599 printf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1);
2602 mch = 0; /* assume chan0 on card */
2603 dotxstart = isr1; /* copy for xmitter starts */
2606 * Shortcut if there is no interrupts for dma channel 0 or 1.
2607 * Skip processing for channel 0 if no incoming hit
2609 if ((isr1 & 0x0F) == 0) {
2617 * Transmit channel - DMA Status Register Evaluation
2620 dmac = &sca->dmac[DMAC_TXCH(mch)];
2623 * get the DMA Status Register contents and write
2624 * back to reset interrupt...
2626 dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2627 SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2630 * Check for (& process) a Counter overflow
2632 if (dsr & SCA_DSR_COF) {
2633 printf("sr%d: TX DMA Counter overflow, "
2634 "txpacket no %lu.\n",
2635 sc->unit, sc->ifsppp.pp_if.if_opackets);
2636 sc->ifsppp.pp_if.if_oerrors++;
2639 * Check for (& process) a Buffer overflow
2641 if (dsr & SCA_DSR_BOF) {
2642 printf("sr%d: TX DMA Buffer overflow, "
2643 "txpacket no %lu, dsr %02x, "
2644 "cda %04x, eda %04x.\n",
2645 sc->unit, sc->ifsppp.pp_if.if_opackets,
2647 SRC_GET16(hc->sca_base, dmac->cda),
2648 SRC_GET16(hc->sca_base, dmac->eda));
2649 sc->ifsppp.pp_if.if_oerrors++;
2652 * Check for (& process) an End of Transfer (OK)
2654 if (dsr & SCA_DSR_EOT) {
2656 * This should be the most common case.
2658 * Clear the IFF_OACTIVE flag.
2660 * Call srstart to start a new transmit if
2661 * there is data to transmit.
2664 printf("sr%d: TX Completed OK\n", sc->unit);
2667 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
2668 sc->ifsppp.pp_if.if_timer = 0;
2670 if (sc->txb_inuse && --sc->txb_inuse)
2675 * Receive channel processing of DMA Status Register
2678 dmac = &sca->dmac[DMAC_RXCH(mch)];
2680 dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2681 SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2684 * End of frame processing (MSG OK?)
2686 if (dsr & SCA_DSR_EOM) {
2690 tt = sc->ifsppp.pp_if.if_ipackets;
2697 if (tt == sc->ifsppp.pp_if.if_ipackets) {
2698 sca_descriptor *rxdesc;
2701 printf("SR: RXINTR isr1 %x, dsr %x, "
2702 "no data %d pkts, orxind %d.\n",
2703 dotxstart, dsr, tt, ind);
2704 printf("SR: rxdesc %x, rxstart %x, "
2705 "rxend %x, rxhind %d, "
2707 sc->rxdesc, sc->rxstart,
2708 sc->rxend, sc->rxhind,
2710 printf("SR: cda %x, eda %x.\n",
2711 SRC_GET16(hc->sca_base, dmac->cda),
2712 SRC_GET16(hc->sca_base, dmac->eda));
2715 SRC_SET_ON(hc->iobase);
2716 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2718 rxdesc = (sca_descriptor *)
2720 (sc->rxdesc & hc->winmsk));
2721 rxdesc = &rxdesc[sc->rxhind];
2723 for (i = 0; i < 3; i++, rxdesc++)
2724 printf("SR: rxdesc->stat %x, "
2730 SRC_SET_OFF(hc->iobase);
2735 * Check for Counter overflow
2737 if (dsr & SCA_DSR_COF) {
2738 printf("sr%d: RX DMA Counter overflow, "
2740 sc->unit, sc->ifsppp.pp_if.if_ipackets);
2741 sc->ifsppp.pp_if.if_ierrors++;
2744 * Check for Buffer overflow
2746 if (dsr & SCA_DSR_BOF) {
2747 printf("sr%d: RX DMA Buffer overflow, "
2748 "rxpkts %lu, rxind %d, "
2749 "cda %x, eda %x, dsr %x.\n",
2750 sc->unit, sc->ifsppp.pp_if.if_ipackets,
2752 SRC_GET16(hc->sca_base, dmac->cda),
2753 SRC_GET16(hc->sca_base, dmac->eda),
2757 * Make sure we eat as many as possible.
2758 * Then get the system running again.
2761 SRC_SET_ON(hc->iobase);
2763 sr_eat_packet(sc, 0);
2764 sc->ifsppp.pp_if.if_ierrors++;
2766 SRC_PUT8(hc->sca_base,
2770 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
2773 printf("sr%d: RX DMA Buffer overflow, "
2774 "rxpkts %lu, rxind %d, "
2775 "cda %x, eda %x, dsr %x. After\n",
2777 sc->ifsppp.pp_if.if_ipackets,
2779 SRC_GET16(hc->sca_base, dmac->cda),
2780 SRC_GET16(hc->sca_base, dmac->eda),
2781 SRC_GET8(hc->sca_base, dmac->dsr));
2785 SRC_SET_OFF(hc->iobase);
2790 if (dsr & SCA_DSR_EOT) {
2792 * If this happen, it means that we are
2793 * receiving faster than what the processor
2796 * XXX We should enable the dma again.
2798 printf("sr%d: RX End of xfer, rxpkts %lu.\n",
2800 sc->ifsppp.pp_if.if_ipackets);
2801 sc->ifsppp.pp_if.if_ierrors++;
2804 isr1 >>= 4; /* process next half of ISR */
2805 mch++; /* and move to next channel */
2806 } while ((mch < NCHAN) && isr1); /* loop for each chn */
2809 * Now that we have done all the urgent things, see if we can fill
2810 * the transmit buffers.
2812 for (mch = 0; mch < NCHAN; mch++) {
2813 if (dotxstart & 0x0C) { /* TX initiation enabled? */
2815 srstart(&sc->ifsppp.pp_if);
2817 dotxstart >>= 4;/* shift for next channel */
2822 * Perform timeout on an FR channel
2824 * Establish a periodic check of open N2 ports; If
2825 * a port is open/active, its DCD state is checked
2826 * and a loss of DCD is recognized (and eventually
2830 sr_modemck(void *arg)
2833 int card; /* card index in table */
2834 int cards; /* card list index */
2835 int mch; /* channel on card */
2836 u_char dcd_v; /* Data Carrier Detect */
2837 u_char got_st0; /* contents of ST0 */
2838 u_char got_st1; /* contents of ST1 */
2839 u_char got_st2; /* contents of ST2 */
2840 u_char got_st3; /* contents of ST3 */
2841 struct sr_hardc *hc; /* card's configuration */
2842 struct sr_hardc *Card[16];/* up to 16 cards in system */
2843 struct sr_softc *sc; /* channel's softc structure */
2844 struct ifnet *ifp; /* interface control table */
2845 msci_channel *msci; /* regs specific to channel */
2850 if (sr_opens == 0) { /* count of "up" channels */
2851 sr_watcher = 0; /* indicate no watcher */
2857 sr_watcher = 1; /* mark that we're online */
2860 * Now we'll need a list of cards to process. Since we can handle
2861 * both ISA and PCI cards (and I didn't think of making this logic
2862 * global YET) we'll generate a single table of card table
2867 for (card = 0; card < NSR; card++) {
2868 hc = &sr_hardc[card];
2870 if (hc->sc == (void *)0)
2884 * OK, we've got work we can do. Let's do it... (Please note that
2885 * this code _only_ deals w/ ISA cards)
2887 for (card = 0; card < cards; card++) {
2888 hc = Card[card];/* get card table */
2890 for (mch = 0; mch < hc->numports; mch++) {
2893 if (sc->attached == 0)
2896 ifp = &sc->ifsppp.pp_if;
2899 * if this channel isn't "up", skip it
2901 if ((ifp->if_flags & IFF_UP) == 0)
2905 * OK, now we can go looking at this channel's
2906 * actual register contents...
2908 msci = &hc->sca->msci[sc->scachan];
2911 * OK, now we'll look into the actual status of this
2914 * I suck in more registers than strictly needed
2916 got_st0 = SRC_GET8(hc->sca_base, msci->st0);
2917 got_st1 = SRC_GET8(hc->sca_base, msci->st1);
2918 got_st2 = SRC_GET8(hc->sca_base, msci->st2);
2919 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2922 * We want to see if the DCD signal is up (DCD is
2925 dcd_v = (got_st3 & SCA_ST3_DCD) == 0;
2928 printf("sr%d: DCD lost\n", sc->unit);
2933 * OK, now set up for the next modem signal checking pass...
2935 timeout(sr_modemck, NULL, hz);
2941 sr_msci_intr(struct sr_hardc *hc, u_char isr0)
2943 printf("src%d: SRINTR: MSCI\n", hc->cunit);
2947 sr_timer_intr(struct sr_hardc *hc, u_char isr2)
2949 printf("src%d: SRINTR: TIMER\n", hc->cunit);
2953 ********************************* END ************************************