1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */
4 * SPDX-License-Identifier: BSD-2-Clause-NetBSD
6 * Copyright (c) 2001 The NetBSD Foundation, Inc.
9 * This code is derived from software contributed to The NetBSD Foundation
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * Device driver for the Sundance Tech. TC9021 10/100/1000
36 * Ethernet controller.
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
42 #ifdef HAVE_KERNEL_OPTION_HEADERS
43 #include "opt_device_polling.h"
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/endian.h>
50 #include <sys/malloc.h>
51 #include <sys/kernel.h>
52 #include <sys/module.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
55 #include <sys/sysctl.h>
56 #include <sys/taskqueue.h>
59 #include <net/ethernet.h>
61 #include <net/if_var.h>
62 #include <net/if_dl.h>
63 #include <net/if_media.h>
64 #include <net/if_types.h>
65 #include <net/if_vlan_var.h>
67 #include <machine/bus.h>
68 #include <machine/resource.h>
72 #include <dev/mii/mii.h>
73 #include <dev/mii/mii_bitbang.h>
74 #include <dev/mii/miivar.h>
76 #include <dev/pci/pcireg.h>
77 #include <dev/pci/pcivar.h>
79 #include <dev/stge/if_stgereg.h>
81 #define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
83 MODULE_DEPEND(stge, pci, 1, 1, 1);
84 MODULE_DEPEND(stge, ether, 1, 1, 1);
85 MODULE_DEPEND(stge, miibus, 1, 1, 1);
87 /* "device miibus" required. See GENERIC if you get errors here. */
88 #include "miibus_if.h"
91 * Devices supported by this driver.
93 static const struct stge_product {
94 uint16_t stge_vendorid;
95 uint16_t stge_deviceid;
96 const char *stge_name;
98 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023,
99 "Sundance ST-1023 Gigabit Ethernet" },
101 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021,
102 "Sundance ST-2021 Gigabit Ethernet" },
104 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021,
105 "Tamarack TC9021 Gigabit Ethernet" },
107 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT,
108 "Tamarack TC9021 Gigabit Ethernet" },
111 * The Sundance sample boards use the Sundance vendor ID,
112 * but the Tamarack product ID.
114 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021,
115 "Sundance TC9021 Gigabit Ethernet" },
117 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT,
118 "Sundance TC9021 Gigabit Ethernet" },
120 { VENDOR_DLINK, DEVICEID_DLINK_DL4000,
121 "D-Link DL-4000 Gigabit Ethernet" },
123 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021,
124 "Antares Gigabit Ethernet" }
127 static int stge_probe(device_t);
128 static int stge_attach(device_t);
129 static int stge_detach(device_t);
130 static int stge_shutdown(device_t);
131 static int stge_suspend(device_t);
132 static int stge_resume(device_t);
134 static int stge_encap(struct stge_softc *, struct mbuf **);
135 static void stge_start(struct ifnet *);
136 static void stge_start_locked(struct ifnet *);
137 static void stge_watchdog(struct stge_softc *);
138 static int stge_ioctl(struct ifnet *, u_long, caddr_t);
139 static void stge_init(void *);
140 static void stge_init_locked(struct stge_softc *);
141 static void stge_vlan_setup(struct stge_softc *);
142 static void stge_stop(struct stge_softc *);
143 static void stge_start_tx(struct stge_softc *);
144 static void stge_start_rx(struct stge_softc *);
145 static void stge_stop_tx(struct stge_softc *);
146 static void stge_stop_rx(struct stge_softc *);
148 static void stge_reset(struct stge_softc *, uint32_t);
149 static int stge_eeprom_wait(struct stge_softc *);
150 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *);
151 static void stge_tick(void *);
152 static void stge_stats_update(struct stge_softc *);
153 static void stge_set_filter(struct stge_softc *);
154 static void stge_set_multi(struct stge_softc *);
156 static void stge_link_task(void *, int);
157 static void stge_intr(void *);
158 static __inline int stge_tx_error(struct stge_softc *);
159 static void stge_txeof(struct stge_softc *);
160 static int stge_rxeof(struct stge_softc *);
161 static __inline void stge_discard_rxbuf(struct stge_softc *, int);
162 static int stge_newbuf(struct stge_softc *, int);
163 #ifndef __NO_STRICT_ALIGNMENT
164 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *);
167 static int stge_miibus_readreg(device_t, int, int);
168 static int stge_miibus_writereg(device_t, int, int, int);
169 static void stge_miibus_statchg(device_t);
170 static int stge_mediachange(struct ifnet *);
171 static void stge_mediastatus(struct ifnet *, struct ifmediareq *);
173 static void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
174 static int stge_dma_alloc(struct stge_softc *);
175 static void stge_dma_free(struct stge_softc *);
176 static void stge_dma_wait(struct stge_softc *);
177 static void stge_init_tx_ring(struct stge_softc *);
178 static int stge_init_rx_ring(struct stge_softc *);
179 #ifdef DEVICE_POLLING
180 static int stge_poll(struct ifnet *, enum poll_cmd, int);
183 static void stge_setwol(struct stge_softc *);
184 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
185 static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS);
186 static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS);
191 static uint32_t stge_mii_bitbang_read(device_t);
192 static void stge_mii_bitbang_write(device_t, uint32_t);
194 static const struct mii_bitbang_ops stge_mii_bitbang_ops = {
195 stge_mii_bitbang_read,
196 stge_mii_bitbang_write,
198 PC_MgmtData, /* MII_BIT_MDO */
199 PC_MgmtData, /* MII_BIT_MDI */
200 PC_MgmtClk, /* MII_BIT_MDC */
201 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */
202 0, /* MII_BIT_DIR_PHY_HOST */
206 static device_method_t stge_methods[] = {
207 /* Device interface */
208 DEVMETHOD(device_probe, stge_probe),
209 DEVMETHOD(device_attach, stge_attach),
210 DEVMETHOD(device_detach, stge_detach),
211 DEVMETHOD(device_shutdown, stge_shutdown),
212 DEVMETHOD(device_suspend, stge_suspend),
213 DEVMETHOD(device_resume, stge_resume),
216 DEVMETHOD(miibus_readreg, stge_miibus_readreg),
217 DEVMETHOD(miibus_writereg, stge_miibus_writereg),
218 DEVMETHOD(miibus_statchg, stge_miibus_statchg),
223 static driver_t stge_driver = {
226 sizeof(struct stge_softc)
229 static devclass_t stge_devclass;
231 DRIVER_MODULE(stge, pci, stge_driver, stge_devclass, 0, 0);
232 DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, 0, 0);
234 static struct resource_spec stge_res_spec_io[] = {
235 { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE },
236 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
240 static struct resource_spec stge_res_spec_mem[] = {
241 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE },
242 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
247 * stge_mii_bitbang_read: [mii bit-bang interface function]
249 * Read the MII serial port for the MII bit-bang module.
252 stge_mii_bitbang_read(device_t dev)
254 struct stge_softc *sc;
257 sc = device_get_softc(dev);
259 val = CSR_READ_1(sc, STGE_PhyCtrl);
260 CSR_BARRIER(sc, STGE_PhyCtrl, 1,
261 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
266 * stge_mii_bitbang_write: [mii big-bang interface function]
268 * Write the MII serial port for the MII bit-bang module.
271 stge_mii_bitbang_write(device_t dev, uint32_t val)
273 struct stge_softc *sc;
275 sc = device_get_softc(dev);
277 CSR_WRITE_1(sc, STGE_PhyCtrl, val);
278 CSR_BARRIER(sc, STGE_PhyCtrl, 1,
279 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
283 * sc_miibus_readreg: [mii interface function]
285 * Read a PHY register on the MII of the TC9021.
288 stge_miibus_readreg(device_t dev, int phy, int reg)
290 struct stge_softc *sc;
293 sc = device_get_softc(dev);
295 if (reg == STGE_PhyCtrl) {
296 /* XXX allow ip1000phy read STGE_PhyCtrl register. */
298 error = CSR_READ_1(sc, STGE_PhyCtrl);
304 val = mii_bitbang_readreg(dev, &stge_mii_bitbang_ops, phy, reg);
310 * stge_miibus_writereg: [mii interface function]
312 * Write a PHY register on the MII of the TC9021.
315 stge_miibus_writereg(device_t dev, int phy, int reg, int val)
317 struct stge_softc *sc;
319 sc = device_get_softc(dev);
322 mii_bitbang_writereg(dev, &stge_mii_bitbang_ops, phy, reg, val);
328 * stge_miibus_statchg: [mii interface function]
330 * Callback from MII layer when media changes.
333 stge_miibus_statchg(device_t dev)
335 struct stge_softc *sc;
337 sc = device_get_softc(dev);
338 taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task);
342 * stge_mediastatus: [ifmedia interface function]
344 * Get the current interface media status.
347 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
349 struct stge_softc *sc;
350 struct mii_data *mii;
353 mii = device_get_softc(sc->sc_miibus);
356 ifmr->ifm_status = mii->mii_media_status;
357 ifmr->ifm_active = mii->mii_media_active;
361 * stge_mediachange: [ifmedia interface function]
363 * Set hardware to newly-selected media.
366 stge_mediachange(struct ifnet *ifp)
368 struct stge_softc *sc;
369 struct mii_data *mii;
372 mii = device_get_softc(sc->sc_miibus);
379 stge_eeprom_wait(struct stge_softc *sc)
383 for (i = 0; i < STGE_TIMEOUT; i++) {
385 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
394 * Read data from the serial EEPROM.
397 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
400 if (stge_eeprom_wait(sc))
401 device_printf(sc->sc_dev, "EEPROM failed to come ready\n");
403 CSR_WRITE_2(sc, STGE_EepromCtrl,
404 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
405 if (stge_eeprom_wait(sc))
406 device_printf(sc->sc_dev, "EEPROM read timed out\n");
407 *data = CSR_READ_2(sc, STGE_EepromData);
411 stge_probe(device_t dev)
413 const struct stge_product *sp;
415 uint16_t vendor, devid;
417 vendor = pci_get_vendor(dev);
418 devid = pci_get_device(dev);
420 for (i = 0; i < nitems(stge_products); i++, sp++) {
421 if (vendor == sp->stge_vendorid &&
422 devid == sp->stge_deviceid) {
423 device_set_desc(dev, sp->stge_name);
424 return (BUS_PROBE_DEFAULT);
432 stge_attach(device_t dev)
434 struct stge_softc *sc;
436 uint8_t enaddr[ETHER_ADDR_LEN];
442 sc = device_get_softc(dev);
445 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
447 mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF);
448 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
449 TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc);
454 pci_enable_busmaster(dev);
455 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
456 val = pci_read_config(dev, PCIR_BAR(1), 4);
458 sc->sc_spec = stge_res_spec_mem;
460 val = pci_read_config(dev, PCIR_BAR(0), 4);
461 if (!PCI_BAR_IO(val)) {
462 device_printf(sc->sc_dev, "couldn't locate IO BAR\n");
466 sc->sc_spec = stge_res_spec_io;
468 error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res);
470 device_printf(dev, "couldn't allocate %s resources\n",
471 sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O");
474 sc->sc_rev = pci_get_revid(dev);
476 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
477 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
478 "rxint_nframe", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
479 &sc->sc_rxint_nframe, 0, sysctl_hw_stge_rxint_nframe, "I",
480 "stge rx interrupt nframe");
482 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
483 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
484 "rxint_dmawait", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
485 &sc->sc_rxint_dmawait, 0, sysctl_hw_stge_rxint_dmawait, "I",
486 "stge rx interrupt dmawait");
488 /* Pull in device tunables. */
489 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
490 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
491 "rxint_nframe", &sc->sc_rxint_nframe);
493 if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN ||
494 sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) {
495 device_printf(dev, "rxint_nframe value out of range; "
496 "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT);
497 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
501 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
502 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
503 "rxint_dmawait", &sc->sc_rxint_dmawait);
505 if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN ||
506 sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) {
507 device_printf(dev, "rxint_dmawait value out of range; "
508 "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT);
509 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
513 if ((error = stge_dma_alloc(sc)) != 0)
517 * Determine if we're copper or fiber. It affects how we
520 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
525 /* Load LED configuration from EEPROM. */
526 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led);
529 * Reset the chip to a known state.
532 stge_reset(sc, STGE_RESET_FULL);
536 * Reading the station address from the EEPROM doesn't seem
537 * to work, at least on my sample boards. Instead, since
538 * the reset sequence does AutoInit, read it from the station
539 * address registers. For Sundance 1023 you can only read it
542 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) {
545 v = CSR_READ_2(sc, STGE_StationAddress0);
546 enaddr[0] = v & 0xff;
548 v = CSR_READ_2(sc, STGE_StationAddress1);
549 enaddr[2] = v & 0xff;
551 v = CSR_READ_2(sc, STGE_StationAddress2);
552 enaddr[4] = v & 0xff;
556 uint16_t myaddr[ETHER_ADDR_LEN / 2];
557 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
558 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i,
560 myaddr[i] = le16toh(myaddr[i]);
562 bcopy(myaddr, enaddr, sizeof(enaddr));
566 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
568 device_printf(sc->sc_dev, "failed to if_alloc()\n");
574 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
575 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
576 ifp->if_ioctl = stge_ioctl;
577 ifp->if_start = stge_start;
578 ifp->if_init = stge_init;
579 ifp->if_snd.ifq_drv_maxlen = STGE_TX_RING_CNT - 1;
580 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
581 IFQ_SET_READY(&ifp->if_snd);
582 /* Revision B3 and earlier chips have checksum bug. */
583 if (sc->sc_rev >= 0x0c) {
584 ifp->if_hwassist = STGE_CSUM_FEATURES;
585 ifp->if_capabilities = IFCAP_HWCSUM;
587 ifp->if_hwassist = 0;
588 ifp->if_capabilities = 0;
590 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
591 ifp->if_capenable = ifp->if_capabilities;
594 * Read some important bits from the PhyCtrl register.
596 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
597 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
599 /* Set up MII bus. */
600 flags = MIIF_DOPAUSE;
601 if (sc->sc_rev >= 0x40 && sc->sc_rev <= 0x4e)
602 flags |= MIIF_MACPRIV0;
603 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, stge_mediachange,
604 stge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
607 device_printf(sc->sc_dev, "attaching PHYs failed\n");
611 ether_ifattach(ifp, enaddr);
613 /* VLAN capability setup */
614 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
615 if (sc->sc_rev >= 0x0c)
616 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
617 ifp->if_capenable = ifp->if_capabilities;
618 #ifdef DEVICE_POLLING
619 ifp->if_capabilities |= IFCAP_POLLING;
622 * Tell the upper layer(s) we support long frames.
623 * Must appear after the call to ether_ifattach() because
624 * ether_ifattach() sets ifi_hdrlen to the default value.
626 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
629 * The manual recommends disabling early transmit, so we
630 * do. It's disabled anyway, if using IP checksumming,
631 * since the entire packet must be in the FIFO in order
632 * for the chip to perform the checksum.
634 sc->sc_txthresh = 0x0fff;
637 * Disable MWI if the PCI layer tells us to.
640 if ((cmd & PCIM_CMD_MWRICEN) == 0)
641 sc->sc_DMACtrl |= DMAC_MWIDisable;
646 error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE,
647 NULL, stge_intr, sc, &sc->sc_ih);
650 device_printf(sc->sc_dev, "couldn't set up IRQ\n");
663 stge_detach(device_t dev)
665 struct stge_softc *sc;
668 sc = device_get_softc(dev);
671 #ifdef DEVICE_POLLING
672 if (ifp && ifp->if_capenable & IFCAP_POLLING)
673 ether_poll_deregister(ifp);
675 if (device_is_attached(dev)) {
681 callout_drain(&sc->sc_tick_ch);
682 taskqueue_drain(taskqueue_swi, &sc->sc_link_task);
686 if (sc->sc_miibus != NULL) {
687 device_delete_child(dev, sc->sc_miibus);
688 sc->sc_miibus = NULL;
690 bus_generic_detach(dev);
699 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih);
702 bus_release_resources(dev, sc->sc_spec, sc->sc_res);
704 mtx_destroy(&sc->sc_mii_mtx);
705 mtx_destroy(&sc->sc_mtx);
710 struct stge_dmamap_arg {
711 bus_addr_t stge_busaddr;
715 stge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
717 struct stge_dmamap_arg *ctx;
722 ctx = (struct stge_dmamap_arg *)arg;
723 ctx->stge_busaddr = segs[0].ds_addr;
727 stge_dma_alloc(struct stge_softc *sc)
729 struct stge_dmamap_arg ctx;
730 struct stge_txdesc *txd;
731 struct stge_rxdesc *rxd;
734 /* create parent tag. */
735 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),/* parent */
736 1, 0, /* algnmnt, boundary */
737 STGE_DMA_MAXADDR, /* lowaddr */
738 BUS_SPACE_MAXADDR, /* highaddr */
739 NULL, NULL, /* filter, filterarg */
740 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
742 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
744 NULL, NULL, /* lockfunc, lockarg */
745 &sc->sc_cdata.stge_parent_tag);
747 device_printf(sc->sc_dev, "failed to create parent DMA tag\n");
750 /* create tag for Tx ring. */
751 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
752 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
753 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
754 BUS_SPACE_MAXADDR, /* highaddr */
755 NULL, NULL, /* filter, filterarg */
756 STGE_TX_RING_SZ, /* maxsize */
758 STGE_TX_RING_SZ, /* maxsegsize */
760 NULL, NULL, /* lockfunc, lockarg */
761 &sc->sc_cdata.stge_tx_ring_tag);
763 device_printf(sc->sc_dev,
764 "failed to allocate Tx ring DMA tag\n");
768 /* create tag for Rx ring. */
769 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
770 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
771 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
772 BUS_SPACE_MAXADDR, /* highaddr */
773 NULL, NULL, /* filter, filterarg */
774 STGE_RX_RING_SZ, /* maxsize */
776 STGE_RX_RING_SZ, /* maxsegsize */
778 NULL, NULL, /* lockfunc, lockarg */
779 &sc->sc_cdata.stge_rx_ring_tag);
781 device_printf(sc->sc_dev,
782 "failed to allocate Rx ring DMA tag\n");
786 /* create tag for Tx buffers. */
787 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
788 1, 0, /* algnmnt, boundary */
789 BUS_SPACE_MAXADDR, /* lowaddr */
790 BUS_SPACE_MAXADDR, /* highaddr */
791 NULL, NULL, /* filter, filterarg */
792 MCLBYTES * STGE_MAXTXSEGS, /* maxsize */
793 STGE_MAXTXSEGS, /* nsegments */
794 MCLBYTES, /* maxsegsize */
796 NULL, NULL, /* lockfunc, lockarg */
797 &sc->sc_cdata.stge_tx_tag);
799 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n");
803 /* create tag for Rx buffers. */
804 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
805 1, 0, /* algnmnt, boundary */
806 BUS_SPACE_MAXADDR, /* lowaddr */
807 BUS_SPACE_MAXADDR, /* highaddr */
808 NULL, NULL, /* filter, filterarg */
809 MCLBYTES, /* maxsize */
811 MCLBYTES, /* maxsegsize */
813 NULL, NULL, /* lockfunc, lockarg */
814 &sc->sc_cdata.stge_rx_tag);
816 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n");
820 /* allocate DMA'able memory and load the DMA map for Tx ring. */
821 error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag,
822 (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT |
823 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_tx_ring_map);
825 device_printf(sc->sc_dev,
826 "failed to allocate DMA'able memory for Tx ring\n");
830 ctx.stge_busaddr = 0;
831 error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag,
832 sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring,
833 STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
834 if (error != 0 || ctx.stge_busaddr == 0) {
835 device_printf(sc->sc_dev,
836 "failed to load DMA'able memory for Tx ring\n");
839 sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr;
841 /* allocate DMA'able memory and load the DMA map for Rx ring. */
842 error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag,
843 (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT |
844 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_rx_ring_map);
846 device_printf(sc->sc_dev,
847 "failed to allocate DMA'able memory for Rx ring\n");
851 ctx.stge_busaddr = 0;
852 error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag,
853 sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring,
854 STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
855 if (error != 0 || ctx.stge_busaddr == 0) {
856 device_printf(sc->sc_dev,
857 "failed to load DMA'able memory for Rx ring\n");
860 sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr;
862 /* create DMA maps for Tx buffers. */
863 for (i = 0; i < STGE_TX_RING_CNT; i++) {
864 txd = &sc->sc_cdata.stge_txdesc[i];
867 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0,
870 device_printf(sc->sc_dev,
871 "failed to create Tx dmamap\n");
875 /* create DMA maps for Rx buffers. */
876 if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
877 &sc->sc_cdata.stge_rx_sparemap)) != 0) {
878 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n");
881 for (i = 0; i < STGE_RX_RING_CNT; i++) {
882 rxd = &sc->sc_cdata.stge_rxdesc[i];
885 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
888 device_printf(sc->sc_dev,
889 "failed to create Rx dmamap\n");
899 stge_dma_free(struct stge_softc *sc)
901 struct stge_txdesc *txd;
902 struct stge_rxdesc *rxd;
906 if (sc->sc_cdata.stge_tx_ring_tag) {
907 if (sc->sc_rdata.stge_tx_ring_paddr)
908 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag,
909 sc->sc_cdata.stge_tx_ring_map);
910 if (sc->sc_rdata.stge_tx_ring)
911 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag,
912 sc->sc_rdata.stge_tx_ring,
913 sc->sc_cdata.stge_tx_ring_map);
914 sc->sc_rdata.stge_tx_ring = NULL;
915 sc->sc_rdata.stge_tx_ring_paddr = 0;
916 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag);
917 sc->sc_cdata.stge_tx_ring_tag = NULL;
920 if (sc->sc_cdata.stge_rx_ring_tag) {
921 if (sc->sc_rdata.stge_rx_ring_paddr)
922 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag,
923 sc->sc_cdata.stge_rx_ring_map);
924 if (sc->sc_rdata.stge_rx_ring)
925 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag,
926 sc->sc_rdata.stge_rx_ring,
927 sc->sc_cdata.stge_rx_ring_map);
928 sc->sc_rdata.stge_rx_ring = NULL;
929 sc->sc_rdata.stge_rx_ring_paddr = 0;
930 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag);
931 sc->sc_cdata.stge_rx_ring_tag = NULL;
934 if (sc->sc_cdata.stge_tx_tag) {
935 for (i = 0; i < STGE_TX_RING_CNT; i++) {
936 txd = &sc->sc_cdata.stge_txdesc[i];
937 if (txd->tx_dmamap) {
938 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
943 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
944 sc->sc_cdata.stge_tx_tag = NULL;
947 if (sc->sc_cdata.stge_rx_tag) {
948 for (i = 0; i < STGE_RX_RING_CNT; i++) {
949 rxd = &sc->sc_cdata.stge_rxdesc[i];
950 if (rxd->rx_dmamap) {
951 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
956 if (sc->sc_cdata.stge_rx_sparemap) {
957 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
958 sc->sc_cdata.stge_rx_sparemap);
959 sc->sc_cdata.stge_rx_sparemap = 0;
961 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
962 sc->sc_cdata.stge_rx_tag = NULL;
965 if (sc->sc_cdata.stge_parent_tag) {
966 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag);
967 sc->sc_cdata.stge_parent_tag = NULL;
974 * Make sure the interface is stopped at reboot time.
977 stge_shutdown(device_t dev)
980 return (stge_suspend(dev));
984 stge_setwol(struct stge_softc *sc)
989 STGE_LOCK_ASSERT(sc);
992 v = CSR_READ_1(sc, STGE_WakeEvent);
993 /* Disable all WOL bits. */
994 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
996 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
997 v |= WE_MagicPktEnable | WE_WakeOnLanEnable;
998 CSR_WRITE_1(sc, STGE_WakeEvent, v);
999 /* Reset Tx and prevent transmission. */
1000 CSR_WRITE_4(sc, STGE_AsicCtrl,
1001 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset);
1003 * TC9021 automatically reset link speed to 100Mbps when it's put
1004 * into sleep so there is no need to try to resetting link speed.
1009 stge_suspend(device_t dev)
1011 struct stge_softc *sc;
1013 sc = device_get_softc(dev);
1017 sc->sc_suspended = 1;
1025 stge_resume(device_t dev)
1027 struct stge_softc *sc;
1031 sc = device_get_softc(dev);
1035 * Clear WOL bits, so special frames wouldn't interfere
1036 * normal Rx operation anymore.
1038 v = CSR_READ_1(sc, STGE_WakeEvent);
1039 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
1040 WE_WakeOnLanEnable);
1041 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1043 if (ifp->if_flags & IFF_UP)
1044 stge_init_locked(sc);
1046 sc->sc_suspended = 0;
1053 stge_dma_wait(struct stge_softc *sc)
1057 for (i = 0; i < STGE_TIMEOUT; i++) {
1059 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
1063 if (i == STGE_TIMEOUT)
1064 device_printf(sc->sc_dev, "DMA wait timed out\n");
1068 stge_encap(struct stge_softc *sc, struct mbuf **m_head)
1070 struct stge_txdesc *txd;
1071 struct stge_tfd *tfd;
1073 bus_dma_segment_t txsegs[STGE_MAXTXSEGS];
1074 int error, i, nsegs, si;
1075 uint64_t csum_flags, tfc;
1077 STGE_LOCK_ASSERT(sc);
1079 if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL)
1082 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1083 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1084 if (error == EFBIG) {
1085 m = m_collapse(*m_head, M_NOWAIT, STGE_MAXTXSEGS);
1092 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1093 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1099 } else if (error != 0)
1109 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) {
1110 if (m->m_pkthdr.csum_flags & CSUM_IP)
1111 csum_flags |= TFD_IPChecksumEnable;
1112 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1113 csum_flags |= TFD_TCPChecksumEnable;
1114 else if (m->m_pkthdr.csum_flags & CSUM_UDP)
1115 csum_flags |= TFD_UDPChecksumEnable;
1118 si = sc->sc_cdata.stge_tx_prod;
1119 tfd = &sc->sc_rdata.stge_tx_ring[si];
1120 for (i = 0; i < nsegs; i++)
1121 tfd->tfd_frags[i].frag_word0 =
1122 htole64(FRAG_ADDR(txsegs[i].ds_addr) |
1123 FRAG_LEN(txsegs[i].ds_len));
1124 sc->sc_cdata.stge_tx_cnt++;
1126 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) |
1127 TFD_FragCount(nsegs) | csum_flags;
1128 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT)
1129 tfc |= TFD_TxDMAIndicate;
1131 /* Update producer index. */
1132 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT;
1134 /* Check if we have a VLAN tag to insert. */
1135 if (m->m_flags & M_VLANTAG)
1136 tfc |= (TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vtag));
1137 tfd->tfd_control = htole64(tfc);
1139 /* Update Tx Queue. */
1140 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q);
1141 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q);
1144 /* Sync descriptors. */
1145 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1146 BUS_DMASYNC_PREWRITE);
1147 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1148 sc->sc_cdata.stge_tx_ring_map,
1149 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1155 * stge_start: [ifnet interface function]
1157 * Start packet transmission on the interface.
1160 stge_start(struct ifnet *ifp)
1162 struct stge_softc *sc;
1166 stge_start_locked(ifp);
1171 stge_start_locked(struct ifnet *ifp)
1173 struct stge_softc *sc;
1174 struct mbuf *m_head;
1179 STGE_LOCK_ASSERT(sc);
1181 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
1182 IFF_DRV_RUNNING || sc->sc_link == 0)
1185 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1186 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) {
1187 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1191 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1195 * Pack the data into the transmit ring. If we
1196 * don't have room, set the OACTIVE flag and wait
1197 * for the NIC to drain the ring.
1199 if (stge_encap(sc, &m_head)) {
1202 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1203 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1209 * If there's a BPF listener, bounce a copy of this frame
1212 ETHER_BPF_MTAP(ifp, m_head);
1217 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow);
1219 /* Set a timeout in case the chip goes out to lunch. */
1220 sc->sc_watchdog_timer = 5;
1227 * Watchdog timer handler.
1230 stge_watchdog(struct stge_softc *sc)
1234 STGE_LOCK_ASSERT(sc);
1236 if (sc->sc_watchdog_timer == 0 || --sc->sc_watchdog_timer)
1240 if_printf(sc->sc_ifp, "device timeout\n");
1241 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1242 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1243 stge_init_locked(sc);
1244 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1245 stge_start_locked(ifp);
1249 * stge_ioctl: [ifnet interface function]
1251 * Handle control requests from the operator.
1254 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1256 struct stge_softc *sc;
1258 struct mii_data *mii;
1262 ifr = (struct ifreq *)data;
1266 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU)
1268 else if (ifp->if_mtu != ifr->ifr_mtu) {
1269 ifp->if_mtu = ifr->ifr_mtu;
1271 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1272 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1273 stge_init_locked(sc);
1280 if ((ifp->if_flags & IFF_UP) != 0) {
1281 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1282 if (((ifp->if_flags ^ sc->sc_if_flags)
1283 & IFF_PROMISC) != 0)
1284 stge_set_filter(sc);
1286 if (sc->sc_detach == 0)
1287 stge_init_locked(sc);
1290 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1293 sc->sc_if_flags = ifp->if_flags;
1299 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1305 mii = device_get_softc(sc->sc_miibus);
1306 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1309 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1310 #ifdef DEVICE_POLLING
1311 if ((mask & IFCAP_POLLING) != 0) {
1312 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1313 error = ether_poll_register(stge_poll, ifp);
1317 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1318 ifp->if_capenable |= IFCAP_POLLING;
1321 error = ether_poll_deregister(ifp);
1325 CSR_WRITE_2(sc, STGE_IntEnable,
1327 ifp->if_capenable &= ~IFCAP_POLLING;
1332 if ((mask & IFCAP_HWCSUM) != 0) {
1333 ifp->if_capenable ^= IFCAP_HWCSUM;
1334 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 &&
1335 (IFCAP_HWCSUM & ifp->if_capabilities) != 0)
1336 ifp->if_hwassist = STGE_CSUM_FEATURES;
1338 ifp->if_hwassist = 0;
1340 if ((mask & IFCAP_WOL) != 0 &&
1341 (ifp->if_capabilities & IFCAP_WOL) != 0) {
1342 if ((mask & IFCAP_WOL_MAGIC) != 0)
1343 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1345 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
1346 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1347 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1349 stge_vlan_setup(sc);
1353 VLAN_CAPABILITIES(ifp);
1356 error = ether_ioctl(ifp, cmd, data);
1364 stge_link_task(void *arg, int pending)
1366 struct stge_softc *sc;
1367 struct mii_data *mii;
1371 sc = (struct stge_softc *)arg;
1374 mii = device_get_softc(sc->sc_miibus);
1375 if (mii->mii_media_status & IFM_ACTIVE) {
1376 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1382 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
1383 sc->sc_MACCtrl |= MC_DuplexSelect;
1384 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_RXPAUSE) != 0)
1385 sc->sc_MACCtrl |= MC_RxFlowControlEnable;
1386 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_TXPAUSE) != 0)
1387 sc->sc_MACCtrl |= MC_TxFlowControlEnable;
1389 * Update STGE_MACCtrl register depending on link status.
1390 * (duplex, flow control etc)
1392 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
1393 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable);
1394 v |= sc->sc_MACCtrl;
1395 CSR_WRITE_4(sc, STGE_MACCtrl, v);
1396 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) {
1397 /* Duplex setting changed, reset Tx/Rx functions. */
1398 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1399 ac |= AC_TxReset | AC_RxReset;
1400 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1401 for (i = 0; i < STGE_TIMEOUT; i++) {
1403 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1406 if (i == STGE_TIMEOUT)
1407 device_printf(sc->sc_dev, "reset failed to complete\n");
1413 stge_tx_error(struct stge_softc *sc)
1419 txstat = CSR_READ_4(sc, STGE_TxStatus);
1420 if ((txstat & TS_TxComplete) == 0)
1423 if ((txstat & TS_TxUnderrun) != 0) {
1426 * There should be a more better way to recover
1427 * from Tx underrun instead of a full reset.
1429 if (sc->sc_nerr++ < STGE_MAXERR)
1430 device_printf(sc->sc_dev, "Tx underrun, "
1432 if (sc->sc_nerr == STGE_MAXERR)
1433 device_printf(sc->sc_dev, "too many errors; "
1434 "not reporting any more\n");
1438 /* Maximum/Late collisions, Re-enable Tx MAC. */
1439 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0)
1440 CSR_WRITE_4(sc, STGE_MACCtrl,
1441 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |
1451 * Interrupt service routine.
1454 stge_intr(void *arg)
1456 struct stge_softc *sc;
1461 sc = (struct stge_softc *)arg;
1466 #ifdef DEVICE_POLLING
1467 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1470 status = CSR_READ_2(sc, STGE_IntStatus);
1471 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0)
1474 /* Disable interrupts. */
1475 for (reinit = 0;;) {
1476 status = CSR_READ_2(sc, STGE_IntStatusAck);
1477 status &= sc->sc_IntEnable;
1480 /* Host interface errors. */
1481 if ((status & IS_HostError) != 0) {
1482 device_printf(sc->sc_dev,
1483 "Host interface error, resetting...\n");
1488 /* Receive interrupts. */
1489 if ((status & IS_RxDMAComplete) != 0) {
1491 if ((status & IS_RFDListEnd) != 0)
1492 CSR_WRITE_4(sc, STGE_DMACtrl,
1496 /* Transmit interrupts. */
1497 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0)
1500 /* Transmission errors.*/
1501 if ((status & IS_TxComplete) != 0) {
1502 if ((reinit = stge_tx_error(sc)) != 0)
1509 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1510 stge_init_locked(sc);
1513 /* Re-enable interrupts. */
1514 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1516 /* Try to get more packets going. */
1517 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1518 stge_start_locked(ifp);
1527 * Helper; handle transmit interrupts.
1530 stge_txeof(struct stge_softc *sc)
1533 struct stge_txdesc *txd;
1537 STGE_LOCK_ASSERT(sc);
1541 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1544 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1545 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD);
1548 * Go through our Tx list and free mbufs for those
1549 * frames which have been transmitted.
1551 for (cons = sc->sc_cdata.stge_tx_cons;;
1552 cons = (cons + 1) % STGE_TX_RING_CNT) {
1553 if (sc->sc_cdata.stge_tx_cnt <= 0)
1555 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control);
1556 if ((control & TFD_TFDDone) == 0)
1558 sc->sc_cdata.stge_tx_cnt--;
1559 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1561 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1562 BUS_DMASYNC_POSTWRITE);
1563 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap);
1565 /* Output counter is updated with statistics register */
1568 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q);
1569 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
1570 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1572 sc->sc_cdata.stge_tx_cons = cons;
1573 if (sc->sc_cdata.stge_tx_cnt == 0)
1574 sc->sc_watchdog_timer = 0;
1576 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1577 sc->sc_cdata.stge_tx_ring_map,
1578 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1581 static __inline void
1582 stge_discard_rxbuf(struct stge_softc *sc, int idx)
1584 struct stge_rfd *rfd;
1586 rfd = &sc->sc_rdata.stge_rx_ring[idx];
1587 rfd->rfd_status = 0;
1590 #ifndef __NO_STRICT_ALIGNMENT
1592 * It seems that TC9021's DMA engine has alignment restrictions in
1593 * DMA scatter operations. The first DMA segment has no address
1594 * alignment restrictins but the rest should be aligned on 4(?) bytes
1595 * boundary. Otherwise it would corrupt random memory. Since we don't
1596 * know which one is used for the first segment in advance we simply
1597 * don't align at all.
1598 * To avoid copying over an entire frame to align, we allocate a new
1599 * mbuf and copy ethernet header to the new mbuf. The new mbuf is
1600 * prepended into the existing mbuf chain.
1602 static __inline struct mbuf *
1603 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m)
1608 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
1609 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
1610 m->m_data += ETHER_HDR_LEN;
1613 MGETHDR(n, M_NOWAIT, MT_DATA);
1615 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
1616 m->m_data += ETHER_HDR_LEN;
1617 m->m_len -= ETHER_HDR_LEN;
1618 n->m_len = ETHER_HDR_LEN;
1619 M_MOVE_PKTHDR(n, m);
1632 * Helper; handle receive interrupts.
1635 stge_rxeof(struct stge_softc *sc)
1638 struct stge_rxdesc *rxd;
1639 struct mbuf *mp, *m;
1642 int cons, prog, rx_npkts;
1644 STGE_LOCK_ASSERT(sc);
1649 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1650 sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD);
1653 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT;
1654 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) {
1655 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status);
1656 status = RFD_RxStatus(status64);
1657 if ((status & RFD_RFDDone) == 0)
1659 #ifdef DEVICE_POLLING
1660 if (ifp->if_capenable & IFCAP_POLLING) {
1661 if (sc->sc_cdata.stge_rxcycles <= 0)
1663 sc->sc_cdata.stge_rxcycles--;
1667 rxd = &sc->sc_cdata.stge_rxdesc[cons];
1671 * If the packet had an error, drop it. Note we count
1672 * the error later in the periodic stats update.
1674 if ((status & RFD_FrameEnd) != 0 && (status &
1675 (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
1676 RFD_RxAlignmentError | RFD_RxFCSError |
1677 RFD_RxLengthError)) != 0) {
1678 stge_discard_rxbuf(sc, cons);
1679 if (sc->sc_cdata.stge_rxhead != NULL) {
1680 m_freem(sc->sc_cdata.stge_rxhead);
1681 STGE_RXCHAIN_RESET(sc);
1686 * Add a new receive buffer to the ring.
1688 if (stge_newbuf(sc, cons) != 0) {
1689 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1690 stge_discard_rxbuf(sc, cons);
1691 if (sc->sc_cdata.stge_rxhead != NULL) {
1692 m_freem(sc->sc_cdata.stge_rxhead);
1693 STGE_RXCHAIN_RESET(sc);
1698 if ((status & RFD_FrameEnd) != 0)
1699 mp->m_len = RFD_RxDMAFrameLen(status) -
1700 sc->sc_cdata.stge_rxlen;
1701 sc->sc_cdata.stge_rxlen += mp->m_len;
1704 if (sc->sc_cdata.stge_rxhead == NULL) {
1705 sc->sc_cdata.stge_rxhead = mp;
1706 sc->sc_cdata.stge_rxtail = mp;
1708 mp->m_flags &= ~M_PKTHDR;
1709 sc->sc_cdata.stge_rxtail->m_next = mp;
1710 sc->sc_cdata.stge_rxtail = mp;
1713 if ((status & RFD_FrameEnd) != 0) {
1714 m = sc->sc_cdata.stge_rxhead;
1715 m->m_pkthdr.rcvif = ifp;
1716 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen;
1718 if (m->m_pkthdr.len > sc->sc_if_framesize) {
1720 STGE_RXCHAIN_RESET(sc);
1724 * Set the incoming checksum information for
1727 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1728 if ((status & RFD_IPDetected) != 0) {
1729 m->m_pkthdr.csum_flags |=
1731 if ((status & RFD_IPError) == 0)
1732 m->m_pkthdr.csum_flags |=
1735 if (((status & RFD_TCPDetected) != 0 &&
1736 (status & RFD_TCPError) == 0) ||
1737 ((status & RFD_UDPDetected) != 0 &&
1738 (status & RFD_UDPError) == 0)) {
1739 m->m_pkthdr.csum_flags |=
1740 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1741 m->m_pkthdr.csum_data = 0xffff;
1745 #ifndef __NO_STRICT_ALIGNMENT
1746 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) {
1747 if ((m = stge_fixup_rx(sc, m)) == NULL) {
1748 STGE_RXCHAIN_RESET(sc);
1753 /* Check for VLAN tagged packets. */
1754 if ((status & RFD_VLANDetected) != 0 &&
1755 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
1756 m->m_pkthdr.ether_vtag = RFD_TCI(status64);
1757 m->m_flags |= M_VLANTAG;
1762 (*ifp->if_input)(ifp, m);
1766 STGE_RXCHAIN_RESET(sc);
1771 /* Update the consumer index. */
1772 sc->sc_cdata.stge_rx_cons = cons;
1773 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1774 sc->sc_cdata.stge_rx_ring_map,
1775 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1780 #ifdef DEVICE_POLLING
1782 stge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1784 struct stge_softc *sc;
1791 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1796 sc->sc_cdata.stge_rxcycles = count;
1797 rx_npkts = stge_rxeof(sc);
1800 if (cmd == POLL_AND_CHECK_STATUS) {
1801 status = CSR_READ_2(sc, STGE_IntStatus);
1802 status &= sc->sc_IntEnable;
1804 if ((status & IS_HostError) != 0) {
1805 device_printf(sc->sc_dev,
1806 "Host interface error, resetting...\n");
1807 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1808 stge_init_locked(sc);
1810 if ((status & IS_TxComplete) != 0) {
1811 if (stge_tx_error(sc) != 0) {
1812 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1813 stge_init_locked(sc);
1819 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1820 stge_start_locked(ifp);
1825 #endif /* DEVICE_POLLING */
1830 * One second timer, used to tick the MII.
1833 stge_tick(void *arg)
1835 struct stge_softc *sc;
1836 struct mii_data *mii;
1838 sc = (struct stge_softc *)arg;
1840 STGE_LOCK_ASSERT(sc);
1842 mii = device_get_softc(sc->sc_miibus);
1845 /* Update statistics counters. */
1846 stge_stats_update(sc);
1849 * Relcaim any pending Tx descriptors to release mbufs in a
1850 * timely manner as we don't generate Tx completion interrupts
1851 * for every frame. This limits the delay to a maximum of one
1854 if (sc->sc_cdata.stge_tx_cnt != 0)
1859 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
1863 * stge_stats_update:
1865 * Read the TC9021 statistics counters.
1868 stge_stats_update(struct stge_softc *sc)
1872 STGE_LOCK_ASSERT(sc);
1876 CSR_READ_4(sc,STGE_OctetRcvOk);
1878 if_inc_counter(ifp, IFCOUNTER_IPACKETS, CSR_READ_4(sc, STGE_FramesRcvdOk));
1880 if_inc_counter(ifp, IFCOUNTER_IERRORS, CSR_READ_2(sc, STGE_FramesLostRxErrors));
1882 CSR_READ_4(sc, STGE_OctetXmtdOk);
1884 if_inc_counter(ifp, IFCOUNTER_OPACKETS, CSR_READ_4(sc, STGE_FramesXmtdOk));
1886 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1887 CSR_READ_4(sc, STGE_LateCollisions) +
1888 CSR_READ_4(sc, STGE_MultiColFrames) +
1889 CSR_READ_4(sc, STGE_SingleColFrames));
1891 if_inc_counter(ifp, IFCOUNTER_OERRORS,
1892 CSR_READ_2(sc, STGE_FramesAbortXSColls) +
1893 CSR_READ_2(sc, STGE_FramesWEXDeferal));
1899 * Perform a soft reset on the TC9021.
1902 stge_reset(struct stge_softc *sc, uint32_t how)
1908 STGE_LOCK_ASSERT(sc);
1911 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1914 ac |= AC_TxReset | AC_FIFO;
1918 ac |= AC_RxReset | AC_FIFO;
1921 case STGE_RESET_FULL:
1924 * Only assert RstOut if we're fiber. We need GMII clocks
1925 * to be present in order for the reset to complete on fiber
1928 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset |
1929 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
1930 (sc->sc_usefiber ? AC_RstOut : 0);
1934 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1936 /* Account for reset problem at 10Mbps. */
1939 for (i = 0; i < STGE_TIMEOUT; i++) {
1940 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1945 if (i == STGE_TIMEOUT)
1946 device_printf(sc->sc_dev, "reset failed to complete\n");
1948 /* Set LED, from Linux IPG driver. */
1949 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1950 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1);
1951 if ((sc->sc_led & 0x01) != 0)
1953 if ((sc->sc_led & 0x03) != 0)
1954 ac |= AC_LEDModeBit1;
1955 if ((sc->sc_led & 0x08) != 0)
1957 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1959 /* Set PHY, from Linux IPG driver */
1960 v = CSR_READ_1(sc, STGE_PhySet);
1961 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet);
1962 v |= ((sc->sc_led & 0x70) >> 4);
1963 CSR_WRITE_1(sc, STGE_PhySet, v);
1967 * stge_init: [ ifnet interface function ]
1969 * Initialize the interface.
1972 stge_init(void *xsc)
1974 struct stge_softc *sc;
1976 sc = (struct stge_softc *)xsc;
1978 stge_init_locked(sc);
1983 stge_init_locked(struct stge_softc *sc)
1986 struct mii_data *mii;
1991 STGE_LOCK_ASSERT(sc);
1994 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1996 mii = device_get_softc(sc->sc_miibus);
1999 * Cancel any pending I/O.
2004 * Reset the chip to a known state.
2006 stge_reset(sc, STGE_RESET_FULL);
2008 /* Init descriptors. */
2009 error = stge_init_rx_ring(sc);
2011 device_printf(sc->sc_dev,
2012 "initialization failed: no memory for rx buffers\n");
2016 stge_init_tx_ring(sc);
2018 /* Set the station address. */
2019 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2020 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
2021 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
2022 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
2025 * Set the statistics masks. Disable all the RMON stats,
2026 * and disable selected stats in the non-RMON stats registers.
2028 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
2029 CSR_WRITE_4(sc, STGE_StatisticsMask,
2030 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
2031 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
2032 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
2035 /* Set up the receive filter. */
2036 stge_set_filter(sc);
2037 /* Program multicast filter. */
2041 * Give the transmit and receive ring to the chip.
2043 CSR_WRITE_4(sc, STGE_TFDListPtrHi,
2044 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0)));
2045 CSR_WRITE_4(sc, STGE_TFDListPtrLo,
2046 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0)));
2048 CSR_WRITE_4(sc, STGE_RFDListPtrHi,
2049 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0)));
2050 CSR_WRITE_4(sc, STGE_RFDListPtrLo,
2051 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0)));
2054 * Initialize the Tx auto-poll period. It's OK to make this number
2055 * large (255 is the max, but we use 127) -- we explicitly kick the
2056 * transmit engine when there's actually a packet.
2058 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2060 /* ..and the Rx auto-poll period. */
2061 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2063 /* Initialize the Tx start threshold. */
2064 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
2066 /* Rx DMA thresholds, from Linux */
2067 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
2068 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
2070 /* Rx early threhold, from Linux */
2071 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
2073 /* Tx DMA thresholds, from Linux */
2074 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
2075 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
2078 * Initialize the Rx DMA interrupt control register. We
2079 * request an interrupt after every incoming packet, but
2080 * defer it for sc_rxint_dmawait us. When the number of
2081 * interrupts pending reaches STGE_RXINT_NFRAME, we stop
2082 * deferring the interrupt, and signal it immediately.
2084 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
2085 RDIC_RxFrameCount(sc->sc_rxint_nframe) |
2086 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait)));
2089 * Initialize the interrupt mask.
2091 sc->sc_IntEnable = IS_HostError | IS_TxComplete |
2092 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
2093 #ifdef DEVICE_POLLING
2094 /* Disable interrupts if we are polling. */
2095 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
2096 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2099 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2102 * Configure the DMA engine.
2103 * XXX Should auto-tune TxBurstLimit.
2105 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3));
2108 * Send a PAUSE frame when we reach 29,696 bytes in the Rx
2109 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes
2112 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
2113 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
2116 * Set the maximum frame size.
2118 sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2119 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize);
2122 * Initialize MacCtrl -- do it before setting the media,
2123 * as setting the media will actually program the register.
2125 * Note: We have to poke the IFS value before poking
2128 /* Tx/Rx MAC should be disabled before programming IFS.*/
2129 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit));
2131 stge_vlan_setup(sc);
2133 if (sc->sc_rev >= 6) { /* >= B.2 */
2134 /* Multi-frag frame bug work-around. */
2135 CSR_WRITE_2(sc, STGE_DebugCtrl,
2136 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
2138 /* Tx Poll Now bug work-around. */
2139 CSR_WRITE_2(sc, STGE_DebugCtrl,
2140 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
2141 /* Tx Poll Now bug work-around. */
2142 CSR_WRITE_2(sc, STGE_DebugCtrl,
2143 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
2146 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2147 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
2148 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2150 * It seems that transmitting frames without checking the state of
2151 * Rx/Tx MAC wedge the hardware.
2158 * Set the current media.
2163 * Start the one second MII clock.
2165 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
2170 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2171 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2175 device_printf(sc->sc_dev, "interface not running\n");
2179 stge_vlan_setup(struct stge_softc *sc)
2186 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl
2187 * MC_AutoVLANuntagging bit.
2188 * MC_AutoVLANtagging bit selects which VLAN source to use
2189 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert
2190 * bit has priority over MC_AutoVLANtagging bit. So we always
2191 * use TFC instead of STGE_VLANTag register.
2193 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2194 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2195 v |= MC_AutoVLANuntagging;
2197 v &= ~MC_AutoVLANuntagging;
2198 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2202 * Stop transmission on the interface.
2205 stge_stop(struct stge_softc *sc)
2208 struct stge_txdesc *txd;
2209 struct stge_rxdesc *rxd;
2213 STGE_LOCK_ASSERT(sc);
2215 * Stop the one second clock.
2217 callout_stop(&sc->sc_tick_ch);
2218 sc->sc_watchdog_timer = 0;
2221 * Disable interrupts.
2223 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2226 * Stop receiver, transmitter, and stats update.
2230 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2231 v |= MC_StatisticsDisable;
2232 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2235 * Stop the transmit and receive DMA.
2238 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
2239 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
2240 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
2241 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
2244 * Free RX and TX mbufs still in the queues.
2246 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2247 rxd = &sc->sc_cdata.stge_rxdesc[i];
2248 if (rxd->rx_m != NULL) {
2249 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag,
2250 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2251 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag,
2257 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2258 txd = &sc->sc_cdata.stge_txdesc[i];
2259 if (txd->tx_m != NULL) {
2260 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag,
2261 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2262 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag,
2270 * Mark the interface down and cancel the watchdog timer.
2273 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2278 stge_start_tx(struct stge_softc *sc)
2283 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2284 if ((v & MC_TxEnabled) != 0)
2287 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2288 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2289 for (i = STGE_TIMEOUT; i > 0; i--) {
2291 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2292 if ((v & MC_TxEnabled) != 0)
2296 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n");
2300 stge_start_rx(struct stge_softc *sc)
2305 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2306 if ((v & MC_RxEnabled) != 0)
2309 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2310 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2311 for (i = STGE_TIMEOUT; i > 0; i--) {
2313 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2314 if ((v & MC_RxEnabled) != 0)
2318 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n");
2322 stge_stop_tx(struct stge_softc *sc)
2327 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2328 if ((v & MC_TxEnabled) == 0)
2331 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2332 for (i = STGE_TIMEOUT; i > 0; i--) {
2334 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2335 if ((v & MC_TxEnabled) == 0)
2339 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n");
2343 stge_stop_rx(struct stge_softc *sc)
2348 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2349 if ((v & MC_RxEnabled) == 0)
2352 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2353 for (i = STGE_TIMEOUT; i > 0; i--) {
2355 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2356 if ((v & MC_RxEnabled) == 0)
2360 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n");
2364 stge_init_tx_ring(struct stge_softc *sc)
2366 struct stge_ring_data *rd;
2367 struct stge_txdesc *txd;
2371 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq);
2372 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq);
2374 sc->sc_cdata.stge_tx_prod = 0;
2375 sc->sc_cdata.stge_tx_cons = 0;
2376 sc->sc_cdata.stge_tx_cnt = 0;
2379 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ);
2380 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2381 if (i == (STGE_TX_RING_CNT - 1))
2382 addr = STGE_TX_RING_ADDR(sc, 0);
2384 addr = STGE_TX_RING_ADDR(sc, i + 1);
2385 rd->stge_tx_ring[i].tfd_next = htole64(addr);
2386 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone);
2387 txd = &sc->sc_cdata.stge_txdesc[i];
2388 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
2391 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
2392 sc->sc_cdata.stge_tx_ring_map,
2393 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2398 stge_init_rx_ring(struct stge_softc *sc)
2400 struct stge_ring_data *rd;
2404 sc->sc_cdata.stge_rx_cons = 0;
2405 STGE_RXCHAIN_RESET(sc);
2408 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ);
2409 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2410 if (stge_newbuf(sc, i) != 0)
2412 if (i == (STGE_RX_RING_CNT - 1))
2413 addr = STGE_RX_RING_ADDR(sc, 0);
2415 addr = STGE_RX_RING_ADDR(sc, i + 1);
2416 rd->stge_rx_ring[i].rfd_next = htole64(addr);
2417 rd->stge_rx_ring[i].rfd_status = 0;
2420 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
2421 sc->sc_cdata.stge_rx_ring_map,
2422 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2430 * Add a receive buffer to the indicated descriptor.
2433 stge_newbuf(struct stge_softc *sc, int idx)
2435 struct stge_rxdesc *rxd;
2436 struct stge_rfd *rfd;
2438 bus_dma_segment_t segs[1];
2442 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2445 m->m_len = m->m_pkthdr.len = MCLBYTES;
2447 * The hardware requires 4bytes aligned DMA address when JUMBO
2450 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN))
2451 m_adj(m, ETHER_ALIGN);
2453 if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag,
2454 sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2458 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2460 rxd = &sc->sc_cdata.stge_rxdesc[idx];
2461 if (rxd->rx_m != NULL) {
2462 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2463 BUS_DMASYNC_POSTREAD);
2464 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap);
2466 map = rxd->rx_dmamap;
2467 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap;
2468 sc->sc_cdata.stge_rx_sparemap = map;
2469 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2470 BUS_DMASYNC_PREREAD);
2473 rfd = &sc->sc_rdata.stge_rx_ring[idx];
2474 rfd->rfd_frag.frag_word0 =
2475 htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len));
2476 rfd->rfd_status = 0;
2484 * Set up the receive filter.
2487 stge_set_filter(struct stge_softc *sc)
2492 STGE_LOCK_ASSERT(sc);
2496 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2497 mode |= RM_ReceiveUnicast;
2498 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2499 mode |= RM_ReceiveBroadcast;
2501 mode &= ~RM_ReceiveBroadcast;
2502 if ((ifp->if_flags & IFF_PROMISC) != 0)
2503 mode |= RM_ReceiveAllFrames;
2505 mode &= ~RM_ReceiveAllFrames;
2507 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2511 stge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
2513 uint32_t crc, *mchash = arg;
2515 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
2516 /* Just want the 6 least significant bits. */
2518 /* Set the corresponding bit in the hash table. */
2519 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2525 stge_set_multi(struct stge_softc *sc)
2532 STGE_LOCK_ASSERT(sc);
2536 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2537 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2538 if ((ifp->if_flags & IFF_PROMISC) != 0)
2539 mode |= RM_ReceiveAllFrames;
2540 else if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2541 mode |= RM_ReceiveMulticast;
2542 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2546 /* clear existing filters. */
2547 CSR_WRITE_4(sc, STGE_HashTable0, 0);
2548 CSR_WRITE_4(sc, STGE_HashTable1, 0);
2551 * Set up the multicast address filter by passing all multicast
2552 * addresses through a CRC generator, and then using the low-order
2553 * 6 bits as an index into the 64 bit multicast hash table. The
2554 * high order bits select the register, while the rest of the bits
2555 * select the bit within the register.
2557 bzero(mchash, sizeof(mchash));
2558 count = if_foreach_llmaddr(ifp, stge_hash_maddr, mchash);
2560 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames);
2562 mode |= RM_ReceiveMulticastHash;
2564 mode &= ~RM_ReceiveMulticastHash;
2566 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
2567 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
2568 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2572 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2578 value = *(int *)arg1;
2579 error = sysctl_handle_int(oidp, &value, 0, req);
2580 if (error || !req->newptr)
2582 if (value < low || value > high)
2584 *(int *)arg1 = value;
2590 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS)
2592 return (sysctl_int_range(oidp, arg1, arg2, req,
2593 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX));
2597 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS)
2599 return (sysctl_int_range(oidp, arg1, arg2, req,
2600 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX));