1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
40 * Device driver for the Sundance Tech. TC9021 10/100/1000
41 * Ethernet controller.
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD$");
47 #ifdef HAVE_KERNEL_OPTION_HEADERS
48 #include "opt_device_polling.h"
51 #include <sys/param.h>
52 #include <sys/systm.h>
53 #include <sys/endian.h>
55 #include <sys/malloc.h>
56 #include <sys/kernel.h>
57 #include <sys/module.h>
58 #include <sys/socket.h>
59 #include <sys/sockio.h>
60 #include <sys/sysctl.h>
61 #include <sys/taskqueue.h>
64 #include <net/ethernet.h>
66 #include <net/if_dl.h>
67 #include <net/if_media.h>
68 #include <net/if_types.h>
69 #include <net/if_vlan_var.h>
71 #include <machine/bus.h>
72 #include <machine/resource.h>
76 #include <dev/mii/mii.h>
77 #include <dev/mii/miivar.h>
79 #include <dev/pci/pcireg.h>
80 #include <dev/pci/pcivar.h>
82 #include <dev/stge/if_stgereg.h>
84 #define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
86 MODULE_DEPEND(stge, pci, 1, 1, 1);
87 MODULE_DEPEND(stge, ether, 1, 1, 1);
88 MODULE_DEPEND(stge, miibus, 1, 1, 1);
90 /* "device miibus" required. See GENERIC if you get errors here. */
91 #include "miibus_if.h"
94 * Devices supported by this driver.
96 static struct stge_product {
97 uint16_t stge_vendorid;
98 uint16_t stge_deviceid;
99 const char *stge_name;
100 } stge_products[] = {
101 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023,
102 "Sundance ST-1023 Gigabit Ethernet" },
104 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021,
105 "Sundance ST-2021 Gigabit Ethernet" },
107 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021,
108 "Tamarack TC9021 Gigabit Ethernet" },
110 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT,
111 "Tamarack TC9021 Gigabit Ethernet" },
114 * The Sundance sample boards use the Sundance vendor ID,
115 * but the Tamarack product ID.
117 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021,
118 "Sundance TC9021 Gigabit Ethernet" },
120 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT,
121 "Sundance TC9021 Gigabit Ethernet" },
123 { VENDOR_DLINK, DEVICEID_DLINK_DL4000,
124 "D-Link DL-4000 Gigabit Ethernet" },
126 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021,
127 "Antares Gigabit Ethernet" }
130 static int stge_probe(device_t);
131 static int stge_attach(device_t);
132 static int stge_detach(device_t);
133 static int stge_shutdown(device_t);
134 static int stge_suspend(device_t);
135 static int stge_resume(device_t);
137 static int stge_encap(struct stge_softc *, struct mbuf **);
138 static void stge_start(struct ifnet *);
139 static void stge_start_locked(struct ifnet *);
140 static void stge_watchdog(struct stge_softc *);
141 static int stge_ioctl(struct ifnet *, u_long, caddr_t);
142 static void stge_init(void *);
143 static void stge_init_locked(struct stge_softc *);
144 static void stge_vlan_setup(struct stge_softc *);
145 static void stge_stop(struct stge_softc *);
146 static void stge_start_tx(struct stge_softc *);
147 static void stge_start_rx(struct stge_softc *);
148 static void stge_stop_tx(struct stge_softc *);
149 static void stge_stop_rx(struct stge_softc *);
151 static void stge_reset(struct stge_softc *, uint32_t);
152 static int stge_eeprom_wait(struct stge_softc *);
153 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *);
154 static void stge_tick(void *);
155 static void stge_stats_update(struct stge_softc *);
156 static void stge_set_filter(struct stge_softc *);
157 static void stge_set_multi(struct stge_softc *);
159 static void stge_link_task(void *, int);
160 static void stge_intr(void *);
161 static __inline int stge_tx_error(struct stge_softc *);
162 static void stge_txeof(struct stge_softc *);
163 static int stge_rxeof(struct stge_softc *);
164 static __inline void stge_discard_rxbuf(struct stge_softc *, int);
165 static int stge_newbuf(struct stge_softc *, int);
166 #ifndef __NO_STRICT_ALIGNMENT
167 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *);
170 static void stge_mii_sync(struct stge_softc *);
171 static void stge_mii_send(struct stge_softc *, uint32_t, int);
172 static int stge_mii_readreg(struct stge_softc *, struct stge_mii_frame *);
173 static int stge_mii_writereg(struct stge_softc *, struct stge_mii_frame *);
174 static int stge_miibus_readreg(device_t, int, int);
175 static int stge_miibus_writereg(device_t, int, int, int);
176 static void stge_miibus_statchg(device_t);
177 static int stge_mediachange(struct ifnet *);
178 static void stge_mediastatus(struct ifnet *, struct ifmediareq *);
180 static void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
181 static int stge_dma_alloc(struct stge_softc *);
182 static void stge_dma_free(struct stge_softc *);
183 static void stge_dma_wait(struct stge_softc *);
184 static void stge_init_tx_ring(struct stge_softc *);
185 static int stge_init_rx_ring(struct stge_softc *);
186 #ifdef DEVICE_POLLING
187 static int stge_poll(struct ifnet *, enum poll_cmd, int);
190 static void stge_setwol(struct stge_softc *);
191 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
192 static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS);
193 static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS);
195 static device_method_t stge_methods[] = {
196 /* Device interface */
197 DEVMETHOD(device_probe, stge_probe),
198 DEVMETHOD(device_attach, stge_attach),
199 DEVMETHOD(device_detach, stge_detach),
200 DEVMETHOD(device_shutdown, stge_shutdown),
201 DEVMETHOD(device_suspend, stge_suspend),
202 DEVMETHOD(device_resume, stge_resume),
205 DEVMETHOD(miibus_readreg, stge_miibus_readreg),
206 DEVMETHOD(miibus_writereg, stge_miibus_writereg),
207 DEVMETHOD(miibus_statchg, stge_miibus_statchg),
213 static driver_t stge_driver = {
216 sizeof(struct stge_softc)
219 static devclass_t stge_devclass;
221 DRIVER_MODULE(stge, pci, stge_driver, stge_devclass, 0, 0);
222 DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, 0, 0);
224 static struct resource_spec stge_res_spec_io[] = {
225 { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE },
226 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
230 static struct resource_spec stge_res_spec_mem[] = {
231 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE },
232 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
237 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) | (x))
239 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) & ~(x))
242 * Sync the PHYs by setting data bit and strobing the clock 32 times.
245 stge_mii_sync(struct stge_softc *sc)
249 MII_SET(PC_MgmtDir | PC_MgmtData);
251 for (i = 0; i < 32; i++) {
260 * Clock a series of bits through the MII.
263 stge_mii_send(struct stge_softc *sc, uint32_t bits, int cnt)
269 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
271 MII_SET(PC_MgmtData);
273 MII_CLR(PC_MgmtData);
282 * Read an PHY register through the MII.
285 stge_mii_readreg(struct stge_softc *sc, struct stge_mii_frame *frame)
290 * Set up frame for RX.
292 frame->mii_stdelim = STGE_MII_STARTDELIM;
293 frame->mii_opcode = STGE_MII_READOP;
294 frame->mii_turnaround = 0;
297 CSR_WRITE_1(sc, STGE_PhyCtrl, 0 | sc->sc_PhyCtrl);
306 * Send command/address info.
308 stge_mii_send(sc, frame->mii_stdelim, 2);
309 stge_mii_send(sc, frame->mii_opcode, 2);
310 stge_mii_send(sc, frame->mii_phyaddr, 5);
311 stge_mii_send(sc, frame->mii_regaddr, 5);
317 MII_CLR((PC_MgmtClk | PC_MgmtData));
325 ack = CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData;
330 * Now try reading data bits. If the ack failed, we still
331 * need to clock through 16 cycles to keep the PHY(s) in sync.
334 for(i = 0; i < 16; i++) {
343 for (i = 0x8000; i; i >>= 1) {
347 if (CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData)
348 frame->mii_data |= i;
367 * Write to a PHY register through the MII.
370 stge_mii_writereg(struct stge_softc *sc, struct stge_mii_frame *frame)
374 * Set up frame for TX.
376 frame->mii_stdelim = STGE_MII_STARTDELIM;
377 frame->mii_opcode = STGE_MII_WRITEOP;
378 frame->mii_turnaround = STGE_MII_TURNAROUND;
381 * Turn on data output.
387 stge_mii_send(sc, frame->mii_stdelim, 2);
388 stge_mii_send(sc, frame->mii_opcode, 2);
389 stge_mii_send(sc, frame->mii_phyaddr, 5);
390 stge_mii_send(sc, frame->mii_regaddr, 5);
391 stge_mii_send(sc, frame->mii_turnaround, 2);
392 stge_mii_send(sc, frame->mii_data, 16);
409 * sc_miibus_readreg: [mii interface function]
411 * Read a PHY register on the MII of the TC9021.
414 stge_miibus_readreg(device_t dev, int phy, int reg)
416 struct stge_softc *sc;
417 struct stge_mii_frame frame;
420 sc = device_get_softc(dev);
422 if (reg == STGE_PhyCtrl) {
423 /* XXX allow ip1000phy read STGE_PhyCtrl register. */
425 error = CSR_READ_1(sc, STGE_PhyCtrl);
429 bzero(&frame, sizeof(frame));
430 frame.mii_phyaddr = phy;
431 frame.mii_regaddr = reg;
434 error = stge_mii_readreg(sc, &frame);
438 /* Don't show errors for PHY probe request */
440 device_printf(sc->sc_dev, "phy read fail\n");
443 return (frame.mii_data);
447 * stge_miibus_writereg: [mii interface function]
449 * Write a PHY register on the MII of the TC9021.
452 stge_miibus_writereg(device_t dev, int phy, int reg, int val)
454 struct stge_softc *sc;
455 struct stge_mii_frame frame;
458 sc = device_get_softc(dev);
460 bzero(&frame, sizeof(frame));
461 frame.mii_phyaddr = phy;
462 frame.mii_regaddr = reg;
463 frame.mii_data = val;
466 error = stge_mii_writereg(sc, &frame);
470 device_printf(sc->sc_dev, "phy write fail\n");
475 * stge_miibus_statchg: [mii interface function]
477 * Callback from MII layer when media changes.
480 stge_miibus_statchg(device_t dev)
482 struct stge_softc *sc;
484 sc = device_get_softc(dev);
485 taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task);
489 * stge_mediastatus: [ifmedia interface function]
491 * Get the current interface media status.
494 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
496 struct stge_softc *sc;
497 struct mii_data *mii;
500 mii = device_get_softc(sc->sc_miibus);
503 ifmr->ifm_status = mii->mii_media_status;
504 ifmr->ifm_active = mii->mii_media_active;
508 * stge_mediachange: [ifmedia interface function]
510 * Set hardware to newly-selected media.
513 stge_mediachange(struct ifnet *ifp)
515 struct stge_softc *sc;
516 struct mii_data *mii;
519 mii = device_get_softc(sc->sc_miibus);
526 stge_eeprom_wait(struct stge_softc *sc)
530 for (i = 0; i < STGE_TIMEOUT; i++) {
532 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
541 * Read data from the serial EEPROM.
544 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
547 if (stge_eeprom_wait(sc))
548 device_printf(sc->sc_dev, "EEPROM failed to come ready\n");
550 CSR_WRITE_2(sc, STGE_EepromCtrl,
551 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
552 if (stge_eeprom_wait(sc))
553 device_printf(sc->sc_dev, "EEPROM read timed out\n");
554 *data = CSR_READ_2(sc, STGE_EepromData);
559 stge_probe(device_t dev)
561 struct stge_product *sp;
563 uint16_t vendor, devid;
565 vendor = pci_get_vendor(dev);
566 devid = pci_get_device(dev);
568 for (i = 0; i < sizeof(stge_products)/sizeof(stge_products[0]);
570 if (vendor == sp->stge_vendorid &&
571 devid == sp->stge_deviceid) {
572 device_set_desc(dev, sp->stge_name);
573 return (BUS_PROBE_DEFAULT);
581 stge_attach(device_t dev)
583 struct stge_softc *sc;
585 uint8_t enaddr[ETHER_ADDR_LEN];
591 sc = device_get_softc(dev);
594 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
596 mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF);
597 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
598 TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc);
603 pci_enable_busmaster(dev);
604 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
605 val = pci_read_config(dev, PCIR_BAR(1), 4);
606 if ((val & 0x01) != 0)
607 sc->sc_spec = stge_res_spec_mem;
609 val = pci_read_config(dev, PCIR_BAR(0), 4);
610 if ((val & 0x01) == 0) {
611 device_printf(sc->sc_dev, "couldn't locate IO BAR\n");
615 sc->sc_spec = stge_res_spec_io;
617 error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res);
619 device_printf(dev, "couldn't allocate %s resources\n",
620 sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O");
623 sc->sc_rev = pci_get_revid(dev);
625 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
626 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
627 "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0,
628 sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe");
630 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
631 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
632 "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0,
633 sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait");
635 /* Pull in device tunables. */
636 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
637 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
638 "rxint_nframe", &sc->sc_rxint_nframe);
640 if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN ||
641 sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) {
642 device_printf(dev, "rxint_nframe value out of range; "
643 "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT);
644 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
648 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
649 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
650 "rxint_dmawait", &sc->sc_rxint_dmawait);
652 if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN ||
653 sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) {
654 device_printf(dev, "rxint_dmawait value out of range; "
655 "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT);
656 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
660 if ((error = stge_dma_alloc(sc) != 0))
664 * Determine if we're copper or fiber. It affects how we
667 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
672 /* Load LED configuration from EEPROM. */
673 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led);
676 * Reset the chip to a known state.
679 stge_reset(sc, STGE_RESET_FULL);
683 * Reading the station address from the EEPROM doesn't seem
684 * to work, at least on my sample boards. Instead, since
685 * the reset sequence does AutoInit, read it from the station
686 * address registers. For Sundance 1023 you can only read it
689 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) {
692 v = CSR_READ_2(sc, STGE_StationAddress0);
693 enaddr[0] = v & 0xff;
695 v = CSR_READ_2(sc, STGE_StationAddress1);
696 enaddr[2] = v & 0xff;
698 v = CSR_READ_2(sc, STGE_StationAddress2);
699 enaddr[4] = v & 0xff;
703 uint16_t myaddr[ETHER_ADDR_LEN / 2];
704 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
705 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i,
707 myaddr[i] = le16toh(myaddr[i]);
709 bcopy(myaddr, enaddr, sizeof(enaddr));
713 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
715 device_printf(sc->sc_dev, "failed to if_alloc()\n");
721 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
722 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
723 ifp->if_ioctl = stge_ioctl;
724 ifp->if_start = stge_start;
725 ifp->if_init = stge_init;
726 ifp->if_mtu = ETHERMTU;
727 ifp->if_snd.ifq_drv_maxlen = STGE_TX_RING_CNT - 1;
728 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
729 IFQ_SET_READY(&ifp->if_snd);
730 /* Revision B3 and earlier chips have checksum bug. */
731 if (sc->sc_rev >= 0x0c) {
732 ifp->if_hwassist = STGE_CSUM_FEATURES;
733 ifp->if_capabilities = IFCAP_HWCSUM;
735 ifp->if_hwassist = 0;
736 ifp->if_capabilities = 0;
738 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
739 ifp->if_capenable = ifp->if_capabilities;
742 * Read some important bits from the PhyCtrl register.
744 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
745 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
747 /* Set up MII bus. */
748 flags = MIIF_DOPAUSE | MIIF_FORCEPAUSE;
749 if (sc->sc_rev >= 0x40 && sc->sc_rev <= 0x4e)
750 flags |= MIIF_MACPRIV0;
751 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, stge_mediachange,
752 stge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
755 device_printf(sc->sc_dev, "attaching PHYs failed\n");
759 ether_ifattach(ifp, enaddr);
761 /* VLAN capability setup */
762 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
763 if (sc->sc_rev >= 0x0c)
764 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
765 ifp->if_capenable = ifp->if_capabilities;
766 #ifdef DEVICE_POLLING
767 ifp->if_capabilities |= IFCAP_POLLING;
770 * Tell the upper layer(s) we support long frames.
771 * Must appear after the call to ether_ifattach() because
772 * ether_ifattach() sets ifi_hdrlen to the default value.
774 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
777 * The manual recommends disabling early transmit, so we
778 * do. It's disabled anyway, if using IP checksumming,
779 * since the entire packet must be in the FIFO in order
780 * for the chip to perform the checksum.
782 sc->sc_txthresh = 0x0fff;
785 * Disable MWI if the PCI layer tells us to.
788 if ((cmd & PCIM_CMD_MWRICEN) == 0)
789 sc->sc_DMACtrl |= DMAC_MWIDisable;
794 error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE,
795 NULL, stge_intr, sc, &sc->sc_ih);
798 device_printf(sc->sc_dev, "couldn't set up IRQ\n");
811 stge_detach(device_t dev)
813 struct stge_softc *sc;
816 sc = device_get_softc(dev);
819 #ifdef DEVICE_POLLING
820 if (ifp && ifp->if_capenable & IFCAP_POLLING)
821 ether_poll_deregister(ifp);
823 if (device_is_attached(dev)) {
829 callout_drain(&sc->sc_tick_ch);
830 taskqueue_drain(taskqueue_swi, &sc->sc_link_task);
834 if (sc->sc_miibus != NULL) {
835 device_delete_child(dev, sc->sc_miibus);
836 sc->sc_miibus = NULL;
838 bus_generic_detach(dev);
847 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih);
850 bus_release_resources(dev, sc->sc_spec, sc->sc_res);
852 mtx_destroy(&sc->sc_mii_mtx);
853 mtx_destroy(&sc->sc_mtx);
858 struct stge_dmamap_arg {
859 bus_addr_t stge_busaddr;
863 stge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
865 struct stge_dmamap_arg *ctx;
870 ctx = (struct stge_dmamap_arg *)arg;
871 ctx->stge_busaddr = segs[0].ds_addr;
875 stge_dma_alloc(struct stge_softc *sc)
877 struct stge_dmamap_arg ctx;
878 struct stge_txdesc *txd;
879 struct stge_rxdesc *rxd;
882 /* create parent tag. */
883 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),/* parent */
884 1, 0, /* algnmnt, boundary */
885 STGE_DMA_MAXADDR, /* lowaddr */
886 BUS_SPACE_MAXADDR, /* highaddr */
887 NULL, NULL, /* filter, filterarg */
888 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
890 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
892 NULL, NULL, /* lockfunc, lockarg */
893 &sc->sc_cdata.stge_parent_tag);
895 device_printf(sc->sc_dev, "failed to create parent DMA tag\n");
898 /* create tag for Tx ring. */
899 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
900 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
901 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
902 BUS_SPACE_MAXADDR, /* highaddr */
903 NULL, NULL, /* filter, filterarg */
904 STGE_TX_RING_SZ, /* maxsize */
906 STGE_TX_RING_SZ, /* maxsegsize */
908 NULL, NULL, /* lockfunc, lockarg */
909 &sc->sc_cdata.stge_tx_ring_tag);
911 device_printf(sc->sc_dev,
912 "failed to allocate Tx ring DMA tag\n");
916 /* create tag for Rx ring. */
917 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
918 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
919 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
920 BUS_SPACE_MAXADDR, /* highaddr */
921 NULL, NULL, /* filter, filterarg */
922 STGE_RX_RING_SZ, /* maxsize */
924 STGE_RX_RING_SZ, /* maxsegsize */
926 NULL, NULL, /* lockfunc, lockarg */
927 &sc->sc_cdata.stge_rx_ring_tag);
929 device_printf(sc->sc_dev,
930 "failed to allocate Rx ring DMA tag\n");
934 /* create tag for Tx buffers. */
935 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
936 1, 0, /* algnmnt, boundary */
937 BUS_SPACE_MAXADDR, /* lowaddr */
938 BUS_SPACE_MAXADDR, /* highaddr */
939 NULL, NULL, /* filter, filterarg */
940 MCLBYTES * STGE_MAXTXSEGS, /* maxsize */
941 STGE_MAXTXSEGS, /* nsegments */
942 MCLBYTES, /* maxsegsize */
944 NULL, NULL, /* lockfunc, lockarg */
945 &sc->sc_cdata.stge_tx_tag);
947 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n");
951 /* create tag for Rx buffers. */
952 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
953 1, 0, /* algnmnt, boundary */
954 BUS_SPACE_MAXADDR, /* lowaddr */
955 BUS_SPACE_MAXADDR, /* highaddr */
956 NULL, NULL, /* filter, filterarg */
957 MCLBYTES, /* maxsize */
959 MCLBYTES, /* maxsegsize */
961 NULL, NULL, /* lockfunc, lockarg */
962 &sc->sc_cdata.stge_rx_tag);
964 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n");
968 /* allocate DMA'able memory and load the DMA map for Tx ring. */
969 error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag,
970 (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
971 &sc->sc_cdata.stge_tx_ring_map);
973 device_printf(sc->sc_dev,
974 "failed to allocate DMA'able memory for Tx ring\n");
978 ctx.stge_busaddr = 0;
979 error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag,
980 sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring,
981 STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
982 if (error != 0 || ctx.stge_busaddr == 0) {
983 device_printf(sc->sc_dev,
984 "failed to load DMA'able memory for Tx ring\n");
987 sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr;
989 /* allocate DMA'able memory and load the DMA map for Rx ring. */
990 error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag,
991 (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
992 &sc->sc_cdata.stge_rx_ring_map);
994 device_printf(sc->sc_dev,
995 "failed to allocate DMA'able memory for Rx ring\n");
999 ctx.stge_busaddr = 0;
1000 error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag,
1001 sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring,
1002 STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1003 if (error != 0 || ctx.stge_busaddr == 0) {
1004 device_printf(sc->sc_dev,
1005 "failed to load DMA'able memory for Rx ring\n");
1008 sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr;
1010 /* create DMA maps for Tx buffers. */
1011 for (i = 0; i < STGE_TX_RING_CNT; i++) {
1012 txd = &sc->sc_cdata.stge_txdesc[i];
1015 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0,
1018 device_printf(sc->sc_dev,
1019 "failed to create Tx dmamap\n");
1023 /* create DMA maps for Rx buffers. */
1024 if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
1025 &sc->sc_cdata.stge_rx_sparemap)) != 0) {
1026 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n");
1029 for (i = 0; i < STGE_RX_RING_CNT; i++) {
1030 rxd = &sc->sc_cdata.stge_rxdesc[i];
1033 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
1036 device_printf(sc->sc_dev,
1037 "failed to create Rx dmamap\n");
1047 stge_dma_free(struct stge_softc *sc)
1049 struct stge_txdesc *txd;
1050 struct stge_rxdesc *rxd;
1054 if (sc->sc_cdata.stge_tx_ring_tag) {
1055 if (sc->sc_cdata.stge_tx_ring_map)
1056 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag,
1057 sc->sc_cdata.stge_tx_ring_map);
1058 if (sc->sc_cdata.stge_tx_ring_map &&
1059 sc->sc_rdata.stge_tx_ring)
1060 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag,
1061 sc->sc_rdata.stge_tx_ring,
1062 sc->sc_cdata.stge_tx_ring_map);
1063 sc->sc_rdata.stge_tx_ring = NULL;
1064 sc->sc_cdata.stge_tx_ring_map = 0;
1065 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag);
1066 sc->sc_cdata.stge_tx_ring_tag = NULL;
1069 if (sc->sc_cdata.stge_rx_ring_tag) {
1070 if (sc->sc_cdata.stge_rx_ring_map)
1071 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag,
1072 sc->sc_cdata.stge_rx_ring_map);
1073 if (sc->sc_cdata.stge_rx_ring_map &&
1074 sc->sc_rdata.stge_rx_ring)
1075 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag,
1076 sc->sc_rdata.stge_rx_ring,
1077 sc->sc_cdata.stge_rx_ring_map);
1078 sc->sc_rdata.stge_rx_ring = NULL;
1079 sc->sc_cdata.stge_rx_ring_map = 0;
1080 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag);
1081 sc->sc_cdata.stge_rx_ring_tag = NULL;
1084 if (sc->sc_cdata.stge_tx_tag) {
1085 for (i = 0; i < STGE_TX_RING_CNT; i++) {
1086 txd = &sc->sc_cdata.stge_txdesc[i];
1087 if (txd->tx_dmamap) {
1088 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
1093 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
1094 sc->sc_cdata.stge_tx_tag = NULL;
1097 if (sc->sc_cdata.stge_rx_tag) {
1098 for (i = 0; i < STGE_RX_RING_CNT; i++) {
1099 rxd = &sc->sc_cdata.stge_rxdesc[i];
1100 if (rxd->rx_dmamap) {
1101 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
1106 if (sc->sc_cdata.stge_rx_sparemap) {
1107 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
1108 sc->sc_cdata.stge_rx_sparemap);
1109 sc->sc_cdata.stge_rx_sparemap = 0;
1111 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
1112 sc->sc_cdata.stge_rx_tag = NULL;
1115 if (sc->sc_cdata.stge_parent_tag) {
1116 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag);
1117 sc->sc_cdata.stge_parent_tag = NULL;
1124 * Make sure the interface is stopped at reboot time.
1127 stge_shutdown(device_t dev)
1130 return (stge_suspend(dev));
1134 stge_setwol(struct stge_softc *sc)
1139 STGE_LOCK_ASSERT(sc);
1142 v = CSR_READ_1(sc, STGE_WakeEvent);
1143 /* Disable all WOL bits. */
1144 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
1145 WE_WakeOnLanEnable);
1146 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1147 v |= WE_MagicPktEnable | WE_WakeOnLanEnable;
1148 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1149 /* Reset Tx and prevent transmission. */
1150 CSR_WRITE_4(sc, STGE_AsicCtrl,
1151 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset);
1153 * TC9021 automatically reset link speed to 100Mbps when it's put
1154 * into sleep so there is no need to try to resetting link speed.
1159 stge_suspend(device_t dev)
1161 struct stge_softc *sc;
1163 sc = device_get_softc(dev);
1167 sc->sc_suspended = 1;
1175 stge_resume(device_t dev)
1177 struct stge_softc *sc;
1181 sc = device_get_softc(dev);
1185 * Clear WOL bits, so special frames wouldn't interfere
1186 * normal Rx operation anymore.
1188 v = CSR_READ_1(sc, STGE_WakeEvent);
1189 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
1190 WE_WakeOnLanEnable);
1191 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1193 if (ifp->if_flags & IFF_UP)
1194 stge_init_locked(sc);
1196 sc->sc_suspended = 0;
1203 stge_dma_wait(struct stge_softc *sc)
1207 for (i = 0; i < STGE_TIMEOUT; i++) {
1209 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
1213 if (i == STGE_TIMEOUT)
1214 device_printf(sc->sc_dev, "DMA wait timed out\n");
1218 stge_encap(struct stge_softc *sc, struct mbuf **m_head)
1220 struct stge_txdesc *txd;
1221 struct stge_tfd *tfd;
1223 bus_dma_segment_t txsegs[STGE_MAXTXSEGS];
1224 int error, i, nsegs, si;
1225 uint64_t csum_flags, tfc;
1227 STGE_LOCK_ASSERT(sc);
1229 if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL)
1232 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1233 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1234 if (error == EFBIG) {
1235 m = m_collapse(*m_head, M_DONTWAIT, STGE_MAXTXSEGS);
1242 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1243 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1249 } else if (error != 0)
1259 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) {
1260 if (m->m_pkthdr.csum_flags & CSUM_IP)
1261 csum_flags |= TFD_IPChecksumEnable;
1262 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1263 csum_flags |= TFD_TCPChecksumEnable;
1264 else if (m->m_pkthdr.csum_flags & CSUM_UDP)
1265 csum_flags |= TFD_UDPChecksumEnable;
1268 si = sc->sc_cdata.stge_tx_prod;
1269 tfd = &sc->sc_rdata.stge_tx_ring[si];
1270 for (i = 0; i < nsegs; i++)
1271 tfd->tfd_frags[i].frag_word0 =
1272 htole64(FRAG_ADDR(txsegs[i].ds_addr) |
1273 FRAG_LEN(txsegs[i].ds_len));
1274 sc->sc_cdata.stge_tx_cnt++;
1276 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) |
1277 TFD_FragCount(nsegs) | csum_flags;
1278 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT)
1279 tfc |= TFD_TxDMAIndicate;
1281 /* Update producer index. */
1282 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT;
1284 /* Check if we have a VLAN tag to insert. */
1285 if (m->m_flags & M_VLANTAG)
1286 tfc |= (TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vtag));
1287 tfd->tfd_control = htole64(tfc);
1289 /* Update Tx Queue. */
1290 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q);
1291 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q);
1294 /* Sync descriptors. */
1295 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1296 BUS_DMASYNC_PREWRITE);
1297 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1298 sc->sc_cdata.stge_tx_ring_map,
1299 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1305 * stge_start: [ifnet interface function]
1307 * Start packet transmission on the interface.
1310 stge_start(struct ifnet *ifp)
1312 struct stge_softc *sc;
1316 stge_start_locked(ifp);
1321 stge_start_locked(struct ifnet *ifp)
1323 struct stge_softc *sc;
1324 struct mbuf *m_head;
1329 STGE_LOCK_ASSERT(sc);
1331 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
1332 IFF_DRV_RUNNING || sc->sc_link == 0)
1335 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1336 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) {
1337 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1341 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1345 * Pack the data into the transmit ring. If we
1346 * don't have room, set the OACTIVE flag and wait
1347 * for the NIC to drain the ring.
1349 if (stge_encap(sc, &m_head)) {
1352 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1353 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1359 * If there's a BPF listener, bounce a copy of this frame
1362 ETHER_BPF_MTAP(ifp, m_head);
1367 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow);
1369 /* Set a timeout in case the chip goes out to lunch. */
1370 sc->sc_watchdog_timer = 5;
1377 * Watchdog timer handler.
1380 stge_watchdog(struct stge_softc *sc)
1384 STGE_LOCK_ASSERT(sc);
1386 if (sc->sc_watchdog_timer == 0 || --sc->sc_watchdog_timer)
1390 if_printf(sc->sc_ifp, "device timeout\n");
1392 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1393 stge_init_locked(sc);
1394 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1395 stge_start_locked(ifp);
1399 * stge_ioctl: [ifnet interface function]
1401 * Handle control requests from the operator.
1404 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1406 struct stge_softc *sc;
1408 struct mii_data *mii;
1412 ifr = (struct ifreq *)data;
1416 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU)
1418 else if (ifp->if_mtu != ifr->ifr_mtu) {
1419 ifp->if_mtu = ifr->ifr_mtu;
1421 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1422 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1423 stge_init_locked(sc);
1430 if ((ifp->if_flags & IFF_UP) != 0) {
1431 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1432 if (((ifp->if_flags ^ sc->sc_if_flags)
1433 & IFF_PROMISC) != 0)
1434 stge_set_filter(sc);
1436 if (sc->sc_detach == 0)
1437 stge_init_locked(sc);
1440 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1443 sc->sc_if_flags = ifp->if_flags;
1449 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1455 mii = device_get_softc(sc->sc_miibus);
1456 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1459 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1460 #ifdef DEVICE_POLLING
1461 if ((mask & IFCAP_POLLING) != 0) {
1462 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1463 error = ether_poll_register(stge_poll, ifp);
1467 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1468 ifp->if_capenable |= IFCAP_POLLING;
1471 error = ether_poll_deregister(ifp);
1475 CSR_WRITE_2(sc, STGE_IntEnable,
1477 ifp->if_capenable &= ~IFCAP_POLLING;
1482 if ((mask & IFCAP_HWCSUM) != 0) {
1483 ifp->if_capenable ^= IFCAP_HWCSUM;
1484 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 &&
1485 (IFCAP_HWCSUM & ifp->if_capabilities) != 0)
1486 ifp->if_hwassist = STGE_CSUM_FEATURES;
1488 ifp->if_hwassist = 0;
1490 if ((mask & IFCAP_WOL) != 0 &&
1491 (ifp->if_capabilities & IFCAP_WOL) != 0) {
1492 if ((mask & IFCAP_WOL_MAGIC) != 0)
1493 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1495 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
1496 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1497 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1499 stge_vlan_setup(sc);
1503 VLAN_CAPABILITIES(ifp);
1506 error = ether_ioctl(ifp, cmd, data);
1514 stge_link_task(void *arg, int pending)
1516 struct stge_softc *sc;
1517 struct mii_data *mii;
1521 sc = (struct stge_softc *)arg;
1524 mii = device_get_softc(sc->sc_miibus);
1525 if (mii->mii_media_status & IFM_ACTIVE) {
1526 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1532 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
1533 sc->sc_MACCtrl |= MC_DuplexSelect;
1534 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_RXPAUSE) != 0)
1535 sc->sc_MACCtrl |= MC_RxFlowControlEnable;
1536 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_TXPAUSE) != 0)
1537 sc->sc_MACCtrl |= MC_TxFlowControlEnable;
1539 * Update STGE_MACCtrl register depending on link status.
1540 * (duplex, flow control etc)
1542 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
1543 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable);
1544 v |= sc->sc_MACCtrl;
1545 CSR_WRITE_4(sc, STGE_MACCtrl, v);
1546 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) {
1547 /* Duplex setting changed, reset Tx/Rx functions. */
1548 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1549 ac |= AC_TxReset | AC_RxReset;
1550 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1551 for (i = 0; i < STGE_TIMEOUT; i++) {
1553 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1556 if (i == STGE_TIMEOUT)
1557 device_printf(sc->sc_dev, "reset failed to complete\n");
1563 stge_tx_error(struct stge_softc *sc)
1569 txstat = CSR_READ_4(sc, STGE_TxStatus);
1570 if ((txstat & TS_TxComplete) == 0)
1573 if ((txstat & TS_TxUnderrun) != 0) {
1576 * There should be a more better way to recover
1577 * from Tx underrun instead of a full reset.
1579 if (sc->sc_nerr++ < STGE_MAXERR)
1580 device_printf(sc->sc_dev, "Tx underrun, "
1582 if (sc->sc_nerr == STGE_MAXERR)
1583 device_printf(sc->sc_dev, "too many errors; "
1584 "not reporting any more\n");
1588 /* Maximum/Late collisions, Re-enable Tx MAC. */
1589 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0)
1590 CSR_WRITE_4(sc, STGE_MACCtrl,
1591 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |
1601 * Interrupt service routine.
1604 stge_intr(void *arg)
1606 struct stge_softc *sc;
1611 sc = (struct stge_softc *)arg;
1616 #ifdef DEVICE_POLLING
1617 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1620 status = CSR_READ_2(sc, STGE_IntStatus);
1621 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0)
1624 /* Disable interrupts. */
1625 for (reinit = 0;;) {
1626 status = CSR_READ_2(sc, STGE_IntStatusAck);
1627 status &= sc->sc_IntEnable;
1630 /* Host interface errors. */
1631 if ((status & IS_HostError) != 0) {
1632 device_printf(sc->sc_dev,
1633 "Host interface error, resetting...\n");
1638 /* Receive interrupts. */
1639 if ((status & IS_RxDMAComplete) != 0) {
1641 if ((status & IS_RFDListEnd) != 0)
1642 CSR_WRITE_4(sc, STGE_DMACtrl,
1646 /* Transmit interrupts. */
1647 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0)
1650 /* Transmission errors.*/
1651 if ((status & IS_TxComplete) != 0) {
1652 if ((reinit = stge_tx_error(sc)) != 0)
1659 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1660 stge_init_locked(sc);
1663 /* Re-enable interrupts. */
1664 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1666 /* Try to get more packets going. */
1667 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1668 stge_start_locked(ifp);
1677 * Helper; handle transmit interrupts.
1680 stge_txeof(struct stge_softc *sc)
1683 struct stge_txdesc *txd;
1687 STGE_LOCK_ASSERT(sc);
1691 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1694 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1695 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD);
1698 * Go through our Tx list and free mbufs for those
1699 * frames which have been transmitted.
1701 for (cons = sc->sc_cdata.stge_tx_cons;;
1702 cons = (cons + 1) % STGE_TX_RING_CNT) {
1703 if (sc->sc_cdata.stge_tx_cnt <= 0)
1705 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control);
1706 if ((control & TFD_TFDDone) == 0)
1708 sc->sc_cdata.stge_tx_cnt--;
1709 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1711 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1712 BUS_DMASYNC_POSTWRITE);
1713 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap);
1715 /* Output counter is updated with statistics register */
1718 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q);
1719 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
1720 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1722 sc->sc_cdata.stge_tx_cons = cons;
1723 if (sc->sc_cdata.stge_tx_cnt == 0)
1724 sc->sc_watchdog_timer = 0;
1726 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1727 sc->sc_cdata.stge_tx_ring_map,
1728 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1731 static __inline void
1732 stge_discard_rxbuf(struct stge_softc *sc, int idx)
1734 struct stge_rfd *rfd;
1736 rfd = &sc->sc_rdata.stge_rx_ring[idx];
1737 rfd->rfd_status = 0;
1740 #ifndef __NO_STRICT_ALIGNMENT
1742 * It seems that TC9021's DMA engine has alignment restrictions in
1743 * DMA scatter operations. The first DMA segment has no address
1744 * alignment restrictins but the rest should be aligned on 4(?) bytes
1745 * boundary. Otherwise it would corrupt random memory. Since we don't
1746 * know which one is used for the first segment in advance we simply
1747 * don't align at all.
1748 * To avoid copying over an entire frame to align, we allocate a new
1749 * mbuf and copy ethernet header to the new mbuf. The new mbuf is
1750 * prepended into the existing mbuf chain.
1752 static __inline struct mbuf *
1753 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m)
1758 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
1759 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
1760 m->m_data += ETHER_HDR_LEN;
1763 MGETHDR(n, M_DONTWAIT, MT_DATA);
1765 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
1766 m->m_data += ETHER_HDR_LEN;
1767 m->m_len -= ETHER_HDR_LEN;
1768 n->m_len = ETHER_HDR_LEN;
1769 M_MOVE_PKTHDR(n, m);
1782 * Helper; handle receive interrupts.
1785 stge_rxeof(struct stge_softc *sc)
1788 struct stge_rxdesc *rxd;
1789 struct mbuf *mp, *m;
1792 int cons, prog, rx_npkts;
1794 STGE_LOCK_ASSERT(sc);
1799 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1800 sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD);
1803 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT;
1804 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) {
1805 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status);
1806 status = RFD_RxStatus(status64);
1807 if ((status & RFD_RFDDone) == 0)
1809 #ifdef DEVICE_POLLING
1810 if (ifp->if_capenable & IFCAP_POLLING) {
1811 if (sc->sc_cdata.stge_rxcycles <= 0)
1813 sc->sc_cdata.stge_rxcycles--;
1817 rxd = &sc->sc_cdata.stge_rxdesc[cons];
1821 * If the packet had an error, drop it. Note we count
1822 * the error later in the periodic stats update.
1824 if ((status & RFD_FrameEnd) != 0 && (status &
1825 (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
1826 RFD_RxAlignmentError | RFD_RxFCSError |
1827 RFD_RxLengthError)) != 0) {
1828 stge_discard_rxbuf(sc, cons);
1829 if (sc->sc_cdata.stge_rxhead != NULL) {
1830 m_freem(sc->sc_cdata.stge_rxhead);
1831 STGE_RXCHAIN_RESET(sc);
1836 * Add a new receive buffer to the ring.
1838 if (stge_newbuf(sc, cons) != 0) {
1840 stge_discard_rxbuf(sc, cons);
1841 if (sc->sc_cdata.stge_rxhead != NULL) {
1842 m_freem(sc->sc_cdata.stge_rxhead);
1843 STGE_RXCHAIN_RESET(sc);
1848 if ((status & RFD_FrameEnd) != 0)
1849 mp->m_len = RFD_RxDMAFrameLen(status) -
1850 sc->sc_cdata.stge_rxlen;
1851 sc->sc_cdata.stge_rxlen += mp->m_len;
1854 if (sc->sc_cdata.stge_rxhead == NULL) {
1855 sc->sc_cdata.stge_rxhead = mp;
1856 sc->sc_cdata.stge_rxtail = mp;
1858 mp->m_flags &= ~M_PKTHDR;
1859 sc->sc_cdata.stge_rxtail->m_next = mp;
1860 sc->sc_cdata.stge_rxtail = mp;
1863 if ((status & RFD_FrameEnd) != 0) {
1864 m = sc->sc_cdata.stge_rxhead;
1865 m->m_pkthdr.rcvif = ifp;
1866 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen;
1868 if (m->m_pkthdr.len > sc->sc_if_framesize) {
1870 STGE_RXCHAIN_RESET(sc);
1874 * Set the incoming checksum information for
1877 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1878 if ((status & RFD_IPDetected) != 0) {
1879 m->m_pkthdr.csum_flags |=
1881 if ((status & RFD_IPError) == 0)
1882 m->m_pkthdr.csum_flags |=
1885 if (((status & RFD_TCPDetected) != 0 &&
1886 (status & RFD_TCPError) == 0) ||
1887 ((status & RFD_UDPDetected) != 0 &&
1888 (status & RFD_UDPError) == 0)) {
1889 m->m_pkthdr.csum_flags |=
1890 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1891 m->m_pkthdr.csum_data = 0xffff;
1895 #ifndef __NO_STRICT_ALIGNMENT
1896 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) {
1897 if ((m = stge_fixup_rx(sc, m)) == NULL) {
1898 STGE_RXCHAIN_RESET(sc);
1903 /* Check for VLAN tagged packets. */
1904 if ((status & RFD_VLANDetected) != 0 &&
1905 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
1906 m->m_pkthdr.ether_vtag = RFD_TCI(status64);
1907 m->m_flags |= M_VLANTAG;
1912 (*ifp->if_input)(ifp, m);
1916 STGE_RXCHAIN_RESET(sc);
1921 /* Update the consumer index. */
1922 sc->sc_cdata.stge_rx_cons = cons;
1923 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1924 sc->sc_cdata.stge_rx_ring_map,
1925 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1930 #ifdef DEVICE_POLLING
1932 stge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1934 struct stge_softc *sc;
1941 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1946 sc->sc_cdata.stge_rxcycles = count;
1947 rx_npkts = stge_rxeof(sc);
1950 if (cmd == POLL_AND_CHECK_STATUS) {
1951 status = CSR_READ_2(sc, STGE_IntStatus);
1952 status &= sc->sc_IntEnable;
1954 if ((status & IS_HostError) != 0) {
1955 device_printf(sc->sc_dev,
1956 "Host interface error, resetting...\n");
1957 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1958 stge_init_locked(sc);
1960 if ((status & IS_TxComplete) != 0) {
1961 if (stge_tx_error(sc) != 0) {
1962 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1963 stge_init_locked(sc);
1970 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1971 stge_start_locked(ifp);
1976 #endif /* DEVICE_POLLING */
1981 * One second timer, used to tick the MII.
1984 stge_tick(void *arg)
1986 struct stge_softc *sc;
1987 struct mii_data *mii;
1989 sc = (struct stge_softc *)arg;
1991 STGE_LOCK_ASSERT(sc);
1993 mii = device_get_softc(sc->sc_miibus);
1996 /* Update statistics counters. */
1997 stge_stats_update(sc);
2000 * Relcaim any pending Tx descriptors to release mbufs in a
2001 * timely manner as we don't generate Tx completion interrupts
2002 * for every frame. This limits the delay to a maximum of one
2005 if (sc->sc_cdata.stge_tx_cnt != 0)
2010 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
2014 * stge_stats_update:
2016 * Read the TC9021 statistics counters.
2019 stge_stats_update(struct stge_softc *sc)
2023 STGE_LOCK_ASSERT(sc);
2027 CSR_READ_4(sc,STGE_OctetRcvOk);
2029 ifp->if_ipackets += CSR_READ_4(sc, STGE_FramesRcvdOk);
2031 ifp->if_ierrors += CSR_READ_2(sc, STGE_FramesLostRxErrors);
2033 CSR_READ_4(sc, STGE_OctetXmtdOk);
2035 ifp->if_opackets += CSR_READ_4(sc, STGE_FramesXmtdOk);
2037 ifp->if_collisions +=
2038 CSR_READ_4(sc, STGE_LateCollisions) +
2039 CSR_READ_4(sc, STGE_MultiColFrames) +
2040 CSR_READ_4(sc, STGE_SingleColFrames);
2043 CSR_READ_2(sc, STGE_FramesAbortXSColls) +
2044 CSR_READ_2(sc, STGE_FramesWEXDeferal);
2050 * Perform a soft reset on the TC9021.
2053 stge_reset(struct stge_softc *sc, uint32_t how)
2059 STGE_LOCK_ASSERT(sc);
2062 ac = CSR_READ_4(sc, STGE_AsicCtrl);
2065 ac |= AC_TxReset | AC_FIFO;
2069 ac |= AC_RxReset | AC_FIFO;
2072 case STGE_RESET_FULL:
2075 * Only assert RstOut if we're fiber. We need GMII clocks
2076 * to be present in order for the reset to complete on fiber
2079 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset |
2080 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
2081 (sc->sc_usefiber ? AC_RstOut : 0);
2085 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
2087 /* Account for reset problem at 10Mbps. */
2090 for (i = 0; i < STGE_TIMEOUT; i++) {
2091 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
2096 if (i == STGE_TIMEOUT)
2097 device_printf(sc->sc_dev, "reset failed to complete\n");
2099 /* Set LED, from Linux IPG driver. */
2100 ac = CSR_READ_4(sc, STGE_AsicCtrl);
2101 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1);
2102 if ((sc->sc_led & 0x01) != 0)
2104 if ((sc->sc_led & 0x03) != 0)
2105 ac |= AC_LEDModeBit1;
2106 if ((sc->sc_led & 0x08) != 0)
2108 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
2110 /* Set PHY, from Linux IPG driver */
2111 v = CSR_READ_1(sc, STGE_PhySet);
2112 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet);
2113 v |= ((sc->sc_led & 0x70) >> 4);
2114 CSR_WRITE_1(sc, STGE_PhySet, v);
2118 * stge_init: [ ifnet interface function ]
2120 * Initialize the interface.
2123 stge_init(void *xsc)
2125 struct stge_softc *sc;
2127 sc = (struct stge_softc *)xsc;
2129 stge_init_locked(sc);
2134 stge_init_locked(struct stge_softc *sc)
2137 struct mii_data *mii;
2142 STGE_LOCK_ASSERT(sc);
2145 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2147 mii = device_get_softc(sc->sc_miibus);
2150 * Cancel any pending I/O.
2155 * Reset the chip to a known state.
2157 stge_reset(sc, STGE_RESET_FULL);
2159 /* Init descriptors. */
2160 error = stge_init_rx_ring(sc);
2162 device_printf(sc->sc_dev,
2163 "initialization failed: no memory for rx buffers\n");
2167 stge_init_tx_ring(sc);
2169 /* Set the station address. */
2170 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2171 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
2172 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
2173 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
2176 * Set the statistics masks. Disable all the RMON stats,
2177 * and disable selected stats in the non-RMON stats registers.
2179 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
2180 CSR_WRITE_4(sc, STGE_StatisticsMask,
2181 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
2182 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
2183 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
2186 /* Set up the receive filter. */
2187 stge_set_filter(sc);
2188 /* Program multicast filter. */
2192 * Give the transmit and receive ring to the chip.
2194 CSR_WRITE_4(sc, STGE_TFDListPtrHi,
2195 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0)));
2196 CSR_WRITE_4(sc, STGE_TFDListPtrLo,
2197 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0)));
2199 CSR_WRITE_4(sc, STGE_RFDListPtrHi,
2200 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0)));
2201 CSR_WRITE_4(sc, STGE_RFDListPtrLo,
2202 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0)));
2205 * Initialize the Tx auto-poll period. It's OK to make this number
2206 * large (255 is the max, but we use 127) -- we explicitly kick the
2207 * transmit engine when there's actually a packet.
2209 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2211 /* ..and the Rx auto-poll period. */
2212 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2214 /* Initialize the Tx start threshold. */
2215 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
2217 /* Rx DMA thresholds, from Linux */
2218 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
2219 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
2221 /* Rx early threhold, from Linux */
2222 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
2224 /* Tx DMA thresholds, from Linux */
2225 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
2226 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
2229 * Initialize the Rx DMA interrupt control register. We
2230 * request an interrupt after every incoming packet, but
2231 * defer it for sc_rxint_dmawait us. When the number of
2232 * interrupts pending reaches STGE_RXINT_NFRAME, we stop
2233 * deferring the interrupt, and signal it immediately.
2235 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
2236 RDIC_RxFrameCount(sc->sc_rxint_nframe) |
2237 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait)));
2240 * Initialize the interrupt mask.
2242 sc->sc_IntEnable = IS_HostError | IS_TxComplete |
2243 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
2244 #ifdef DEVICE_POLLING
2245 /* Disable interrupts if we are polling. */
2246 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
2247 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2250 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2253 * Configure the DMA engine.
2254 * XXX Should auto-tune TxBurstLimit.
2256 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3));
2259 * Send a PAUSE frame when we reach 29,696 bytes in the Rx
2260 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes
2263 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
2264 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
2267 * Set the maximum frame size.
2269 sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2270 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize);
2273 * Initialize MacCtrl -- do it before setting the media,
2274 * as setting the media will actually program the register.
2276 * Note: We have to poke the IFS value before poking
2279 /* Tx/Rx MAC should be disabled before programming IFS.*/
2280 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit));
2282 stge_vlan_setup(sc);
2284 if (sc->sc_rev >= 6) { /* >= B.2 */
2285 /* Multi-frag frame bug work-around. */
2286 CSR_WRITE_2(sc, STGE_DebugCtrl,
2287 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
2289 /* Tx Poll Now bug work-around. */
2290 CSR_WRITE_2(sc, STGE_DebugCtrl,
2291 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
2292 /* Tx Poll Now bug work-around. */
2293 CSR_WRITE_2(sc, STGE_DebugCtrl,
2294 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
2297 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2298 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
2299 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2301 * It seems that transmitting frames without checking the state of
2302 * Rx/Tx MAC wedge the hardware.
2309 * Set the current media.
2314 * Start the one second MII clock.
2316 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
2321 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2322 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2326 device_printf(sc->sc_dev, "interface not running\n");
2330 stge_vlan_setup(struct stge_softc *sc)
2337 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl
2338 * MC_AutoVLANuntagging bit.
2339 * MC_AutoVLANtagging bit selects which VLAN source to use
2340 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert
2341 * bit has priority over MC_AutoVLANtagging bit. So we always
2342 * use TFC instead of STGE_VLANTag register.
2344 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2345 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2346 v |= MC_AutoVLANuntagging;
2348 v &= ~MC_AutoVLANuntagging;
2349 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2353 * Stop transmission on the interface.
2356 stge_stop(struct stge_softc *sc)
2359 struct stge_txdesc *txd;
2360 struct stge_rxdesc *rxd;
2364 STGE_LOCK_ASSERT(sc);
2366 * Stop the one second clock.
2368 callout_stop(&sc->sc_tick_ch);
2369 sc->sc_watchdog_timer = 0;
2372 * Disable interrupts.
2374 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2377 * Stop receiver, transmitter, and stats update.
2381 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2382 v |= MC_StatisticsDisable;
2383 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2386 * Stop the transmit and receive DMA.
2389 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
2390 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
2391 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
2392 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
2395 * Free RX and TX mbufs still in the queues.
2397 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2398 rxd = &sc->sc_cdata.stge_rxdesc[i];
2399 if (rxd->rx_m != NULL) {
2400 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag,
2401 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2402 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag,
2408 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2409 txd = &sc->sc_cdata.stge_txdesc[i];
2410 if (txd->tx_m != NULL) {
2411 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag,
2412 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2413 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag,
2421 * Mark the interface down and cancel the watchdog timer.
2424 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2429 stge_start_tx(struct stge_softc *sc)
2434 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2435 if ((v & MC_TxEnabled) != 0)
2438 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2439 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2440 for (i = STGE_TIMEOUT; i > 0; i--) {
2442 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2443 if ((v & MC_TxEnabled) != 0)
2447 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n");
2451 stge_start_rx(struct stge_softc *sc)
2456 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2457 if ((v & MC_RxEnabled) != 0)
2460 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2461 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2462 for (i = STGE_TIMEOUT; i > 0; i--) {
2464 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2465 if ((v & MC_RxEnabled) != 0)
2469 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n");
2473 stge_stop_tx(struct stge_softc *sc)
2478 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2479 if ((v & MC_TxEnabled) == 0)
2482 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2483 for (i = STGE_TIMEOUT; i > 0; i--) {
2485 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2486 if ((v & MC_TxEnabled) == 0)
2490 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n");
2494 stge_stop_rx(struct stge_softc *sc)
2499 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2500 if ((v & MC_RxEnabled) == 0)
2503 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2504 for (i = STGE_TIMEOUT; i > 0; i--) {
2506 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2507 if ((v & MC_RxEnabled) == 0)
2511 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n");
2515 stge_init_tx_ring(struct stge_softc *sc)
2517 struct stge_ring_data *rd;
2518 struct stge_txdesc *txd;
2522 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq);
2523 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq);
2525 sc->sc_cdata.stge_tx_prod = 0;
2526 sc->sc_cdata.stge_tx_cons = 0;
2527 sc->sc_cdata.stge_tx_cnt = 0;
2530 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ);
2531 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2532 if (i == (STGE_TX_RING_CNT - 1))
2533 addr = STGE_TX_RING_ADDR(sc, 0);
2535 addr = STGE_TX_RING_ADDR(sc, i + 1);
2536 rd->stge_tx_ring[i].tfd_next = htole64(addr);
2537 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone);
2538 txd = &sc->sc_cdata.stge_txdesc[i];
2539 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
2542 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
2543 sc->sc_cdata.stge_tx_ring_map,
2544 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2549 stge_init_rx_ring(struct stge_softc *sc)
2551 struct stge_ring_data *rd;
2555 sc->sc_cdata.stge_rx_cons = 0;
2556 STGE_RXCHAIN_RESET(sc);
2559 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ);
2560 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2561 if (stge_newbuf(sc, i) != 0)
2563 if (i == (STGE_RX_RING_CNT - 1))
2564 addr = STGE_RX_RING_ADDR(sc, 0);
2566 addr = STGE_RX_RING_ADDR(sc, i + 1);
2567 rd->stge_rx_ring[i].rfd_next = htole64(addr);
2568 rd->stge_rx_ring[i].rfd_status = 0;
2571 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
2572 sc->sc_cdata.stge_rx_ring_map,
2573 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2581 * Add a receive buffer to the indicated descriptor.
2584 stge_newbuf(struct stge_softc *sc, int idx)
2586 struct stge_rxdesc *rxd;
2587 struct stge_rfd *rfd;
2589 bus_dma_segment_t segs[1];
2593 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2596 m->m_len = m->m_pkthdr.len = MCLBYTES;
2598 * The hardware requires 4bytes aligned DMA address when JUMBO
2601 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN))
2602 m_adj(m, ETHER_ALIGN);
2604 if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag,
2605 sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2609 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2611 rxd = &sc->sc_cdata.stge_rxdesc[idx];
2612 if (rxd->rx_m != NULL) {
2613 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2614 BUS_DMASYNC_POSTREAD);
2615 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap);
2617 map = rxd->rx_dmamap;
2618 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap;
2619 sc->sc_cdata.stge_rx_sparemap = map;
2620 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2621 BUS_DMASYNC_PREREAD);
2624 rfd = &sc->sc_rdata.stge_rx_ring[idx];
2625 rfd->rfd_frag.frag_word0 =
2626 htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len));
2627 rfd->rfd_status = 0;
2635 * Set up the receive filter.
2638 stge_set_filter(struct stge_softc *sc)
2643 STGE_LOCK_ASSERT(sc);
2647 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2648 mode |= RM_ReceiveUnicast;
2649 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2650 mode |= RM_ReceiveBroadcast;
2652 mode &= ~RM_ReceiveBroadcast;
2653 if ((ifp->if_flags & IFF_PROMISC) != 0)
2654 mode |= RM_ReceiveAllFrames;
2656 mode &= ~RM_ReceiveAllFrames;
2658 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2662 stge_set_multi(struct stge_softc *sc)
2665 struct ifmultiaddr *ifma;
2671 STGE_LOCK_ASSERT(sc);
2675 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2676 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2677 if ((ifp->if_flags & IFF_PROMISC) != 0)
2678 mode |= RM_ReceiveAllFrames;
2679 else if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2680 mode |= RM_ReceiveMulticast;
2681 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2685 /* clear existing filters. */
2686 CSR_WRITE_4(sc, STGE_HashTable0, 0);
2687 CSR_WRITE_4(sc, STGE_HashTable1, 0);
2690 * Set up the multicast address filter by passing all multicast
2691 * addresses through a CRC generator, and then using the low-order
2692 * 6 bits as an index into the 64 bit multicast hash table. The
2693 * high order bits select the register, while the rest of the bits
2694 * select the bit within the register.
2697 bzero(mchash, sizeof(mchash));
2700 if_maddr_rlock(sc->sc_ifp);
2701 TAILQ_FOREACH(ifma, &sc->sc_ifp->if_multiaddrs, ifma_link) {
2702 if (ifma->ifma_addr->sa_family != AF_LINK)
2704 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2705 ifma->ifma_addr), ETHER_ADDR_LEN);
2707 /* Just want the 6 least significant bits. */
2710 /* Set the corresponding bit in the hash table. */
2711 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2714 if_maddr_runlock(ifp);
2716 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames);
2718 mode |= RM_ReceiveMulticastHash;
2720 mode &= ~RM_ReceiveMulticastHash;
2722 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
2723 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
2724 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2728 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2734 value = *(int *)arg1;
2735 error = sysctl_handle_int(oidp, &value, 0, req);
2736 if (error || !req->newptr)
2738 if (value < low || value > high)
2740 *(int *)arg1 = value;
2746 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS)
2748 return (sysctl_int_range(oidp, arg1, arg2, req,
2749 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX));
2753 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS)
2755 return (sysctl_int_range(oidp, arg1, arg2, req,
2756 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX));