1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
33 * Device driver for the Sundance Tech. TC9021 10/100/1000
34 * Ethernet controller.
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
40 #ifdef HAVE_KERNEL_OPTION_HEADERS
41 #include "opt_device_polling.h"
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/endian.h>
48 #include <sys/malloc.h>
49 #include <sys/kernel.h>
50 #include <sys/module.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/taskqueue.h>
57 #include <net/ethernet.h>
59 #include <net/if_var.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
62 #include <net/if_types.h>
63 #include <net/if_vlan_var.h>
65 #include <machine/bus.h>
66 #include <machine/resource.h>
70 #include <dev/mii/mii.h>
71 #include <dev/mii/mii_bitbang.h>
72 #include <dev/mii/miivar.h>
74 #include <dev/pci/pcireg.h>
75 #include <dev/pci/pcivar.h>
77 #include <dev/stge/if_stgereg.h>
79 #define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
81 MODULE_DEPEND(stge, pci, 1, 1, 1);
82 MODULE_DEPEND(stge, ether, 1, 1, 1);
83 MODULE_DEPEND(stge, miibus, 1, 1, 1);
85 /* "device miibus" required. See GENERIC if you get errors here. */
86 #include "miibus_if.h"
89 * Devices supported by this driver.
91 static const struct stge_product {
92 uint16_t stge_vendorid;
93 uint16_t stge_deviceid;
94 const char *stge_name;
96 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023,
97 "Sundance ST-1023 Gigabit Ethernet" },
99 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021,
100 "Sundance ST-2021 Gigabit Ethernet" },
102 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021,
103 "Tamarack TC9021 Gigabit Ethernet" },
105 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT,
106 "Tamarack TC9021 Gigabit Ethernet" },
109 * The Sundance sample boards use the Sundance vendor ID,
110 * but the Tamarack product ID.
112 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021,
113 "Sundance TC9021 Gigabit Ethernet" },
115 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT,
116 "Sundance TC9021 Gigabit Ethernet" },
118 { VENDOR_DLINK, DEVICEID_DLINK_DL4000,
119 "D-Link DL-4000 Gigabit Ethernet" },
121 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021,
122 "Antares Gigabit Ethernet" }
125 static int stge_probe(device_t);
126 static int stge_attach(device_t);
127 static int stge_detach(device_t);
128 static int stge_shutdown(device_t);
129 static int stge_suspend(device_t);
130 static int stge_resume(device_t);
132 static int stge_encap(struct stge_softc *, struct mbuf **);
133 static void stge_start(struct ifnet *);
134 static void stge_start_locked(struct ifnet *);
135 static void stge_watchdog(struct stge_softc *);
136 static int stge_ioctl(struct ifnet *, u_long, caddr_t);
137 static void stge_init(void *);
138 static void stge_init_locked(struct stge_softc *);
139 static void stge_vlan_setup(struct stge_softc *);
140 static void stge_stop(struct stge_softc *);
141 static void stge_start_tx(struct stge_softc *);
142 static void stge_start_rx(struct stge_softc *);
143 static void stge_stop_tx(struct stge_softc *);
144 static void stge_stop_rx(struct stge_softc *);
146 static void stge_reset(struct stge_softc *, uint32_t);
147 static int stge_eeprom_wait(struct stge_softc *);
148 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *);
149 static void stge_tick(void *);
150 static void stge_stats_update(struct stge_softc *);
151 static void stge_set_filter(struct stge_softc *);
152 static void stge_set_multi(struct stge_softc *);
154 static void stge_link_task(void *, int);
155 static void stge_intr(void *);
156 static __inline int stge_tx_error(struct stge_softc *);
157 static void stge_txeof(struct stge_softc *);
158 static int stge_rxeof(struct stge_softc *);
159 static __inline void stge_discard_rxbuf(struct stge_softc *, int);
160 static int stge_newbuf(struct stge_softc *, int);
161 #ifndef __NO_STRICT_ALIGNMENT
162 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *);
165 static int stge_miibus_readreg(device_t, int, int);
166 static int stge_miibus_writereg(device_t, int, int, int);
167 static void stge_miibus_statchg(device_t);
168 static int stge_mediachange(struct ifnet *);
169 static void stge_mediastatus(struct ifnet *, struct ifmediareq *);
171 static void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
172 static int stge_dma_alloc(struct stge_softc *);
173 static void stge_dma_free(struct stge_softc *);
174 static void stge_dma_wait(struct stge_softc *);
175 static void stge_init_tx_ring(struct stge_softc *);
176 static int stge_init_rx_ring(struct stge_softc *);
177 #ifdef DEVICE_POLLING
178 static int stge_poll(struct ifnet *, enum poll_cmd, int);
181 static void stge_setwol(struct stge_softc *);
182 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
183 static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS);
184 static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS);
189 static uint32_t stge_mii_bitbang_read(device_t);
190 static void stge_mii_bitbang_write(device_t, uint32_t);
192 static const struct mii_bitbang_ops stge_mii_bitbang_ops = {
193 stge_mii_bitbang_read,
194 stge_mii_bitbang_write,
196 PC_MgmtData, /* MII_BIT_MDO */
197 PC_MgmtData, /* MII_BIT_MDI */
198 PC_MgmtClk, /* MII_BIT_MDC */
199 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */
200 0, /* MII_BIT_DIR_PHY_HOST */
204 static device_method_t stge_methods[] = {
205 /* Device interface */
206 DEVMETHOD(device_probe, stge_probe),
207 DEVMETHOD(device_attach, stge_attach),
208 DEVMETHOD(device_detach, stge_detach),
209 DEVMETHOD(device_shutdown, stge_shutdown),
210 DEVMETHOD(device_suspend, stge_suspend),
211 DEVMETHOD(device_resume, stge_resume),
214 DEVMETHOD(miibus_readreg, stge_miibus_readreg),
215 DEVMETHOD(miibus_writereg, stge_miibus_writereg),
216 DEVMETHOD(miibus_statchg, stge_miibus_statchg),
221 static driver_t stge_driver = {
224 sizeof(struct stge_softc)
227 static devclass_t stge_devclass;
229 DRIVER_MODULE(stge, pci, stge_driver, stge_devclass, 0, 0);
230 DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, 0, 0);
232 static struct resource_spec stge_res_spec_io[] = {
233 { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE },
234 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
238 static struct resource_spec stge_res_spec_mem[] = {
239 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE },
240 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
245 * stge_mii_bitbang_read: [mii bit-bang interface function]
247 * Read the MII serial port for the MII bit-bang module.
250 stge_mii_bitbang_read(device_t dev)
252 struct stge_softc *sc;
255 sc = device_get_softc(dev);
257 val = CSR_READ_1(sc, STGE_PhyCtrl);
258 CSR_BARRIER(sc, STGE_PhyCtrl, 1,
259 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
264 * stge_mii_bitbang_write: [mii big-bang interface function]
266 * Write the MII serial port for the MII bit-bang module.
269 stge_mii_bitbang_write(device_t dev, uint32_t val)
271 struct stge_softc *sc;
273 sc = device_get_softc(dev);
275 CSR_WRITE_1(sc, STGE_PhyCtrl, val);
276 CSR_BARRIER(sc, STGE_PhyCtrl, 1,
277 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
281 * sc_miibus_readreg: [mii interface function]
283 * Read a PHY register on the MII of the TC9021.
286 stge_miibus_readreg(device_t dev, int phy, int reg)
288 struct stge_softc *sc;
291 sc = device_get_softc(dev);
293 if (reg == STGE_PhyCtrl) {
294 /* XXX allow ip1000phy read STGE_PhyCtrl register. */
296 error = CSR_READ_1(sc, STGE_PhyCtrl);
302 val = mii_bitbang_readreg(dev, &stge_mii_bitbang_ops, phy, reg);
308 * stge_miibus_writereg: [mii interface function]
310 * Write a PHY register on the MII of the TC9021.
313 stge_miibus_writereg(device_t dev, int phy, int reg, int val)
315 struct stge_softc *sc;
317 sc = device_get_softc(dev);
320 mii_bitbang_writereg(dev, &stge_mii_bitbang_ops, phy, reg, val);
326 * stge_miibus_statchg: [mii interface function]
328 * Callback from MII layer when media changes.
331 stge_miibus_statchg(device_t dev)
333 struct stge_softc *sc;
335 sc = device_get_softc(dev);
336 taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task);
340 * stge_mediastatus: [ifmedia interface function]
342 * Get the current interface media status.
345 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
347 struct stge_softc *sc;
348 struct mii_data *mii;
351 mii = device_get_softc(sc->sc_miibus);
354 ifmr->ifm_status = mii->mii_media_status;
355 ifmr->ifm_active = mii->mii_media_active;
359 * stge_mediachange: [ifmedia interface function]
361 * Set hardware to newly-selected media.
364 stge_mediachange(struct ifnet *ifp)
366 struct stge_softc *sc;
367 struct mii_data *mii;
370 mii = device_get_softc(sc->sc_miibus);
377 stge_eeprom_wait(struct stge_softc *sc)
381 for (i = 0; i < STGE_TIMEOUT; i++) {
383 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
392 * Read data from the serial EEPROM.
395 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
398 if (stge_eeprom_wait(sc))
399 device_printf(sc->sc_dev, "EEPROM failed to come ready\n");
401 CSR_WRITE_2(sc, STGE_EepromCtrl,
402 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
403 if (stge_eeprom_wait(sc))
404 device_printf(sc->sc_dev, "EEPROM read timed out\n");
405 *data = CSR_READ_2(sc, STGE_EepromData);
410 stge_probe(device_t dev)
412 const struct stge_product *sp;
414 uint16_t vendor, devid;
416 vendor = pci_get_vendor(dev);
417 devid = pci_get_device(dev);
419 for (i = 0; i < nitems(stge_products); i++, sp++) {
420 if (vendor == sp->stge_vendorid &&
421 devid == sp->stge_deviceid) {
422 device_set_desc(dev, sp->stge_name);
423 return (BUS_PROBE_DEFAULT);
431 stge_attach(device_t dev)
433 struct stge_softc *sc;
435 uint8_t enaddr[ETHER_ADDR_LEN];
441 sc = device_get_softc(dev);
444 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
446 mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF);
447 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
448 TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc);
453 pci_enable_busmaster(dev);
454 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
455 val = pci_read_config(dev, PCIR_BAR(1), 4);
457 sc->sc_spec = stge_res_spec_mem;
459 val = pci_read_config(dev, PCIR_BAR(0), 4);
460 if (!PCI_BAR_IO(val)) {
461 device_printf(sc->sc_dev, "couldn't locate IO BAR\n");
465 sc->sc_spec = stge_res_spec_io;
467 error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res);
469 device_printf(dev, "couldn't allocate %s resources\n",
470 sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O");
473 sc->sc_rev = pci_get_revid(dev);
475 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
476 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
477 "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0,
478 sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe");
480 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
481 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
482 "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0,
483 sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait");
485 /* Pull in device tunables. */
486 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
487 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
488 "rxint_nframe", &sc->sc_rxint_nframe);
490 if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN ||
491 sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) {
492 device_printf(dev, "rxint_nframe value out of range; "
493 "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT);
494 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
498 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
499 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
500 "rxint_dmawait", &sc->sc_rxint_dmawait);
502 if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN ||
503 sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) {
504 device_printf(dev, "rxint_dmawait value out of range; "
505 "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT);
506 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
510 if ((error = stge_dma_alloc(sc)) != 0)
514 * Determine if we're copper or fiber. It affects how we
517 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
522 /* Load LED configuration from EEPROM. */
523 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led);
526 * Reset the chip to a known state.
529 stge_reset(sc, STGE_RESET_FULL);
533 * Reading the station address from the EEPROM doesn't seem
534 * to work, at least on my sample boards. Instead, since
535 * the reset sequence does AutoInit, read it from the station
536 * address registers. For Sundance 1023 you can only read it
539 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) {
542 v = CSR_READ_2(sc, STGE_StationAddress0);
543 enaddr[0] = v & 0xff;
545 v = CSR_READ_2(sc, STGE_StationAddress1);
546 enaddr[2] = v & 0xff;
548 v = CSR_READ_2(sc, STGE_StationAddress2);
549 enaddr[4] = v & 0xff;
553 uint16_t myaddr[ETHER_ADDR_LEN / 2];
554 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
555 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i,
557 myaddr[i] = le16toh(myaddr[i]);
559 bcopy(myaddr, enaddr, sizeof(enaddr));
563 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
565 device_printf(sc->sc_dev, "failed to if_alloc()\n");
571 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
572 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
573 ifp->if_ioctl = stge_ioctl;
574 ifp->if_start = stge_start;
575 ifp->if_init = stge_init;
576 ifp->if_snd.ifq_drv_maxlen = STGE_TX_RING_CNT - 1;
577 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
578 IFQ_SET_READY(&ifp->if_snd);
579 /* Revision B3 and earlier chips have checksum bug. */
580 if (sc->sc_rev >= 0x0c) {
581 ifp->if_hwassist = STGE_CSUM_FEATURES;
582 ifp->if_capabilities = IFCAP_HWCSUM;
584 ifp->if_hwassist = 0;
585 ifp->if_capabilities = 0;
587 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
588 ifp->if_capenable = ifp->if_capabilities;
591 * Read some important bits from the PhyCtrl register.
593 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
594 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
596 /* Set up MII bus. */
597 flags = MIIF_DOPAUSE;
598 if (sc->sc_rev >= 0x40 && sc->sc_rev <= 0x4e)
599 flags |= MIIF_MACPRIV0;
600 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, stge_mediachange,
601 stge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
604 device_printf(sc->sc_dev, "attaching PHYs failed\n");
608 ether_ifattach(ifp, enaddr);
610 /* VLAN capability setup */
611 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
612 if (sc->sc_rev >= 0x0c)
613 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
614 ifp->if_capenable = ifp->if_capabilities;
615 #ifdef DEVICE_POLLING
616 ifp->if_capabilities |= IFCAP_POLLING;
619 * Tell the upper layer(s) we support long frames.
620 * Must appear after the call to ether_ifattach() because
621 * ether_ifattach() sets ifi_hdrlen to the default value.
623 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
626 * The manual recommends disabling early transmit, so we
627 * do. It's disabled anyway, if using IP checksumming,
628 * since the entire packet must be in the FIFO in order
629 * for the chip to perform the checksum.
631 sc->sc_txthresh = 0x0fff;
634 * Disable MWI if the PCI layer tells us to.
637 if ((cmd & PCIM_CMD_MWRICEN) == 0)
638 sc->sc_DMACtrl |= DMAC_MWIDisable;
643 error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE,
644 NULL, stge_intr, sc, &sc->sc_ih);
647 device_printf(sc->sc_dev, "couldn't set up IRQ\n");
660 stge_detach(device_t dev)
662 struct stge_softc *sc;
665 sc = device_get_softc(dev);
668 #ifdef DEVICE_POLLING
669 if (ifp && ifp->if_capenable & IFCAP_POLLING)
670 ether_poll_deregister(ifp);
672 if (device_is_attached(dev)) {
678 callout_drain(&sc->sc_tick_ch);
679 taskqueue_drain(taskqueue_swi, &sc->sc_link_task);
683 if (sc->sc_miibus != NULL) {
684 device_delete_child(dev, sc->sc_miibus);
685 sc->sc_miibus = NULL;
687 bus_generic_detach(dev);
696 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih);
699 bus_release_resources(dev, sc->sc_spec, sc->sc_res);
701 mtx_destroy(&sc->sc_mii_mtx);
702 mtx_destroy(&sc->sc_mtx);
707 struct stge_dmamap_arg {
708 bus_addr_t stge_busaddr;
712 stge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
714 struct stge_dmamap_arg *ctx;
719 ctx = (struct stge_dmamap_arg *)arg;
720 ctx->stge_busaddr = segs[0].ds_addr;
724 stge_dma_alloc(struct stge_softc *sc)
726 struct stge_dmamap_arg ctx;
727 struct stge_txdesc *txd;
728 struct stge_rxdesc *rxd;
731 /* create parent tag. */
732 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),/* parent */
733 1, 0, /* algnmnt, boundary */
734 STGE_DMA_MAXADDR, /* lowaddr */
735 BUS_SPACE_MAXADDR, /* highaddr */
736 NULL, NULL, /* filter, filterarg */
737 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
739 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
741 NULL, NULL, /* lockfunc, lockarg */
742 &sc->sc_cdata.stge_parent_tag);
744 device_printf(sc->sc_dev, "failed to create parent DMA tag\n");
747 /* create tag for Tx ring. */
748 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
749 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
750 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
751 BUS_SPACE_MAXADDR, /* highaddr */
752 NULL, NULL, /* filter, filterarg */
753 STGE_TX_RING_SZ, /* maxsize */
755 STGE_TX_RING_SZ, /* maxsegsize */
757 NULL, NULL, /* lockfunc, lockarg */
758 &sc->sc_cdata.stge_tx_ring_tag);
760 device_printf(sc->sc_dev,
761 "failed to allocate Tx ring DMA tag\n");
765 /* create tag for Rx ring. */
766 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
767 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
768 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
769 BUS_SPACE_MAXADDR, /* highaddr */
770 NULL, NULL, /* filter, filterarg */
771 STGE_RX_RING_SZ, /* maxsize */
773 STGE_RX_RING_SZ, /* maxsegsize */
775 NULL, NULL, /* lockfunc, lockarg */
776 &sc->sc_cdata.stge_rx_ring_tag);
778 device_printf(sc->sc_dev,
779 "failed to allocate Rx ring DMA tag\n");
783 /* create tag for Tx buffers. */
784 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
785 1, 0, /* algnmnt, boundary */
786 BUS_SPACE_MAXADDR, /* lowaddr */
787 BUS_SPACE_MAXADDR, /* highaddr */
788 NULL, NULL, /* filter, filterarg */
789 MCLBYTES * STGE_MAXTXSEGS, /* maxsize */
790 STGE_MAXTXSEGS, /* nsegments */
791 MCLBYTES, /* maxsegsize */
793 NULL, NULL, /* lockfunc, lockarg */
794 &sc->sc_cdata.stge_tx_tag);
796 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n");
800 /* create tag for Rx buffers. */
801 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
802 1, 0, /* algnmnt, boundary */
803 BUS_SPACE_MAXADDR, /* lowaddr */
804 BUS_SPACE_MAXADDR, /* highaddr */
805 NULL, NULL, /* filter, filterarg */
806 MCLBYTES, /* maxsize */
808 MCLBYTES, /* maxsegsize */
810 NULL, NULL, /* lockfunc, lockarg */
811 &sc->sc_cdata.stge_rx_tag);
813 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n");
817 /* allocate DMA'able memory and load the DMA map for Tx ring. */
818 error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag,
819 (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT |
820 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_tx_ring_map);
822 device_printf(sc->sc_dev,
823 "failed to allocate DMA'able memory for Tx ring\n");
827 ctx.stge_busaddr = 0;
828 error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag,
829 sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring,
830 STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
831 if (error != 0 || ctx.stge_busaddr == 0) {
832 device_printf(sc->sc_dev,
833 "failed to load DMA'able memory for Tx ring\n");
836 sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr;
838 /* allocate DMA'able memory and load the DMA map for Rx ring. */
839 error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag,
840 (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT |
841 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_rx_ring_map);
843 device_printf(sc->sc_dev,
844 "failed to allocate DMA'able memory for Rx ring\n");
848 ctx.stge_busaddr = 0;
849 error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag,
850 sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring,
851 STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
852 if (error != 0 || ctx.stge_busaddr == 0) {
853 device_printf(sc->sc_dev,
854 "failed to load DMA'able memory for Rx ring\n");
857 sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr;
859 /* create DMA maps for Tx buffers. */
860 for (i = 0; i < STGE_TX_RING_CNT; i++) {
861 txd = &sc->sc_cdata.stge_txdesc[i];
864 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0,
867 device_printf(sc->sc_dev,
868 "failed to create Tx dmamap\n");
872 /* create DMA maps for Rx buffers. */
873 if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
874 &sc->sc_cdata.stge_rx_sparemap)) != 0) {
875 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n");
878 for (i = 0; i < STGE_RX_RING_CNT; i++) {
879 rxd = &sc->sc_cdata.stge_rxdesc[i];
882 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
885 device_printf(sc->sc_dev,
886 "failed to create Rx dmamap\n");
896 stge_dma_free(struct stge_softc *sc)
898 struct stge_txdesc *txd;
899 struct stge_rxdesc *rxd;
903 if (sc->sc_cdata.stge_tx_ring_tag) {
904 if (sc->sc_rdata.stge_tx_ring_paddr)
905 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag,
906 sc->sc_cdata.stge_tx_ring_map);
907 if (sc->sc_rdata.stge_tx_ring)
908 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag,
909 sc->sc_rdata.stge_tx_ring,
910 sc->sc_cdata.stge_tx_ring_map);
911 sc->sc_rdata.stge_tx_ring = NULL;
912 sc->sc_rdata.stge_tx_ring_paddr = 0;
913 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag);
914 sc->sc_cdata.stge_tx_ring_tag = NULL;
917 if (sc->sc_cdata.stge_rx_ring_tag) {
918 if (sc->sc_rdata.stge_rx_ring_paddr)
919 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag,
920 sc->sc_cdata.stge_rx_ring_map);
921 if (sc->sc_rdata.stge_rx_ring)
922 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag,
923 sc->sc_rdata.stge_rx_ring,
924 sc->sc_cdata.stge_rx_ring_map);
925 sc->sc_rdata.stge_rx_ring = NULL;
926 sc->sc_rdata.stge_rx_ring_paddr = 0;
927 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag);
928 sc->sc_cdata.stge_rx_ring_tag = NULL;
931 if (sc->sc_cdata.stge_tx_tag) {
932 for (i = 0; i < STGE_TX_RING_CNT; i++) {
933 txd = &sc->sc_cdata.stge_txdesc[i];
934 if (txd->tx_dmamap) {
935 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
940 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
941 sc->sc_cdata.stge_tx_tag = NULL;
944 if (sc->sc_cdata.stge_rx_tag) {
945 for (i = 0; i < STGE_RX_RING_CNT; i++) {
946 rxd = &sc->sc_cdata.stge_rxdesc[i];
947 if (rxd->rx_dmamap) {
948 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
953 if (sc->sc_cdata.stge_rx_sparemap) {
954 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
955 sc->sc_cdata.stge_rx_sparemap);
956 sc->sc_cdata.stge_rx_sparemap = 0;
958 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
959 sc->sc_cdata.stge_rx_tag = NULL;
962 if (sc->sc_cdata.stge_parent_tag) {
963 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag);
964 sc->sc_cdata.stge_parent_tag = NULL;
971 * Make sure the interface is stopped at reboot time.
974 stge_shutdown(device_t dev)
977 return (stge_suspend(dev));
981 stge_setwol(struct stge_softc *sc)
986 STGE_LOCK_ASSERT(sc);
989 v = CSR_READ_1(sc, STGE_WakeEvent);
990 /* Disable all WOL bits. */
991 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
993 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
994 v |= WE_MagicPktEnable | WE_WakeOnLanEnable;
995 CSR_WRITE_1(sc, STGE_WakeEvent, v);
996 /* Reset Tx and prevent transmission. */
997 CSR_WRITE_4(sc, STGE_AsicCtrl,
998 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset);
1000 * TC9021 automatically reset link speed to 100Mbps when it's put
1001 * into sleep so there is no need to try to resetting link speed.
1006 stge_suspend(device_t dev)
1008 struct stge_softc *sc;
1010 sc = device_get_softc(dev);
1014 sc->sc_suspended = 1;
1022 stge_resume(device_t dev)
1024 struct stge_softc *sc;
1028 sc = device_get_softc(dev);
1032 * Clear WOL bits, so special frames wouldn't interfere
1033 * normal Rx operation anymore.
1035 v = CSR_READ_1(sc, STGE_WakeEvent);
1036 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
1037 WE_WakeOnLanEnable);
1038 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1040 if (ifp->if_flags & IFF_UP)
1041 stge_init_locked(sc);
1043 sc->sc_suspended = 0;
1050 stge_dma_wait(struct stge_softc *sc)
1054 for (i = 0; i < STGE_TIMEOUT; i++) {
1056 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
1060 if (i == STGE_TIMEOUT)
1061 device_printf(sc->sc_dev, "DMA wait timed out\n");
1065 stge_encap(struct stge_softc *sc, struct mbuf **m_head)
1067 struct stge_txdesc *txd;
1068 struct stge_tfd *tfd;
1070 bus_dma_segment_t txsegs[STGE_MAXTXSEGS];
1071 int error, i, nsegs, si;
1072 uint64_t csum_flags, tfc;
1074 STGE_LOCK_ASSERT(sc);
1076 if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL)
1079 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1080 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1081 if (error == EFBIG) {
1082 m = m_collapse(*m_head, M_NOWAIT, STGE_MAXTXSEGS);
1089 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1090 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1096 } else if (error != 0)
1106 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) {
1107 if (m->m_pkthdr.csum_flags & CSUM_IP)
1108 csum_flags |= TFD_IPChecksumEnable;
1109 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1110 csum_flags |= TFD_TCPChecksumEnable;
1111 else if (m->m_pkthdr.csum_flags & CSUM_UDP)
1112 csum_flags |= TFD_UDPChecksumEnable;
1115 si = sc->sc_cdata.stge_tx_prod;
1116 tfd = &sc->sc_rdata.stge_tx_ring[si];
1117 for (i = 0; i < nsegs; i++)
1118 tfd->tfd_frags[i].frag_word0 =
1119 htole64(FRAG_ADDR(txsegs[i].ds_addr) |
1120 FRAG_LEN(txsegs[i].ds_len));
1121 sc->sc_cdata.stge_tx_cnt++;
1123 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) |
1124 TFD_FragCount(nsegs) | csum_flags;
1125 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT)
1126 tfc |= TFD_TxDMAIndicate;
1128 /* Update producer index. */
1129 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT;
1131 /* Check if we have a VLAN tag to insert. */
1132 if (m->m_flags & M_VLANTAG)
1133 tfc |= (TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vtag));
1134 tfd->tfd_control = htole64(tfc);
1136 /* Update Tx Queue. */
1137 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q);
1138 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q);
1141 /* Sync descriptors. */
1142 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1143 BUS_DMASYNC_PREWRITE);
1144 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1145 sc->sc_cdata.stge_tx_ring_map,
1146 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1152 * stge_start: [ifnet interface function]
1154 * Start packet transmission on the interface.
1157 stge_start(struct ifnet *ifp)
1159 struct stge_softc *sc;
1163 stge_start_locked(ifp);
1168 stge_start_locked(struct ifnet *ifp)
1170 struct stge_softc *sc;
1171 struct mbuf *m_head;
1176 STGE_LOCK_ASSERT(sc);
1178 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
1179 IFF_DRV_RUNNING || sc->sc_link == 0)
1182 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1183 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) {
1184 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1188 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1192 * Pack the data into the transmit ring. If we
1193 * don't have room, set the OACTIVE flag and wait
1194 * for the NIC to drain the ring.
1196 if (stge_encap(sc, &m_head)) {
1199 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1200 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1206 * If there's a BPF listener, bounce a copy of this frame
1209 ETHER_BPF_MTAP(ifp, m_head);
1214 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow);
1216 /* Set a timeout in case the chip goes out to lunch. */
1217 sc->sc_watchdog_timer = 5;
1224 * Watchdog timer handler.
1227 stge_watchdog(struct stge_softc *sc)
1231 STGE_LOCK_ASSERT(sc);
1233 if (sc->sc_watchdog_timer == 0 || --sc->sc_watchdog_timer)
1237 if_printf(sc->sc_ifp, "device timeout\n");
1238 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1239 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1240 stge_init_locked(sc);
1241 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1242 stge_start_locked(ifp);
1246 * stge_ioctl: [ifnet interface function]
1248 * Handle control requests from the operator.
1251 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1253 struct stge_softc *sc;
1255 struct mii_data *mii;
1259 ifr = (struct ifreq *)data;
1263 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU)
1265 else if (ifp->if_mtu != ifr->ifr_mtu) {
1266 ifp->if_mtu = ifr->ifr_mtu;
1268 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1269 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1270 stge_init_locked(sc);
1277 if ((ifp->if_flags & IFF_UP) != 0) {
1278 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1279 if (((ifp->if_flags ^ sc->sc_if_flags)
1280 & IFF_PROMISC) != 0)
1281 stge_set_filter(sc);
1283 if (sc->sc_detach == 0)
1284 stge_init_locked(sc);
1287 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1290 sc->sc_if_flags = ifp->if_flags;
1296 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1302 mii = device_get_softc(sc->sc_miibus);
1303 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1306 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1307 #ifdef DEVICE_POLLING
1308 if ((mask & IFCAP_POLLING) != 0) {
1309 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1310 error = ether_poll_register(stge_poll, ifp);
1314 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1315 ifp->if_capenable |= IFCAP_POLLING;
1318 error = ether_poll_deregister(ifp);
1322 CSR_WRITE_2(sc, STGE_IntEnable,
1324 ifp->if_capenable &= ~IFCAP_POLLING;
1329 if ((mask & IFCAP_HWCSUM) != 0) {
1330 ifp->if_capenable ^= IFCAP_HWCSUM;
1331 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 &&
1332 (IFCAP_HWCSUM & ifp->if_capabilities) != 0)
1333 ifp->if_hwassist = STGE_CSUM_FEATURES;
1335 ifp->if_hwassist = 0;
1337 if ((mask & IFCAP_WOL) != 0 &&
1338 (ifp->if_capabilities & IFCAP_WOL) != 0) {
1339 if ((mask & IFCAP_WOL_MAGIC) != 0)
1340 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1342 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
1343 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1344 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1346 stge_vlan_setup(sc);
1350 VLAN_CAPABILITIES(ifp);
1353 error = ether_ioctl(ifp, cmd, data);
1361 stge_link_task(void *arg, int pending)
1363 struct stge_softc *sc;
1364 struct mii_data *mii;
1368 sc = (struct stge_softc *)arg;
1371 mii = device_get_softc(sc->sc_miibus);
1372 if (mii->mii_media_status & IFM_ACTIVE) {
1373 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1379 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
1380 sc->sc_MACCtrl |= MC_DuplexSelect;
1381 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_RXPAUSE) != 0)
1382 sc->sc_MACCtrl |= MC_RxFlowControlEnable;
1383 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_TXPAUSE) != 0)
1384 sc->sc_MACCtrl |= MC_TxFlowControlEnable;
1386 * Update STGE_MACCtrl register depending on link status.
1387 * (duplex, flow control etc)
1389 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
1390 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable);
1391 v |= sc->sc_MACCtrl;
1392 CSR_WRITE_4(sc, STGE_MACCtrl, v);
1393 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) {
1394 /* Duplex setting changed, reset Tx/Rx functions. */
1395 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1396 ac |= AC_TxReset | AC_RxReset;
1397 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1398 for (i = 0; i < STGE_TIMEOUT; i++) {
1400 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1403 if (i == STGE_TIMEOUT)
1404 device_printf(sc->sc_dev, "reset failed to complete\n");
1410 stge_tx_error(struct stge_softc *sc)
1416 txstat = CSR_READ_4(sc, STGE_TxStatus);
1417 if ((txstat & TS_TxComplete) == 0)
1420 if ((txstat & TS_TxUnderrun) != 0) {
1423 * There should be a more better way to recover
1424 * from Tx underrun instead of a full reset.
1426 if (sc->sc_nerr++ < STGE_MAXERR)
1427 device_printf(sc->sc_dev, "Tx underrun, "
1429 if (sc->sc_nerr == STGE_MAXERR)
1430 device_printf(sc->sc_dev, "too many errors; "
1431 "not reporting any more\n");
1435 /* Maximum/Late collisions, Re-enable Tx MAC. */
1436 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0)
1437 CSR_WRITE_4(sc, STGE_MACCtrl,
1438 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |
1448 * Interrupt service routine.
1451 stge_intr(void *arg)
1453 struct stge_softc *sc;
1458 sc = (struct stge_softc *)arg;
1463 #ifdef DEVICE_POLLING
1464 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1467 status = CSR_READ_2(sc, STGE_IntStatus);
1468 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0)
1471 /* Disable interrupts. */
1472 for (reinit = 0;;) {
1473 status = CSR_READ_2(sc, STGE_IntStatusAck);
1474 status &= sc->sc_IntEnable;
1477 /* Host interface errors. */
1478 if ((status & IS_HostError) != 0) {
1479 device_printf(sc->sc_dev,
1480 "Host interface error, resetting...\n");
1485 /* Receive interrupts. */
1486 if ((status & IS_RxDMAComplete) != 0) {
1488 if ((status & IS_RFDListEnd) != 0)
1489 CSR_WRITE_4(sc, STGE_DMACtrl,
1493 /* Transmit interrupts. */
1494 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0)
1497 /* Transmission errors.*/
1498 if ((status & IS_TxComplete) != 0) {
1499 if ((reinit = stge_tx_error(sc)) != 0)
1506 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1507 stge_init_locked(sc);
1510 /* Re-enable interrupts. */
1511 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1513 /* Try to get more packets going. */
1514 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1515 stge_start_locked(ifp);
1524 * Helper; handle transmit interrupts.
1527 stge_txeof(struct stge_softc *sc)
1530 struct stge_txdesc *txd;
1534 STGE_LOCK_ASSERT(sc);
1538 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1541 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1542 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD);
1545 * Go through our Tx list and free mbufs for those
1546 * frames which have been transmitted.
1548 for (cons = sc->sc_cdata.stge_tx_cons;;
1549 cons = (cons + 1) % STGE_TX_RING_CNT) {
1550 if (sc->sc_cdata.stge_tx_cnt <= 0)
1552 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control);
1553 if ((control & TFD_TFDDone) == 0)
1555 sc->sc_cdata.stge_tx_cnt--;
1556 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1558 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1559 BUS_DMASYNC_POSTWRITE);
1560 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap);
1562 /* Output counter is updated with statistics register */
1565 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q);
1566 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
1567 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1569 sc->sc_cdata.stge_tx_cons = cons;
1570 if (sc->sc_cdata.stge_tx_cnt == 0)
1571 sc->sc_watchdog_timer = 0;
1573 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1574 sc->sc_cdata.stge_tx_ring_map,
1575 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1578 static __inline void
1579 stge_discard_rxbuf(struct stge_softc *sc, int idx)
1581 struct stge_rfd *rfd;
1583 rfd = &sc->sc_rdata.stge_rx_ring[idx];
1584 rfd->rfd_status = 0;
1587 #ifndef __NO_STRICT_ALIGNMENT
1589 * It seems that TC9021's DMA engine has alignment restrictions in
1590 * DMA scatter operations. The first DMA segment has no address
1591 * alignment restrictins but the rest should be aligned on 4(?) bytes
1592 * boundary. Otherwise it would corrupt random memory. Since we don't
1593 * know which one is used for the first segment in advance we simply
1594 * don't align at all.
1595 * To avoid copying over an entire frame to align, we allocate a new
1596 * mbuf and copy ethernet header to the new mbuf. The new mbuf is
1597 * prepended into the existing mbuf chain.
1599 static __inline struct mbuf *
1600 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m)
1605 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
1606 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
1607 m->m_data += ETHER_HDR_LEN;
1610 MGETHDR(n, M_NOWAIT, MT_DATA);
1612 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
1613 m->m_data += ETHER_HDR_LEN;
1614 m->m_len -= ETHER_HDR_LEN;
1615 n->m_len = ETHER_HDR_LEN;
1616 M_MOVE_PKTHDR(n, m);
1629 * Helper; handle receive interrupts.
1632 stge_rxeof(struct stge_softc *sc)
1635 struct stge_rxdesc *rxd;
1636 struct mbuf *mp, *m;
1639 int cons, prog, rx_npkts;
1641 STGE_LOCK_ASSERT(sc);
1646 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1647 sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD);
1650 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT;
1651 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) {
1652 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status);
1653 status = RFD_RxStatus(status64);
1654 if ((status & RFD_RFDDone) == 0)
1656 #ifdef DEVICE_POLLING
1657 if (ifp->if_capenable & IFCAP_POLLING) {
1658 if (sc->sc_cdata.stge_rxcycles <= 0)
1660 sc->sc_cdata.stge_rxcycles--;
1664 rxd = &sc->sc_cdata.stge_rxdesc[cons];
1668 * If the packet had an error, drop it. Note we count
1669 * the error later in the periodic stats update.
1671 if ((status & RFD_FrameEnd) != 0 && (status &
1672 (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
1673 RFD_RxAlignmentError | RFD_RxFCSError |
1674 RFD_RxLengthError)) != 0) {
1675 stge_discard_rxbuf(sc, cons);
1676 if (sc->sc_cdata.stge_rxhead != NULL) {
1677 m_freem(sc->sc_cdata.stge_rxhead);
1678 STGE_RXCHAIN_RESET(sc);
1683 * Add a new receive buffer to the ring.
1685 if (stge_newbuf(sc, cons) != 0) {
1686 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1687 stge_discard_rxbuf(sc, cons);
1688 if (sc->sc_cdata.stge_rxhead != NULL) {
1689 m_freem(sc->sc_cdata.stge_rxhead);
1690 STGE_RXCHAIN_RESET(sc);
1695 if ((status & RFD_FrameEnd) != 0)
1696 mp->m_len = RFD_RxDMAFrameLen(status) -
1697 sc->sc_cdata.stge_rxlen;
1698 sc->sc_cdata.stge_rxlen += mp->m_len;
1701 if (sc->sc_cdata.stge_rxhead == NULL) {
1702 sc->sc_cdata.stge_rxhead = mp;
1703 sc->sc_cdata.stge_rxtail = mp;
1705 mp->m_flags &= ~M_PKTHDR;
1706 sc->sc_cdata.stge_rxtail->m_next = mp;
1707 sc->sc_cdata.stge_rxtail = mp;
1710 if ((status & RFD_FrameEnd) != 0) {
1711 m = sc->sc_cdata.stge_rxhead;
1712 m->m_pkthdr.rcvif = ifp;
1713 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen;
1715 if (m->m_pkthdr.len > sc->sc_if_framesize) {
1717 STGE_RXCHAIN_RESET(sc);
1721 * Set the incoming checksum information for
1724 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1725 if ((status & RFD_IPDetected) != 0) {
1726 m->m_pkthdr.csum_flags |=
1728 if ((status & RFD_IPError) == 0)
1729 m->m_pkthdr.csum_flags |=
1732 if (((status & RFD_TCPDetected) != 0 &&
1733 (status & RFD_TCPError) == 0) ||
1734 ((status & RFD_UDPDetected) != 0 &&
1735 (status & RFD_UDPError) == 0)) {
1736 m->m_pkthdr.csum_flags |=
1737 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1738 m->m_pkthdr.csum_data = 0xffff;
1742 #ifndef __NO_STRICT_ALIGNMENT
1743 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) {
1744 if ((m = stge_fixup_rx(sc, m)) == NULL) {
1745 STGE_RXCHAIN_RESET(sc);
1750 /* Check for VLAN tagged packets. */
1751 if ((status & RFD_VLANDetected) != 0 &&
1752 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
1753 m->m_pkthdr.ether_vtag = RFD_TCI(status64);
1754 m->m_flags |= M_VLANTAG;
1759 (*ifp->if_input)(ifp, m);
1763 STGE_RXCHAIN_RESET(sc);
1768 /* Update the consumer index. */
1769 sc->sc_cdata.stge_rx_cons = cons;
1770 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1771 sc->sc_cdata.stge_rx_ring_map,
1772 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1777 #ifdef DEVICE_POLLING
1779 stge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1781 struct stge_softc *sc;
1788 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1793 sc->sc_cdata.stge_rxcycles = count;
1794 rx_npkts = stge_rxeof(sc);
1797 if (cmd == POLL_AND_CHECK_STATUS) {
1798 status = CSR_READ_2(sc, STGE_IntStatus);
1799 status &= sc->sc_IntEnable;
1801 if ((status & IS_HostError) != 0) {
1802 device_printf(sc->sc_dev,
1803 "Host interface error, resetting...\n");
1804 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1805 stge_init_locked(sc);
1807 if ((status & IS_TxComplete) != 0) {
1808 if (stge_tx_error(sc) != 0) {
1809 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1810 stge_init_locked(sc);
1817 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1818 stge_start_locked(ifp);
1823 #endif /* DEVICE_POLLING */
1828 * One second timer, used to tick the MII.
1831 stge_tick(void *arg)
1833 struct stge_softc *sc;
1834 struct mii_data *mii;
1836 sc = (struct stge_softc *)arg;
1838 STGE_LOCK_ASSERT(sc);
1840 mii = device_get_softc(sc->sc_miibus);
1843 /* Update statistics counters. */
1844 stge_stats_update(sc);
1847 * Relcaim any pending Tx descriptors to release mbufs in a
1848 * timely manner as we don't generate Tx completion interrupts
1849 * for every frame. This limits the delay to a maximum of one
1852 if (sc->sc_cdata.stge_tx_cnt != 0)
1857 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
1861 * stge_stats_update:
1863 * Read the TC9021 statistics counters.
1866 stge_stats_update(struct stge_softc *sc)
1870 STGE_LOCK_ASSERT(sc);
1874 CSR_READ_4(sc,STGE_OctetRcvOk);
1876 if_inc_counter(ifp, IFCOUNTER_IPACKETS, CSR_READ_4(sc, STGE_FramesRcvdOk));
1878 if_inc_counter(ifp, IFCOUNTER_IERRORS, CSR_READ_2(sc, STGE_FramesLostRxErrors));
1880 CSR_READ_4(sc, STGE_OctetXmtdOk);
1882 if_inc_counter(ifp, IFCOUNTER_OPACKETS, CSR_READ_4(sc, STGE_FramesXmtdOk));
1884 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1885 CSR_READ_4(sc, STGE_LateCollisions) +
1886 CSR_READ_4(sc, STGE_MultiColFrames) +
1887 CSR_READ_4(sc, STGE_SingleColFrames));
1889 if_inc_counter(ifp, IFCOUNTER_OERRORS,
1890 CSR_READ_2(sc, STGE_FramesAbortXSColls) +
1891 CSR_READ_2(sc, STGE_FramesWEXDeferal));
1897 * Perform a soft reset on the TC9021.
1900 stge_reset(struct stge_softc *sc, uint32_t how)
1906 STGE_LOCK_ASSERT(sc);
1909 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1912 ac |= AC_TxReset | AC_FIFO;
1916 ac |= AC_RxReset | AC_FIFO;
1919 case STGE_RESET_FULL:
1922 * Only assert RstOut if we're fiber. We need GMII clocks
1923 * to be present in order for the reset to complete on fiber
1926 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset |
1927 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
1928 (sc->sc_usefiber ? AC_RstOut : 0);
1932 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1934 /* Account for reset problem at 10Mbps. */
1937 for (i = 0; i < STGE_TIMEOUT; i++) {
1938 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1943 if (i == STGE_TIMEOUT)
1944 device_printf(sc->sc_dev, "reset failed to complete\n");
1946 /* Set LED, from Linux IPG driver. */
1947 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1948 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1);
1949 if ((sc->sc_led & 0x01) != 0)
1951 if ((sc->sc_led & 0x03) != 0)
1952 ac |= AC_LEDModeBit1;
1953 if ((sc->sc_led & 0x08) != 0)
1955 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1957 /* Set PHY, from Linux IPG driver */
1958 v = CSR_READ_1(sc, STGE_PhySet);
1959 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet);
1960 v |= ((sc->sc_led & 0x70) >> 4);
1961 CSR_WRITE_1(sc, STGE_PhySet, v);
1965 * stge_init: [ ifnet interface function ]
1967 * Initialize the interface.
1970 stge_init(void *xsc)
1972 struct stge_softc *sc;
1974 sc = (struct stge_softc *)xsc;
1976 stge_init_locked(sc);
1981 stge_init_locked(struct stge_softc *sc)
1984 struct mii_data *mii;
1989 STGE_LOCK_ASSERT(sc);
1992 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1994 mii = device_get_softc(sc->sc_miibus);
1997 * Cancel any pending I/O.
2002 * Reset the chip to a known state.
2004 stge_reset(sc, STGE_RESET_FULL);
2006 /* Init descriptors. */
2007 error = stge_init_rx_ring(sc);
2009 device_printf(sc->sc_dev,
2010 "initialization failed: no memory for rx buffers\n");
2014 stge_init_tx_ring(sc);
2016 /* Set the station address. */
2017 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2018 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
2019 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
2020 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
2023 * Set the statistics masks. Disable all the RMON stats,
2024 * and disable selected stats in the non-RMON stats registers.
2026 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
2027 CSR_WRITE_4(sc, STGE_StatisticsMask,
2028 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
2029 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
2030 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
2033 /* Set up the receive filter. */
2034 stge_set_filter(sc);
2035 /* Program multicast filter. */
2039 * Give the transmit and receive ring to the chip.
2041 CSR_WRITE_4(sc, STGE_TFDListPtrHi,
2042 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0)));
2043 CSR_WRITE_4(sc, STGE_TFDListPtrLo,
2044 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0)));
2046 CSR_WRITE_4(sc, STGE_RFDListPtrHi,
2047 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0)));
2048 CSR_WRITE_4(sc, STGE_RFDListPtrLo,
2049 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0)));
2052 * Initialize the Tx auto-poll period. It's OK to make this number
2053 * large (255 is the max, but we use 127) -- we explicitly kick the
2054 * transmit engine when there's actually a packet.
2056 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2058 /* ..and the Rx auto-poll period. */
2059 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2061 /* Initialize the Tx start threshold. */
2062 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
2064 /* Rx DMA thresholds, from Linux */
2065 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
2066 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
2068 /* Rx early threhold, from Linux */
2069 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
2071 /* Tx DMA thresholds, from Linux */
2072 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
2073 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
2076 * Initialize the Rx DMA interrupt control register. We
2077 * request an interrupt after every incoming packet, but
2078 * defer it for sc_rxint_dmawait us. When the number of
2079 * interrupts pending reaches STGE_RXINT_NFRAME, we stop
2080 * deferring the interrupt, and signal it immediately.
2082 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
2083 RDIC_RxFrameCount(sc->sc_rxint_nframe) |
2084 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait)));
2087 * Initialize the interrupt mask.
2089 sc->sc_IntEnable = IS_HostError | IS_TxComplete |
2090 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
2091 #ifdef DEVICE_POLLING
2092 /* Disable interrupts if we are polling. */
2093 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
2094 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2097 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2100 * Configure the DMA engine.
2101 * XXX Should auto-tune TxBurstLimit.
2103 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3));
2106 * Send a PAUSE frame when we reach 29,696 bytes in the Rx
2107 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes
2110 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
2111 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
2114 * Set the maximum frame size.
2116 sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2117 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize);
2120 * Initialize MacCtrl -- do it before setting the media,
2121 * as setting the media will actually program the register.
2123 * Note: We have to poke the IFS value before poking
2126 /* Tx/Rx MAC should be disabled before programming IFS.*/
2127 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit));
2129 stge_vlan_setup(sc);
2131 if (sc->sc_rev >= 6) { /* >= B.2 */
2132 /* Multi-frag frame bug work-around. */
2133 CSR_WRITE_2(sc, STGE_DebugCtrl,
2134 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
2136 /* Tx Poll Now bug work-around. */
2137 CSR_WRITE_2(sc, STGE_DebugCtrl,
2138 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
2139 /* Tx Poll Now bug work-around. */
2140 CSR_WRITE_2(sc, STGE_DebugCtrl,
2141 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
2144 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2145 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
2146 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2148 * It seems that transmitting frames without checking the state of
2149 * Rx/Tx MAC wedge the hardware.
2156 * Set the current media.
2161 * Start the one second MII clock.
2163 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
2168 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2169 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2173 device_printf(sc->sc_dev, "interface not running\n");
2177 stge_vlan_setup(struct stge_softc *sc)
2184 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl
2185 * MC_AutoVLANuntagging bit.
2186 * MC_AutoVLANtagging bit selects which VLAN source to use
2187 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert
2188 * bit has priority over MC_AutoVLANtagging bit. So we always
2189 * use TFC instead of STGE_VLANTag register.
2191 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2192 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2193 v |= MC_AutoVLANuntagging;
2195 v &= ~MC_AutoVLANuntagging;
2196 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2200 * Stop transmission on the interface.
2203 stge_stop(struct stge_softc *sc)
2206 struct stge_txdesc *txd;
2207 struct stge_rxdesc *rxd;
2211 STGE_LOCK_ASSERT(sc);
2213 * Stop the one second clock.
2215 callout_stop(&sc->sc_tick_ch);
2216 sc->sc_watchdog_timer = 0;
2219 * Disable interrupts.
2221 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2224 * Stop receiver, transmitter, and stats update.
2228 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2229 v |= MC_StatisticsDisable;
2230 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2233 * Stop the transmit and receive DMA.
2236 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
2237 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
2238 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
2239 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
2242 * Free RX and TX mbufs still in the queues.
2244 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2245 rxd = &sc->sc_cdata.stge_rxdesc[i];
2246 if (rxd->rx_m != NULL) {
2247 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag,
2248 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2249 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag,
2255 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2256 txd = &sc->sc_cdata.stge_txdesc[i];
2257 if (txd->tx_m != NULL) {
2258 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag,
2259 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2260 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag,
2268 * Mark the interface down and cancel the watchdog timer.
2271 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2276 stge_start_tx(struct stge_softc *sc)
2281 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2282 if ((v & MC_TxEnabled) != 0)
2285 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2286 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2287 for (i = STGE_TIMEOUT; i > 0; i--) {
2289 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2290 if ((v & MC_TxEnabled) != 0)
2294 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n");
2298 stge_start_rx(struct stge_softc *sc)
2303 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2304 if ((v & MC_RxEnabled) != 0)
2307 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2308 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2309 for (i = STGE_TIMEOUT; i > 0; i--) {
2311 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2312 if ((v & MC_RxEnabled) != 0)
2316 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n");
2320 stge_stop_tx(struct stge_softc *sc)
2325 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2326 if ((v & MC_TxEnabled) == 0)
2329 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2330 for (i = STGE_TIMEOUT; i > 0; i--) {
2332 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2333 if ((v & MC_TxEnabled) == 0)
2337 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n");
2341 stge_stop_rx(struct stge_softc *sc)
2346 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2347 if ((v & MC_RxEnabled) == 0)
2350 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2351 for (i = STGE_TIMEOUT; i > 0; i--) {
2353 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2354 if ((v & MC_RxEnabled) == 0)
2358 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n");
2362 stge_init_tx_ring(struct stge_softc *sc)
2364 struct stge_ring_data *rd;
2365 struct stge_txdesc *txd;
2369 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq);
2370 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq);
2372 sc->sc_cdata.stge_tx_prod = 0;
2373 sc->sc_cdata.stge_tx_cons = 0;
2374 sc->sc_cdata.stge_tx_cnt = 0;
2377 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ);
2378 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2379 if (i == (STGE_TX_RING_CNT - 1))
2380 addr = STGE_TX_RING_ADDR(sc, 0);
2382 addr = STGE_TX_RING_ADDR(sc, i + 1);
2383 rd->stge_tx_ring[i].tfd_next = htole64(addr);
2384 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone);
2385 txd = &sc->sc_cdata.stge_txdesc[i];
2386 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
2389 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
2390 sc->sc_cdata.stge_tx_ring_map,
2391 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2396 stge_init_rx_ring(struct stge_softc *sc)
2398 struct stge_ring_data *rd;
2402 sc->sc_cdata.stge_rx_cons = 0;
2403 STGE_RXCHAIN_RESET(sc);
2406 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ);
2407 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2408 if (stge_newbuf(sc, i) != 0)
2410 if (i == (STGE_RX_RING_CNT - 1))
2411 addr = STGE_RX_RING_ADDR(sc, 0);
2413 addr = STGE_RX_RING_ADDR(sc, i + 1);
2414 rd->stge_rx_ring[i].rfd_next = htole64(addr);
2415 rd->stge_rx_ring[i].rfd_status = 0;
2418 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
2419 sc->sc_cdata.stge_rx_ring_map,
2420 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2428 * Add a receive buffer to the indicated descriptor.
2431 stge_newbuf(struct stge_softc *sc, int idx)
2433 struct stge_rxdesc *rxd;
2434 struct stge_rfd *rfd;
2436 bus_dma_segment_t segs[1];
2440 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2443 m->m_len = m->m_pkthdr.len = MCLBYTES;
2445 * The hardware requires 4bytes aligned DMA address when JUMBO
2448 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN))
2449 m_adj(m, ETHER_ALIGN);
2451 if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag,
2452 sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2456 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2458 rxd = &sc->sc_cdata.stge_rxdesc[idx];
2459 if (rxd->rx_m != NULL) {
2460 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2461 BUS_DMASYNC_POSTREAD);
2462 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap);
2464 map = rxd->rx_dmamap;
2465 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap;
2466 sc->sc_cdata.stge_rx_sparemap = map;
2467 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2468 BUS_DMASYNC_PREREAD);
2471 rfd = &sc->sc_rdata.stge_rx_ring[idx];
2472 rfd->rfd_frag.frag_word0 =
2473 htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len));
2474 rfd->rfd_status = 0;
2482 * Set up the receive filter.
2485 stge_set_filter(struct stge_softc *sc)
2490 STGE_LOCK_ASSERT(sc);
2494 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2495 mode |= RM_ReceiveUnicast;
2496 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2497 mode |= RM_ReceiveBroadcast;
2499 mode &= ~RM_ReceiveBroadcast;
2500 if ((ifp->if_flags & IFF_PROMISC) != 0)
2501 mode |= RM_ReceiveAllFrames;
2503 mode &= ~RM_ReceiveAllFrames;
2505 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2509 stge_set_multi(struct stge_softc *sc)
2512 struct ifmultiaddr *ifma;
2518 STGE_LOCK_ASSERT(sc);
2522 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2523 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2524 if ((ifp->if_flags & IFF_PROMISC) != 0)
2525 mode |= RM_ReceiveAllFrames;
2526 else if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2527 mode |= RM_ReceiveMulticast;
2528 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2532 /* clear existing filters. */
2533 CSR_WRITE_4(sc, STGE_HashTable0, 0);
2534 CSR_WRITE_4(sc, STGE_HashTable1, 0);
2537 * Set up the multicast address filter by passing all multicast
2538 * addresses through a CRC generator, and then using the low-order
2539 * 6 bits as an index into the 64 bit multicast hash table. The
2540 * high order bits select the register, while the rest of the bits
2541 * select the bit within the register.
2544 bzero(mchash, sizeof(mchash));
2547 if_maddr_rlock(sc->sc_ifp);
2548 TAILQ_FOREACH(ifma, &sc->sc_ifp->if_multiaddrs, ifma_link) {
2549 if (ifma->ifma_addr->sa_family != AF_LINK)
2551 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2552 ifma->ifma_addr), ETHER_ADDR_LEN);
2554 /* Just want the 6 least significant bits. */
2557 /* Set the corresponding bit in the hash table. */
2558 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2561 if_maddr_runlock(ifp);
2563 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames);
2565 mode |= RM_ReceiveMulticastHash;
2567 mode &= ~RM_ReceiveMulticastHash;
2569 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
2570 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
2571 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2575 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2581 value = *(int *)arg1;
2582 error = sysctl_handle_int(oidp, &value, 0, req);
2583 if (error || !req->newptr)
2585 if (value < low || value > high)
2587 *(int *)arg1 = value;
2593 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS)
2595 return (sysctl_int_range(oidp, arg1, arg2, req,
2596 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX));
2600 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS)
2602 return (sysctl_int_range(oidp, arg1, arg2, req,
2603 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX));