1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
40 * Device driver for the Sundance Tech. TC9021 10/100/1000
41 * Ethernet controller.
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD$");
47 #ifdef HAVE_KERNEL_OPTION_HEADERS
48 #include "opt_device_polling.h"
51 #include <sys/param.h>
52 #include <sys/systm.h>
53 #include <sys/endian.h>
55 #include <sys/malloc.h>
56 #include <sys/kernel.h>
57 #include <sys/module.h>
58 #include <sys/socket.h>
59 #include <sys/sockio.h>
60 #include <sys/sysctl.h>
61 #include <sys/taskqueue.h>
64 #include <net/ethernet.h>
66 #include <net/if_dl.h>
67 #include <net/if_media.h>
68 #include <net/if_types.h>
69 #include <net/if_vlan_var.h>
71 #include <machine/bus.h>
72 #include <machine/resource.h>
76 #include <dev/mii/mii.h>
77 #include <dev/mii/miivar.h>
79 #include <dev/pci/pcireg.h>
80 #include <dev/pci/pcivar.h>
82 #include <dev/stge/if_stgereg.h>
84 #define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
86 MODULE_DEPEND(stge, pci, 1, 1, 1);
87 MODULE_DEPEND(stge, ether, 1, 1, 1);
88 MODULE_DEPEND(stge, miibus, 1, 1, 1);
90 /* "device miibus" required. See GENERIC if you get errors here. */
91 #include "miibus_if.h"
94 * Devices supported by this driver.
96 static struct stge_product {
97 uint16_t stge_vendorid;
98 uint16_t stge_deviceid;
99 const char *stge_name;
100 } stge_products[] = {
101 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023,
102 "Sundance ST-1023 Gigabit Ethernet" },
104 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021,
105 "Sundance ST-2021 Gigabit Ethernet" },
107 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021,
108 "Tamarack TC9021 Gigabit Ethernet" },
110 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT,
111 "Tamarack TC9021 Gigabit Ethernet" },
114 * The Sundance sample boards use the Sundance vendor ID,
115 * but the Tamarack product ID.
117 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021,
118 "Sundance TC9021 Gigabit Ethernet" },
120 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT,
121 "Sundance TC9021 Gigabit Ethernet" },
123 { VENDOR_DLINK, DEVICEID_DLINK_DL4000,
124 "D-Link DL-4000 Gigabit Ethernet" },
126 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021,
127 "Antares Gigabit Ethernet" }
130 static int stge_probe(device_t);
131 static int stge_attach(device_t);
132 static int stge_detach(device_t);
133 static void stge_shutdown(device_t);
134 static int stge_suspend(device_t);
135 static int stge_resume(device_t);
137 static int stge_encap(struct stge_softc *, struct mbuf **);
138 static void stge_start(struct ifnet *);
139 static void stge_start_locked(struct ifnet *);
140 static void stge_watchdog(struct ifnet *);
141 static int stge_ioctl(struct ifnet *, u_long, caddr_t);
142 static void stge_init(void *);
143 static void stge_init_locked(struct stge_softc *);
144 static void stge_vlan_setup(struct stge_softc *);
145 static void stge_stop(struct stge_softc *);
146 static void stge_start_tx(struct stge_softc *);
147 static void stge_start_rx(struct stge_softc *);
148 static void stge_stop_tx(struct stge_softc *);
149 static void stge_stop_rx(struct stge_softc *);
151 static void stge_reset(struct stge_softc *, uint32_t);
152 static int stge_eeprom_wait(struct stge_softc *);
153 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *);
154 static void stge_tick(void *);
155 static void stge_stats_update(struct stge_softc *);
156 static void stge_set_filter(struct stge_softc *);
157 static void stge_set_multi(struct stge_softc *);
159 static void stge_link_task(void *, int);
160 static void stge_intr(void *);
161 static __inline int stge_tx_error(struct stge_softc *);
162 static void stge_txeof(struct stge_softc *);
163 static void stge_rxeof(struct stge_softc *);
164 static __inline void stge_discard_rxbuf(struct stge_softc *, int);
165 static int stge_newbuf(struct stge_softc *, int);
166 #ifndef __NO_STRICT_ALIGNMENT
167 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *);
170 static void stge_mii_sync(struct stge_softc *);
171 static void stge_mii_send(struct stge_softc *, uint32_t, int);
172 static int stge_mii_readreg(struct stge_softc *, struct stge_mii_frame *);
173 static int stge_mii_writereg(struct stge_softc *, struct stge_mii_frame *);
174 static int stge_miibus_readreg(device_t, int, int);
175 static int stge_miibus_writereg(device_t, int, int, int);
176 static void stge_miibus_statchg(device_t);
177 static int stge_mediachange(struct ifnet *);
178 static void stge_mediastatus(struct ifnet *, struct ifmediareq *);
180 static void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
181 static int stge_dma_alloc(struct stge_softc *);
182 static void stge_dma_free(struct stge_softc *);
183 static void stge_dma_wait(struct stge_softc *);
184 static void stge_init_tx_ring(struct stge_softc *);
185 static int stge_init_rx_ring(struct stge_softc *);
186 #ifdef DEVICE_POLLING
187 static void stge_poll(struct ifnet *, enum poll_cmd, int);
190 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
191 static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS);
192 static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS);
194 static device_method_t stge_methods[] = {
195 /* Device interface */
196 DEVMETHOD(device_probe, stge_probe),
197 DEVMETHOD(device_attach, stge_attach),
198 DEVMETHOD(device_detach, stge_detach),
199 DEVMETHOD(device_shutdown, stge_shutdown),
200 DEVMETHOD(device_suspend, stge_suspend),
201 DEVMETHOD(device_resume, stge_resume),
204 DEVMETHOD(miibus_readreg, stge_miibus_readreg),
205 DEVMETHOD(miibus_writereg, stge_miibus_writereg),
206 DEVMETHOD(miibus_statchg, stge_miibus_statchg),
212 static driver_t stge_driver = {
215 sizeof(struct stge_softc)
218 static devclass_t stge_devclass;
220 DRIVER_MODULE(stge, pci, stge_driver, stge_devclass, 0, 0);
221 DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, 0, 0);
223 static struct resource_spec stge_res_spec_io[] = {
224 { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE },
225 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
229 static struct resource_spec stge_res_spec_mem[] = {
230 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE },
231 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
236 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) | (x))
238 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) & ~(x))
241 * Sync the PHYs by setting data bit and strobing the clock 32 times.
244 stge_mii_sync(struct stge_softc *sc)
248 MII_SET(PC_MgmtDir | PC_MgmtData);
250 for (i = 0; i < 32; i++) {
259 * Clock a series of bits through the MII.
262 stge_mii_send(struct stge_softc *sc, uint32_t bits, int cnt)
268 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
270 MII_SET(PC_MgmtData);
272 MII_CLR(PC_MgmtData);
281 * Read an PHY register through the MII.
284 stge_mii_readreg(struct stge_softc *sc, struct stge_mii_frame *frame)
289 * Set up frame for RX.
291 frame->mii_stdelim = STGE_MII_STARTDELIM;
292 frame->mii_opcode = STGE_MII_READOP;
293 frame->mii_turnaround = 0;
296 CSR_WRITE_1(sc, STGE_PhyCtrl, 0 | sc->sc_PhyCtrl);
305 * Send command/address info.
307 stge_mii_send(sc, frame->mii_stdelim, 2);
308 stge_mii_send(sc, frame->mii_opcode, 2);
309 stge_mii_send(sc, frame->mii_phyaddr, 5);
310 stge_mii_send(sc, frame->mii_regaddr, 5);
316 MII_CLR((PC_MgmtClk | PC_MgmtData));
324 ack = CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData;
329 * Now try reading data bits. If the ack failed, we still
330 * need to clock through 16 cycles to keep the PHY(s) in sync.
333 for(i = 0; i < 16; i++) {
342 for (i = 0x8000; i; i >>= 1) {
346 if (CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData)
347 frame->mii_data |= i;
366 * Write to a PHY register through the MII.
369 stge_mii_writereg(struct stge_softc *sc, struct stge_mii_frame *frame)
373 * Set up frame for TX.
375 frame->mii_stdelim = STGE_MII_STARTDELIM;
376 frame->mii_opcode = STGE_MII_WRITEOP;
377 frame->mii_turnaround = STGE_MII_TURNAROUND;
380 * Turn on data output.
386 stge_mii_send(sc, frame->mii_stdelim, 2);
387 stge_mii_send(sc, frame->mii_opcode, 2);
388 stge_mii_send(sc, frame->mii_phyaddr, 5);
389 stge_mii_send(sc, frame->mii_regaddr, 5);
390 stge_mii_send(sc, frame->mii_turnaround, 2);
391 stge_mii_send(sc, frame->mii_data, 16);
408 * sc_miibus_readreg: [mii interface function]
410 * Read a PHY register on the MII of the TC9021.
413 stge_miibus_readreg(device_t dev, int phy, int reg)
415 struct stge_softc *sc;
416 struct stge_mii_frame frame;
419 sc = device_get_softc(dev);
421 if (reg == STGE_PhyCtrl) {
422 /* XXX allow ip1000phy read STGE_PhyCtrl register. */
424 error = CSR_READ_1(sc, STGE_PhyCtrl);
428 bzero(&frame, sizeof(frame));
429 frame.mii_phyaddr = phy;
430 frame.mii_regaddr = reg;
433 error = stge_mii_readreg(sc, &frame);
437 /* Don't show errors for PHY probe request */
439 device_printf(sc->sc_dev, "phy read fail\n");
442 return (frame.mii_data);
446 * stge_miibus_writereg: [mii interface function]
448 * Write a PHY register on the MII of the TC9021.
451 stge_miibus_writereg(device_t dev, int phy, int reg, int val)
453 struct stge_softc *sc;
454 struct stge_mii_frame frame;
457 sc = device_get_softc(dev);
459 bzero(&frame, sizeof(frame));
460 frame.mii_phyaddr = phy;
461 frame.mii_regaddr = reg;
462 frame.mii_data = val;
465 error = stge_mii_writereg(sc, &frame);
469 device_printf(sc->sc_dev, "phy write fail\n");
474 * stge_miibus_statchg: [mii interface function]
476 * Callback from MII layer when media changes.
479 stge_miibus_statchg(device_t dev)
481 struct stge_softc *sc;
482 struct mii_data *mii;
484 sc = device_get_softc(dev);
485 mii = device_get_softc(sc->sc_miibus);
488 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE) {
494 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
495 sc->sc_MACCtrl |= MC_DuplexSelect;
496 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) != 0)
497 sc->sc_MACCtrl |= MC_RxFlowControlEnable;
498 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) != 0)
499 sc->sc_MACCtrl |= MC_TxFlowControlEnable;
501 * We can't access STGE_MACCtrl register in this context due to
502 * the races between MII layer and driver which accesses this
503 * register to program MAC. In order to solve the race, we defer
504 * STGE_MACCtrl programming until we know we are out of MII.
506 taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task);
511 * stge_mediastatus: [ifmedia interface function]
513 * Get the current interface media status.
516 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
518 struct stge_softc *sc;
519 struct mii_data *mii;
522 mii = device_get_softc(sc->sc_miibus);
525 ifmr->ifm_status = mii->mii_media_status;
526 ifmr->ifm_active = mii->mii_media_active;
530 * stge_mediachange: [ifmedia interface function]
532 * Set hardware to newly-selected media.
535 stge_mediachange(struct ifnet *ifp)
537 struct stge_softc *sc;
538 struct mii_data *mii;
541 mii = device_get_softc(sc->sc_miibus);
548 stge_eeprom_wait(struct stge_softc *sc)
552 for (i = 0; i < STGE_TIMEOUT; i++) {
554 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
563 * Read data from the serial EEPROM.
566 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
569 if (stge_eeprom_wait(sc))
570 device_printf(sc->sc_dev, "EEPROM failed to come ready\n");
572 CSR_WRITE_2(sc, STGE_EepromCtrl,
573 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
574 if (stge_eeprom_wait(sc))
575 device_printf(sc->sc_dev, "EEPROM read timed out\n");
576 *data = CSR_READ_2(sc, STGE_EepromData);
581 stge_probe(device_t dev)
583 struct stge_product *sp;
585 uint16_t vendor, devid;
587 vendor = pci_get_vendor(dev);
588 devid = pci_get_device(dev);
590 for (i = 0; i < sizeof(stge_products)/sizeof(stge_products[0]);
592 if (vendor == sp->stge_vendorid &&
593 devid == sp->stge_deviceid) {
594 device_set_desc(dev, sp->stge_name);
595 return (BUS_PROBE_DEFAULT);
603 stge_attach(device_t dev)
605 struct stge_softc *sc;
607 uint8_t enaddr[ETHER_ADDR_LEN];
613 sc = device_get_softc(dev);
616 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
618 mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF);
619 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
620 TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc);
625 pci_enable_busmaster(dev);
626 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
627 val = pci_read_config(dev, PCIR_BAR(1), 4);
628 if ((val & 0x01) != 0)
629 sc->sc_spec = stge_res_spec_mem;
631 val = pci_read_config(dev, PCIR_BAR(0), 4);
632 if ((val & 0x01) == 0) {
633 device_printf(sc->sc_dev, "couldn't locate IO BAR\n");
637 sc->sc_spec = stge_res_spec_io;
639 error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res);
641 device_printf(dev, "couldn't allocate %s resources\n",
642 sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O");
645 sc->sc_rev = pci_get_revid(dev);
647 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
648 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
649 "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0,
650 sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe");
652 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
653 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
654 "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0,
655 sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait");
657 /* Pull in device tunables. */
658 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
659 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
660 "rxint_nframe", &sc->sc_rxint_nframe);
662 if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN ||
663 sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) {
664 device_printf(dev, "rxint_nframe value out of range; "
665 "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT);
666 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
670 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
671 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
672 "rxint_dmawait", &sc->sc_rxint_dmawait);
674 if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN ||
675 sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) {
676 device_printf(dev, "rxint_dmawait value out of range; "
677 "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT);
678 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
682 if ((error = stge_dma_alloc(sc) != 0))
686 * Determine if we're copper or fiber. It affects how we
689 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
694 /* Load LED configuration from EEPROM. */
695 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led);
698 * Reset the chip to a known state.
701 stge_reset(sc, STGE_RESET_FULL);
705 * Reading the station address from the EEPROM doesn't seem
706 * to work, at least on my sample boards. Instead, since
707 * the reset sequence does AutoInit, read it from the station
708 * address registers. For Sundance 1023 you can only read it
711 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) {
714 v = CSR_READ_2(sc, STGE_StationAddress0);
715 enaddr[0] = v & 0xff;
717 v = CSR_READ_2(sc, STGE_StationAddress1);
718 enaddr[2] = v & 0xff;
720 v = CSR_READ_2(sc, STGE_StationAddress2);
721 enaddr[4] = v & 0xff;
725 uint16_t myaddr[ETHER_ADDR_LEN / 2];
726 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
727 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i,
729 myaddr[i] = le16toh(myaddr[i]);
731 bcopy(myaddr, enaddr, sizeof(enaddr));
735 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
737 device_printf(sc->sc_dev, "failed to if_alloc()\n");
743 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
744 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
745 ifp->if_ioctl = stge_ioctl;
746 ifp->if_start = stge_start;
747 ifp->if_watchdog = stge_watchdog;
748 ifp->if_init = stge_init;
749 ifp->if_mtu = ETHERMTU;
750 ifp->if_snd.ifq_drv_maxlen = STGE_TX_RING_CNT - 1;
751 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
752 IFQ_SET_READY(&ifp->if_snd);
753 /* Revision B3 and earlier chips have checksum bug. */
754 if (sc->sc_rev >= 0x0c) {
755 ifp->if_hwassist = STGE_CSUM_FEATURES;
756 ifp->if_capabilities = IFCAP_HWCSUM;
758 ifp->if_hwassist = 0;
759 ifp->if_capabilities = 0;
761 ifp->if_capenable = ifp->if_capabilities;
764 * Read some important bits from the PhyCtrl register.
766 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
767 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
769 /* Set up MII bus. */
770 if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, stge_mediachange,
771 stge_mediastatus)) != 0) {
772 device_printf(sc->sc_dev, "no PHY found!\n");
776 ether_ifattach(ifp, enaddr);
778 /* VLAN capability setup */
779 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
780 if (sc->sc_rev >= 0x0c)
781 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
782 ifp->if_capenable = ifp->if_capabilities;
783 #ifdef DEVICE_POLLING
784 ifp->if_capabilities |= IFCAP_POLLING;
787 * Tell the upper layer(s) we support long frames.
788 * Must appear after the call to ether_ifattach() because
789 * ether_ifattach() sets ifi_hdrlen to the default value.
791 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
794 * The manual recommends disabling early transmit, so we
795 * do. It's disabled anyway, if using IP checksumming,
796 * since the entire packet must be in the FIFO in order
797 * for the chip to perform the checksum.
799 sc->sc_txthresh = 0x0fff;
802 * Disable MWI if the PCI layer tells us to.
805 if ((cmd & PCIM_CMD_MWRICEN) == 0)
806 sc->sc_DMACtrl |= DMAC_MWIDisable;
811 error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE,
812 NULL, stge_intr, sc, &sc->sc_ih);
815 device_printf(sc->sc_dev, "couldn't set up IRQ\n");
828 stge_detach(device_t dev)
830 struct stge_softc *sc;
833 sc = device_get_softc(dev);
836 #ifdef DEVICE_POLLING
837 if (ifp && ifp->if_capenable & IFCAP_POLLING)
838 ether_poll_deregister(ifp);
840 if (device_is_attached(dev)) {
846 callout_drain(&sc->sc_tick_ch);
847 taskqueue_drain(taskqueue_swi, &sc->sc_link_task);
851 if (sc->sc_miibus != NULL) {
852 device_delete_child(dev, sc->sc_miibus);
853 sc->sc_miibus = NULL;
855 bus_generic_detach(dev);
864 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih);
867 bus_release_resources(dev, sc->sc_spec, sc->sc_res);
869 mtx_destroy(&sc->sc_mii_mtx);
870 mtx_destroy(&sc->sc_mtx);
875 struct stge_dmamap_arg {
876 bus_addr_t stge_busaddr;
880 stge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
882 struct stge_dmamap_arg *ctx;
887 ctx = (struct stge_dmamap_arg *)arg;
888 ctx->stge_busaddr = segs[0].ds_addr;
892 stge_dma_alloc(struct stge_softc *sc)
894 struct stge_dmamap_arg ctx;
895 struct stge_txdesc *txd;
896 struct stge_rxdesc *rxd;
899 /* create parent tag. */
900 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),/* parent */
901 1, 0, /* algnmnt, boundary */
902 STGE_DMA_MAXADDR, /* lowaddr */
903 BUS_SPACE_MAXADDR, /* highaddr */
904 NULL, NULL, /* filter, filterarg */
905 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
907 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
909 NULL, NULL, /* lockfunc, lockarg */
910 &sc->sc_cdata.stge_parent_tag);
912 device_printf(sc->sc_dev, "failed to create parent DMA tag\n");
915 /* create tag for Tx ring. */
916 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
917 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
918 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
919 BUS_SPACE_MAXADDR, /* highaddr */
920 NULL, NULL, /* filter, filterarg */
921 STGE_TX_RING_SZ, /* maxsize */
923 STGE_TX_RING_SZ, /* maxsegsize */
925 NULL, NULL, /* lockfunc, lockarg */
926 &sc->sc_cdata.stge_tx_ring_tag);
928 device_printf(sc->sc_dev,
929 "failed to allocate Tx ring DMA tag\n");
933 /* create tag for Rx ring. */
934 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
935 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
936 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
937 BUS_SPACE_MAXADDR, /* highaddr */
938 NULL, NULL, /* filter, filterarg */
939 STGE_RX_RING_SZ, /* maxsize */
941 STGE_RX_RING_SZ, /* maxsegsize */
943 NULL, NULL, /* lockfunc, lockarg */
944 &sc->sc_cdata.stge_rx_ring_tag);
946 device_printf(sc->sc_dev,
947 "failed to allocate Rx ring DMA tag\n");
951 /* create tag for Tx buffers. */
952 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
953 1, 0, /* algnmnt, boundary */
954 BUS_SPACE_MAXADDR, /* lowaddr */
955 BUS_SPACE_MAXADDR, /* highaddr */
956 NULL, NULL, /* filter, filterarg */
957 MCLBYTES * STGE_MAXTXSEGS, /* maxsize */
958 STGE_MAXTXSEGS, /* nsegments */
959 MCLBYTES, /* maxsegsize */
961 NULL, NULL, /* lockfunc, lockarg */
962 &sc->sc_cdata.stge_tx_tag);
964 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n");
968 /* create tag for Rx buffers. */
969 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
970 1, 0, /* algnmnt, boundary */
971 BUS_SPACE_MAXADDR, /* lowaddr */
972 BUS_SPACE_MAXADDR, /* highaddr */
973 NULL, NULL, /* filter, filterarg */
974 MCLBYTES, /* maxsize */
976 MCLBYTES, /* maxsegsize */
978 NULL, NULL, /* lockfunc, lockarg */
979 &sc->sc_cdata.stge_rx_tag);
981 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n");
985 /* allocate DMA'able memory and load the DMA map for Tx ring. */
986 error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag,
987 (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
988 &sc->sc_cdata.stge_tx_ring_map);
990 device_printf(sc->sc_dev,
991 "failed to allocate DMA'able memory for Tx ring\n");
995 ctx.stge_busaddr = 0;
996 error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag,
997 sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring,
998 STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
999 if (error != 0 || ctx.stge_busaddr == 0) {
1000 device_printf(sc->sc_dev,
1001 "failed to load DMA'able memory for Tx ring\n");
1004 sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr;
1006 /* allocate DMA'able memory and load the DMA map for Rx ring. */
1007 error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag,
1008 (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1009 &sc->sc_cdata.stge_rx_ring_map);
1011 device_printf(sc->sc_dev,
1012 "failed to allocate DMA'able memory for Rx ring\n");
1016 ctx.stge_busaddr = 0;
1017 error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag,
1018 sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring,
1019 STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1020 if (error != 0 || ctx.stge_busaddr == 0) {
1021 device_printf(sc->sc_dev,
1022 "failed to load DMA'able memory for Rx ring\n");
1025 sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr;
1027 /* create DMA maps for Tx buffers. */
1028 for (i = 0; i < STGE_TX_RING_CNT; i++) {
1029 txd = &sc->sc_cdata.stge_txdesc[i];
1032 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0,
1035 device_printf(sc->sc_dev,
1036 "failed to create Tx dmamap\n");
1040 /* create DMA maps for Rx buffers. */
1041 if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
1042 &sc->sc_cdata.stge_rx_sparemap)) != 0) {
1043 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n");
1046 for (i = 0; i < STGE_RX_RING_CNT; i++) {
1047 rxd = &sc->sc_cdata.stge_rxdesc[i];
1050 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
1053 device_printf(sc->sc_dev,
1054 "failed to create Rx dmamap\n");
1064 stge_dma_free(struct stge_softc *sc)
1066 struct stge_txdesc *txd;
1067 struct stge_rxdesc *rxd;
1071 if (sc->sc_cdata.stge_tx_ring_tag) {
1072 if (sc->sc_cdata.stge_tx_ring_map)
1073 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag,
1074 sc->sc_cdata.stge_tx_ring_map);
1075 if (sc->sc_cdata.stge_tx_ring_map &&
1076 sc->sc_rdata.stge_tx_ring)
1077 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag,
1078 sc->sc_rdata.stge_tx_ring,
1079 sc->sc_cdata.stge_tx_ring_map);
1080 sc->sc_rdata.stge_tx_ring = NULL;
1081 sc->sc_cdata.stge_tx_ring_map = 0;
1082 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag);
1083 sc->sc_cdata.stge_tx_ring_tag = NULL;
1086 if (sc->sc_cdata.stge_rx_ring_tag) {
1087 if (sc->sc_cdata.stge_rx_ring_map)
1088 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag,
1089 sc->sc_cdata.stge_rx_ring_map);
1090 if (sc->sc_cdata.stge_rx_ring_map &&
1091 sc->sc_rdata.stge_rx_ring)
1092 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag,
1093 sc->sc_rdata.stge_rx_ring,
1094 sc->sc_cdata.stge_rx_ring_map);
1095 sc->sc_rdata.stge_rx_ring = NULL;
1096 sc->sc_cdata.stge_rx_ring_map = 0;
1097 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag);
1098 sc->sc_cdata.stge_rx_ring_tag = NULL;
1101 if (sc->sc_cdata.stge_tx_tag) {
1102 for (i = 0; i < STGE_TX_RING_CNT; i++) {
1103 txd = &sc->sc_cdata.stge_txdesc[i];
1104 if (txd->tx_dmamap) {
1105 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
1110 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
1111 sc->sc_cdata.stge_tx_tag = NULL;
1114 if (sc->sc_cdata.stge_rx_tag) {
1115 for (i = 0; i < STGE_RX_RING_CNT; i++) {
1116 rxd = &sc->sc_cdata.stge_rxdesc[i];
1117 if (rxd->rx_dmamap) {
1118 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
1123 if (sc->sc_cdata.stge_rx_sparemap) {
1124 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
1125 sc->sc_cdata.stge_rx_sparemap);
1126 sc->sc_cdata.stge_rx_sparemap = 0;
1128 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
1129 sc->sc_cdata.stge_rx_tag = NULL;
1132 if (sc->sc_cdata.stge_parent_tag) {
1133 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag);
1134 sc->sc_cdata.stge_parent_tag = NULL;
1141 * Make sure the interface is stopped at reboot time.
1144 stge_shutdown(device_t dev)
1146 struct stge_softc *sc;
1148 sc = device_get_softc(dev);
1156 stge_suspend(device_t dev)
1158 struct stge_softc *sc;
1160 sc = device_get_softc(dev);
1164 sc->sc_suspended = 1;
1171 stge_resume(device_t dev)
1173 struct stge_softc *sc;
1176 sc = device_get_softc(dev);
1180 if (ifp->if_flags & IFF_UP)
1181 stge_init_locked(sc);
1183 sc->sc_suspended = 0;
1190 stge_dma_wait(struct stge_softc *sc)
1194 for (i = 0; i < STGE_TIMEOUT; i++) {
1196 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
1200 if (i == STGE_TIMEOUT)
1201 device_printf(sc->sc_dev, "DMA wait timed out\n");
1205 stge_encap(struct stge_softc *sc, struct mbuf **m_head)
1207 struct stge_txdesc *txd;
1208 struct stge_tfd *tfd;
1210 bus_dma_segment_t txsegs[STGE_MAXTXSEGS];
1211 int error, i, nsegs, si;
1212 uint64_t csum_flags, tfc;
1214 STGE_LOCK_ASSERT(sc);
1216 if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL)
1219 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1220 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1221 if (error == EFBIG) {
1222 m = m_defrag(*m_head, M_DONTWAIT);
1229 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1230 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1236 } else if (error != 0)
1246 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) {
1247 if (m->m_pkthdr.csum_flags & CSUM_IP)
1248 csum_flags |= TFD_IPChecksumEnable;
1249 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1250 csum_flags |= TFD_TCPChecksumEnable;
1251 else if (m->m_pkthdr.csum_flags & CSUM_UDP)
1252 csum_flags |= TFD_UDPChecksumEnable;
1255 si = sc->sc_cdata.stge_tx_prod;
1256 tfd = &sc->sc_rdata.stge_tx_ring[si];
1257 for (i = 0; i < nsegs; i++)
1258 tfd->tfd_frags[i].frag_word0 =
1259 htole64(FRAG_ADDR(txsegs[i].ds_addr) |
1260 FRAG_LEN(txsegs[i].ds_len));
1261 sc->sc_cdata.stge_tx_cnt++;
1263 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) |
1264 TFD_FragCount(nsegs) | csum_flags;
1265 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT)
1266 tfc |= TFD_TxDMAIndicate;
1268 /* Update producer index. */
1269 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT;
1271 /* Check if we have a VLAN tag to insert. */
1272 if (m->m_flags & M_VLANTAG)
1273 tfc |= (TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vtag));
1274 tfd->tfd_control = htole64(tfc);
1276 /* Update Tx Queue. */
1277 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q);
1278 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q);
1281 /* Sync descriptors. */
1282 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1283 BUS_DMASYNC_PREWRITE);
1284 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1285 sc->sc_cdata.stge_tx_ring_map,
1286 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1292 * stge_start: [ifnet interface function]
1294 * Start packet transmission on the interface.
1297 stge_start(struct ifnet *ifp)
1299 struct stge_softc *sc;
1303 stge_start_locked(ifp);
1308 stge_start_locked(struct ifnet *ifp)
1310 struct stge_softc *sc;
1311 struct mbuf *m_head;
1316 STGE_LOCK_ASSERT(sc);
1318 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
1322 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1323 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) {
1324 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1328 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1332 * Pack the data into the transmit ring. If we
1333 * don't have room, set the OACTIVE flag and wait
1334 * for the NIC to drain the ring.
1336 if (stge_encap(sc, &m_head)) {
1339 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1340 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1346 * If there's a BPF listener, bounce a copy of this frame
1349 ETHER_BPF_MTAP(ifp, m_head);
1354 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow);
1356 /* Set a timeout in case the chip goes out to lunch. */
1362 * stge_watchdog: [ifnet interface function]
1364 * Watchdog timer handler.
1367 stge_watchdog(struct ifnet *ifp)
1369 struct stge_softc *sc;
1374 if_printf(sc->sc_ifp, "device timeout\n");
1376 stge_init_locked(sc);
1381 * stge_ioctl: [ifnet interface function]
1383 * Handle control requests from the operator.
1386 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1388 struct stge_softc *sc;
1390 struct mii_data *mii;
1394 ifr = (struct ifreq *)data;
1398 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU)
1400 else if (ifp->if_mtu != ifr->ifr_mtu) {
1401 ifp->if_mtu = ifr->ifr_mtu;
1403 stge_init_locked(sc);
1409 if ((ifp->if_flags & IFF_UP) != 0) {
1410 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1411 if (((ifp->if_flags ^ sc->sc_if_flags)
1412 & IFF_PROMISC) != 0)
1413 stge_set_filter(sc);
1415 if (sc->sc_detach == 0)
1416 stge_init_locked(sc);
1419 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1422 sc->sc_if_flags = ifp->if_flags;
1428 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1434 mii = device_get_softc(sc->sc_miibus);
1435 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1438 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1439 #ifdef DEVICE_POLLING
1440 if ((mask & IFCAP_POLLING) != 0) {
1441 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1442 error = ether_poll_register(stge_poll, ifp);
1446 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1447 ifp->if_capenable |= IFCAP_POLLING;
1450 error = ether_poll_deregister(ifp);
1454 CSR_WRITE_2(sc, STGE_IntEnable,
1456 ifp->if_capenable &= ~IFCAP_POLLING;
1461 if ((mask & IFCAP_HWCSUM) != 0) {
1462 ifp->if_capenable ^= IFCAP_HWCSUM;
1463 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 &&
1464 (IFCAP_HWCSUM & ifp->if_capabilities) != 0)
1465 ifp->if_hwassist = STGE_CSUM_FEATURES;
1467 ifp->if_hwassist = 0;
1469 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
1470 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1471 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1473 stge_vlan_setup(sc);
1477 VLAN_CAPABILITIES(ifp);
1480 error = ether_ioctl(ifp, cmd, data);
1488 stge_link_task(void *arg, int pending)
1490 struct stge_softc *sc;
1494 sc = (struct stge_softc *)arg;
1497 * Update STGE_MACCtrl register depending on link status.
1498 * (duplex, flow control etc)
1500 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
1501 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable);
1502 v |= sc->sc_MACCtrl;
1503 CSR_WRITE_4(sc, STGE_MACCtrl, v);
1504 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) {
1505 /* Duplex setting changed, reset Tx/Rx functions. */
1506 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1507 ac |= AC_TxReset | AC_RxReset;
1508 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1509 for (i = 0; i < STGE_TIMEOUT; i++) {
1511 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1514 if (i == STGE_TIMEOUT)
1515 device_printf(sc->sc_dev, "reset failed to complete\n");
1521 stge_tx_error(struct stge_softc *sc)
1527 txstat = CSR_READ_4(sc, STGE_TxStatus);
1528 if ((txstat & TS_TxComplete) == 0)
1531 if ((txstat & TS_TxUnderrun) != 0) {
1534 * There should be a more better way to recover
1535 * from Tx underrun instead of a full reset.
1537 if (sc->sc_nerr++ < STGE_MAXERR)
1538 device_printf(sc->sc_dev, "Tx underrun, "
1540 if (sc->sc_nerr == STGE_MAXERR)
1541 device_printf(sc->sc_dev, "too many errors; "
1542 "not reporting any more\n");
1546 /* Maximum/Late collisions, Re-enable Tx MAC. */
1547 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0)
1548 CSR_WRITE_4(sc, STGE_MACCtrl,
1549 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |
1559 * Interrupt service routine.
1562 stge_intr(void *arg)
1564 struct stge_softc *sc;
1569 sc = (struct stge_softc *)arg;
1574 #ifdef DEVICE_POLLING
1575 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1578 status = CSR_READ_2(sc, STGE_IntStatus);
1579 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0)
1582 /* Disable interrupts. */
1583 for (reinit = 0;;) {
1584 status = CSR_READ_2(sc, STGE_IntStatusAck);
1585 status &= sc->sc_IntEnable;
1588 /* Host interface errors. */
1589 if ((status & IS_HostError) != 0) {
1590 device_printf(sc->sc_dev,
1591 "Host interface error, resetting...\n");
1596 /* Receive interrupts. */
1597 if ((status & IS_RxDMAComplete) != 0) {
1599 if ((status & IS_RFDListEnd) != 0)
1600 CSR_WRITE_4(sc, STGE_DMACtrl,
1604 /* Transmit interrupts. */
1605 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0)
1608 /* Transmission errors.*/
1609 if ((status & IS_TxComplete) != 0) {
1610 if ((reinit = stge_tx_error(sc)) != 0)
1617 stge_init_locked(sc);
1619 /* Re-enable interrupts. */
1620 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1622 /* Try to get more packets going. */
1623 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1624 stge_start_locked(ifp);
1633 * Helper; handle transmit interrupts.
1636 stge_txeof(struct stge_softc *sc)
1639 struct stge_txdesc *txd;
1643 STGE_LOCK_ASSERT(sc);
1647 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1650 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1651 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD);
1654 * Go through our Tx list and free mbufs for those
1655 * frames which have been transmitted.
1657 for (cons = sc->sc_cdata.stge_tx_cons;;
1658 cons = (cons + 1) % STGE_TX_RING_CNT) {
1659 if (sc->sc_cdata.stge_tx_cnt <= 0)
1661 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control);
1662 if ((control & TFD_TFDDone) == 0)
1664 sc->sc_cdata.stge_tx_cnt--;
1665 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1667 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1668 BUS_DMASYNC_POSTWRITE);
1669 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap);
1671 /* Output counter is updated with statistics register */
1674 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q);
1675 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
1676 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1678 sc->sc_cdata.stge_tx_cons = cons;
1679 if (sc->sc_cdata.stge_tx_cnt == 0)
1682 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1683 sc->sc_cdata.stge_tx_ring_map,
1684 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1687 static __inline void
1688 stge_discard_rxbuf(struct stge_softc *sc, int idx)
1690 struct stge_rfd *rfd;
1692 rfd = &sc->sc_rdata.stge_rx_ring[idx];
1693 rfd->rfd_status = 0;
1696 #ifndef __NO_STRICT_ALIGNMENT
1698 * It seems that TC9021's DMA engine has alignment restrictions in
1699 * DMA scatter operations. The first DMA segment has no address
1700 * alignment restrictins but the rest should be aligned on 4(?) bytes
1701 * boundary. Otherwise it would corrupt random memory. Since we don't
1702 * know which one is used for the first segment in advance we simply
1703 * don't align at all.
1704 * To avoid copying over an entire frame to align, we allocate a new
1705 * mbuf and copy ethernet header to the new mbuf. The new mbuf is
1706 * prepended into the existing mbuf chain.
1708 static __inline struct mbuf *
1709 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m)
1714 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
1715 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
1716 m->m_data += ETHER_HDR_LEN;
1719 MGETHDR(n, M_DONTWAIT, MT_DATA);
1721 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
1722 m->m_data += ETHER_HDR_LEN;
1723 m->m_len -= ETHER_HDR_LEN;
1724 n->m_len = ETHER_HDR_LEN;
1725 M_MOVE_PKTHDR(n, m);
1738 * Helper; handle receive interrupts.
1741 stge_rxeof(struct stge_softc *sc)
1744 struct stge_rxdesc *rxd;
1745 struct mbuf *mp, *m;
1750 STGE_LOCK_ASSERT(sc);
1754 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1755 sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD);
1758 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT;
1759 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) {
1760 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status);
1761 status = RFD_RxStatus(status64);
1762 if ((status & RFD_RFDDone) == 0)
1764 #ifdef DEVICE_POLLING
1765 if (ifp->if_capenable & IFCAP_POLLING) {
1766 if (sc->sc_cdata.stge_rxcycles <= 0)
1768 sc->sc_cdata.stge_rxcycles--;
1772 rxd = &sc->sc_cdata.stge_rxdesc[cons];
1776 * If the packet had an error, drop it. Note we count
1777 * the error later in the periodic stats update.
1779 if ((status & RFD_FrameEnd) != 0 && (status &
1780 (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
1781 RFD_RxAlignmentError | RFD_RxFCSError |
1782 RFD_RxLengthError)) != 0) {
1783 stge_discard_rxbuf(sc, cons);
1784 if (sc->sc_cdata.stge_rxhead != NULL) {
1785 m_freem(sc->sc_cdata.stge_rxhead);
1786 STGE_RXCHAIN_RESET(sc);
1791 * Add a new receive buffer to the ring.
1793 if (stge_newbuf(sc, cons) != 0) {
1795 stge_discard_rxbuf(sc, cons);
1796 if (sc->sc_cdata.stge_rxhead != NULL) {
1797 m_freem(sc->sc_cdata.stge_rxhead);
1798 STGE_RXCHAIN_RESET(sc);
1803 if ((status & RFD_FrameEnd) != 0)
1804 mp->m_len = RFD_RxDMAFrameLen(status) -
1805 sc->sc_cdata.stge_rxlen;
1806 sc->sc_cdata.stge_rxlen += mp->m_len;
1809 if (sc->sc_cdata.stge_rxhead == NULL) {
1810 sc->sc_cdata.stge_rxhead = mp;
1811 sc->sc_cdata.stge_rxtail = mp;
1813 mp->m_flags &= ~M_PKTHDR;
1814 sc->sc_cdata.stge_rxtail->m_next = mp;
1815 sc->sc_cdata.stge_rxtail = mp;
1818 if ((status & RFD_FrameEnd) != 0) {
1819 m = sc->sc_cdata.stge_rxhead;
1820 m->m_pkthdr.rcvif = ifp;
1821 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen;
1823 if (m->m_pkthdr.len > sc->sc_if_framesize) {
1825 STGE_RXCHAIN_RESET(sc);
1829 * Set the incoming checksum information for
1832 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1833 if ((status & RFD_IPDetected) != 0) {
1834 m->m_pkthdr.csum_flags |=
1836 if ((status & RFD_IPError) == 0)
1837 m->m_pkthdr.csum_flags |=
1840 if (((status & RFD_TCPDetected) != 0 &&
1841 (status & RFD_TCPError) == 0) ||
1842 ((status & RFD_UDPDetected) != 0 &&
1843 (status & RFD_UDPError) == 0)) {
1844 m->m_pkthdr.csum_flags |=
1845 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1846 m->m_pkthdr.csum_data = 0xffff;
1850 #ifndef __NO_STRICT_ALIGNMENT
1851 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) {
1852 if ((m = stge_fixup_rx(sc, m)) == NULL) {
1853 STGE_RXCHAIN_RESET(sc);
1858 /* Check for VLAN tagged packets. */
1859 if ((status & RFD_VLANDetected) != 0 &&
1860 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
1861 m->m_pkthdr.ether_vtag = RFD_TCI(status64);
1862 m->m_flags |= M_VLANTAG;
1867 (*ifp->if_input)(ifp, m);
1870 STGE_RXCHAIN_RESET(sc);
1875 /* Update the consumer index. */
1876 sc->sc_cdata.stge_rx_cons = cons;
1877 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1878 sc->sc_cdata.stge_rx_ring_map,
1879 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1883 #ifdef DEVICE_POLLING
1885 stge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1887 struct stge_softc *sc;
1892 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1897 sc->sc_cdata.stge_rxcycles = count;
1901 if (cmd == POLL_AND_CHECK_STATUS) {
1902 status = CSR_READ_2(sc, STGE_IntStatus);
1903 status &= sc->sc_IntEnable;
1905 if ((status & IS_HostError) != 0) {
1906 device_printf(sc->sc_dev,
1907 "Host interface error, resetting...\n");
1908 stge_init_locked(sc);
1910 if ((status & IS_TxComplete) != 0) {
1911 if (stge_tx_error(sc) != 0)
1912 stge_init_locked(sc);
1918 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1919 stge_start_locked(ifp);
1923 #endif /* DEVICE_POLLING */
1928 * One second timer, used to tick the MII.
1931 stge_tick(void *arg)
1933 struct stge_softc *sc;
1934 struct mii_data *mii;
1936 sc = (struct stge_softc *)arg;
1938 STGE_LOCK_ASSERT(sc);
1940 mii = device_get_softc(sc->sc_miibus);
1943 /* Update statistics counters. */
1944 stge_stats_update(sc);
1947 * Relcaim any pending Tx descriptors to release mbufs in a
1948 * timely manner as we don't generate Tx completion interrupts
1949 * for every frame. This limits the delay to a maximum of one
1952 if (sc->sc_cdata.stge_tx_cnt != 0)
1955 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
1959 * stge_stats_update:
1961 * Read the TC9021 statistics counters.
1964 stge_stats_update(struct stge_softc *sc)
1968 STGE_LOCK_ASSERT(sc);
1972 CSR_READ_4(sc,STGE_OctetRcvOk);
1974 ifp->if_ipackets += CSR_READ_4(sc, STGE_FramesRcvdOk);
1976 ifp->if_ierrors += CSR_READ_2(sc, STGE_FramesLostRxErrors);
1978 CSR_READ_4(sc, STGE_OctetXmtdOk);
1980 ifp->if_opackets += CSR_READ_4(sc, STGE_FramesXmtdOk);
1982 ifp->if_collisions +=
1983 CSR_READ_4(sc, STGE_LateCollisions) +
1984 CSR_READ_4(sc, STGE_MultiColFrames) +
1985 CSR_READ_4(sc, STGE_SingleColFrames);
1988 CSR_READ_2(sc, STGE_FramesAbortXSColls) +
1989 CSR_READ_2(sc, STGE_FramesWEXDeferal);
1995 * Perform a soft reset on the TC9021.
1998 stge_reset(struct stge_softc *sc, uint32_t how)
2004 STGE_LOCK_ASSERT(sc);
2007 ac = CSR_READ_4(sc, STGE_AsicCtrl);
2010 ac |= AC_TxReset | AC_FIFO;
2014 ac |= AC_RxReset | AC_FIFO;
2017 case STGE_RESET_FULL:
2020 * Only assert RstOut if we're fiber. We need GMII clocks
2021 * to be present in order for the reset to complete on fiber
2024 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset |
2025 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
2026 (sc->sc_usefiber ? AC_RstOut : 0);
2030 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
2032 /* Account for reset problem at 10Mbps. */
2035 for (i = 0; i < STGE_TIMEOUT; i++) {
2036 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
2041 if (i == STGE_TIMEOUT)
2042 device_printf(sc->sc_dev, "reset failed to complete\n");
2044 /* Set LED, from Linux IPG driver. */
2045 ac = CSR_READ_4(sc, STGE_AsicCtrl);
2046 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1);
2047 if ((sc->sc_led & 0x01) != 0)
2049 if ((sc->sc_led & 0x03) != 0)
2050 ac |= AC_LEDModeBit1;
2051 if ((sc->sc_led & 0x08) != 0)
2053 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
2055 /* Set PHY, from Linux IPG driver */
2056 v = CSR_READ_1(sc, STGE_PhySet);
2057 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet);
2058 v |= ((sc->sc_led & 0x70) >> 4);
2059 CSR_WRITE_1(sc, STGE_PhySet, v);
2063 * stge_init: [ ifnet interface function ]
2065 * Initialize the interface.
2068 stge_init(void *xsc)
2070 struct stge_softc *sc;
2072 sc = (struct stge_softc *)xsc;
2074 stge_init_locked(sc);
2079 stge_init_locked(struct stge_softc *sc)
2082 struct mii_data *mii;
2087 STGE_LOCK_ASSERT(sc);
2090 mii = device_get_softc(sc->sc_miibus);
2093 * Cancel any pending I/O.
2097 /* Init descriptors. */
2098 error = stge_init_rx_ring(sc);
2100 device_printf(sc->sc_dev,
2101 "initialization failed: no memory for rx buffers\n");
2105 stge_init_tx_ring(sc);
2107 /* Set the station address. */
2108 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2109 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
2110 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
2111 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
2114 * Set the statistics masks. Disable all the RMON stats,
2115 * and disable selected stats in the non-RMON stats registers.
2117 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
2118 CSR_WRITE_4(sc, STGE_StatisticsMask,
2119 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
2120 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
2121 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
2124 /* Set up the receive filter. */
2125 stge_set_filter(sc);
2126 /* Program multicast filter. */
2130 * Give the transmit and receive ring to the chip.
2132 CSR_WRITE_4(sc, STGE_TFDListPtrHi,
2133 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0)));
2134 CSR_WRITE_4(sc, STGE_TFDListPtrLo,
2135 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0)));
2137 CSR_WRITE_4(sc, STGE_RFDListPtrHi,
2138 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0)));
2139 CSR_WRITE_4(sc, STGE_RFDListPtrLo,
2140 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0)));
2143 * Initialize the Tx auto-poll period. It's OK to make this number
2144 * large (255 is the max, but we use 127) -- we explicitly kick the
2145 * transmit engine when there's actually a packet.
2147 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2149 /* ..and the Rx auto-poll period. */
2150 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2152 /* Initialize the Tx start threshold. */
2153 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
2155 /* Rx DMA thresholds, from Linux */
2156 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
2157 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
2159 /* Rx early threhold, from Linux */
2160 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
2162 /* Tx DMA thresholds, from Linux */
2163 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
2164 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
2167 * Initialize the Rx DMA interrupt control register. We
2168 * request an interrupt after every incoming packet, but
2169 * defer it for sc_rxint_dmawait us. When the number of
2170 * interrupts pending reaches STGE_RXINT_NFRAME, we stop
2171 * deferring the interrupt, and signal it immediately.
2173 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
2174 RDIC_RxFrameCount(sc->sc_rxint_nframe) |
2175 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait)));
2178 * Initialize the interrupt mask.
2180 sc->sc_IntEnable = IS_HostError | IS_TxComplete |
2181 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
2182 #ifdef DEVICE_POLLING
2183 /* Disable interrupts if we are polling. */
2184 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
2185 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2188 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2191 * Configure the DMA engine.
2192 * XXX Should auto-tune TxBurstLimit.
2194 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3));
2197 * Send a PAUSE frame when we reach 29,696 bytes in the Rx
2198 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes
2201 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
2202 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
2205 * Set the maximum frame size.
2207 sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2208 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize);
2211 * Initialize MacCtrl -- do it before setting the media,
2212 * as setting the media will actually program the register.
2214 * Note: We have to poke the IFS value before poking
2217 /* Tx/Rx MAC should be disabled before programming IFS.*/
2218 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit));
2220 stge_vlan_setup(sc);
2222 if (sc->sc_rev >= 6) { /* >= B.2 */
2223 /* Multi-frag frame bug work-around. */
2224 CSR_WRITE_2(sc, STGE_DebugCtrl,
2225 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
2227 /* Tx Poll Now bug work-around. */
2228 CSR_WRITE_2(sc, STGE_DebugCtrl,
2229 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
2230 /* Tx Poll Now bug work-around. */
2231 CSR_WRITE_2(sc, STGE_DebugCtrl,
2232 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
2235 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2236 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
2237 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2239 * It seems that transmitting frames without checking the state of
2240 * Rx/Tx MAC wedge the hardware.
2246 * Set the current media.
2251 * Start the one second MII clock.
2253 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
2258 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2259 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2263 device_printf(sc->sc_dev, "interface not running\n");
2267 stge_vlan_setup(struct stge_softc *sc)
2274 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl
2275 * MC_AutoVLANuntagging bit.
2276 * MC_AutoVLANtagging bit selects which VLAN source to use
2277 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert
2278 * bit has priority over MC_AutoVLANtagging bit. So we always
2279 * use TFC instead of STGE_VLANTag register.
2281 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2282 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2283 v |= MC_AutoVLANuntagging;
2285 v &= ~MC_AutoVLANuntagging;
2286 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2290 * Stop transmission on the interface.
2293 stge_stop(struct stge_softc *sc)
2296 struct stge_txdesc *txd;
2297 struct stge_rxdesc *rxd;
2301 STGE_LOCK_ASSERT(sc);
2303 * Stop the one second clock.
2305 callout_stop(&sc->sc_tick_ch);
2308 * Reset the chip to a known state.
2310 stge_reset(sc, STGE_RESET_FULL);
2313 * Disable interrupts.
2315 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2318 * Stop receiver, transmitter, and stats update.
2322 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2323 v |= MC_StatisticsDisable;
2324 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2327 * Stop the transmit and receive DMA.
2330 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
2331 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
2332 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
2333 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
2336 * Free RX and TX mbufs still in the queues.
2338 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2339 rxd = &sc->sc_cdata.stge_rxdesc[i];
2340 if (rxd->rx_m != NULL) {
2341 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag,
2342 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2343 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag,
2349 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2350 txd = &sc->sc_cdata.stge_txdesc[i];
2351 if (txd->tx_m != NULL) {
2352 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag,
2353 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2354 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag,
2362 * Mark the interface down and cancel the watchdog timer.
2365 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2370 stge_start_tx(struct stge_softc *sc)
2375 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2376 if ((v & MC_TxEnabled) != 0)
2379 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2380 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2381 for (i = STGE_TIMEOUT; i > 0; i--) {
2383 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2384 if ((v & MC_TxEnabled) != 0)
2388 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n");
2392 stge_start_rx(struct stge_softc *sc)
2397 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2398 if ((v & MC_RxEnabled) != 0)
2401 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2402 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2403 for (i = STGE_TIMEOUT; i > 0; i--) {
2405 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2406 if ((v & MC_RxEnabled) != 0)
2410 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n");
2414 stge_stop_tx(struct stge_softc *sc)
2419 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2420 if ((v & MC_TxEnabled) == 0)
2423 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2424 for (i = STGE_TIMEOUT; i > 0; i--) {
2426 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2427 if ((v & MC_TxEnabled) == 0)
2431 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n");
2435 stge_stop_rx(struct stge_softc *sc)
2440 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2441 if ((v & MC_RxEnabled) == 0)
2444 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2445 for (i = STGE_TIMEOUT; i > 0; i--) {
2447 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2448 if ((v & MC_RxEnabled) == 0)
2452 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n");
2456 stge_init_tx_ring(struct stge_softc *sc)
2458 struct stge_ring_data *rd;
2459 struct stge_txdesc *txd;
2463 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq);
2464 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq);
2466 sc->sc_cdata.stge_tx_prod = 0;
2467 sc->sc_cdata.stge_tx_cons = 0;
2468 sc->sc_cdata.stge_tx_cnt = 0;
2471 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ);
2472 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2473 if (i == (STGE_TX_RING_CNT - 1))
2474 addr = STGE_TX_RING_ADDR(sc, 0);
2476 addr = STGE_TX_RING_ADDR(sc, i + 1);
2477 rd->stge_tx_ring[i].tfd_next = htole64(addr);
2478 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone);
2479 txd = &sc->sc_cdata.stge_txdesc[i];
2480 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
2483 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
2484 sc->sc_cdata.stge_tx_ring_map,
2485 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2490 stge_init_rx_ring(struct stge_softc *sc)
2492 struct stge_ring_data *rd;
2496 sc->sc_cdata.stge_rx_cons = 0;
2497 STGE_RXCHAIN_RESET(sc);
2500 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ);
2501 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2502 if (stge_newbuf(sc, i) != 0)
2504 if (i == (STGE_RX_RING_CNT - 1))
2505 addr = STGE_RX_RING_ADDR(sc, 0);
2507 addr = STGE_RX_RING_ADDR(sc, i + 1);
2508 rd->stge_rx_ring[i].rfd_next = htole64(addr);
2509 rd->stge_rx_ring[i].rfd_status = 0;
2512 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
2513 sc->sc_cdata.stge_rx_ring_map,
2514 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2522 * Add a receive buffer to the indicated descriptor.
2525 stge_newbuf(struct stge_softc *sc, int idx)
2527 struct stge_rxdesc *rxd;
2528 struct stge_rfd *rfd;
2530 bus_dma_segment_t segs[1];
2534 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2537 m->m_len = m->m_pkthdr.len = MCLBYTES;
2539 * The hardware requires 4bytes aligned DMA address when JUMBO
2542 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN))
2543 m_adj(m, ETHER_ALIGN);
2545 if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag,
2546 sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2550 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2552 rxd = &sc->sc_cdata.stge_rxdesc[idx];
2553 if (rxd->rx_m != NULL) {
2554 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2555 BUS_DMASYNC_POSTREAD);
2556 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap);
2558 map = rxd->rx_dmamap;
2559 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap;
2560 sc->sc_cdata.stge_rx_sparemap = map;
2561 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2562 BUS_DMASYNC_PREREAD);
2565 rfd = &sc->sc_rdata.stge_rx_ring[idx];
2566 rfd->rfd_frag.frag_word0 =
2567 htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len));
2568 rfd->rfd_status = 0;
2576 * Set up the receive filter.
2579 stge_set_filter(struct stge_softc *sc)
2584 STGE_LOCK_ASSERT(sc);
2588 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2589 mode |= RM_ReceiveUnicast;
2590 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2591 mode |= RM_ReceiveBroadcast;
2593 mode &= ~RM_ReceiveBroadcast;
2594 if ((ifp->if_flags & IFF_PROMISC) != 0)
2595 mode |= RM_ReceiveAllFrames;
2597 mode &= ~RM_ReceiveAllFrames;
2599 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2603 stge_set_multi(struct stge_softc *sc)
2606 struct ifmultiaddr *ifma;
2612 STGE_LOCK_ASSERT(sc);
2616 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2617 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2618 if ((ifp->if_flags & IFF_PROMISC) != 0)
2619 mode |= RM_ReceiveAllFrames;
2620 else if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2621 mode |= RM_ReceiveMulticast;
2622 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2626 /* clear existing filters. */
2627 CSR_WRITE_4(sc, STGE_HashTable0, 0);
2628 CSR_WRITE_4(sc, STGE_HashTable1, 0);
2631 * Set up the multicast address filter by passing all multicast
2632 * addresses through a CRC generator, and then using the low-order
2633 * 6 bits as an index into the 64 bit multicast hash table. The
2634 * high order bits select the register, while the rest of the bits
2635 * select the bit within the register.
2638 bzero(mchash, sizeof(mchash));
2641 IF_ADDR_LOCK(sc->sc_ifp);
2642 TAILQ_FOREACH(ifma, &sc->sc_ifp->if_multiaddrs, ifma_link) {
2643 if (ifma->ifma_addr->sa_family != AF_LINK)
2645 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2646 ifma->ifma_addr), ETHER_ADDR_LEN);
2648 /* Just want the 6 least significant bits. */
2651 /* Set the corresponding bit in the hash table. */
2652 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2655 IF_ADDR_UNLOCK(ifp);
2657 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames);
2659 mode |= RM_ReceiveMulticastHash;
2661 mode &= ~RM_ReceiveMulticastHash;
2663 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
2664 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
2665 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2669 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2675 value = *(int *)arg1;
2676 error = sysctl_handle_int(oidp, &value, 0, req);
2677 if (error || !req->newptr)
2679 if (value < low || value > high)
2681 *(int *)arg1 = value;
2687 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS)
2689 return (sysctl_int_range(oidp, arg1, arg2, req,
2690 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX));
2694 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS)
2696 return (sysctl_int_range(oidp, arg1, arg2, req,
2697 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX));