2 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010
3 * PCI-SCSI controllers.
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
7 * This driver also supports the following Symbios/LSI PCI-SCSI chips:
8 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895,
9 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode.
12 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver.
13 * Copyright (C) 1998-1999 Gerard Roudier
15 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
16 * a port of the FreeBSD ncr driver to Linux-1.2.13.
18 * The original ncr driver has been written for 386bsd and FreeBSD by
19 * Wolfgang Stanglmeier <wolf@cologne.de>
20 * Stefan Esser <se@mi.Uni-Koeln.de>
21 * Copyright (C) 1994 Wolfgang Stanglmeier
23 * The initialisation code, and part of the code that addresses
24 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM
25 * written by Justin T. Gibbs.
27 * Other major contributions:
29 * NVRAM detection and reading.
30 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
32 *-----------------------------------------------------------------------------
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. The name of the author may not be used to endorse or promote products
43 * derived from this software without specific prior written permission.
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
49 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 #define PCI_VENDOR_NCR 0x1000
69 * PCI device identifier of SYMBIOS chips.
71 #define PCI_ID_SYM53C810 1
72 #define PCI_ID_SYM53C810AP 5
73 #define PCI_ID_SYM53C815 4
74 #define PCI_ID_SYM53C820 2
75 #define PCI_ID_SYM53C825 3
76 #define PCI_ID_SYM53C860 6
77 #define PCI_ID_SYM53C875 0xf
78 #define PCI_ID_SYM53C875_2 0x8f
79 #define PCI_ID_SYM53C885 0xd
80 #define PCI_ID_SYM53C895 0xc
81 #define PCI_ID_SYM53C896 0xb
82 #define PCI_ID_SYM53C895A 0x12
83 #define PCI_ID_LSI53C1010 0x20
84 #define PCI_ID_LSI53C1010_2 0x21
85 #define PCI_ID_LSI53C1510D 0xa
88 * SYM53C8XX device features descriptor.
92 unsigned short revision_id;
94 u_char burst_max; /* log-base-2 of max burst */
99 #define FE_LED0 (1<<0)
100 #define FE_WIDE (1<<1) /* Wide data transfers */
101 #define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
102 #define FE_ULTRA2 (1<<3) /* Ultra 2 - 40 Mtrans/sec */
103 #define FE_DBLR (1<<4) /* Clock doubler present */
104 #define FE_QUAD (1<<5) /* Clock quadrupler present */
105 #define FE_ERL (1<<6) /* Enable read line */
106 #define FE_CLSE (1<<7) /* Cache line size enable */
107 #define FE_WRIE (1<<8) /* Write & Invalidate enable */
108 #define FE_ERMP (1<<9) /* Enable read multiple */
109 #define FE_BOF (1<<10) /* Burst opcode fetch */
110 #define FE_DFS (1<<11) /* DMA fifo size */
111 #define FE_PFEN (1<<12) /* Prefetch enable */
112 #define FE_LDSTR (1<<13) /* Load/Store supported */
113 #define FE_RAM (1<<14) /* On chip RAM present */
114 #define FE_CLK80 (1<<15) /* Board clock is 80 MHz */
115 #define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
116 #define FE_64BIT (1<<17) /* 64-bit PCI BUS interface */
117 #define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
118 #define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
119 #define FE_LEDC (1<<20) /* Hardware control of LED */
120 #define FE_ULTRA3 (1<<21) /* Ultra 3 - 80 Mtrans/sec DT */
121 #define FE_66MHZ (1<<22) /* 66MHz PCI support */
122 #define FE_CRC (1<<23) /* CRC support */
123 #define FE_DIFF (1<<24) /* SCSI HVD support */
124 #define FE_DFBC (1<<25) /* Have DFBC register */
125 #define FE_LCKFRQ (1<<26) /* Have LCKFRQ */
126 #define FE_C10 (1<<27) /* Various C10 core (mis)features */
127 #define FE_U3EN (1<<28) /* U3EN bit usable */
128 #define FE_DAC (1<<29) /* Support PCI DAC (64 bit addressing) */
130 #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
131 #define FE_CACHE0_SET (FE_CACHE_SET & ~FE_ERL)
132 #define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
136 * Symbios NVRAM data format
138 #define SYMBIOS_NVRAM_SIZE 368
139 #define SYMBIOS_NVRAM_ADDRESS 0x100
141 struct Symbios_nvram {
143 u_short type; /* 0x0000 */
144 u_short byte_count; /* excluding header/trailer */
147 /* Controller set up 20 bytes */
148 u_char v_major; /* 0x00 */
149 u_char v_minor; /* 0x30 */
152 #define SYMBIOS_SCAM_ENABLE (1)
153 #define SYMBIOS_PARITY_ENABLE (1<<1)
154 #define SYMBIOS_VERBOSE_MSGS (1<<2)
155 #define SYMBIOS_CHS_MAPPING (1<<3)
156 #define SYMBIOS_NO_NVRAM (1<<3) /* ??? */
158 #define SYMBIOS_SCAN_HI_LO (1)
160 #define SYMBIOS_TERM_CANT_PROGRAM (0)
161 #define SYMBIOS_TERM_ENABLED (1)
162 #define SYMBIOS_TERM_DISABLED (2)
164 #define SYMBIOS_RMVBL_NO_SUPPORT (0)
165 #define SYMBIOS_RMVBL_BOOT_DEVICE (1)
166 #define SYMBIOS_RMVBL_MEDIA_INSTALLED (2)
168 u_char num_hba; /* 0x04 */
169 u_char num_devices; /* 0x10 */
170 u_char max_scam_devices; /* 0x04 */
171 u_char num_valid_scam_devices; /* 0x00 */
173 #define SYMBIOS_AVOID_BUS_RESET (1<<2)
175 /* Boot order 14 bytes * 4 */
177 u_short type; /* 4:8xx / 0:nok */
178 u_short device_id; /* PCI device id */
179 u_short vendor_id; /* PCI vendor id */
180 u_char bus_nr; /* PCI bus number */
181 u_char device_fn; /* PCI device/function number << 3*/
184 #define SYMBIOS_INIT_SCAN_AT_BOOT (1)
185 u_short io_port; /* PCI io_port address */
188 /* Targets 8 bytes * 16 */
189 struct Symbios_target {
191 #define SYMBIOS_DISCONNECT_ENABLE (1)
192 #define SYMBIOS_SCAN_AT_BOOT_TIME (1<<1)
193 #define SYMBIOS_SCAN_LUNS (1<<2)
194 #define SYMBIOS_QUEUE_TAGS_ENABLED (1<<3)
196 u_char bus_width; /* 0x08/0x10 */
198 u_short sync_period; /* 4*period factor */
201 /* Scam table 8 bytes * 4 */
202 struct Symbios_scam {
205 #define SYMBIOS_SCAM_DEFAULT_METHOD (0)
206 #define SYMBIOS_SCAM_DONT_ASSIGN (1)
207 #define SYMBIOS_SCAM_SET_SPECIFIC_ID (2)
208 #define SYMBIOS_SCAM_USE_ORDER_GIVEN (3)
210 #define SYMBIOS_SCAM_UNKNOWN (0)
211 #define SYMBIOS_SCAM_DEVICE_NOT_FOUND (1)
212 #define SYMBIOS_SCAM_ID_NOT_SET (2)
213 #define SYMBIOS_SCAM_ID_VALID (3)
218 u_char spare_devices[15*8];
219 u_char trailer[6]; /* 0xfe 0xfe 0x00 0x00 0x00 0x00 */
221 typedef struct Symbios_nvram Symbios_nvram;
222 typedef struct Symbios_host Symbios_host;
223 typedef struct Symbios_target Symbios_target;
224 typedef struct Symbios_scam Symbios_scam;
227 * Tekram NvRAM data format.
229 #define TEKRAM_NVRAM_SIZE 64
230 #define TEKRAM_93C46_NVRAM_ADDRESS 0
231 #define TEKRAM_24C16_NVRAM_ADDRESS 0x40
233 struct Tekram_nvram {
234 struct Tekram_target {
236 #define TEKRAM_PARITY_CHECK (1)
237 #define TEKRAM_SYNC_NEGO (1<<1)
238 #define TEKRAM_DISCONNECT_ENABLE (1<<2)
239 #define TEKRAM_START_CMD (1<<3)
240 #define TEKRAM_TAGGED_COMMANDS (1<<4)
241 #define TEKRAM_WIDE_NEGO (1<<5)
247 #define TEKRAM_MORE_THAN_2_DRIVES (1)
248 #define TEKRAM_DRIVES_SUP_1GB (1<<1)
249 #define TEKRAM_RESET_ON_POWER_ON (1<<2)
250 #define TEKRAM_ACTIVE_NEGATION (1<<3)
251 #define TEKRAM_IMMEDIATE_SEEK (1<<4)
252 #define TEKRAM_SCAN_LUNS (1<<5)
253 #define TEKRAM_REMOVABLE_FLAGS (3<<6) /* 0: disable; 1: boot device; 2:all */
254 u_char boot_delay_index;
255 u_char max_tags_index;
257 #define TEKRAM_F2_F6_ENABLED (1)
260 typedef struct Tekram_nvram Tekram_nvram;
261 typedef struct Tekram_target Tekram_target;
264 * SYM53C8XX IO register data structure.
267 /*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */
269 /*01*/ u8 nc_scntl1; /* no reset */
270 #define ISCON 0x10 /* connected to scsi */
271 #define CRST 0x08 /* force reset */
272 #define IARB 0x02 /* immediate arbitration */
274 /*02*/ u8 nc_scntl2; /* no disconnect expected */
275 #define SDU 0x80 /* cmd: disconnect will raise error */
276 #define CHM 0x40 /* sta: chained mode */
277 #define WSS 0x08 /* sta: wide scsi send [W]*/
278 #define WSR 0x01 /* sta: wide scsi received [W]*/
280 /*03*/ u8 nc_scntl3; /* cnf system clock dependent */
281 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
282 #define ULTRA 0x80 /* cmd: ULTRA enable */
283 /* bits 0-2, 7 rsvd for C1010 */
285 /*04*/ u8 nc_scid; /* cnf host adapter scsi address */
286 #define RRE 0x40 /* r/w:e enable response to resel. */
287 #define SRE 0x20 /* r/w:e enable response to select */
289 /*05*/ u8 nc_sxfer; /* ### Sync speed and count */
290 /* bits 6-7 rsvd for C1010 */
292 /*06*/ u8 nc_sdid; /* ### Destination-ID */
294 /*07*/ u8 nc_gpreg; /* ??? IO-Pins */
296 /*08*/ u8 nc_sfbr; /* ### First byte received */
299 #define CREQ 0x80 /* r/w: SCSI-REQ */
300 #define CACK 0x40 /* r/w: SCSI-ACK */
301 #define CBSY 0x20 /* r/w: SCSI-BSY */
302 #define CSEL 0x10 /* r/w: SCSI-SEL */
303 #define CATN 0x08 /* r/w: SCSI-ATN */
304 #define CMSG 0x04 /* r/w: SCSI-MSG */
305 #define CC_D 0x02 /* r/w: SCSI-C_D */
306 #define CI_O 0x01 /* r/w: SCSI-I_O */
313 #define DFE 0x80 /* sta: dma fifo empty */
314 #define MDPE 0x40 /* int: master data parity error */
315 #define BF 0x20 /* int: script: bus fault */
316 #define ABRT 0x10 /* int: script: command aborted */
317 #define SSI 0x08 /* int: script: single step */
318 #define SIR 0x04 /* int: script: interrupt instruct. */
319 #define IID 0x01 /* int: script: illegal instruct. */
322 #define ILF 0x80 /* sta: data in SIDL register lsb */
323 #define ORF 0x40 /* sta: data in SODR register lsb */
324 #define OLF 0x20 /* sta: data in SODL register lsb */
325 #define AIP 0x10 /* sta: arbitration in progress */
326 #define LOA 0x08 /* sta: arbitration lost */
327 #define WOA 0x04 /* sta: arbitration won */
328 #define IRST 0x02 /* sta: scsi reset signal */
329 #define SDP 0x01 /* sta: scsi parity signal */
332 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
335 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
336 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
337 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
338 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
339 #define LDSC 0x02 /* sta: disconnect & reconnect */
341 /*10*/ u8 nc_dsa; /* --> Base page */
346 /*14*/ u8 nc_istat; /* --> Main Command and status */
347 #define CABRT 0x80 /* cmd: abort current operation */
348 #define SRST 0x40 /* mod: reset chip */
349 #define SIGP 0x20 /* r/w: message from host to script */
350 #define SEM 0x10 /* r/w: message between host + script */
351 #define CON 0x08 /* sta: connected to scsi */
352 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
353 #define SIP 0x02 /* sta: scsi-interrupt */
354 #define DIP 0x01 /* sta: host/script interrupt */
356 /*15*/ u8 nc_istat1; /* 896 only */
357 /*16*/ u8 nc_mbox0; /* 896 only */
358 /*17*/ u8 nc_mbox1; /* 896 only */
365 /* bits 0-2,7 rsvd for C1010 */
368 #define FLF 0x08 /* cmd: flush dma fifo */
369 #define CLF 0x04 /* cmd: clear dma fifo */
370 #define FM 0x02 /* mod: fetch pin mode */
371 #define WRIE 0x01 /* mod: write and invalidate enable */
372 /* bits 4-7 rsvd for C1010 */
374 /*1c*/ u32 nc_temp; /* ### Temporary stack */
378 #define BDIS 0x80 /* mod: burst disable */
379 #define MPEE 0x08 /* mod: master parity error enable */
382 #define DFS 0x20 /* mod: dma fifo size */
383 /* bits 0-1, 3-7 rsvd for C1010 */
387 /*24*/ u32 nc_dbc; /* ### Byte count and command */
388 /*28*/ u32 nc_dnad; /* ### Next command register */
389 /*2c*/ u32 nc_dsp; /* --> Script Pointer */
390 /*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */
392 /*34*/ u8 nc_scratcha; /* Temporary register a */
393 /*35*/ u8 nc_scratcha1;
394 /*36*/ u8 nc_scratcha2;
395 /*37*/ u8 nc_scratcha3;
398 #define BL_2 0x80 /* mod: burst length shift value +2 */
399 #define BL_1 0x40 /* mod: burst length shift value +1 */
400 #define ERL 0x08 /* mod: enable read line */
401 #define ERMP 0x04 /* mod: enable read multiple */
402 #define BOF 0x02 /* mod: burst op code fetch */
407 /*3b*/ u8 nc_dcntl; /* --> Script execution control */
408 #define CLSE 0x80 /* mod: cache line size enable */
409 #define PFF 0x40 /* cmd: pre-fetch flush */
410 #define PFEN 0x20 /* mod: pre-fetch enable */
411 #define SSM 0x10 /* mod: single step mode */
412 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
413 #define STD 0x04 /* cmd: start dma mode */
414 #define IRQD 0x02 /* mod: irq disable */
415 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
416 /* bits 0-1 rsvd for C1010 */
420 /*40*/ u16 nc_sien; /* -->: interrupt enable */
421 /*42*/ u16 nc_sist; /* <--: interrupt status */
422 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
423 #define STO 0x0400/* sta: timeout (select) */
424 #define GEN 0x0200/* sta: timeout (general) */
425 #define HTH 0x0100/* sta: timeout (handshake) */
426 #define MA 0x80 /* sta: phase mismatch */
427 #define CMP 0x40 /* sta: arbitration complete */
428 #define SEL 0x20 /* sta: selected by another device */
429 #define RSL 0x10 /* sta: reselected by another device*/
430 #define SGE 0x08 /* sta: gross error (over/underflow)*/
431 #define UDC 0x04 /* sta: unexpected disconnect */
432 #define RST 0x02 /* sta: scsi bus reset detected */
433 #define PAR 0x01 /* sta: scsi parity error */
439 /*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/
440 /*49*/ u8 nc_stime1; /* cmd: timeout user defined */
441 /*4a*/ u16 nc_respid; /* sta: Reselect-IDs */
446 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
447 #define DBLEN 0x08 /* clock doubler running */
448 #define DBLSEL 0x04 /* clock doubler selected */
452 #define ROF 0x40 /* reset scsi offset (after gross error!) */
453 #define EXT 0x02 /* extended filtering */
456 #define TE 0x80 /* c: tolerAnt enable */
457 #define HSC 0x20 /* c: Halt SCSI Clock */
458 #define CSF 0x02 /* c: clear scsi fifo */
460 /*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */
462 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
463 #define SMODE_HVD 0x40 /* High Voltage Differential */
464 #define SMODE_SE 0x80 /* Single Ended */
465 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
466 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
467 /* bits 0-5 rsvd for C1010 */
470 /*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */
471 /*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
472 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
473 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
474 #define ENNDJ 0x20 /* Enable Non Data PM Jump */
475 #define DISFC 0x10 /* Disable Auto FIFO Clear */
476 #define DILS 0x02 /* Disable Internal Load/Store */
477 #define DPR 0x01 /* Disable Pipe Req */
479 /*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */
480 #define ZMOD 0x80 /* High Impedance Mode */
481 #define DDAC 0x08 /* Disable Dual Address Cycle */
482 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
483 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
484 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
486 /*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */
489 /*5c*/ u8 nc_scr0; /* Working register B */
494 /*60*/ u8 nc_scrx[64]; /* Working register C-R */
495 /*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */
496 /*a4*/ u32 nc_mmws; /* Memory Move Write Selector */
497 /*a8*/ u32 nc_sfs; /* Script Fetch Selector */
498 /*ac*/ u32 nc_drs; /* DSA Relative Selector */
499 /*b0*/ u32 nc_sbms; /* Static Block Move Selector */
500 /*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
501 /*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
502 /*bc*/ u16 nc_scntl4; /* C1010 only */
503 #define U3EN 0x80 /* Enable Ultra 3 */
504 #define AIPCKEN 0x40 /* AIP checking enable */
505 /* Also enable AIP generation on C10-33*/
506 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT edge */
507 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST edge */
508 #define XCLKS_DT 0x02 /* Extra clock of data set on DT edge */
509 #define XCLKS_ST 0x01 /* Extra clock of data set on ST edge */
510 /*be*/ u8 nc_aipcntl0; /* AIP Control 0 C1010 only */
511 /*bf*/ u8 nc_aipcntl1; /* AIP Control 1 C1010 only */
512 #define DISAIP 0x08 /* Disable AIP generation C10-66 only */
513 /*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
514 /*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
515 /*c8*/ u8 nc_rbc; /* Remaining Byte Count */
520 /*cc*/ u8 nc_ua; /* Updated Address */
524 /*d0*/ u32 nc_esa; /* Entry Storage Address */
525 /*d4*/ u8 nc_ia; /* Instruction Address */
529 /*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
530 /*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */
531 /* Following for C1010 only */
532 /*e0*/ u16 nc_crcpad; /* CRC Value */
533 /*e2*/ u8 nc_crccntl0; /* CRC control register */
534 #define SNDCRC 0x10 /* Send CRC Request */
535 /*e3*/ u8 nc_crccntl1; /* CRC control register */
536 /*e4*/ u32 nc_crcdata; /* CRC data register */
539 /*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */
542 /*-----------------------------------------------------------
544 * Utility macros for the script.
546 *-----------------------------------------------------------
549 #define REGJ(p,r) (offsetof(struct sym_reg, p ## r))
550 #define REG(r) REGJ (nc_, r)
554 /*-----------------------------------------------------------
558 *-----------------------------------------------------------
561 #define SCR_DATA_OUT 0x00000000
562 #define SCR_DATA_IN 0x01000000
563 #define SCR_COMMAND 0x02000000
564 #define SCR_STATUS 0x03000000
565 #define SCR_DT_DATA_OUT 0x04000000
566 #define SCR_DT_DATA_IN 0x05000000
567 #define SCR_MSG_OUT 0x06000000
568 #define SCR_MSG_IN 0x07000000
569 /* DT phases are illegal for non Ultra3 mode */
570 #define SCR_ILG_OUT 0x04000000
571 #define SCR_ILG_IN 0x05000000
573 /*-----------------------------------------------------------
575 * Data transfer via SCSI.
577 *-----------------------------------------------------------
588 *-----------------------------------------------------------
591 #define OPC_MOVE 0x08000000
593 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
594 #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
595 #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
597 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
598 #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
599 #define SCR_CHMOV_TBL (0x10000000)
606 /*-----------------------------------------------------------
610 *-----------------------------------------------------------
612 * SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
613 * <<alternate_address>>
615 * SEL_TBL | << dnad_offset>> [ | REL_JMP]
616 * <<alternate_address>>
618 *-----------------------------------------------------------
621 #define SCR_SEL_ABS 0x40000000
622 #define SCR_SEL_ABS_ATN 0x41000000
623 #define SCR_SEL_TBL 0x42000000
624 #define SCR_SEL_TBL_ATN 0x43000000
627 u_char sel_scntl4; /* C1010 only */
633 #define SCR_JMP_REL 0x04000000
634 #define SCR_ID(id) (((u32)(id)) << 16)
636 /*-----------------------------------------------------------
638 * Waiting for Disconnect or Reselect
640 *-----------------------------------------------------------
643 * dummy: <<alternate_address>>
646 * <<alternate_address>>
648 *-----------------------------------------------------------
651 #define SCR_WAIT_DISC 0x48000000
652 #define SCR_WAIT_RESEL 0x50000000
654 /*-----------------------------------------------------------
658 *-----------------------------------------------------------
664 *-----------------------------------------------------------
667 #define SCR_SET(f) (0x58000000 | (f))
668 #define SCR_CLR(f) (0x60000000 | (f))
670 #define SCR_CARRY 0x00000400
671 #define SCR_TRG 0x00000200
672 #define SCR_ACK 0x00000040
673 #define SCR_ATN 0x00000008
676 /*-----------------------------------------------------------
678 * Memory to memory move
680 *-----------------------------------------------------------
683 * << source_address >>
684 * << destination_address >>
686 * SCR_COPY sets the NO FLUSH option by default.
687 * SCR_COPY_F does not set this option.
689 * For chips which do not support this option,
690 * sym_copy_and_bind() will remove this bit.
692 *-----------------------------------------------------------
695 #define SCR_NO_FLUSH 0x01000000
697 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
698 #define SCR_COPY_F(n) (0xc0000000 | (n))
700 /*-----------------------------------------------------------
702 * Register move and binary operations
704 *-----------------------------------------------------------
706 * SFBR_REG (reg, op, data) reg = SFBR op data
709 * REG_SFBR (reg, op, data) SFBR = reg op data
712 * REG_REG (reg, op, data) reg = reg op data
715 *-----------------------------------------------------------
717 * On 825A, 875, 895 and 896 chips the content
718 * of SFBR register can be used as data (SCR_SFBR_DATA).
719 * The 896 has additionnal IO registers starting at
720 * offset 0x80. Bit 7 of register offset is stored in
721 * bit 7 of the SCRIPTS instruction first DWORD.
723 *-----------------------------------------------------------
726 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
728 #define SCR_SFBR_REG(reg,op,data) \
729 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
731 #define SCR_REG_SFBR(reg,op,data) \
732 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
734 #define SCR_REG_REG(reg,op,data) \
735 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
738 #define SCR_LOAD 0x00000000
739 #define SCR_SHL 0x01000000
740 #define SCR_OR 0x02000000
741 #define SCR_XOR 0x03000000
742 #define SCR_AND 0x04000000
743 #define SCR_SHR 0x05000000
744 #define SCR_ADD 0x06000000
745 #define SCR_ADDC 0x07000000
747 #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
749 /*-----------------------------------------------------------
751 * FROM_REG (reg) SFBR = reg
754 * TO_REG (reg) reg = SFBR
757 * LOAD_REG (reg, data) reg = <data>
760 * LOAD_SFBR(data) SFBR = <data>
763 *-----------------------------------------------------------
766 #define SCR_FROM_REG(reg) \
767 SCR_REG_SFBR(reg,SCR_OR,0)
769 #define SCR_TO_REG(reg) \
770 SCR_SFBR_REG(reg,SCR_OR,0)
772 #define SCR_LOAD_REG(reg,data) \
773 SCR_REG_REG(reg,SCR_LOAD,data)
775 #define SCR_LOAD_SFBR(data) \
776 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
778 /*-----------------------------------------------------------
780 * LOAD from memory to register.
781 * STORE from register to memory.
783 * Only supported by 810A, 860, 825A, 875, 895 and 896.
785 *-----------------------------------------------------------
790 * LOAD_REL (LEN) (DSA relative)
793 *-----------------------------------------------------------
796 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
797 #define SCR_NO_FLUSH2 0x02000000
798 #define SCR_DSA_REL2 0x10000000
800 #define SCR_LOAD_R(reg, how, n) \
801 (0xe1000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))
803 #define SCR_STORE_R(reg, how, n) \
804 (0xe0000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))
806 #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
807 #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
808 #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
809 #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
811 #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
812 #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
813 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
814 #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
817 /*-----------------------------------------------------------
819 * Waiting for Disconnect or Reselect
821 *-----------------------------------------------------------
823 * JUMP [ | IFTRUE/IFFALSE ( ... ) ]
826 * JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
829 * CALL [ | IFTRUE/IFFALSE ( ... ) ]
832 * CALLR [ | IFTRUE/IFFALSE ( ... ) ]
835 * RETURN [ | IFTRUE/IFFALSE ( ... ) ]
838 * INT [ | IFTRUE/IFFALSE ( ... ) ]
841 * INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
850 *-----------------------------------------------------------
853 #define SCR_NO_OP 0x80000000
854 #define SCR_JUMP 0x80080000
855 #define SCR_JUMP64 0x80480000
856 #define SCR_JUMPR 0x80880000
857 #define SCR_CALL 0x88080000
858 #define SCR_CALLR 0x88880000
859 #define SCR_RETURN 0x90080000
860 #define SCR_INT 0x98080000
861 #define SCR_INT_FLY 0x98180000
863 #define IFFALSE(arg) (0x00080000 | (arg))
864 #define IFTRUE(arg) (0x00000000 | (arg))
866 #define WHEN(phase) (0x00030000 | (phase))
867 #define IF(phase) (0x00020000 | (phase))
869 #define DATA(D) (0x00040000 | ((D) & 0xff))
870 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
872 #define CARRYSET (0x00200000)
874 /*-----------------------------------------------------------
878 *-----------------------------------------------------------
885 #define M_COMPLETE (0x00)
886 #define M_EXTENDED (0x01)
887 #define M_SAVE_DP (0x02)
888 #define M_RESTORE_DP (0x03)
889 #define M_DISCONNECT (0x04)
890 #define M_ID_ERROR (0x05)
891 #define M_ABORT (0x06)
892 #define M_REJECT (0x07)
893 #define M_NOOP (0x08)
894 #define M_PARITY (0x09)
895 #define M_LCOMPLETE (0x0a)
896 #define M_FCOMPLETE (0x0b)
897 #define M_RESET (0x0c)
898 #define M_ABORT_TAG (0x0d)
899 #define M_CLEAR_QUEUE (0x0e)
900 #define M_INIT_REC (0x0f)
901 #define M_REL_REC (0x10)
902 #define M_TERMINATE (0x11)
903 #define M_SIMPLE_TAG (0x20)
904 #define M_HEAD_TAG (0x21)
905 #define M_ORDERED_TAG (0x22)
906 #define M_IGN_RESIDUE (0x23)
907 #define M_IDENTIFY (0x80)
909 #define M_X_MODIFY_DP (0x00)
910 #define M_X_SYNC_REQ (0x01)
911 #define M_X_WIDE_REQ (0x03)
912 #define M_X_PPR_REQ (0x04)
915 * PPR protocol options
917 #define PPR_OPT_IU (0x01)
918 #define PPR_OPT_DT (0x02)
919 #define PPR_OPT_QAS (0x04)
920 #define PPR_OPT_MASK (0x07)
926 #define S_GOOD (0x00)
927 #define S_CHECK_COND (0x02)
928 #define S_COND_MET (0x04)
929 #define S_BUSY (0x08)
931 #define S_INT_COND_MET (0x14)
932 #define S_CONFLICT (0x18)
933 #define S_TERMINATED (0x20)
934 #define S_QUEUE_FULL (0x28)
935 #define S_ILLEGAL (0xff)
937 #endif /* defined SYM_DEFS_H */