2 * SPDX-License-Identifier: BSD-3-Clause
4 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010
5 * PCI-SCSI controllers.
7 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
9 * This driver also supports the following Symbios/LSI PCI-SCSI chips:
10 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895,
11 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode.
14 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver.
15 * Copyright (C) 1998-1999 Gerard Roudier
17 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
18 * a port of the FreeBSD ncr driver to Linux-1.2.13.
20 * The original ncr driver has been written for 386bsd and FreeBSD by
21 * Wolfgang Stanglmeier <wolf@cologne.de>
22 * Stefan Esser <se@mi.Uni-Koeln.de>
23 * Copyright (C) 1994 Wolfgang Stanglmeier
25 * The initialisation code, and part of the code that addresses
26 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM
27 * written by Justin T. Gibbs.
29 * Other major contributions:
31 * NVRAM detection and reading.
32 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
34 *-----------------------------------------------------------------------------
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
44 * 3. The name of the author may not be used to endorse or promote products
45 * derived from this software without specific prior written permission.
47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
51 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
63 * Scripts for SYMBIOS-Processor
65 * We have to know the offsets of all labels before we reach
66 * them (for forward jumps). Therefore we declare a struct
67 * here. If you make changes inside the script,
69 * DONT FORGET TO CHANGE THE LENGTHS HERE!
73 * Script fragments which are loaded into the on-chip RAM
74 * of 825A, 875, 876, 895, 895A, 896 and 1010 chips.
75 * Must not exceed 4K bytes.
79 u32 getjob_begin [ 4];
85 #ifdef SYM_CONF_IARB_SUPPORT
102 #ifdef SYM_CONF_IARB_SUPPORT
109 u32 complete_error [ 4];
114 u32 disconnect [ 20];
115 #ifdef SYM_CONF_IARB_SUPPORT
120 #ifdef SYM_CONF_IARB_SUPPORT
126 u32 reselected [ 22];
127 u32 resel_scntl4 [ 20];
129 #if SYM_CONF_MAX_TASK*4 > 512
131 #elif SYM_CONF_MAX_TASK*4 > 256
138 u32 resel_no_tag [ 6];
139 u32 data_in [SYM_CONF_MAX_SG * 2];
141 u32 data_out [SYM_CONF_MAX_SG * 2];
144 u32 pm0_data_out [ 6];
145 u32 pm0_data_end [ 6];
147 u32 pm1_data_out [ 6];
148 u32 pm1_data_end [ 6];
152 * Script fragments which stay in main memory for all chips
153 * except for chips that support 8K on-chip RAM.
158 u32 sel_for_abort [ 18];
159 u32 sel_for_abort_1 [ 2];
160 u32 msg_in_etc [ 12];
161 u32 msg_received [ 4];
162 u32 msg_weird_seen [ 4];
163 u32 msg_extended [ 20];
174 u32 nego_bad_phase [ 4];
176 u32 msg_out_done [ 4];
178 u32 data_ovrun1 [ 22];
179 u32 data_ovrun2 [ 8];
180 u32 abort_resel [ 16];
181 u32 resend_ident [ 4];
182 u32 ident_break [ 4];
183 u32 ident_break_atn [ 4];
185 u32 resel_bad_lun [ 4];
187 u32 bad_i_t_l_q [ 4];
196 u32 pm_wsr_handle [ 42];
197 u32 wsr_ma_helper [ 4];
202 u32 pm0_data_addr [ 1];
203 u32 pm1_data_addr [ 1];
209 /* End of data area */
215 static const struct SYM_FWA_SCR SYM_FWA_SCR = {
216 /*--------------------------< START >----------------------------*/ {
219 * Will be patched with a NO_OP if LED
220 * not needed or not desired.
222 SCR_REG_REG (gpreg, SCR_AND, 0xfe),
227 SCR_FROM_REG (ctest2),
230 * Stop here if the C code wants to perform
231 * some error recovery procedure manually.
232 * (Indicate this by setting SEM in ISTAT)
234 SCR_FROM_REG (istat),
237 * Report to the C code the next position in
238 * the start queue the SCRIPTS will schedule.
239 * The C code must not change SCRATCHA.
241 SCR_LOAD_ABS (scratcha, 4),
243 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
246 * Start the next job.
248 * @DSA = start point for this job.
249 * SCRATCHA = address of this job in the start queue.
251 * We will restore startpos with SCRATCHA if we fails the
252 * arbitration or if it is the idle job.
254 * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS
255 * is a critical path. If it is partially executed, it then
256 * may happen that the job address is not yet in the DSA
257 * and the next queue position points to the next JOB.
259 SCR_LOAD_ABS (dsa, 4),
261 SCR_LOAD_REL (temp, 4),
263 }/*-------------------------< GETJOB_BEGIN >---------------------*/,{
264 SCR_STORE_ABS (temp, 4),
266 SCR_LOAD_REL (dsa, 4),
268 }/*-------------------------< GETJOB_END >-----------------------*/,{
269 SCR_LOAD_REL (temp, 4),
273 }/*-------------------------< SELECT >---------------------------*/,{
275 * DSA contains the address of a scheduled
278 * SCRATCHA contains the address of the start queue
279 * entry which points to the next job.
281 * Set Initiator mode.
283 * (Target mode is left as an exercise for the reader)
288 * And try to select this target.
290 SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select),
293 * Now there are 4 possibilities:
295 * (1) The chip loses arbitration.
296 * This is ok, because it will try again,
297 * when the bus becomes idle.
298 * (But beware of the timeout function!)
300 * (2) The chip is reselected.
301 * Then the script processor takes the jump
302 * to the RESELECT label.
304 * (3) The chip wins arbitration.
305 * Then it will execute SCRIPTS instruction until
306 * the next instruction that checks SCSI phase.
307 * Then will stop and wait for selection to be
308 * complete or selection time-out to occur.
310 * After having won arbitration, the SCRIPTS
311 * processor is able to execute instructions while
312 * the SCSI core is performing SCSI selection.
315 * load the savep (saved data pointer) into
316 * the actual data pointer.
318 SCR_LOAD_REL (temp, 4),
319 offsetof (struct sym_ccb, phys.head.savep),
321 * Initialize the status registers
323 SCR_LOAD_REL (scr0, 4),
324 offsetof (struct sym_ccb, phys.head.status),
325 }/*-------------------------< WF_SEL_DONE >----------------------*/,{
326 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)),
327 SIR_SEL_ATN_NO_MSG_OUT,
328 }/*-------------------------< SEL_DONE >-------------------------*/,{
330 * C1010-33 errata work-around.
331 * Due to a race, the SCSI core may not have
332 * loaded SCNTL3 on SEL_TBL instruction.
333 * We reload it once phase is stable.
334 * Patched with a NOOP for other chips.
336 SCR_LOAD_REL (scntl3, 1),
337 offsetof(struct sym_dsb, select.sel_scntl3),
338 }/*-------------------------< SEND_IDENT >-----------------------*/,{
340 * Selection complete.
341 * Send the IDENTIFY and possibly the TAG message
342 * and negotiation message if present.
344 SCR_MOVE_TBL ^ SCR_MSG_OUT,
345 offsetof (struct sym_dsb, smsg),
346 }/*-------------------------< SELECT2 >--------------------------*/,{
347 #ifdef SYM_CONF_IARB_SUPPORT
349 * Set IMMEDIATE ARBITRATION if we have been given
350 * a hint to do so. (Some job to do after this one).
352 SCR_FROM_REG (HF_REG),
354 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
356 SCR_REG_REG (scntl1, SCR_OR, IARB),
360 * Anticipate the COMMAND phase.
361 * This is the PHASE we expect at this point.
363 SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)),
364 PADDR_A (sel_no_cmd),
365 }/*-------------------------< COMMAND >--------------------------*/,{
367 * ... and send the command
369 SCR_MOVE_TBL ^ SCR_COMMAND,
370 offsetof (struct sym_dsb, cmd),
371 }/*-------------------------< DISPATCH >-------------------------*/,{
373 * MSG_IN is the only phase that shall be
374 * entered at least once for each (re)selection.
375 * So we test it first.
377 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
379 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)),
380 PADDR_A (datao_phase),
381 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)),
382 PADDR_A (datai_phase),
383 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)),
385 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)),
387 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)),
390 * Discard as many illegal phases as
391 * required and tell the C code about.
393 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)),
395 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT,
397 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)),
399 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)),
401 SCR_MOVE_ABS (1) ^ SCR_ILG_IN,
403 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)),
409 }/*-------------------------< SEL_NO_CMD >-----------------------*/,{
411 * The target does not switch to command
412 * phase after IDENTIFY has been sent.
414 * If it stays in MSG OUT phase send it
415 * the IDENTIFY again.
417 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
418 PADDR_B (resend_ident),
420 * If target does not switch to MSG IN phase
421 * and we sent a negotiation, assert the
422 * failure immediately.
424 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
426 SCR_FROM_REG (HS_REG),
428 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
431 * Jump to dispatcher.
435 }/*-------------------------< INIT >-----------------------------*/,{
437 * Wait for the SCSI RESET signal to be
438 * inactive before restarting operations,
439 * since the chip may hang on SEL_ATN
440 * if SCSI RESET is active.
442 SCR_FROM_REG (sstat0),
444 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
448 }/*-------------------------< CLRACK >---------------------------*/,{
450 * Terminate possible pending message phase.
456 }/*-------------------------< DISP_STATUS >----------------------*/,{
458 * Anticipate STATUS phase.
460 * Does spare 3 SCRIPTS instructions when we have
461 * completed the INPUT of the data.
463 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)),
467 }/*-------------------------< DATAI_DONE >-----------------------*/,{
469 * If the device still wants to send us data,
470 * we must count the extra bytes.
472 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_IN)),
473 PADDR_B (data_ovrun),
475 * If the SWIDE is not full, jump to dispatcher.
476 * We anticipate a STATUS phase.
478 SCR_FROM_REG (scntl2),
480 SCR_JUMP ^ IFFALSE (MASK (WSR, WSR)),
481 PADDR_A (disp_status),
484 * Clear this condition.
486 SCR_REG_REG (scntl2, SCR_OR, WSR),
489 * We are expecting an IGNORE RESIDUE message
490 * from the device, otherwise we are in data
491 * overrun condition. Check against MSG_IN phase.
493 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
495 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
496 PADDR_A (disp_status),
498 * We are in MSG_IN phase,
499 * Read the first byte of the message.
500 * If it is not an IGNORE RESIDUE message,
501 * signal overrun and jump to message
504 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
506 SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)),
508 SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)),
511 * We got the message we expected.
512 * Read the 2nd byte, and jump to dispatcher.
516 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
521 PADDR_A (disp_status),
522 }/*-------------------------< DATAO_DONE >-----------------------*/,{
524 * If the device wants us to send more data,
525 * we must count the extra bytes.
527 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_OUT)),
528 PADDR_B (data_ovrun),
530 * If the SODL is not full jump to dispatcher.
531 * We anticipate a STATUS phase.
533 SCR_FROM_REG (scntl2),
535 SCR_JUMP ^ IFFALSE (MASK (WSS, WSS)),
536 PADDR_A (disp_status),
538 * The SODL is full, clear this condition.
540 SCR_REG_REG (scntl2, SCR_OR, WSS),
543 * And signal a DATA UNDERRUN condition
550 }/*-------------------------< DATAI_PHASE >----------------------*/,{
553 }/*-------------------------< DATAO_PHASE >----------------------*/,{
555 * C1010-66 errata work-around.
556 * Extra clocks of data hold must be inserted
557 * in DATA OUT phase on 33 MHz PCI BUS.
558 * Patched with a NOOP for other chips.
560 SCR_REG_REG (scntl4, SCR_OR, (XCLKH_DT|XCLKH_ST)),
564 }/*-------------------------< MSG_IN >---------------------------*/,{
566 * Get the first byte of the message.
568 * The script processor doesn't negate the
569 * ACK signal after this transfer.
571 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
573 }/*-------------------------< MSG_IN2 >--------------------------*/,{
575 * Check first against 1 byte messages
576 * that we handle from SCRIPTS.
578 SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)),
580 SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)),
581 PADDR_A (disconnect),
582 SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)),
584 SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)),
585 PADDR_A (restore_dp),
587 * We handle all other messages from the
588 * C code, so no need to waste on-chip RAM
592 PADDR_B (msg_in_etc),
593 }/*-------------------------< STATUS >---------------------------*/,{
597 SCR_MOVE_ABS (1) ^ SCR_STATUS,
599 #ifdef SYM_CONF_IARB_SUPPORT
601 * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION,
602 * since we may have to tamper the start queue from
605 SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)),
607 SCR_REG_REG (scntl1, SCR_AND, ~IARB),
611 * save status to scsi_status.
616 SCR_LOAD_REG (HS_REG, HS_COMPLETE),
619 * Anticipate the MESSAGE PHASE for
620 * the TASK COMPLETE message.
622 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
626 }/*-------------------------< COMPLETE >-------------------------*/,{
630 * Copy the data pointer to LASTP.
632 SCR_STORE_REL (temp, 4),
633 offsetof (struct sym_ccb, phys.head.lastp),
635 * When we terminate the cycle by clearing ACK,
636 * the target may disconnect immediately.
638 * We don't want to be told of an "unexpected disconnect",
639 * so we disable this feature.
641 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
644 * Terminate cycle ...
646 SCR_CLR (SCR_ACK|SCR_ATN),
649 * ... and wait for the disconnect.
653 }/*-------------------------< COMPLETE2 >------------------------*/,{
657 SCR_STORE_REL (scr0, 4),
658 offsetof (struct sym_ccb, phys.head.status),
660 * Some bridges may reorder DMA writes to memory.
661 * We donnot want the CPU to deal with completions
662 * without all the posted write having been flushed
663 * to memory. This DUMMY READ should flush posted
664 * buffers prior to the CPU having to deal with
667 SCR_LOAD_REL (scr0, 4), /* DUMMY READ */
668 offsetof (struct sym_ccb, phys.head.status),
671 * If command resulted in not GOOD status,
672 * call the C code if needed.
674 SCR_FROM_REG (SS_REG),
676 SCR_CALL ^ IFFALSE (DATA (S_GOOD)),
677 PADDR_B (bad_status),
679 * If we performed an auto-sense, call
680 * the C code to synchronyze task aborts
681 * with UNIT ATTENTION conditions.
683 SCR_FROM_REG (HF_REG),
685 SCR_JUMPR ^ IFTRUE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
687 }/*-------------------------< COMPLETE_ERROR >-------------------*/,{
688 SCR_LOAD_ABS (scratcha, 4),
692 }/*-------------------------< DONE >-----------------------------*/,{
694 * Copy the DSA to the DONE QUEUE and
695 * signal completion to the host.
696 * If we are interrupted between DONE
697 * and DONE_END, we must reset, otherwise
698 * the completed CCB may be lost.
700 SCR_STORE_ABS (dsa, 4),
702 SCR_LOAD_ABS (dsa, 4),
704 SCR_LOAD_ABS (scratcha, 4),
706 SCR_STORE_REL (scratcha, 4),
709 * The instruction below reads the DONE QUEUE next
710 * free position from memory.
711 * In addition it ensures that all PCI posted writes
712 * are flushed and so the DSA value of the done
713 * CCB is visible by the CPU before INTFLY is raised.
715 SCR_LOAD_REL (temp, 4),
719 SCR_STORE_ABS (temp, 4),
721 }/*-------------------------< DONE_END >-------------------------*/,{
724 }/*-------------------------< SAVE_DP >--------------------------*/,{
726 * Clear ACK immediately.
727 * No need to delay it.
732 * Keep track we received a SAVE DP, so
733 * we will switch to the other PM context
734 * on the next PM since the DP may point
735 * to the current PM context.
737 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED),
741 * Copy the data pointer to SAVEP.
743 SCR_STORE_REL (temp, 4),
744 offsetof (struct sym_ccb, phys.head.savep),
747 }/*-------------------------< RESTORE_DP >-----------------------*/,{
749 * RESTORE_DP message:
750 * Copy SAVEP to actual data pointer.
752 SCR_LOAD_REL (temp, 4),
753 offsetof (struct sym_ccb, phys.head.savep),
756 }/*-------------------------< DISCONNECT >-----------------------*/,{
760 * disable the "unexpected disconnect" feature,
761 * and remove the ACK signal.
763 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
765 SCR_CLR (SCR_ACK|SCR_ATN),
768 * Wait for the disconnect.
773 * Status is: DISCONNECTED.
775 SCR_LOAD_REG (HS_REG, HS_DISCONNECT),
780 SCR_STORE_REL (scr0, 4),
781 offsetof (struct sym_ccb, phys.head.status),
783 * If QUIRK_AUTOSAVE is set,
784 * do a "save pointer" operation.
786 SCR_FROM_REG (QU_REG),
788 SCR_JUMP ^ IFFALSE (MASK (SYM_QUIRK_AUTOSAVE, SYM_QUIRK_AUTOSAVE)),
791 * like SAVE_DP message:
792 * Remember we saved the data pointer.
793 * Copy data pointer to SAVEP.
795 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED),
797 SCR_STORE_REL (temp, 4),
798 offsetof (struct sym_ccb, phys.head.savep),
801 }/*-------------------------< IDLE >-----------------------------*/,{
804 * Switch the LED off and wait for reselect.
805 * Will be patched with a NO_OP if LED
806 * not needed or not desired.
808 SCR_REG_REG (gpreg, SCR_OR, 0x01),
810 #ifdef SYM_CONF_IARB_SUPPORT
814 }/*-------------------------< UNGETJOB >-------------------------*/,{
815 #ifdef SYM_CONF_IARB_SUPPORT
817 * Set IMMEDIATE ARBITRATION, for the next time.
818 * This will give us better chance to win arbitration
819 * for the job we just wanted to do.
821 SCR_REG_REG (scntl1, SCR_OR, IARB),
825 * We are not able to restart the SCRIPTS if we are
826 * interrupted and these instruction haven't been
827 * all executed. BTW, this is very unlikely to
828 * happen, but we check that from the C code.
830 SCR_LOAD_REG (dsa, 0xff),
832 SCR_STORE_ABS (scratcha, 4),
834 }/*-------------------------< RESELECT >-------------------------*/,{
836 * Make sure we are in initiator mode.
841 * Sleep waiting for a reselection.
845 }/*-------------------------< RESELECTED >-----------------------*/,{
848 * Will be patched with a NO_OP if LED
849 * not needed or not desired.
851 SCR_REG_REG (gpreg, SCR_AND, 0xfe),
854 * load the target id into the sdid
856 SCR_REG_SFBR (ssid, SCR_AND, 0x8F),
861 * Load the target control block address
863 SCR_LOAD_ABS (dsa, 4),
865 SCR_SFBR_REG (dsa, SCR_SHL, 0),
867 SCR_REG_REG (dsa, SCR_SHL, 0),
869 SCR_REG_REG (dsa, SCR_AND, 0x3c),
871 SCR_LOAD_REL (dsa, 4),
874 * We expect MESSAGE IN phase.
875 * If not, get help from the C code.
877 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
880 * Load the legacy synchronous transfer registers.
882 SCR_LOAD_REL (scntl3, 1),
883 offsetof(struct sym_tcb, head.wval),
884 SCR_LOAD_REL (sxfer, 1),
885 offsetof(struct sym_tcb, head.sval),
886 }/*-------------------------< RESEL_SCNTL4 >---------------------*/,{
888 * The C1010 uses a new synchronous timing scheme.
889 * Will be patched with a NO_OP if not a C1010.
891 SCR_LOAD_REL (scntl4, 1),
892 offsetof(struct sym_tcb, head.uval),
894 * Get the IDENTIFY message.
896 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
899 * If IDENTIFY LUN #0, use a faster path
900 * to find the LCB structure.
902 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
903 PADDR_A (resel_lun0),
905 * If message isn't an IDENTIFY,
906 * tell the C code about.
908 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
909 SIR_RESEL_NO_IDENTIFY,
911 * It is an IDENTIFY message,
912 * Load the LUN control block address.
914 SCR_LOAD_REL (dsa, 4),
915 offsetof(struct sym_tcb, head.luntbl_sa),
916 SCR_SFBR_REG (dsa, SCR_SHL, 0),
918 SCR_REG_REG (dsa, SCR_SHL, 0),
920 SCR_REG_REG (dsa, SCR_AND, 0xfc),
922 SCR_LOAD_REL (dsa, 4),
926 }/*-------------------------< RESEL_LUN0 >-----------------------*/,{
928 * LUN 0 special case (but usual one :))
930 SCR_LOAD_REL (dsa, 4),
931 offsetof(struct sym_tcb, head.lun0_sa),
933 * Jump indirectly to the reselect action for this LUN.
935 SCR_LOAD_REL (temp, 4),
936 offsetof(struct sym_lcb, head.resel_sa),
939 /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */
940 }/*-------------------------< RESEL_TAG >------------------------*/,{
942 * ACK the IDENTIFY previously received.
947 * It shall be a tagged command.
949 * The C code will deal with errors.
950 * Aggressive optimization, isn't it? :)
952 SCR_MOVE_ABS (2) ^ SCR_MSG_IN,
955 * Load the pointer to the tagged task
956 * table for this LUN.
958 SCR_LOAD_REL (dsa, 4),
959 offsetof(struct sym_lcb, head.itlq_tbl_sa),
961 * The SIDL still contains the TAG value.
962 * Aggressive optimization, isn't it? :):)
964 SCR_REG_SFBR (sidl, SCR_SHL, 0),
966 #if SYM_CONF_MAX_TASK*4 > 512
967 SCR_JUMPR ^ IFFALSE (CARRYSET),
969 SCR_REG_REG (dsa1, SCR_OR, 2),
971 SCR_REG_REG (sfbr, SCR_SHL, 0),
973 SCR_JUMPR ^ IFFALSE (CARRYSET),
975 SCR_REG_REG (dsa1, SCR_OR, 1),
977 #elif SYM_CONF_MAX_TASK*4 > 256
978 SCR_JUMPR ^ IFFALSE (CARRYSET),
980 SCR_REG_REG (dsa1, SCR_OR, 1),
984 * Retrieve the DSA of this task.
985 * JUMP indirectly to the restart point of the CCB.
987 SCR_SFBR_REG (dsa, SCR_AND, 0xfc),
989 SCR_LOAD_REL (dsa, 4),
991 SCR_LOAD_REL (temp, 4),
992 offsetof(struct sym_ccb, phys.head.go.restart),
995 /* In normal situations we branch to RESEL_DSA */
996 }/*-------------------------< RESEL_DSA >------------------------*/,{
998 * ACK the IDENTIFY or TAG previously received.
1002 }/*-------------------------< RESEL_DSA1 >-----------------------*/,{
1004 * load the savep (saved pointer) into
1005 * the actual data pointer.
1007 SCR_LOAD_REL (temp, 4),
1008 offsetof (struct sym_ccb, phys.head.savep),
1010 * Initialize the status registers
1012 SCR_LOAD_REL (scr0, 4),
1013 offsetof (struct sym_ccb, phys.head.status),
1015 * Jump to dispatcher.
1019 }/*-------------------------< RESEL_NO_TAG >---------------------*/,{
1021 * Load the DSA with the unique ITL task.
1023 SCR_LOAD_REL (dsa, 4),
1024 offsetof(struct sym_lcb, head.itl_task_sa),
1026 * JUMP indirectly to the restart point of the CCB.
1028 SCR_LOAD_REL (temp, 4),
1029 offsetof(struct sym_ccb, phys.head.go.restart),
1032 /* In normal situations we branch to RESEL_DSA */
1033 }/*-------------------------< DATA_IN >--------------------------*/,{
1035 * Because the size depends on the
1036 * #define SYM_CONF_MAX_SG parameter,
1037 * it is filled in at runtime.
1039 * ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1040 * || SCR_CHMOV_TBL ^ SCR_DATA_IN,
1041 * || offsetof (struct sym_dsb, data[ i]),
1042 * ##==========================================
1045 }/*-------------------------< DATA_IN2 >-------------------------*/,{
1047 PADDR_A (datai_done),
1049 PADDR_B (data_ovrun),
1050 }/*-------------------------< DATA_OUT >-------------------------*/,{
1052 * Because the size depends on the
1053 * #define SYM_CONF_MAX_SG parameter,
1054 * it is filled in at runtime.
1056 * ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1057 * || SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1058 * || offsetof (struct sym_dsb, data[ i]),
1059 * ##==========================================
1062 }/*-------------------------< DATA_OUT2 >------------------------*/,{
1064 PADDR_A (datao_done),
1066 PADDR_B (data_ovrun),
1067 }/*-------------------------< PM0_DATA >-------------------------*/,{
1069 * Read our host flags to SFBR, so we will be able
1070 * to check against the data direction we expect.
1072 SCR_FROM_REG (HF_REG),
1075 * Check against actual DATA PHASE.
1077 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
1078 PADDR_A (pm0_data_out),
1080 * Actual phase is DATA IN.
1081 * Check against expected direction.
1083 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1084 PADDR_B (data_ovrun),
1086 * Keep track we are moving data from the
1087 * PM0 DATA mini-script.
1089 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
1092 * Move the data to memory.
1094 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1095 offsetof (struct sym_ccb, phys.pm0.sg),
1097 PADDR_A (pm0_data_end),
1098 }/*-------------------------< PM0_DATA_OUT >---------------------*/,{
1100 * Actual phase is DATA OUT.
1101 * Check against expected direction.
1103 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
1104 PADDR_B (data_ovrun),
1106 * Keep track we are moving data from the
1107 * PM0 DATA mini-script.
1109 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
1112 * Move the data from memory.
1114 SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1115 offsetof (struct sym_ccb, phys.pm0.sg),
1116 }/*-------------------------< PM0_DATA_END >---------------------*/,{
1118 * Clear the flag that told we were moving
1119 * data from the PM0 DATA mini-script.
1121 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)),
1124 * Return to the previous DATA script which
1125 * is guaranteed by design (if no bug) to be
1126 * the main DATA script for this transfer.
1128 SCR_LOAD_REL (temp, 4),
1129 offsetof (struct sym_ccb, phys.pm0.ret),
1132 }/*-------------------------< PM1_DATA >-------------------------*/,{
1134 * Read our host flags to SFBR, so we will be able
1135 * to check against the data direction we expect.
1137 SCR_FROM_REG (HF_REG),
1140 * Check against actual DATA PHASE.
1142 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
1143 PADDR_A (pm1_data_out),
1145 * Actual phase is DATA IN.
1146 * Check against expected direction.
1148 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1149 PADDR_B (data_ovrun),
1151 * Keep track we are moving data from the
1152 * PM1 DATA mini-script.
1154 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
1157 * Move the data to memory.
1159 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1160 offsetof (struct sym_ccb, phys.pm1.sg),
1162 PADDR_A (pm1_data_end),
1163 }/*-------------------------< PM1_DATA_OUT >---------------------*/,{
1165 * Actual phase is DATA OUT.
1166 * Check against expected direction.
1168 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
1169 PADDR_B (data_ovrun),
1171 * Keep track we are moving data from the
1172 * PM1 DATA mini-script.
1174 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
1177 * Move the data from memory.
1179 SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1180 offsetof (struct sym_ccb, phys.pm1.sg),
1181 }/*-------------------------< PM1_DATA_END >---------------------*/,{
1183 * Clear the flag that told we were moving
1184 * data from the PM1 DATA mini-script.
1186 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)),
1189 * Return to the previous DATA script which
1190 * is guaranteed by design (if no bug) to be
1191 * the main DATA script for this transfer.
1193 SCR_LOAD_REL (temp, 4),
1194 offsetof (struct sym_ccb, phys.pm1.ret),
1197 }/*-------------------------<>-----------------------------------*/
1200 static const struct SYM_FWB_SCR SYM_FWB_SCR = {
1201 /*--------------------------< START64 >--------------------------*/ {
1203 * SCRIPT entry point for the 895A, 896 and 1010.
1204 * For now, there is no specific stuff for those
1205 * chips at this point, but this may come.
1209 }/*-------------------------< NO_DATA >--------------------------*/,{
1211 PADDR_B (data_ovrun),
1212 }/*-------------------------< SEL_FOR_ABORT >--------------------*/,{
1214 * We are jumped here by the C code, if we have
1215 * some target to reset or some disconnected
1216 * job to abort. Since error recovery is a serious
1217 * busyness, we will really reset the SCSI BUS, if
1218 * case of a SCSI interrupt occurring in this path.
1222 * Set initiator mode.
1227 * And try to select this target.
1229 SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel),
1232 * Wait for the selection to complete or
1233 * the selection to time out.
1235 SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1241 SIR_TARGET_SELECTED,
1243 * The C code should let us continue here.
1244 * Send the 'kiss of death' message.
1245 * We expect an immediate disconnect once
1246 * the target has eaten the message.
1248 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1250 SCR_MOVE_TBL ^ SCR_MSG_OUT,
1251 offsetof (struct sym_hcb, abrt_tbl),
1252 SCR_CLR (SCR_ACK|SCR_ATN),
1257 * Tell the C code that we are done.
1261 }/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{
1263 * Jump at scheduler.
1267 }/*-------------------------< MSG_IN_ETC >-----------------------*/,{
1269 * If it is an EXTENDED (variable size message)
1272 SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)),
1273 PADDR_B (msg_extended),
1275 * Let the C code handle any other
1278 SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)),
1279 PADDR_B (msg_received),
1280 SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)),
1281 PADDR_B (msg_received),
1283 * We donnot handle 2 bytes messages from SCRIPTS.
1284 * So, let the C code deal with these ones too.
1286 SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)),
1287 PADDR_B (msg_weird_seen),
1290 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1292 }/*-------------------------< MSG_RECEIVED >---------------------*/,{
1293 SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */
1297 }/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{
1298 SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */
1302 }/*-------------------------< MSG_EXTENDED >---------------------*/,{
1304 * Clear ACK and get the next byte
1305 * assumed to be the message length.
1309 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1312 * Try to catch some unlikely situations as 0 length
1313 * or too large the length.
1315 SCR_JUMP ^ IFTRUE (DATA (0)),
1316 PADDR_B (msg_weird_seen),
1317 SCR_TO_REG (scratcha),
1319 SCR_REG_REG (sfbr, SCR_ADD, (256-8)),
1321 SCR_JUMP ^ IFTRUE (CARRYSET),
1322 PADDR_B (msg_weird_seen),
1324 * We donnot handle extended messages from SCRIPTS.
1325 * Read the amount of data corresponding to the
1326 * message length and call the C code.
1328 SCR_STORE_REL (scratcha, 1),
1329 offsetof (struct sym_dsb, smsg_ext.size),
1332 SCR_MOVE_TBL ^ SCR_MSG_IN,
1333 offsetof (struct sym_dsb, smsg_ext),
1335 PADDR_B (msg_received),
1336 }/*-------------------------< MSG_BAD >--------------------------*/,{
1338 * unimplemented message - reject it.
1346 }/*-------------------------< MSG_WEIRD >------------------------*/,{
1348 * weird message received
1349 * ignore all MSG IN phases and reject it.
1355 }/*-------------------------< MSG_WEIRD1 >-----------------------*/,{
1358 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
1360 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1363 PADDR_B (msg_weird1),
1364 }/*-------------------------< WDTR_RESP >------------------------*/,{
1366 * let the target fetch our answer.
1372 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1373 PADDR_B (nego_bad_phase),
1374 }/*-------------------------< SEND_WDTR >------------------------*/,{
1376 * Send the M_X_WIDE_REQ
1378 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT,
1381 PADDR_B (msg_out_done),
1382 }/*-------------------------< SDTR_RESP >------------------------*/,{
1384 * let the target fetch our answer.
1390 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1391 PADDR_B (nego_bad_phase),
1392 }/*-------------------------< SEND_SDTR >------------------------*/,{
1394 * Send the M_X_SYNC_REQ
1396 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT,
1399 PADDR_B (msg_out_done),
1400 }/*-------------------------< PPR_RESP >-------------------------*/,{
1402 * let the target fetch our answer.
1408 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1409 PADDR_B (nego_bad_phase),
1410 }/*-------------------------< SEND_PPR >-------------------------*/,{
1412 * Send the M_X_PPR_REQ
1414 SCR_MOVE_ABS (8) ^ SCR_MSG_OUT,
1417 PADDR_B (msg_out_done),
1418 }/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{
1423 }/*-------------------------< MSG_OUT >--------------------------*/,{
1425 * The target requests a message.
1426 * We donnot send messages that may
1427 * require the device to go to bus free.
1429 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
1432 * ... wait for the next phase
1433 * if it's a message out, send it again, ...
1435 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
1437 }/*-------------------------< MSG_OUT_DONE >---------------------*/,{
1439 * Let the C code be aware of the
1440 * sent message and clear the message.
1445 * ... and process the next phase
1449 }/*-------------------------< DATA_OVRUN >-----------------------*/,{
1451 * Use scratcha to count the extra bytes.
1453 SCR_LOAD_ABS (scratcha, 4),
1455 }/*-------------------------< DATA_OVRUN1 >----------------------*/,{
1457 * The target may want to transfer too much data.
1459 * If phase is DATA OUT write 1 byte and count it.
1461 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)),
1463 SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT,
1466 PADDR_B (data_ovrun2),
1468 * If WSR is set, clear this condition, and
1471 SCR_FROM_REG (scntl2),
1473 SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
1475 SCR_REG_REG (scntl2, SCR_OR, WSR),
1478 PADDR_B (data_ovrun2),
1480 * Finally check against DATA IN phase.
1481 * Signal data overrun to the C code
1482 * and jump to dispatcher if not so.
1483 * Read 1 byte otherwise and count it.
1485 SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)),
1491 SCR_CHMOV_ABS (1) ^ SCR_DATA_IN,
1493 }/*-------------------------< DATA_OVRUN2 >----------------------*/,{
1496 * This will allow to return a negative
1499 SCR_REG_REG (scratcha, SCR_ADD, 0x01),
1501 SCR_REG_REG (scratcha1, SCR_ADDC, 0),
1503 SCR_REG_REG (scratcha2, SCR_ADDC, 0),
1506 * .. and repeat as required.
1509 PADDR_B (data_ovrun1),
1510 }/*-------------------------< ABORT_RESEL >----------------------*/,{
1516 * send the abort/abortag/reset message
1517 * we expect an immediate disconnect
1519 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1521 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
1523 SCR_CLR (SCR_ACK|SCR_ATN),
1531 }/*-------------------------< RESEND_IDENT >---------------------*/,{
1533 * The target stays in MSG OUT phase after having acked
1534 * Identify [+ Tag [+ Extended message ]]. Targets shall
1535 * behave this way on parity error.
1536 * We must send it again all the messages.
1538 SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */
1539 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */
1541 PADDR_A (send_ident),
1542 }/*-------------------------< IDENT_BREAK >----------------------*/,{
1547 }/*-------------------------< IDENT_BREAK_ATN >------------------*/,{
1552 }/*-------------------------< SDATA_IN >-------------------------*/,{
1553 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1554 offsetof (struct sym_dsb, sense),
1556 PADDR_A (datai_done),
1558 PADDR_B (data_ovrun),
1559 }/*-------------------------< RESEL_BAD_LUN >--------------------*/,{
1561 * Message is an IDENTIFY, but lun is unknown.
1562 * Signal problem to C code for logging the event.
1563 * Send a M_ABORT to clear all pending tasks.
1568 PADDR_B (abort_resel),
1569 }/*-------------------------< BAD_I_T_L >------------------------*/,{
1571 * We donnot have a task for that I_T_L.
1572 * Signal problem to C code for logging the event.
1573 * Send a M_ABORT message.
1576 SIR_RESEL_BAD_I_T_L,
1578 PADDR_B (abort_resel),
1579 }/*-------------------------< BAD_I_T_L_Q >----------------------*/,{
1581 * We donnot have a task that matches the tag.
1582 * Signal problem to C code for logging the event.
1583 * Send a M_ABORTTAG message.
1586 SIR_RESEL_BAD_I_T_L_Q,
1588 PADDR_B (abort_resel),
1589 }/*-------------------------< BAD_STATUS >-----------------------*/,{
1591 * Anything different from INTERMEDIATE
1592 * CONDITION MET should be a bad SCSI status,
1593 * given that GOOD status has already been tested.
1596 SCR_LOAD_ABS (scratcha, 4),
1598 SCR_INT ^ IFFALSE (DATA (S_COND_MET)),
1599 SIR_BAD_SCSI_STATUS,
1602 }/*-------------------------< PM_HANDLE >------------------------*/,{
1604 * Phase mismatch handling.
1606 * Since we have to deal with 2 SCSI data pointers
1607 * (current and saved), we need at least 2 contexts.
1608 * Each context (pm0 and pm1) has a saved area, a
1609 * SAVE mini-script and a DATA phase mini-script.
1612 * Get the PM handling flags.
1614 SCR_FROM_REG (HF_REG),
1617 * If no flags (1rst PM for example), avoid
1618 * all the below heavy flags testing.
1619 * This makes the normal case a bit faster.
1621 SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED))),
1622 PADDR_B (pm_handle1),
1624 * If we received a SAVE DP, switch to the
1625 * other PM context since the savep may point
1626 * to the current PM context.
1628 SCR_JUMPR ^ IFFALSE (MASK (HF_DP_SAVED, HF_DP_SAVED)),
1630 SCR_REG_REG (sfbr, SCR_XOR, HF_ACT_PM),
1633 * If we have been interrupt in a PM DATA mini-script,
1634 * we take the return address from the corresponding
1636 * This ensure the return address always points to the
1637 * main DATA script for this transfer.
1639 SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1))),
1640 PADDR_B (pm_handle1),
1641 SCR_JUMPR ^ IFFALSE (MASK (HF_IN_PM0, HF_IN_PM0)),
1643 SCR_LOAD_REL (ia, 4),
1644 offsetof(struct sym_ccb, phys.pm0.ret),
1647 SCR_LOAD_REL (ia, 4),
1648 offsetof(struct sym_ccb, phys.pm1.ret),
1651 }/*-------------------------< PM_HANDLE1 >-----------------------*/,{
1654 * Update the return address so that it
1655 * will point after the interrupted MOVE.
1657 SCR_REG_REG (ia, SCR_ADD, 8),
1659 SCR_REG_REG (ia1, SCR_ADDC, 0),
1661 }/*-------------------------< PM_SAVE >--------------------------*/,{
1663 * Clear all the flags that told us if we were
1664 * interrupted in a PM DATA mini-script and/or
1665 * we received a SAVE DP.
1667 SCR_SFBR_REG (HF_REG, SCR_AND, (~(HF_IN_PM0|HF_IN_PM1|HF_DP_SAVED))),
1670 * Choose the current PM context.
1672 SCR_JUMP ^ IFTRUE (MASK (HF_ACT_PM, HF_ACT_PM)),
1674 }/*-------------------------< PM0_SAVE >-------------------------*/,{
1675 SCR_STORE_REL (ia, 4),
1676 offsetof(struct sym_ccb, phys.pm0.ret),
1678 * If WSR bit is set, either UA and RBC may
1679 * have to be changed whether the device wants
1680 * to ignore this residue or not.
1682 SCR_FROM_REG (scntl2),
1684 SCR_CALL ^ IFTRUE (MASK (WSR, WSR)),
1685 PADDR_B (pm_wsr_handle),
1687 * Save the remaining byte count, the updated
1688 * address and the return address.
1690 SCR_STORE_REL (rbc, 4),
1691 offsetof(struct sym_ccb, phys.pm0.sg.size),
1692 SCR_STORE_REL (ua, 4),
1693 offsetof(struct sym_ccb, phys.pm0.sg.addr),
1695 * Set the current pointer at the PM0 DATA mini-script.
1697 SCR_LOAD_ABS (temp, 4),
1698 PADDR_B (pm0_data_addr),
1701 }/*-------------------------< PM1_SAVE >-------------------------*/,{
1702 SCR_STORE_REL (ia, 4),
1703 offsetof(struct sym_ccb, phys.pm1.ret),
1705 * If WSR bit is set, either UA and RBC may
1706 * have to be changed whether the device wants
1707 * to ignore this residue or not.
1709 SCR_FROM_REG (scntl2),
1711 SCR_CALL ^ IFTRUE (MASK (WSR, WSR)),
1712 PADDR_B (pm_wsr_handle),
1714 * Save the remaining byte count, the updated
1715 * address and the return address.
1717 SCR_STORE_REL (rbc, 4),
1718 offsetof(struct sym_ccb, phys.pm1.sg.size),
1719 SCR_STORE_REL (ua, 4),
1720 offsetof(struct sym_ccb, phys.pm1.sg.addr),
1722 * Set the current pointer at the PM1 DATA mini-script.
1724 SCR_LOAD_ABS (temp, 4),
1725 PADDR_B (pm1_data_addr),
1728 }/*-------------------------< PM_WSR_HANDLE >--------------------*/,{
1730 * Phase mismatch handling from SCRIPT with WSR set.
1731 * Such a condition can occur if the chip wants to
1732 * execute a CHMOV(size > 1) when the WSR bit is
1733 * set and the target changes PHASE.
1735 * We must move the residual byte to memory.
1737 * UA contains bit 0..31 of the address to
1738 * move the residual byte.
1739 * Move it to the table indirect.
1741 SCR_STORE_REL (ua, 4),
1742 offsetof (struct sym_ccb, phys.wresid.addr),
1744 * Increment UA (move address to next position).
1746 SCR_REG_REG (ua, SCR_ADD, 1),
1748 SCR_REG_REG (ua1, SCR_ADDC, 0),
1750 SCR_REG_REG (ua2, SCR_ADDC, 0),
1752 SCR_REG_REG (ua3, SCR_ADDC, 0),
1755 * Compute SCRATCHA as:
1756 * - size to transfer = 1 byte.
1757 * - bit 24..31 = high address bit [32...39].
1759 SCR_LOAD_ABS (scratcha, 4),
1761 SCR_REG_REG (scratcha, SCR_OR, 1),
1763 SCR_FROM_REG (rbc3),
1765 SCR_TO_REG (scratcha3),
1768 * Move this value to the table indirect.
1770 SCR_STORE_REL (scratcha, 4),
1771 offsetof (struct sym_ccb, phys.wresid.size),
1773 * Wait for a valid phase.
1774 * While testing with bogus QUANTUM drives, the C1010
1775 * sometimes raised a spurious phase mismatch with
1776 * WSR and the CHMOV(1) triggered another PM.
1777 * Waiting explicitely for the PHASE seemed to avoid
1778 * the nested phase mismatch. Btw, this didn't happen
1779 * using my IBM drives.
1781 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_IN)),
1784 * Perform the move of the residual byte.
1786 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1787 offsetof (struct sym_ccb, phys.wresid),
1789 * We can now handle the phase mismatch with UA fixed.
1790 * RBC[0..23]=0 is a special case that does not require
1791 * a PM context. The C code also checks against this.
1795 SCR_RETURN ^ IFFALSE (DATA (0)),
1797 SCR_FROM_REG (rbc1),
1799 SCR_RETURN ^ IFFALSE (DATA (0)),
1801 SCR_FROM_REG (rbc2),
1803 SCR_RETURN ^ IFFALSE (DATA (0)),
1807 * Not only we donnot need a PM context, but this would
1808 * lead to a bogus CHMOV(0). This condition means that
1809 * the residual was the last byte to move from this CHMOV.
1810 * So, we just have to move the current data script pointer
1811 * (i.e. TEMP) to the SCRIPTS address following the
1812 * interrupted CHMOV and jump to dispatcher.
1814 SCR_STORE_ABS (ia, 4),
1816 SCR_LOAD_ABS (temp, 4),
1820 }/*-------------------------< WSR_MA_HELPER >--------------------*/,{
1822 * Helper for the C code when WSR bit is set.
1823 * Perform the move of the residual byte.
1825 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1826 offsetof (struct sym_ccb, phys.wresid),
1829 }/*-------------------------< ZERO >-----------------------------*/,{
1831 }/*-------------------------< SCRATCH >--------------------------*/,{
1833 }/*-------------------------< PM0_DATA_ADDR >--------------------*/,{
1835 }/*-------------------------< PM1_DATA_ADDR >--------------------*/,{
1837 }/*-------------------------< SAVED_DSA >------------------------*/,{
1839 }/*-------------------------< SAVED_DRS >------------------------*/,{
1841 }/*-------------------------< DONE_POS >-------------------------*/,{
1843 }/*-------------------------< STARTPOS >-------------------------*/,{
1845 }/*-------------------------< TARGTBL >--------------------------*/,{
1848 }/*-------------------------< SNOOPTEST >------------------------*/,{
1850 * Read the variable from memory.
1852 SCR_LOAD_REL (scratcha, 4),
1853 offsetof(struct sym_hcb, cache),
1855 * Write the variable to memory.
1857 SCR_STORE_REL (temp, 4),
1858 offsetof(struct sym_hcb, cache),
1860 * Read back the variable from memory.
1862 SCR_LOAD_REL (temp, 4),
1863 offsetof(struct sym_hcb, cache),
1864 }/*-------------------------< SNOOPEND >-------------------------*/,{
1870 }/*-------------------------<>-----------------------------------*/