2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012 Robert N. M. Watson
7 * This software was developed by SRI International and the University of
8 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
9 * ("CTSRD"), as part of the DARPA CRASH research programme.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
39 #include <sys/consio.h> /* struct vt_mode */
40 #include <sys/endian.h>
41 #include <sys/fbio.h> /* video_adapter_t */
43 #include <sys/mutex.h>
45 #include <sys/systm.h>
48 #include <machine/bus.h>
49 #include <machine/resource.h>
50 #include <machine/vm.h>
52 #include <dev/terasic/mtl/terasic_mtl.h>
54 static d_mmap_t terasic_mtl_reg_mmap;
55 static d_read_t terasic_mtl_reg_read;
56 static d_write_t terasic_mtl_reg_write;
58 static struct cdevsw terasic_mtl_reg_cdevsw = {
59 .d_version = D_VERSION,
60 .d_mmap = terasic_mtl_reg_mmap,
61 .d_read = terasic_mtl_reg_read,
62 .d_write = terasic_mtl_reg_write,
63 .d_name = "terasic_mtl_reg",
67 * All I/O to/from the MTL register device must be 32-bit, and aligned to
71 terasic_mtl_reg_read(struct cdev *dev, struct uio *uio, int flag)
73 struct terasic_mtl_softc *sc;
78 if (uio->uio_offset < 0 || uio->uio_offset % 4 != 0 ||
79 uio->uio_resid % 4 != 0)
82 size = rman_get_size(sc->mtl_reg_res);
84 if ((uio->uio_offset + uio->uio_resid < 0) ||
85 (uio->uio_offset + uio->uio_resid > size))
87 while (uio->uio_resid > 0) {
88 offset = uio->uio_offset;
89 if (offset + sizeof(v) > size)
91 v = bus_read_4(sc->mtl_reg_res, offset);
92 error = uiomove(&v, sizeof(v), uio);
100 terasic_mtl_reg_write(struct cdev *dev, struct uio *uio, int flag)
102 struct terasic_mtl_softc *sc;
107 if (uio->uio_offset < 0 || uio->uio_offset % 4 != 0 ||
108 uio->uio_resid % 4 != 0)
111 size = rman_get_size(sc->mtl_reg_res);
113 while (uio->uio_resid > 0) {
114 offset = uio->uio_offset;
115 if (offset + sizeof(v) > size)
117 error = uiomove(&v, sizeof(v), uio);
120 bus_write_4(sc->mtl_reg_res, offset, v);
126 terasic_mtl_reg_mmap(struct cdev *dev, vm_ooffset_t offset, vm_paddr_t *paddr,
127 int nprot, vm_memattr_t *memattr)
129 struct terasic_mtl_softc *sc;
134 if (trunc_page(offset) == offset &&
135 offset + PAGE_SIZE > offset &&
136 rman_get_size(sc->mtl_reg_res) >= offset + PAGE_SIZE) {
137 *paddr = rman_get_start(sc->mtl_reg_res) + offset;
138 *memattr = VM_MEMATTR_UNCACHEABLE;
145 terasic_mtl_reg_blend_get(struct terasic_mtl_softc *sc, uint32_t *blendp)
148 *blendp = le32toh(bus_read_4(sc->mtl_reg_res, TERASIC_MTL_OFF_BLEND));
152 terasic_mtl_reg_blend_set(struct terasic_mtl_softc *sc, uint32_t blend)
155 bus_write_4(sc->mtl_reg_res, TERASIC_MTL_OFF_BLEND, htole32(blend));
159 terasic_mtl_blend_default_set(struct terasic_mtl_softc *sc, uint8_t colour)
163 TERASIC_MTL_LOCK(sc);
164 terasic_mtl_reg_blend_get(sc, &v);
165 v &= ~TERASIC_MTL_BLEND_DEFAULT_MASK;
166 v |= colour << TERASIC_MTL_BLEND_DEFAULT_SHIFT;
167 terasic_mtl_reg_blend_set(sc, v);
168 TERASIC_MTL_UNLOCK(sc);
172 terasic_mtl_blend_pixel_set(struct terasic_mtl_softc *sc, uint8_t alpha)
176 TERASIC_MTL_LOCK(sc);
177 terasic_mtl_reg_blend_get(sc, &v);
178 v &= ~TERASIC_MTL_BLEND_PIXEL_MASK;
179 v |= alpha << TERASIC_MTL_BLEND_PIXEL_SHIFT;
180 terasic_mtl_reg_blend_set(sc, v);
181 TERASIC_MTL_UNLOCK(sc);
185 terasic_mtl_blend_textfg_set(struct terasic_mtl_softc *sc, uint8_t alpha)
189 TERASIC_MTL_LOCK(sc);
190 terasic_mtl_reg_blend_get(sc, &v);
191 v &= ~TERASIC_MTL_BLEND_TEXTFG_MASK;
192 v |= alpha << TERASIC_MTL_BLEND_TEXTFG_SHIFT;
193 terasic_mtl_reg_blend_set(sc, v);
194 TERASIC_MTL_UNLOCK(sc);
198 terasic_mtl_blend_textbg_set(struct terasic_mtl_softc *sc, uint8_t alpha)
202 TERASIC_MTL_LOCK(sc);
203 terasic_mtl_reg_blend_get(sc, &v);
204 v &= ~TERASIC_MTL_BLEND_TEXTBG_MASK;
205 v |= alpha << TERASIC_MTL_BLEND_TEXTBG_SHIFT;
206 terasic_mtl_reg_blend_set(sc, v);
207 TERASIC_MTL_UNLOCK(sc);
211 terasic_mtl_reg_pixel_endian_set(struct terasic_mtl_softc *sc, int endian_swap)
215 TERASIC_MTL_LOCK(sc);
216 terasic_mtl_reg_blend_get(sc, &v);
218 v |= TERASIC_MTL_BLEND_PIXEL_ENDIAN_SWAP;
220 v &= ~TERASIC_MTL_BLEND_PIXEL_ENDIAN_SWAP;
221 terasic_mtl_reg_blend_set(sc, v);
222 TERASIC_MTL_UNLOCK(sc);
226 terasic_mtl_reg_textcursor_get(struct terasic_mtl_softc *sc, uint8_t *colp,
231 v = bus_read_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTCURSOR);
233 *colp = (v & TERASIC_MTL_TEXTCURSOR_COL_MASK) >>
234 TERASIC_MTL_TEXTCURSOR_COL_SHIFT;
235 *rowp = (v & TERASIC_MTL_TEXTCURSOR_ROW_MASK);
239 terasic_mtl_reg_textcursor_set(struct terasic_mtl_softc *sc, uint8_t col,
244 v = (col << TERASIC_MTL_TEXTCURSOR_COL_SHIFT) | row;
246 bus_write_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTCURSOR, v);
250 terasic_mtl_reg_blank(struct terasic_mtl_softc *sc)
253 device_printf(sc->mtl_dev, "%s: not yet\n", __func__);
257 terasic_mtl_reg_textframebufaddr_get(struct terasic_mtl_softc *sc,
262 addr = bus_read_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTFRAMEBUFADDR);
263 *addrp = le32toh(addr);
267 terasic_mtl_reg_textframebufaddr_set(struct terasic_mtl_softc *sc,
271 addr = htole32(addr);
272 bus_write_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTFRAMEBUFADDR, addr);
276 terasic_mtl_reg_attach(struct terasic_mtl_softc *sc)
279 sc->mtl_reg_cdev = make_dev(&terasic_mtl_reg_cdevsw, sc->mtl_unit,
280 UID_ROOT, GID_WHEEL, 0400, "mtl_reg%d", sc->mtl_unit);
281 if (sc->mtl_reg_cdev == NULL) {
282 device_printf(sc->mtl_dev, "%s: make_dev failed\n", __func__);
285 /* XXXRW: Slight race between make_dev(9) and here. */
286 sc->mtl_reg_cdev->si_drv1 = sc;
291 terasic_mtl_reg_detach(struct terasic_mtl_softc *sc)
294 if (sc->mtl_reg_cdev != NULL)
295 destroy_dev(sc->mtl_reg_cdev);