2 * Copyright (c) 2012 Robert N. M. Watson
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
37 #include <sys/consio.h> /* struct vt_mode */
38 #include <sys/endian.h>
39 #include <sys/fbio.h> /* video_adapter_t */
41 #include <sys/mutex.h>
43 #include <sys/systm.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
48 #include <machine/vm.h>
50 #include <dev/terasic/mtl/terasic_mtl.h>
52 static d_mmap_t terasic_mtl_reg_mmap;
53 static d_read_t terasic_mtl_reg_read;
54 static d_write_t terasic_mtl_reg_write;
56 static struct cdevsw terasic_mtl_reg_cdevsw = {
57 .d_version = D_VERSION,
58 .d_mmap = terasic_mtl_reg_mmap,
59 .d_read = terasic_mtl_reg_read,
60 .d_write = terasic_mtl_reg_write,
61 .d_name = "terasic_mtl_reg",
65 * All I/O to/from the MTL register device must be 32-bit, and aligned to
69 terasic_mtl_reg_read(struct cdev *dev, struct uio *uio, int flag)
71 struct terasic_mtl_softc *sc;
76 if (uio->uio_offset < 0 || uio->uio_offset % 4 != 0 ||
77 uio->uio_resid % 4 != 0)
80 size = rman_get_size(sc->mtl_reg_res);
82 if ((uio->uio_offset + uio->uio_resid < 0) ||
83 (uio->uio_offset + uio->uio_resid > size))
85 while (uio->uio_resid > 0) {
86 offset = uio->uio_offset;
87 if (offset + sizeof(v) > size)
89 v = bus_read_4(sc->mtl_reg_res, offset);
90 error = uiomove(&v, sizeof(v), uio);
98 terasic_mtl_reg_write(struct cdev *dev, struct uio *uio, int flag)
100 struct terasic_mtl_softc *sc;
105 if (uio->uio_offset < 0 || uio->uio_offset % 4 != 0 ||
106 uio->uio_resid % 4 != 0)
109 size = rman_get_size(sc->mtl_reg_res);
111 while (uio->uio_resid > 0) {
112 offset = uio->uio_offset;
113 if (offset + sizeof(v) > size)
115 error = uiomove(&v, sizeof(v), uio);
118 bus_write_4(sc->mtl_reg_res, offset, v);
124 terasic_mtl_reg_mmap(struct cdev *dev, vm_ooffset_t offset, vm_paddr_t *paddr,
125 int nprot, vm_memattr_t *memattr)
127 struct terasic_mtl_softc *sc;
132 if (trunc_page(offset) == offset &&
133 rman_get_size(sc->mtl_reg_res) >= offset + PAGE_SIZE) {
134 *paddr = rman_get_start(sc->mtl_reg_res) + offset;
135 *memattr = VM_MEMATTR_UNCACHEABLE;
142 terasic_mtl_reg_blend_get(struct terasic_mtl_softc *sc, uint32_t *blendp)
145 *blendp = le32toh(bus_read_4(sc->mtl_reg_res, TERASIC_MTL_OFF_BLEND));
149 terasic_mtl_reg_blend_set(struct terasic_mtl_softc *sc, uint32_t blend)
152 bus_write_4(sc->mtl_reg_res, TERASIC_MTL_OFF_BLEND, htole32(blend));
156 terasic_mtl_blend_default_set(struct terasic_mtl_softc *sc, uint8_t colour)
160 TERASIC_MTL_LOCK(sc);
161 terasic_mtl_reg_blend_get(sc, &v);
162 v &= ~TERASIC_MTL_BLEND_DEFAULT_MASK;
163 v |= colour << TERASIC_MTL_BLEND_DEFAULT_SHIFT;
164 terasic_mtl_reg_blend_set(sc, v);
165 TERASIC_MTL_UNLOCK(sc);
169 terasic_mtl_blend_pixel_set(struct terasic_mtl_softc *sc, uint8_t alpha)
173 TERASIC_MTL_LOCK(sc);
174 terasic_mtl_reg_blend_get(sc, &v);
175 v &= ~TERASIC_MTL_BLEND_PIXEL_MASK;
176 v |= alpha << TERASIC_MTL_BLEND_PIXEL_SHIFT;
177 terasic_mtl_reg_blend_set(sc, v);
178 TERASIC_MTL_UNLOCK(sc);
182 terasic_mtl_blend_textfg_set(struct terasic_mtl_softc *sc, uint8_t alpha)
186 TERASIC_MTL_LOCK(sc);
187 terasic_mtl_reg_blend_get(sc, &v);
188 v &= ~TERASIC_MTL_BLEND_TEXTFG_MASK;
189 v |= alpha << TERASIC_MTL_BLEND_TEXTFG_SHIFT;
190 terasic_mtl_reg_blend_set(sc, v);
191 TERASIC_MTL_UNLOCK(sc);
195 terasic_mtl_blend_textbg_set(struct terasic_mtl_softc *sc, uint8_t alpha)
199 TERASIC_MTL_LOCK(sc);
200 terasic_mtl_reg_blend_get(sc, &v);
201 v &= ~TERASIC_MTL_BLEND_TEXTBG_MASK;
202 v |= alpha << TERASIC_MTL_BLEND_TEXTBG_SHIFT;
203 terasic_mtl_reg_blend_set(sc, v);
204 TERASIC_MTL_UNLOCK(sc);
208 terasic_mtl_reg_pixel_endian_set(struct terasic_mtl_softc *sc, int endian_swap)
212 TERASIC_MTL_LOCK(sc);
213 terasic_mtl_reg_blend_get(sc, &v);
215 v |= TERASIC_MTL_BLEND_PIXEL_ENDIAN_SWAP;
217 v &= ~TERASIC_MTL_BLEND_PIXEL_ENDIAN_SWAP;
218 terasic_mtl_reg_blend_set(sc, v);
219 TERASIC_MTL_UNLOCK(sc);
223 terasic_mtl_reg_textcursor_get(struct terasic_mtl_softc *sc, uint8_t *colp,
228 v = bus_read_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTCURSOR);
230 *colp = (v & TERASIC_MTL_TEXTCURSOR_COL_MASK) >>
231 TERASIC_MTL_TEXTCURSOR_COL_SHIFT;
232 *rowp = (v & TERASIC_MTL_TEXTCURSOR_ROW_MASK);
236 terasic_mtl_reg_textcursor_set(struct terasic_mtl_softc *sc, uint8_t col,
241 v = (col << TERASIC_MTL_TEXTCURSOR_COL_SHIFT) | row;
243 bus_write_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTCURSOR, v);
247 terasic_mtl_reg_blank(struct terasic_mtl_softc *sc)
250 device_printf(sc->mtl_dev, "%s: not yet\n", __func__);
254 terasic_mtl_reg_textframebufaddr_get(struct terasic_mtl_softc *sc,
259 addr = bus_read_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTFRAMEBUFADDR);
260 *addrp = le32toh(addr);
264 terasic_mtl_reg_textframebufaddr_set(struct terasic_mtl_softc *sc,
268 addr = htole32(addr);
269 bus_write_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTFRAMEBUFADDR, addr);
273 terasic_mtl_reg_attach(struct terasic_mtl_softc *sc)
276 sc->mtl_reg_cdev = make_dev(&terasic_mtl_reg_cdevsw, sc->mtl_unit,
277 UID_ROOT, GID_WHEEL, 0400, "mtl_reg%d", sc->mtl_unit);
278 if (sc->mtl_reg_cdev == NULL) {
279 device_printf(sc->mtl_dev, "%s: make_dev failed\n", __func__);
282 /* XXXRW: Slight race between make_dev(9) and here. */
283 sc->mtl_reg_cdev->si_drv1 = sc;
288 terasic_mtl_reg_detach(struct terasic_mtl_softc *sc)
291 if (sc->mtl_reg_cdev != NULL)
292 destroy_dev(sc->mtl_reg_cdev);