2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
35 * Manuals, sample driver and firmware source kits are available
36 * from http://www.alteon.com/support/openkits.
38 * Written by Bill Paul <wpaul@ctr.columbia.edu>
39 * Electrical Engineering Department
40 * Columbia University, New York City
44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
48 * filtering and jumbo (9014 byte) frames. The hardware is largely
49 * controlled by firmware, which must be loaded into the NIC during
52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
53 * revision, which supports new features such as extended commands,
54 * extended jumbo receive ring desciptors and a mini receive ring.
56 * Alteon Networks is to be commended for releasing such a vast amount
57 * of development material for the Tigon NIC without requiring an NDA
58 * (although they really should have done it a long time ago). With
59 * any luck, the other vendors will finally wise up and follow Alteon's
62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
63 * this driver by #including it as a C header file. This bloats the
64 * driver somewhat, but it's the easiest method considering that the
65 * driver code and firmware code need to be kept in sync. The source
66 * for the firmware is not provided with the FreeBSD distribution since
67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
69 * The following people deserve special thanks:
70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
72 * - Raymond Lee of Netgear, for providing a pair of Netgear
73 * GA620 Tigon 2 boards for testing
74 * - Ulf Zimmermann, for bringing the GA260 to my attention and
75 * convincing me to write this driver.
76 * - Andrew Gallatin for providing FreeBSD/Alpha support.
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/sockio.h>
88 #include <sys/malloc.h>
89 #include <sys/kernel.h>
90 #include <sys/module.h>
91 #include <sys/socket.h>
92 #include <sys/queue.h>
94 #include <sys/sf_buf.h>
97 #include <net/if_arp.h>
98 #include <net/ethernet.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
101 #include <net/if_types.h>
102 #include <net/if_vlan_var.h>
106 #include <netinet/in_systm.h>
107 #include <netinet/in.h>
108 #include <netinet/ip.h>
110 #include <machine/bus.h>
111 #include <machine/resource.h>
113 #include <sys/rman.h>
115 /* #define TI_PRIVATE_JUMBOS */
116 #ifndef TI_PRIVATE_JUMBOS
118 #include <vm/vm_page.h>
121 #include <dev/pci/pcireg.h>
122 #include <dev/pci/pcivar.h>
124 #include <sys/tiio.h>
125 #include <dev/ti/if_tireg.h>
126 #include <dev/ti/ti_fw.h>
127 #include <dev/ti/ti_fw2.h>
129 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
131 * We can only turn on header splitting if we're using extended receive
134 #if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS)
135 #error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive"
136 #endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */
144 * Various supported device vendors/types and their names.
147 static const struct ti_type const ti_devs[] = {
148 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
149 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
150 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
151 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
152 { TC_VENDORID, TC_DEVICEID_3C985,
153 "3Com 3c985-SX Gigabit Ethernet" },
154 { NG_VENDORID, NG_DEVICEID_GA620,
155 "Netgear GA620 1000baseSX Gigabit Ethernet" },
156 { NG_VENDORID, NG_DEVICEID_GA620T,
157 "Netgear GA620 1000baseT Gigabit Ethernet" },
158 { SGI_VENDORID, SGI_DEVICEID_TIGON,
159 "Silicon Graphics Gigabit Ethernet" },
160 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
161 "Farallon PN9000SX Gigabit Ethernet" },
166 static d_open_t ti_open;
167 static d_close_t ti_close;
168 static d_ioctl_t ti_ioctl2;
170 static struct cdevsw ti_cdevsw = {
171 .d_version = D_VERSION,
175 .d_ioctl = ti_ioctl2,
179 static int ti_probe(device_t);
180 static int ti_attach(device_t);
181 static int ti_detach(device_t);
182 static void ti_txeof(struct ti_softc *);
183 static void ti_rxeof(struct ti_softc *);
185 static void ti_stats_update(struct ti_softc *);
186 static int ti_encap(struct ti_softc *, struct mbuf **);
188 static void ti_intr(void *);
189 static void ti_start(struct ifnet *);
190 static void ti_start_locked(struct ifnet *);
191 static int ti_ioctl(struct ifnet *, u_long, caddr_t);
192 static void ti_init(void *);
193 static void ti_init_locked(void *);
194 static void ti_init2(struct ti_softc *);
195 static void ti_stop(struct ti_softc *);
196 static void ti_watchdog(void *);
197 static int ti_shutdown(device_t);
198 static int ti_ifmedia_upd(struct ifnet *);
199 static int ti_ifmedia_upd_locked(struct ti_softc *);
200 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
202 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
203 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
204 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
206 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
207 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
208 static void ti_setmulti(struct ti_softc *);
210 static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *);
211 static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *);
212 static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t);
213 static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int,
215 static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t,
217 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
218 static void ti_loadfw(struct ti_softc *);
219 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
220 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
221 static void ti_handle_events(struct ti_softc *);
222 static int ti_alloc_dmamaps(struct ti_softc *);
223 static void ti_free_dmamaps(struct ti_softc *);
224 static int ti_alloc_jumbo_mem(struct ti_softc *);
225 #ifdef TI_PRIVATE_JUMBOS
226 static void *ti_jalloc(struct ti_softc *);
227 static void ti_jfree(void *, void *);
228 #endif /* TI_PRIVATE_JUMBOS */
229 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
230 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
231 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
232 static int ti_init_rx_ring_std(struct ti_softc *);
233 static void ti_free_rx_ring_std(struct ti_softc *);
234 static int ti_init_rx_ring_jumbo(struct ti_softc *);
235 static void ti_free_rx_ring_jumbo(struct ti_softc *);
236 static int ti_init_rx_ring_mini(struct ti_softc *);
237 static void ti_free_rx_ring_mini(struct ti_softc *);
238 static void ti_free_tx_ring(struct ti_softc *);
239 static int ti_init_tx_ring(struct ti_softc *);
241 static int ti_64bitslot_war(struct ti_softc *);
242 static int ti_chipinit(struct ti_softc *);
243 static int ti_gibinit(struct ti_softc *);
245 #ifdef TI_JUMBO_HDRSPLIT
246 static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len,
248 #endif /* TI_JUMBO_HDRSPLIT */
250 static device_method_t ti_methods[] = {
251 /* Device interface */
252 DEVMETHOD(device_probe, ti_probe),
253 DEVMETHOD(device_attach, ti_attach),
254 DEVMETHOD(device_detach, ti_detach),
255 DEVMETHOD(device_shutdown, ti_shutdown),
259 static driver_t ti_driver = {
262 sizeof(struct ti_softc)
265 static devclass_t ti_devclass;
267 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
268 MODULE_DEPEND(ti, pci, 1, 1, 1);
269 MODULE_DEPEND(ti, ether, 1, 1, 1);
272 * Send an instruction or address to the EEPROM, check for ACK.
275 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
280 * Make sure we're in TX mode.
282 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
285 * Feed in each bit and stobe the clock.
287 for (i = 0x80; i; i >>= 1) {
289 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
291 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
294 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
296 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
302 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
307 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
308 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
309 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
315 * Read a byte of data stored in the EEPROM at address 'addr.'
316 * We have to send two address bytes since the EEPROM can hold
317 * more than 256 bytes of data.
320 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
328 * Send write control code to EEPROM.
330 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
331 device_printf(sc->ti_dev,
332 "failed to send write command, status: %x\n",
333 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
338 * Send first byte of address of byte we want to read.
340 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
341 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
342 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
346 * Send second byte address of byte we want to read.
348 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
349 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
350 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
357 * Send read control code to EEPROM.
359 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
360 device_printf(sc->ti_dev,
361 "failed to send read command, status: %x\n",
362 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
367 * Start reading bits from EEPROM.
369 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
370 for (i = 0x80; i; i >>= 1) {
371 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
373 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
375 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
382 * No ACK generated for read, so just return byte.
391 * Read a sequence of bytes from the EEPROM.
394 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
399 for (i = 0; i < cnt; i++) {
400 err = ti_eeprom_getbyte(sc, off + i, &byte);
406 return (err ? 1 : 0);
410 * NIC memory read function.
411 * Can be used to copy data from NIC local memory.
414 ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
416 int segptr, segsize, cnt;
427 segsize = TI_WINLEN - (segptr % TI_WINLEN);
428 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
429 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
430 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
440 * NIC memory write function.
441 * Can be used to copy data into NIC local memory.
444 ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
446 int segptr, segsize, cnt;
457 segsize = TI_WINLEN - (segptr % TI_WINLEN);
458 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
459 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
460 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
469 * NIC memory read function.
470 * Can be used to clear a section of NIC local memory.
473 ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len)
475 int segptr, segsize, cnt;
484 segsize = TI_WINLEN - (segptr % TI_WINLEN);
485 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
486 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
487 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4);
494 ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
495 caddr_t buf, int useraddr, int readdata)
497 int segptr, segsize, cnt;
500 uint8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN];
507 * At the moment, we don't handle non-aligned cases, we just bail.
508 * If this proves to be a problem, it will be fixed.
511 && (tigon_addr & 0x3)) {
512 device_printf(sc->ti_dev, "%s: tigon address %#x isn't "
513 "word-aligned\n", __func__, tigon_addr);
514 device_printf(sc->ti_dev, "%s: unaligned writes aren't "
515 "yet supported\n", __func__);
519 segptr = tigon_addr & ~0x3;
520 segresid = tigon_addr - segptr;
523 * This is the non-aligned amount left over that we'll need to
528 /* Add in the left over amount at the front of the buffer */
533 * If resid + segresid is >= 4, add multiples of 4 to the count and
534 * decrease the residual by that much.
537 resid -= resid & ~0x3;
544 * Save the old window base value.
546 origwin = CSR_READ_4(sc, TI_WINBASE);
549 bus_size_t ti_offset;
554 segsize = TI_WINLEN - (segptr % TI_WINLEN);
555 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
557 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
561 bus_space_read_region_4(sc->ti_btag,
562 sc->ti_bhandle, ti_offset,
563 (uint32_t *)tmparray,
567 * Yeah, this is a little on the kludgy
568 * side, but at least this code is only
569 * used for debugging.
571 ti_bcopy_swap(tmparray, tmparray2, segsize,
576 copyout(&tmparray2[segresid], ptr,
580 copyout(tmparray2, ptr, segsize);
585 ti_bcopy_swap(tmparray, tmparray2,
586 segsize, TI_SWAP_NTOH);
588 bcopy(&tmparray2[segresid], ptr,
593 ti_bcopy_swap(tmparray, ptr, segsize,
600 copyin(ptr, tmparray2, segsize);
602 ti_bcopy_swap(tmparray2, tmparray, segsize,
605 ti_bcopy_swap(ptr, tmparray, segsize,
608 bus_space_write_region_4(sc->ti_btag,
609 sc->ti_bhandle, ti_offset,
610 (uint32_t *)tmparray,
619 * Handle leftover, non-word-aligned bytes.
622 uint32_t tmpval, tmpval2;
623 bus_size_t ti_offset;
626 * Set the segment pointer.
628 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
630 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
633 * First, grab whatever is in our source/destination.
634 * We'll obviously need this for reads, but also for
635 * writes, since we'll be doing read/modify/write.
637 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
638 ti_offset, &tmpval, 1);
641 * Next, translate this from little-endian to big-endian
642 * (at least on i386 boxes).
644 tmpval2 = ntohl(tmpval);
648 * If we're reading, just copy the leftover number
649 * of bytes from the host byte order buffer to
654 copyout(&tmpval2, ptr, resid);
657 bcopy(&tmpval2, ptr, resid);
660 * If we're writing, first copy the bytes to be
661 * written into the network byte order buffer,
662 * leaving the rest of the buffer with whatever was
663 * originally in there. Then, swap the bytes
664 * around into host order and write them out.
666 * XXX KDM the read side of this has been verified
667 * to work, but the write side of it has not been
668 * verified. So user beware.
672 copyin(ptr, &tmpval2, resid);
675 bcopy(ptr, &tmpval2, resid);
677 tmpval = htonl(tmpval2);
679 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
680 ti_offset, &tmpval, 1);
684 CSR_WRITE_4(sc, TI_WINBASE, origwin);
690 ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
691 caddr_t buf, int useraddr, int readdata, int cpu)
695 uint32_t tmpval, tmpval2;
701 * At the moment, we don't handle non-aligned cases, we just bail.
702 * If this proves to be a problem, it will be fixed.
704 if (tigon_addr & 0x3) {
705 device_printf(sc->ti_dev, "%s: tigon address %#x "
706 "isn't word-aligned\n", __func__, tigon_addr);
711 device_printf(sc->ti_dev, "%s: transfer length %d "
712 "isn't word-aligned\n", __func__, len);
721 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
724 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
726 tmpval = ntohl(tmpval2);
729 * Note: I've used this debugging interface
730 * extensively with Alteon's 12.3.15 firmware,
731 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
733 * When you compile the firmware without
734 * optimization, which is necessary sometimes in
735 * order to properly step through it, you sometimes
736 * read out a bogus value of 0xc0017c instead of
737 * whatever was supposed to be in that scratchpad
738 * location. That value is on the stack somewhere,
739 * but I've never been able to figure out what was
740 * causing the problem.
742 * The address seems to pop up in random places,
743 * often not in the same place on two subsequent
746 * In any case, the underlying data doesn't seem
747 * to be affected, just the value read out.
752 if (tmpval2 == 0xc0017c)
753 device_printf(sc->ti_dev, "found 0xc0017c at "
754 "%#x (tmpval2)\n", segptr);
756 if (tmpval == 0xc0017c)
757 device_printf(sc->ti_dev, "found 0xc0017c at "
758 "%#x (tmpval)\n", segptr);
761 copyout(&tmpval, ptr, 4);
763 bcopy(&tmpval, ptr, 4);
766 copyin(ptr, &tmpval2, 4);
768 bcopy(ptr, &tmpval2, 4);
770 tmpval = htonl(tmpval2);
772 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
784 ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type)
786 const uint8_t *tmpsrc;
791 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n",
801 if (swap_type == TI_SWAP_NTOH)
802 *(uint32_t *)tmpdst =
803 ntohl(*(const uint32_t *)tmpsrc);
805 *(uint32_t *)tmpdst =
806 htonl(*(const uint32_t *)tmpsrc);
817 * Load firmware image into the NIC. Check that the firmware revision
818 * is acceptable and see if we want the firmware for the Tigon 1 or
822 ti_loadfw(struct ti_softc *sc)
827 switch (sc->ti_hwrev) {
829 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
830 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
831 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
832 device_printf(sc->ti_dev, "firmware revision mismatch; "
833 "want %d.%d.%d, got %d.%d.%d\n",
834 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
835 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
836 tigonFwReleaseMinor, tigonFwReleaseFix);
839 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
840 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
841 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen,
843 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen);
844 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen);
845 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
847 case TI_HWREV_TIGON_II:
848 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
849 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
850 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
851 device_printf(sc->ti_dev, "firmware revision mismatch; "
852 "want %d.%d.%d, got %d.%d.%d\n",
853 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
854 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
855 tigon2FwReleaseMinor, tigon2FwReleaseFix);
858 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen,
860 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen,
862 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
864 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen);
865 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen);
866 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
869 device_printf(sc->ti_dev,
870 "can't load firmware: unknown hardware rev\n");
876 * Send the NIC a command via the command ring.
879 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
883 index = sc->ti_cmd_saved_prodidx;
884 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
885 TI_INC(index, TI_CMD_RING_CNT);
886 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
887 sc->ti_cmd_saved_prodidx = index;
891 * Send the NIC an extended command. The 'len' parameter specifies the
892 * number of command slots to include after the initial command.
895 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len)
900 index = sc->ti_cmd_saved_prodidx;
901 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
902 TI_INC(index, TI_CMD_RING_CNT);
903 for (i = 0; i < len; i++) {
904 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
905 *(uint32_t *)(&arg[i * 4]));
906 TI_INC(index, TI_CMD_RING_CNT);
908 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
909 sc->ti_cmd_saved_prodidx = index;
913 * Handle events that have triggered interrupts.
916 ti_handle_events(struct ti_softc *sc)
918 struct ti_event_desc *e;
920 if (sc->ti_rdata->ti_event_ring == NULL)
923 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
924 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
925 switch (TI_EVENT_EVENT(e)) {
926 case TI_EV_LINKSTAT_CHANGED:
927 sc->ti_linkstat = TI_EVENT_CODE(e);
928 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
929 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
930 sc->ti_ifp->if_baudrate = IF_Mbps(100);
932 device_printf(sc->ti_dev,
934 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
935 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
936 sc->ti_ifp->if_baudrate = IF_Gbps(1UL);
938 device_printf(sc->ti_dev,
939 "gigabit link up\n");
940 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
941 if_link_state_change(sc->ti_ifp,
943 sc->ti_ifp->if_baudrate = 0;
945 device_printf(sc->ti_dev,
950 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
951 device_printf(sc->ti_dev, "invalid command\n");
952 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
953 device_printf(sc->ti_dev, "unknown command\n");
954 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
955 device_printf(sc->ti_dev, "bad config data\n");
957 case TI_EV_FIRMWARE_UP:
960 case TI_EV_STATS_UPDATED:
963 case TI_EV_RESET_JUMBO_RING:
964 case TI_EV_MCAST_UPDATED:
968 device_printf(sc->ti_dev, "unknown event: %d\n",
972 /* Advance the consumer index. */
973 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
974 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
979 ti_alloc_dmamaps(struct ti_softc *sc)
983 for (i = 0; i < TI_TX_RING_CNT; i++) {
984 sc->ti_cdata.ti_txdesc[i].tx_m = NULL;
985 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0;
986 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0,
987 &sc->ti_cdata.ti_txdesc[i].tx_dmamap))
990 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
991 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
992 &sc->ti_cdata.ti_rx_std_maps[i]))
996 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
997 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0,
998 &sc->ti_cdata.ti_rx_jumbo_maps[i]))
1002 /* Mini ring is not available on Tigon 1. */
1003 if (sc->ti_hwrev == TI_HWREV_TIGON)
1006 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1007 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
1008 &sc->ti_cdata.ti_rx_mini_maps[i]))
1016 ti_free_dmamaps(struct ti_softc *sc)
1020 if (sc->ti_mbuftx_dmat)
1021 for (i = 0; i < TI_TX_RING_CNT; i++)
1022 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) {
1023 bus_dmamap_destroy(sc->ti_mbuftx_dmat,
1024 sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1025 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0;
1028 if (sc->ti_mbufrx_dmat)
1029 for (i = 0; i < TI_STD_RX_RING_CNT; i++)
1030 if (sc->ti_cdata.ti_rx_std_maps[i]) {
1031 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1032 sc->ti_cdata.ti_rx_std_maps[i]);
1033 sc->ti_cdata.ti_rx_std_maps[i] = 0;
1036 if (sc->ti_jumbo_dmat)
1037 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++)
1038 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) {
1039 bus_dmamap_destroy(sc->ti_jumbo_dmat,
1040 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1041 sc->ti_cdata.ti_rx_jumbo_maps[i] = 0;
1043 if (sc->ti_mbufrx_dmat)
1044 for (i = 0; i < TI_MINI_RX_RING_CNT; i++)
1045 if (sc->ti_cdata.ti_rx_mini_maps[i]) {
1046 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1047 sc->ti_cdata.ti_rx_mini_maps[i]);
1048 sc->ti_cdata.ti_rx_mini_maps[i] = 0;
1052 #ifdef TI_PRIVATE_JUMBOS
1055 * Memory management for the jumbo receive ring is a pain in the
1056 * butt. We need to allocate at least 9018 bytes of space per frame,
1057 * _and_ it has to be contiguous (unless you use the extended
1058 * jumbo descriptor format). Using malloc() all the time won't
1059 * work: malloc() allocates memory in powers of two, which means we
1060 * would end up wasting a considerable amount of space by allocating
1061 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
1062 * to do our own memory management.
1064 * The driver needs to allocate a contiguous chunk of memory at boot
1065 * time. We then chop this up ourselves into 9K pieces and use them
1066 * as external mbuf storage.
1068 * One issue here is how much memory to allocate. The jumbo ring has
1069 * 256 slots in it, but at 9K per slot than can consume over 2MB of
1070 * RAM. This is a bit much, especially considering we also need
1071 * RAM for the standard ring and mini ring (on the Tigon 2). To
1072 * save space, we only actually allocate enough memory for 64 slots
1073 * by default, which works out to between 500 and 600K. This can
1074 * be tuned by changing a #define in if_tireg.h.
1078 ti_alloc_jumbo_mem(struct ti_softc *sc)
1080 struct ti_jpool_entry *entry;
1085 * Grab a big chunk o' storage. Since we are chopping this pool up
1086 * into ~9k chunks, there doesn't appear to be a need to use page
1089 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
1090 1, 0, /* algnmnt, boundary */
1091 BUS_SPACE_MAXADDR, /* lowaddr */
1092 BUS_SPACE_MAXADDR, /* highaddr */
1093 NULL, NULL, /* filter, filterarg */
1094 TI_JMEM, /* maxsize */
1096 TI_JMEM, /* maxsegsize */
1098 NULL, NULL, /* lockfunc, lockarg */
1099 &sc->ti_jumbo_dmat) != 0) {
1100 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1104 if (bus_dmamem_alloc(sc->ti_jumbo_dmat,
1105 (void**)&sc->ti_cdata.ti_jumbo_buf,
1106 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
1107 &sc->ti_jumbo_dmamap) != 0) {
1108 device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n");
1112 SLIST_INIT(&sc->ti_jfree_listhead);
1113 SLIST_INIT(&sc->ti_jinuse_listhead);
1116 * Now divide it up into 9K pieces and save the addresses
1119 ptr = sc->ti_cdata.ti_jumbo_buf;
1120 for (i = 0; i < TI_JSLOTS; i++) {
1121 sc->ti_cdata.ti_jslots[i] = ptr;
1123 entry = malloc(sizeof(struct ti_jpool_entry),
1124 M_DEVBUF, M_NOWAIT);
1125 if (entry == NULL) {
1126 device_printf(sc->ti_dev, "no memory for jumbo "
1131 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1138 * Allocate a jumbo buffer.
1140 static void *ti_jalloc(struct ti_softc *sc)
1142 struct ti_jpool_entry *entry;
1144 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
1146 if (entry == NULL) {
1147 device_printf(sc->ti_dev, "no free jumbo buffers\n");
1151 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
1152 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
1153 return (sc->ti_cdata.ti_jslots[entry->slot]);
1157 * Release a jumbo buffer.
1160 ti_jfree(void *buf, void *args)
1162 struct ti_softc *sc;
1164 struct ti_jpool_entry *entry;
1166 /* Extract the softc struct pointer. */
1167 sc = (struct ti_softc *)args;
1170 panic("ti_jfree: didn't get softc pointer!");
1172 /* calculate the slot this buffer belongs to */
1173 i = ((vm_offset_t)buf
1174 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
1176 if ((i < 0) || (i >= TI_JSLOTS))
1177 panic("ti_jfree: asked to free buffer that we don't manage!");
1179 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
1181 panic("ti_jfree: buffer not in use!");
1183 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
1184 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1190 ti_alloc_jumbo_mem(struct ti_softc *sc)
1194 * The VM system will take care of providing aligned pages. Alignment
1195 * is set to 1 here so that busdma resources won't be wasted.
1197 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
1198 1, 0, /* algnmnt, boundary */
1199 BUS_SPACE_MAXADDR, /* lowaddr */
1200 BUS_SPACE_MAXADDR, /* highaddr */
1201 NULL, NULL, /* filter, filterarg */
1202 PAGE_SIZE * 4 /*XXX*/, /* maxsize */
1204 PAGE_SIZE, /* maxsegsize */
1206 NULL, NULL, /* lockfunc, lockarg */
1207 &sc->ti_jumbo_dmat) != 0) {
1208 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1215 #endif /* TI_PRIVATE_JUMBOS */
1218 * Intialize a standard receive ring descriptor.
1221 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m)
1224 bus_dma_segment_t segs;
1225 struct mbuf *m_new = NULL;
1226 struct ti_rx_desc *r;
1231 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1235 MCLGET(m_new, M_DONTWAIT);
1236 if (!(m_new->m_flags & M_EXT)) {
1240 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1243 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1244 m_new->m_data = m_new->m_ext.ext_buf;
1247 m_adj(m_new, ETHER_ALIGN);
1248 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
1249 r = &sc->ti_rdata->ti_rx_std_ring[i];
1250 map = sc->ti_cdata.ti_rx_std_maps[i];
1251 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs,
1256 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1257 r->ti_len = segs.ds_len;
1258 r->ti_type = TI_BDTYPE_RECV_BD;
1260 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1261 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1264 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD);
1269 * Intialize a mini receive ring descriptor. This only applies to
1273 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m)
1275 bus_dma_segment_t segs;
1277 struct mbuf *m_new = NULL;
1278 struct ti_rx_desc *r;
1283 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1284 if (m_new == NULL) {
1287 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1290 m_new->m_data = m_new->m_pktdat;
1291 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1294 m_adj(m_new, ETHER_ALIGN);
1295 r = &sc->ti_rdata->ti_rx_mini_ring[i];
1296 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
1297 map = sc->ti_cdata.ti_rx_mini_maps[i];
1298 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs,
1303 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1304 r->ti_len = segs.ds_len;
1305 r->ti_type = TI_BDTYPE_RECV_BD;
1306 r->ti_flags = TI_BDFLAG_MINI_RING;
1307 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1308 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1311 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD);
1315 #ifdef TI_PRIVATE_JUMBOS
1318 * Initialize a jumbo receive ring descriptor. This allocates
1319 * a jumbo buffer from the pool managed internally by the driver.
1322 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m)
1325 struct mbuf *m_new = NULL;
1326 struct ti_rx_desc *r;
1328 bus_dma_segment_t segs;
1331 caddr_t *buf = NULL;
1333 /* Allocate the mbuf. */
1334 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1335 if (m_new == NULL) {
1339 /* Allocate the jumbo buffer */
1340 buf = ti_jalloc(sc);
1343 device_printf(sc->ti_dev, "jumbo allocation failed "
1344 "-- packet dropped!\n");
1348 /* Attach the buffer to the mbuf. */
1349 m_new->m_data = (void *) buf;
1350 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
1351 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, buf,
1352 (struct ti_softc *)sc, 0, EXT_NET_DRV);
1355 m_new->m_data = m_new->m_ext.ext_buf;
1356 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
1359 m_adj(m_new, ETHER_ALIGN);
1360 /* Set up the descriptor. */
1361 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
1362 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
1363 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1364 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs,
1369 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1370 r->ti_len = segs.ds_len;
1371 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1372 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1373 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1374 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1377 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD);
1383 #if (PAGE_SIZE == 4096)
1389 #define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1390 #define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1391 #define NFS_HDR_LEN (UDP_HDR_LEN)
1392 static int HDR_LEN = TCP_HDR_LEN;
1395 * Initialize a jumbo receive ring descriptor. This allocates
1396 * a jumbo buffer from the pool managed internally by the driver.
1399 ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old)
1402 struct mbuf *cur, *m_new = NULL;
1403 struct mbuf *m[3] = {NULL, NULL, NULL};
1404 struct ti_rx_desc_ext *r;
1407 /* 1 extra buf to make nobufs easy*/
1408 struct sf_buf *sf[3] = {NULL, NULL, NULL};
1410 bus_dma_segment_t segs[4];
1413 if (m_old != NULL) {
1415 cur = m_old->m_next;
1416 for (i = 0; i <= NPAYLOAD; i++){
1421 /* Allocate the mbufs. */
1422 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1423 if (m_new == NULL) {
1424 device_printf(sc->ti_dev, "mbuf allocation failed "
1425 "-- packet dropped!\n");
1428 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
1429 if (m[NPAYLOAD] == NULL) {
1430 device_printf(sc->ti_dev, "cluster mbuf allocation "
1431 "failed -- packet dropped!\n");
1434 MCLGET(m[NPAYLOAD], M_DONTWAIT);
1435 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1436 device_printf(sc->ti_dev, "mbuf allocation failed "
1437 "-- packet dropped!\n");
1440 m[NPAYLOAD]->m_len = MCLBYTES;
1442 for (i = 0; i < NPAYLOAD; i++){
1443 MGET(m[i], M_DONTWAIT, MT_DATA);
1445 device_printf(sc->ti_dev, "mbuf allocation "
1446 "failed -- packet dropped!\n");
1449 frame = vm_page_alloc(NULL, color++,
1450 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1452 if (frame == NULL) {
1453 device_printf(sc->ti_dev, "buffer allocation "
1454 "failed -- packet dropped!\n");
1455 printf(" index %d page %d\n", idx, i);
1458 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1459 if (sf[i] == NULL) {
1460 vm_page_unwire(frame, 0);
1461 vm_page_free(frame);
1462 device_printf(sc->ti_dev, "buffer allocation "
1463 "failed -- packet dropped!\n");
1464 printf(" index %d page %d\n", idx, i);
1468 for (i = 0; i < NPAYLOAD; i++){
1469 /* Attach the buffer to the mbuf. */
1470 m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1471 m[i]->m_len = PAGE_SIZE;
1472 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1473 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i],
1475 m[i]->m_next = m[i+1];
1477 /* link the buffers to the header */
1478 m_new->m_next = m[0];
1479 m_new->m_data += ETHER_ALIGN;
1480 if (sc->ti_hdrsplit)
1481 m_new->m_len = MHLEN - ETHER_ALIGN;
1483 m_new->m_len = HDR_LEN;
1484 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1487 /* Set up the descriptor. */
1488 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx];
1489 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1490 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1491 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs,
1494 if ((nsegs < 1) || (nsegs > 4))
1496 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr);
1497 r->ti_len0 = m_new->m_len;
1499 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr);
1500 r->ti_len1 = PAGE_SIZE;
1502 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr);
1503 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1505 if (PAGE_SIZE == 4096) {
1506 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr);
1507 r->ti_len3 = MCLBYTES;
1511 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1513 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1515 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1516 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1520 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD);
1527 * This can only be called before the mbufs are strung together.
1528 * If the mbufs are strung together, m_freem() will free the chain,
1529 * so that the later mbufs will be freed multiple times.
1534 for (i = 0; i < 3; i++) {
1538 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
1545 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1546 * that's 1MB or memory, which is a lot. For now, we fill only the first
1547 * 256 ring entries and hope that our CPU is fast enough to keep up with
1551 ti_init_rx_ring_std(struct ti_softc *sc)
1554 struct ti_cmd_desc cmd;
1556 for (i = 0; i < TI_SSLOTS; i++) {
1557 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
1561 TI_UPDATE_STDPROD(sc, i - 1);
1568 ti_free_rx_ring_std(struct ti_softc *sc)
1573 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1574 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1575 map = sc->ti_cdata.ti_rx_std_maps[i];
1576 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1577 BUS_DMASYNC_POSTREAD);
1578 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1579 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1580 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1582 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
1583 sizeof(struct ti_rx_desc));
1588 ti_init_rx_ring_jumbo(struct ti_softc *sc)
1590 struct ti_cmd_desc cmd;
1593 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1594 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1598 TI_UPDATE_JUMBOPROD(sc, i - 1);
1599 sc->ti_jumbo = i - 1;
1605 ti_free_rx_ring_jumbo(struct ti_softc *sc)
1610 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1611 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1612 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1613 bus_dmamap_sync(sc->ti_jumbo_dmat, map,
1614 BUS_DMASYNC_POSTREAD);
1615 bus_dmamap_unload(sc->ti_jumbo_dmat, map);
1616 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1617 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1619 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
1620 sizeof(struct ti_rx_desc));
1625 ti_init_rx_ring_mini(struct ti_softc *sc)
1629 for (i = 0; i < TI_MSLOTS; i++) {
1630 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
1634 TI_UPDATE_MINIPROD(sc, i - 1);
1635 sc->ti_mini = i - 1;
1641 ti_free_rx_ring_mini(struct ti_softc *sc)
1646 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1647 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1648 map = sc->ti_cdata.ti_rx_mini_maps[i];
1649 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1650 BUS_DMASYNC_POSTREAD);
1651 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1652 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1653 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1655 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1656 sizeof(struct ti_rx_desc));
1661 ti_free_tx_ring(struct ti_softc *sc)
1663 struct ti_txdesc *txd;
1666 if (sc->ti_rdata->ti_tx_ring == NULL)
1669 for (i = 0; i < TI_TX_RING_CNT; i++) {
1670 txd = &sc->ti_cdata.ti_txdesc[i];
1671 if (txd->tx_m != NULL) {
1672 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
1673 BUS_DMASYNC_POSTWRITE);
1674 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
1678 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1679 sizeof(struct ti_tx_desc));
1684 ti_init_tx_ring(struct ti_softc *sc)
1686 struct ti_txdesc *txd;
1689 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq);
1690 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq);
1691 for (i = 0; i < TI_TX_RING_CNT; i++) {
1692 txd = &sc->ti_cdata.ti_txdesc[i];
1693 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
1696 sc->ti_tx_saved_considx = 0;
1697 sc->ti_tx_saved_prodidx = 0;
1698 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1703 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1704 * but we have to support the old way too so that Tigon 1 cards will
1708 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
1710 struct ti_cmd_desc cmd;
1712 uint32_t ext[2] = {0, 0};
1714 m = (uint16_t *)&addr->octet[0];
1716 switch (sc->ti_hwrev) {
1717 case TI_HWREV_TIGON:
1718 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1719 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1720 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1722 case TI_HWREV_TIGON_II:
1723 ext[0] = htons(m[0]);
1724 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1725 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1728 device_printf(sc->ti_dev, "unknown hwrev\n");
1734 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
1736 struct ti_cmd_desc cmd;
1738 uint32_t ext[2] = {0, 0};
1740 m = (uint16_t *)&addr->octet[0];
1742 switch (sc->ti_hwrev) {
1743 case TI_HWREV_TIGON:
1744 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1745 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1746 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1748 case TI_HWREV_TIGON_II:
1749 ext[0] = htons(m[0]);
1750 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1751 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1754 device_printf(sc->ti_dev, "unknown hwrev\n");
1760 * Configure the Tigon's multicast address filter.
1762 * The actual multicast table management is a bit of a pain, thanks to
1763 * slight brain damage on the part of both Alteon and us. With our
1764 * multicast code, we are only alerted when the multicast address table
1765 * changes and at that point we only have the current list of addresses:
1766 * we only know the current state, not the previous state, so we don't
1767 * actually know what addresses were removed or added. The firmware has
1768 * state, but we can't get our grubby mits on it, and there is no 'delete
1769 * all multicast addresses' command. Hence, we have to maintain our own
1770 * state so we know what addresses have been programmed into the NIC at
1774 ti_setmulti(struct ti_softc *sc)
1777 struct ifmultiaddr *ifma;
1778 struct ti_cmd_desc cmd;
1779 struct ti_mc_entry *mc;
1786 if (ifp->if_flags & IFF_ALLMULTI) {
1787 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1790 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1793 /* Disable interrupts. */
1794 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1795 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1797 /* First, zot all the existing filters. */
1798 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1799 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1800 ti_del_mcast(sc, &mc->mc_addr);
1801 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1805 /* Now program new ones. */
1806 if_maddr_rlock(ifp);
1807 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1808 if (ifma->ifma_addr->sa_family != AF_LINK)
1810 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1812 device_printf(sc->ti_dev,
1813 "no memory for mcast filter entry\n");
1816 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1817 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1818 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1819 ti_add_mcast(sc, &mc->mc_addr);
1821 if_maddr_runlock(ifp);
1823 /* Re-enable interrupts. */
1824 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1828 * Check to see if the BIOS has configured us for a 64 bit slot when
1829 * we aren't actually in one. If we detect this condition, we can work
1830 * around it on the Tigon 2 by setting a bit in the PCI state register,
1831 * but for the Tigon 1 we must give up and abort the interface attach.
1833 static int ti_64bitslot_war(struct ti_softc *sc)
1836 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1837 CSR_WRITE_4(sc, 0x600, 0);
1838 CSR_WRITE_4(sc, 0x604, 0);
1839 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1840 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1841 if (sc->ti_hwrev == TI_HWREV_TIGON)
1844 TI_SETBIT(sc, TI_PCI_STATE,
1845 TI_PCISTATE_32BIT_BUS);
1855 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1856 * self-test results.
1859 ti_chipinit(struct ti_softc *sc)
1862 uint32_t pci_writemax = 0;
1865 /* Initialize link to down state. */
1866 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1868 /* Set endianness before we access any non-PCI registers. */
1869 #if 0 && BYTE_ORDER == BIG_ENDIAN
1870 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1871 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1873 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1874 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1877 /* Check the ROM failed bit to see if self-tests passed. */
1878 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1879 device_printf(sc->ti_dev, "board self-diagnostics failed!\n");
1884 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1886 /* Figure out the hardware revision. */
1887 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1888 case TI_REV_TIGON_I:
1889 sc->ti_hwrev = TI_HWREV_TIGON;
1891 case TI_REV_TIGON_II:
1892 sc->ti_hwrev = TI_HWREV_TIGON_II;
1895 device_printf(sc->ti_dev, "unsupported chip revision\n");
1899 /* Do special setup for Tigon 2. */
1900 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1901 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1902 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1903 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1907 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
1908 * can't do header splitting.
1910 #ifdef TI_JUMBO_HDRSPLIT
1911 if (sc->ti_hwrev != TI_HWREV_TIGON)
1912 sc->ti_hdrsplit = 1;
1914 device_printf(sc->ti_dev,
1915 "can't do header splitting on a Tigon I board\n");
1916 #endif /* TI_JUMBO_HDRSPLIT */
1918 /* Set up the PCI state register. */
1919 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1920 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1921 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1924 /* Clear the read/write max DMA parameters. */
1925 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1926 TI_PCISTATE_READ_MAXDMA));
1928 /* Get cache line size. */
1929 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1932 * If the system has set enabled the PCI memory write
1933 * and invalidate command in the command register, set
1934 * the write max parameter accordingly. This is necessary
1935 * to use MWI with the Tigon 2.
1937 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1938 switch (cacheline) {
1947 /* Disable PCI memory write and invalidate. */
1949 device_printf(sc->ti_dev, "cache line size %d"
1950 " not supported; disabling PCI MWI\n",
1952 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1953 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1958 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1960 /* This sets the min dma param all the way up (0xff). */
1961 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1963 if (sc->ti_hdrsplit)
1964 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
1968 /* Configure DMA variables. */
1969 #if BYTE_ORDER == BIG_ENDIAN
1970 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1971 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1972 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1973 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
1974 #else /* BYTE_ORDER */
1975 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1976 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1977 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
1978 #endif /* BYTE_ORDER */
1981 * Only allow 1 DMA channel to be active at a time.
1982 * I don't think this is a good idea, but without it
1983 * the firmware racks up lots of nicDmaReadRingFull
1984 * errors. This is not compatible with hardware checksums.
1986 if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0)
1987 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1989 /* Recommended settings from Tigon manual. */
1990 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1991 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1993 if (ti_64bitslot_war(sc)) {
1994 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, "
2003 * Initialize the general information block and firmware, and
2004 * start the CPU(s) running.
2007 ti_gibinit(struct ti_softc *sc)
2017 rdphys = sc->ti_rdata_phys;
2019 /* Disable interrupts for now. */
2020 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2023 * Tell the chip where to find the general information block.
2024 * While this struct could go into >4GB memory, we allocate it in a
2025 * single slab with the other descriptors, and those don't seem to
2026 * support being located in a 64-bit region.
2028 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
2029 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info));
2031 /* Load the firmware into SRAM. */
2034 /* Set up the contents of the general info and ring control blocks. */
2036 /* Set up the event ring and producer pointer. */
2037 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
2039 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring);
2041 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
2042 rdphys + TI_RD_OFF(ti_ev_prodidx_r);
2043 sc->ti_ev_prodidx.ti_idx = 0;
2044 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
2045 sc->ti_ev_saved_considx = 0;
2047 /* Set up the command ring and producer mailbox. */
2048 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
2050 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
2052 rcb->ti_max_len = 0;
2053 for (i = 0; i < TI_CMD_RING_CNT; i++) {
2054 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
2056 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
2057 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
2058 sc->ti_cmd_saved_prodidx = 0;
2061 * Assign the address of the stats refresh buffer.
2062 * We re-use the current stats buffer for this to
2065 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
2066 rdphys + TI_RD_OFF(ti_info.ti_stats);
2068 /* Set up the standard receive ring. */
2069 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
2070 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring);
2071 rcb->ti_max_len = TI_FRAMELEN;
2073 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2074 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2075 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2076 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2077 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2079 /* Set up the jumbo receive ring. */
2080 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
2081 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring);
2083 #ifdef TI_PRIVATE_JUMBOS
2084 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
2087 rcb->ti_max_len = PAGE_SIZE;
2088 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
2090 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2091 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2092 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2093 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2094 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2097 * Set up the mini ring. Only activated on the
2098 * Tigon 2 but the slot in the config block is
2099 * still there on the Tigon 1.
2101 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
2102 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring);
2103 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
2104 if (sc->ti_hwrev == TI_HWREV_TIGON)
2105 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
2108 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2109 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2110 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2111 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2112 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2115 * Set up the receive return ring.
2117 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
2118 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring);
2120 rcb->ti_max_len = TI_RETURN_RING_CNT;
2121 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
2122 rdphys + TI_RD_OFF(ti_return_prodidx_r);
2125 * Set up the tx ring. Note: for the Tigon 2, we have the option
2126 * of putting the transmit ring in the host's address space and
2127 * letting the chip DMA it instead of leaving the ring in the NIC's
2128 * memory and accessing it through the shared memory region. We
2129 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
2130 * so we have to revert to the shared memory scheme if we detect
2133 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
2134 bzero((char *)sc->ti_rdata->ti_tx_ring,
2135 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
2136 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
2137 if (sc->ti_hwrev == TI_HWREV_TIGON)
2140 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
2141 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2142 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2143 if (sc->ti_ifp->if_capenable & IFCAP_TXCSUM)
2144 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2145 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2146 rcb->ti_max_len = TI_TX_RING_CNT;
2147 if (sc->ti_hwrev == TI_HWREV_TIGON)
2148 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
2150 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring);
2151 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
2152 rdphys + TI_RD_OFF(ti_tx_considx_r);
2154 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2155 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2157 /* Set up tuneables */
2159 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2160 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
2161 (sc->ti_rx_coal_ticks / 10));
2164 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2165 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2166 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2167 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2168 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2169 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2171 /* Turn interrupts on. */
2172 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2173 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2176 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2182 ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2184 struct ti_softc *sc;
2187 if (error || nseg != 1)
2191 * All of the Tigon data structures need to live at <4GB. This
2192 * cast is fine since busdma was told about this constraint.
2194 sc->ti_rdata_phys = segs[0].ds_addr;
2199 * Probe for a Tigon chip. Check the PCI vendor and device IDs
2200 * against our list and return its name if we find a match.
2203 ti_probe(device_t dev)
2205 const struct ti_type *t;
2209 while (t->ti_name != NULL) {
2210 if ((pci_get_vendor(dev) == t->ti_vid) &&
2211 (pci_get_device(dev) == t->ti_did)) {
2212 device_set_desc(dev, t->ti_name);
2213 return (BUS_PROBE_DEFAULT);
2222 ti_attach(device_t dev)
2225 struct ti_softc *sc;
2229 sc = device_get_softc(dev);
2232 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2234 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0);
2235 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2236 ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
2238 device_printf(dev, "can not if_alloc()\n");
2242 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES;
2243 sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
2244 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities;
2247 * Map control/status registers.
2249 pci_enable_busmaster(dev);
2252 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2255 if (sc->ti_res == NULL) {
2256 device_printf(dev, "couldn't map memory\n");
2261 sc->ti_btag = rman_get_bustag(sc->ti_res);
2262 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2264 /* Allocate interrupt */
2267 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2268 RF_SHAREABLE | RF_ACTIVE);
2270 if (sc->ti_irq == NULL) {
2271 device_printf(dev, "couldn't map interrupt\n");
2276 if (ti_chipinit(sc)) {
2277 device_printf(dev, "chip initialization failed\n");
2282 /* Zero out the NIC's on-board SRAM. */
2283 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
2285 /* Init again -- zeroing memory may have clobbered some registers. */
2286 if (ti_chipinit(sc)) {
2287 device_printf(dev, "chip initialization failed\n");
2293 * Get station address from the EEPROM. Note: the manual states
2294 * that the MAC address is at offset 0x8c, however the data is
2295 * stored as two longwords (since that's how it's loaded into
2296 * the NIC). This means the MAC address is actually preceded
2297 * by two zero bytes. We need to skip over those.
2299 if (ti_read_eeprom(sc, eaddr,
2300 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2301 device_printf(dev, "failed to read station address\n");
2306 /* Allocate the general information block and ring buffers. */
2307 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
2308 1, 0, /* algnmnt, boundary */
2309 BUS_SPACE_MAXADDR, /* lowaddr */
2310 BUS_SPACE_MAXADDR, /* highaddr */
2311 NULL, NULL, /* filter, filterarg */
2312 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
2314 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
2316 NULL, NULL, /* lockfunc, lockarg */
2317 &sc->ti_parent_dmat) != 0) {
2318 device_printf(dev, "Failed to allocate parent dmat\n");
2323 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2324 PAGE_SIZE, 0, /* algnmnt, boundary */
2325 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
2326 BUS_SPACE_MAXADDR, /* highaddr */
2327 NULL, NULL, /* filter, filterarg */
2328 sizeof(struct ti_ring_data), /* maxsize */
2330 sizeof(struct ti_ring_data), /* maxsegsize */
2332 NULL, NULL, /* lockfunc, lockarg */
2333 &sc->ti_rdata_dmat) != 0) {
2334 device_printf(dev, "Failed to allocate rdata dmat\n");
2339 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata,
2340 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
2341 &sc->ti_rdata_dmamap) != 0) {
2342 device_printf(dev, "Failed to allocate rdata memory\n");
2347 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2348 sc->ti_rdata, sizeof(struct ti_ring_data),
2349 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) {
2350 device_printf(dev, "Failed to load rdata segments\n");
2355 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
2357 /* Try to allocate memory for jumbo buffers. */
2358 if (ti_alloc_jumbo_mem(sc)) {
2359 device_printf(dev, "jumbo buffer allocation failed\n");
2364 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2365 1, 0, /* algnmnt, boundary */
2366 BUS_SPACE_MAXADDR, /* lowaddr */
2367 BUS_SPACE_MAXADDR, /* highaddr */
2368 NULL, NULL, /* filter, filterarg */
2369 MCLBYTES * TI_MAXTXSEGS,/* maxsize */
2370 TI_MAXTXSEGS, /* nsegments */
2371 MCLBYTES, /* maxsegsize */
2373 NULL, NULL, /* lockfunc, lockarg */
2374 &sc->ti_mbuftx_dmat) != 0) {
2375 device_printf(dev, "Failed to allocate rdata dmat\n");
2380 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2381 1, 0, /* algnmnt, boundary */
2382 BUS_SPACE_MAXADDR, /* lowaddr */
2383 BUS_SPACE_MAXADDR, /* highaddr */
2384 NULL, NULL, /* filter, filterarg */
2385 MCLBYTES, /* maxsize */
2387 MCLBYTES, /* maxsegsize */
2389 NULL, NULL, /* lockfunc, lockarg */
2390 &sc->ti_mbufrx_dmat) != 0) {
2391 device_printf(dev, "Failed to allocate rdata dmat\n");
2396 if (ti_alloc_dmamaps(sc)) {
2397 device_printf(dev, "dma map creation failed\n");
2403 * We really need a better way to tell a 1000baseTX card
2404 * from a 1000baseSX one, since in theory there could be
2405 * OEMed 1000baseTX cards from lame vendors who aren't
2406 * clever enough to change the PCI ID. For the moment
2407 * though, the AceNIC is the only copper card available.
2409 if (pci_get_vendor(dev) == ALT_VENDORID &&
2410 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2412 /* Ok, it's not the only copper card available. */
2413 if (pci_get_vendor(dev) == NG_VENDORID &&
2414 pci_get_device(dev) == NG_DEVICEID_GA620T)
2417 /* Set default tuneable values. */
2418 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
2420 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
2422 sc->ti_rx_coal_ticks = 170;
2423 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
2424 sc->ti_rx_max_coal_bds = 64;
2426 sc->ti_tx_max_coal_bds = 128;
2428 sc->ti_tx_max_coal_bds = 32;
2429 sc->ti_tx_buf_ratio = 21;
2431 /* Set up ifnet structure */
2433 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2434 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2435 ifp->if_ioctl = ti_ioctl;
2436 ifp->if_start = ti_start;
2437 ifp->if_init = ti_init;
2438 ifp->if_baudrate = IF_Gbps(1UL);
2439 ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1;
2440 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2441 IFQ_SET_READY(&ifp->if_snd);
2443 /* Set up ifmedia support. */
2444 if (sc->ti_copper) {
2446 * Copper cards allow manual 10/100 mode selection,
2447 * but not manual 1000baseTX mode selection. Why?
2448 * Becuase currently there's no way to specify the
2449 * master/slave setting through the firmware interface,
2450 * so Alteon decided to just bag it and handle it
2451 * via autonegotiation.
2453 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2454 ifmedia_add(&sc->ifmedia,
2455 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2456 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2457 ifmedia_add(&sc->ifmedia,
2458 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2459 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2460 ifmedia_add(&sc->ifmedia,
2461 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2463 /* Fiber cards don't support 10/100 modes. */
2464 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2465 ifmedia_add(&sc->ifmedia,
2466 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2468 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2469 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2472 * We're assuming here that card initialization is a sequential
2473 * thing. If it isn't, multiple cards probing at the same time
2474 * could stomp on the list of softcs here.
2477 /* Register the device */
2478 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT,
2479 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev));
2480 sc->dev->si_drv1 = sc;
2483 * Call MI attach routine.
2485 ether_ifattach(ifp, eaddr);
2487 /* VLAN capability setup. */
2488 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM |
2489 IFCAP_VLAN_HWTAGGING;
2490 ifp->if_capenable = ifp->if_capabilities;
2491 /* Tell the upper layer we support VLAN over-sized frames. */
2492 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
2494 /* Driver supports link state tracking. */
2495 ifp->if_capabilities |= IFCAP_LINKSTATE;
2496 ifp->if_capenable |= IFCAP_LINKSTATE;
2498 /* Hook interrupt last to avoid having to lock softc */
2499 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE,
2500 NULL, ti_intr, sc, &sc->ti_intrhand);
2503 device_printf(dev, "couldn't set up irq\n");
2515 * Shutdown hardware and free up resources. This can be called any
2516 * time after the mutex has been initialized. It is called in both
2517 * the error case in attach and the normal detach case so it needs
2518 * to be careful about only freeing resources that have actually been
2522 ti_detach(device_t dev)
2524 struct ti_softc *sc;
2527 sc = device_get_softc(dev);
2529 destroy_dev(sc->dev);
2530 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2532 if (device_is_attached(dev)) {
2533 ether_ifdetach(ifp);
2539 /* These should only be active if attach succeeded */
2540 callout_drain(&sc->ti_watchdog);
2541 bus_generic_detach(dev);
2542 ti_free_dmamaps(sc);
2543 ifmedia_removeall(&sc->ifmedia);
2545 #ifdef TI_PRIVATE_JUMBOS
2546 if (sc->ti_cdata.ti_jumbo_buf)
2547 bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf,
2548 sc->ti_jumbo_dmamap);
2550 if (sc->ti_jumbo_dmat)
2551 bus_dma_tag_destroy(sc->ti_jumbo_dmat);
2552 if (sc->ti_mbuftx_dmat)
2553 bus_dma_tag_destroy(sc->ti_mbuftx_dmat);
2554 if (sc->ti_mbufrx_dmat)
2555 bus_dma_tag_destroy(sc->ti_mbufrx_dmat);
2556 if (sc->ti_rdata && sc->ti_rdata_dmamap)
2557 bus_dmamap_unload(sc->ti_rdata_dmat, sc->ti_rdata_dmamap);
2559 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata,
2560 sc->ti_rdata_dmamap);
2561 if (sc->ti_rdata_dmat)
2562 bus_dma_tag_destroy(sc->ti_rdata_dmat);
2563 if (sc->ti_parent_dmat)
2564 bus_dma_tag_destroy(sc->ti_parent_dmat);
2565 if (sc->ti_intrhand)
2566 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2568 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2570 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
2576 mtx_destroy(&sc->ti_mtx);
2581 #ifdef TI_JUMBO_HDRSPLIT
2583 * If hdr_len is 0, that means that header splitting wasn't done on
2584 * this packet for some reason. The two most likely reasons are that
2585 * the protocol isn't a supported protocol for splitting, or this
2586 * packet had a fragment offset that wasn't 0.
2588 * The header length, if it is non-zero, will always be the length of
2589 * the headers on the packet, but that length could be longer than the
2590 * first mbuf. So we take the minimum of the two as the actual
2593 static __inline void
2594 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2597 int lengths[4] = {0, 0, 0, 0};
2598 struct mbuf *m, *mp;
2601 top->m_len = min(hdr_len, top->m_len);
2602 pkt_len -= top->m_len;
2603 lengths[i++] = top->m_len;
2606 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2607 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2608 pkt_len -= m->m_len;
2609 lengths[i++] = m->m_len;
2615 printf("got split packet: ");
2617 printf("got non-split packet: ");
2619 printf("%d,%d,%d,%d = %d\n", lengths[0],
2620 lengths[1], lengths[2], lengths[3],
2621 lengths[0] + lengths[1] + lengths[2] +
2626 panic("header splitting didn't");
2633 if (mp->m_next != NULL)
2634 panic("ti_hdr_split: last mbuf in chain should be null");
2636 #endif /* TI_JUMBO_HDRSPLIT */
2639 * Frame reception handling. This is called if there's a frame
2640 * on the receive return list.
2642 * Note: we have to be able to handle three possibilities here:
2643 * 1) the frame is from the mini receive ring (can only happen)
2644 * on Tigon 2 boards)
2645 * 2) the frame is from the jumbo recieve ring
2646 * 3) the frame is from the standard receive ring
2650 ti_rxeof(struct ti_softc *sc)
2654 struct ti_cmd_desc cmd;
2655 int jumbocnt, minicnt, stdcnt;
2661 jumbocnt = minicnt = stdcnt = 0;
2662 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2663 struct ti_rx_desc *cur_rx;
2665 struct mbuf *m = NULL;
2666 uint16_t vlan_tag = 0;
2670 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
2671 rxidx = cur_rx->ti_idx;
2672 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2674 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2676 vlan_tag = cur_rx->ti_vlan_tag;
2679 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2681 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2682 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2683 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2684 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx];
2685 bus_dmamap_sync(sc->ti_jumbo_dmat, map,
2686 BUS_DMASYNC_POSTREAD);
2687 bus_dmamap_unload(sc->ti_jumbo_dmat, map);
2688 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2690 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2693 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2695 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2698 #ifdef TI_PRIVATE_JUMBOS
2699 m->m_len = cur_rx->ti_len;
2700 #else /* TI_PRIVATE_JUMBOS */
2701 #ifdef TI_JUMBO_HDRSPLIT
2702 if (sc->ti_hdrsplit)
2703 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2704 cur_rx->ti_len, rxidx);
2706 #endif /* TI_JUMBO_HDRSPLIT */
2707 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len);
2708 #endif /* TI_PRIVATE_JUMBOS */
2709 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2711 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2712 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2713 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
2714 map = sc->ti_cdata.ti_rx_mini_maps[rxidx];
2715 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
2716 BUS_DMASYNC_POSTREAD);
2717 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
2718 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2720 ti_newbuf_mini(sc, sc->ti_mini, m);
2723 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
2725 ti_newbuf_mini(sc, sc->ti_mini, m);
2728 m->m_len = cur_rx->ti_len;
2731 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2732 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2733 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
2734 map = sc->ti_cdata.ti_rx_std_maps[rxidx];
2735 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
2736 BUS_DMASYNC_POSTREAD);
2737 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
2738 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2740 ti_newbuf_std(sc, sc->ti_std, m);
2743 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
2745 ti_newbuf_std(sc, sc->ti_std, m);
2748 m->m_len = cur_rx->ti_len;
2751 m->m_pkthdr.len = cur_rx->ti_len;
2753 m->m_pkthdr.rcvif = ifp;
2755 if (ifp->if_capenable & IFCAP_RXCSUM) {
2756 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) {
2757 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2758 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2759 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2761 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) {
2762 m->m_pkthdr.csum_data =
2763 cur_rx->ti_tcp_udp_cksum;
2764 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2769 * If we received a packet with a vlan tag,
2770 * tag it before passing the packet upward.
2773 m->m_pkthdr.ether_vtag = vlan_tag;
2774 m->m_flags |= M_VLANTAG;
2777 (*ifp->if_input)(ifp, m);
2781 /* Only necessary on the Tigon 1. */
2782 if (sc->ti_hwrev == TI_HWREV_TIGON)
2783 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2784 sc->ti_rx_saved_considx);
2787 TI_UPDATE_STDPROD(sc, sc->ti_std);
2789 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2791 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2795 ti_txeof(struct ti_softc *sc)
2797 struct ti_txdesc *txd;
2798 struct ti_tx_desc txdesc;
2799 struct ti_tx_desc *cur_tx = NULL;
2805 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2809 * Go through our tx ring and free mbufs for those
2810 * frames that have been sent.
2812 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx;
2813 TI_INC(idx, TI_TX_RING_CNT)) {
2814 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2815 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc),
2816 sizeof(txdesc), &txdesc);
2819 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
2821 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2822 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0)
2824 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2825 BUS_DMASYNC_POSTWRITE);
2826 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2831 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q);
2832 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
2833 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2835 sc->ti_tx_saved_considx = idx;
2837 sc->ti_timer = sc->ti_txcnt > 0 ? 5 : 0;
2843 struct ti_softc *sc;
2851 /* Avoid this for now -- checking this register is expensive. */
2852 /* Make sure this is really our interrupt. */
2853 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2859 /* Ack interrupt and stop others from occuring. */
2860 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2862 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2863 /* Check RX return ring producer/consumer */
2866 /* Check TX ring producer/consumer */
2870 ti_handle_events(sc);
2872 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2873 /* Re-enable interrupts. */
2874 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2875 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2876 ti_start_locked(ifp);
2883 ti_stats_update(struct ti_softc *sc)
2889 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2890 BUS_DMASYNC_POSTREAD);
2892 ifp->if_collisions +=
2893 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2894 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2895 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2896 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2899 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2900 BUS_DMASYNC_PREREAD);
2904 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2905 * pointers to descriptors.
2908 ti_encap(struct ti_softc *sc, struct mbuf **m_head)
2910 struct ti_txdesc *txd;
2911 struct ti_tx_desc *f;
2912 struct ti_tx_desc txdesc;
2914 bus_dma_segment_t txsegs[TI_MAXTXSEGS];
2915 uint16_t csum_flags;
2916 int error, frag, i, nseg;
2918 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL)
2921 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2922 *m_head, txsegs, &nseg, 0);
2923 if (error == EFBIG) {
2924 m = m_defrag(*m_head, M_DONTWAIT);
2931 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat,
2932 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2938 } else if (error != 0)
2946 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) {
2947 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2953 if (m->m_pkthdr.csum_flags) {
2954 if (m->m_pkthdr.csum_flags & CSUM_IP)
2955 csum_flags |= TI_BDFLAG_IP_CKSUM;
2956 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2957 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2958 if (m->m_flags & M_LASTFRAG)
2959 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2960 else if (m->m_flags & M_FRAG)
2961 csum_flags |= TI_BDFLAG_IP_FRAG;
2964 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2965 BUS_DMASYNC_PREWRITE);
2966 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2967 BUS_DMASYNC_PREWRITE);
2969 frag = sc->ti_tx_saved_prodidx;
2970 for (i = 0; i < nseg; i++) {
2971 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2972 bzero(&txdesc, sizeof(txdesc));
2975 f = &sc->ti_rdata->ti_tx_ring[frag];
2976 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr);
2977 f->ti_len = txsegs[i].ds_len;
2978 f->ti_flags = csum_flags;
2979 if (m->m_flags & M_VLANTAG) {
2980 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2981 f->ti_vlan_tag = m->m_pkthdr.ether_vtag;
2986 if (sc->ti_hwrev == TI_HWREV_TIGON)
2987 ti_mem_write(sc, TI_TX_RING_BASE + frag *
2988 sizeof(txdesc), sizeof(txdesc), &txdesc);
2989 TI_INC(frag, TI_TX_RING_CNT);
2992 sc->ti_tx_saved_prodidx = frag;
2993 /* set TI_BDFLAG_END on the last descriptor */
2994 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT;
2995 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2996 txdesc.ti_flags |= TI_BDFLAG_END;
2997 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc),
2998 sizeof(txdesc), &txdesc);
3000 sc->ti_rdata->ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END;
3002 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q);
3003 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q);
3005 sc->ti_txcnt += nseg;
3011 ti_start(struct ifnet *ifp)
3013 struct ti_softc *sc;
3017 ti_start_locked(ifp);
3022 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3023 * to the mbuf data regions directly in the transmit descriptors.
3026 ti_start_locked(struct ifnet *ifp)
3028 struct ti_softc *sc;
3029 struct mbuf *m_head = NULL;
3034 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
3035 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) {
3036 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3042 * safety overkill. If this is a fragmented packet chain
3043 * with delayed TCP/UDP checksums, then only encapsulate
3044 * it if we have enough descriptors to handle the entire
3046 * (paranoia -- may not actually be needed)
3048 if (m_head->m_flags & M_FIRSTFRAG &&
3049 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3050 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
3051 m_head->m_pkthdr.csum_data + 16) {
3052 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3053 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3059 * Pack the data into the transmit ring. If we
3060 * don't have room, set the OACTIVE flag and wait
3061 * for the NIC to drain the ring.
3063 if (ti_encap(sc, &m_head)) {
3066 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3067 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3073 * If there's a BPF listener, bounce a copy of this frame
3076 ETHER_BPF_MTAP(ifp, m_head);
3081 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx);
3084 * Set a timeout in case the chip goes out to lunch.
3093 struct ti_softc *sc;
3102 ti_init_locked(void *xsc)
3104 struct ti_softc *sc = xsc;
3106 if (sc->ti_ifp->if_drv_flags & IFF_DRV_RUNNING)
3109 /* Cancel pending I/O and flush buffers. */
3112 /* Init the gen info block, ring control blocks and firmware. */
3113 if (ti_gibinit(sc)) {
3114 device_printf(sc->ti_dev, "initialization failure\n");
3119 static void ti_init2(struct ti_softc *sc)
3121 struct ti_cmd_desc cmd;
3124 struct ifmedia *ifm;
3131 /* Specify MTU and interface index. */
3132 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev));
3133 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
3134 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
3135 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
3137 /* Load our MAC address. */
3138 ea = IF_LLADDR(sc->ti_ifp);
3139 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]);
3140 CSR_WRITE_4(sc, TI_GCR_PAR1,
3141 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]);
3142 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
3144 /* Enable or disable promiscuous mode as needed. */
3145 if (ifp->if_flags & IFF_PROMISC) {
3146 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
3148 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
3151 /* Program multicast filter. */
3155 * If this is a Tigon 1, we should tell the
3156 * firmware to use software packet filtering.
3158 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3159 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
3163 if (ti_init_rx_ring_std(sc) != 0) {
3165 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n");
3169 /* Init jumbo RX ring. */
3170 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3171 if (ti_init_rx_ring_jumbo(sc) != 0) {
3173 device_printf(sc->ti_dev,
3174 "no memory for jumbo Rx buffers.\n");
3180 * If this is a Tigon 2, we can also configure the
3183 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
3184 if (ti_init_rx_ring_mini(sc) != 0) {
3186 device_printf(sc->ti_dev,
3187 "no memory for mini Rx buffers.\n");
3192 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
3193 sc->ti_rx_saved_considx = 0;
3196 ti_init_tx_ring(sc);
3198 /* Tell firmware we're alive. */
3199 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
3201 /* Enable host interrupts. */
3202 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3204 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3205 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3206 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3209 * Make sure to set media properly. We have to do this
3210 * here since we have to issue commands in order to set
3211 * the link negotiation and we can't issue commands until
3212 * the firmware is running.
3215 tmp = ifm->ifm_media;
3216 ifm->ifm_media = ifm->ifm_cur->ifm_media;
3217 ti_ifmedia_upd_locked(sc);
3218 ifm->ifm_media = tmp;
3222 * Set media options.
3225 ti_ifmedia_upd(struct ifnet *ifp)
3227 struct ti_softc *sc;
3232 error = ti_ifmedia_upd(ifp);
3239 ti_ifmedia_upd_locked(struct ti_softc *sc)
3241 struct ifmedia *ifm;
3242 struct ti_cmd_desc cmd;
3247 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3252 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3255 * Transmit flow control doesn't work on the Tigon 1.
3257 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3260 * Transmit flow control can also cause problems on the
3261 * Tigon 2, apparantly with both the copper and fiber
3262 * boards. The symptom is that the interface will just
3263 * hang. This was reproduced with Alteon 180 switches.
3266 if (sc->ti_hwrev != TI_HWREV_TIGON)
3267 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3270 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3271 TI_GLNK_FULL_DUPLEX| flowctl |
3272 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
3274 flowctl = TI_LNK_RX_FLOWCTL_Y;
3276 if (sc->ti_hwrev != TI_HWREV_TIGON)
3277 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3280 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
3281 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
3282 TI_LNK_AUTONEGENB|TI_LNK_ENB);
3283 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3284 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
3288 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3290 if (sc->ti_hwrev != TI_HWREV_TIGON)
3291 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3294 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3295 flowctl |TI_GLNK_ENB);
3296 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
3297 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3298 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
3300 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3301 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3307 flowctl = TI_LNK_RX_FLOWCTL_Y;
3309 if (sc->ti_hwrev != TI_HWREV_TIGON)
3310 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3313 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3314 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3315 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3316 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3317 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3319 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3321 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3322 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3324 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3326 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3327 TI_CMD_CODE_NEGOTIATE_10_100, 0);
3335 * Report current media status.
3338 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3340 struct ti_softc *sc;
3347 ifmr->ifm_status = IFM_AVALID;
3348 ifmr->ifm_active = IFM_ETHER;
3350 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
3355 ifmr->ifm_status |= IFM_ACTIVE;
3357 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3358 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3360 ifmr->ifm_active |= IFM_1000_T;
3362 ifmr->ifm_active |= IFM_1000_SX;
3363 if (media & TI_GLNK_FULL_DUPLEX)
3364 ifmr->ifm_active |= IFM_FDX;
3366 ifmr->ifm_active |= IFM_HDX;
3367 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3368 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3369 if (sc->ti_copper) {
3370 if (media & TI_LNK_100MB)
3371 ifmr->ifm_active |= IFM_100_TX;
3372 if (media & TI_LNK_10MB)
3373 ifmr->ifm_active |= IFM_10_T;
3375 if (media & TI_LNK_100MB)
3376 ifmr->ifm_active |= IFM_100_FX;
3377 if (media & TI_LNK_10MB)
3378 ifmr->ifm_active |= IFM_10_FL;
3380 if (media & TI_LNK_FULL_DUPLEX)
3381 ifmr->ifm_active |= IFM_FDX;
3382 if (media & TI_LNK_HALF_DUPLEX)
3383 ifmr->ifm_active |= IFM_HDX;
3389 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3391 struct ti_softc *sc = ifp->if_softc;
3392 struct ifreq *ifr = (struct ifreq *) data;
3393 struct ti_cmd_desc cmd;
3394 int mask, error = 0;
3399 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU)
3402 ifp->if_mtu = ifr->ifr_mtu;
3403 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3404 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3412 if (ifp->if_flags & IFF_UP) {
3414 * If only the state of the PROMISC flag changed,
3415 * then just use the 'set promisc mode' command
3416 * instead of reinitializing the entire NIC. Doing
3417 * a full re-init means reloading the firmware and
3418 * waiting for it to start up, which may take a
3421 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3422 ifp->if_flags & IFF_PROMISC &&
3423 !(sc->ti_if_flags & IFF_PROMISC)) {
3424 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3425 TI_CMD_CODE_PROMISC_ENB, 0);
3426 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3427 !(ifp->if_flags & IFF_PROMISC) &&
3428 sc->ti_if_flags & IFF_PROMISC) {
3429 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3430 TI_CMD_CODE_PROMISC_DIS, 0);
3434 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3438 sc->ti_if_flags = ifp->if_flags;
3444 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3450 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3454 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3455 if ((mask & IFCAP_TXCSUM) != 0 &&
3456 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3457 ifp->if_capenable ^= IFCAP_TXCSUM;
3458 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3459 ifp->if_hwassist |= TI_CSUM_FEATURES;
3461 ifp->if_hwassist &= ~TI_CSUM_FEATURES;
3463 if ((mask & IFCAP_RXCSUM) != 0 &&
3464 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3465 ifp->if_capenable ^= IFCAP_RXCSUM;
3466 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3467 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0)
3468 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3469 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
3470 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
3471 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
3472 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM |
3473 IFCAP_VLAN_HWTAGGING)) != 0) {
3474 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3475 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3480 VLAN_CAPABILITIES(ifp);
3483 error = ether_ioctl(ifp, command, data);
3491 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3493 struct ti_softc *sc;
3500 sc->ti_flags |= TI_FLAG_DEBUGING;
3507 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3509 struct ti_softc *sc;
3516 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3523 * This ioctl routine goes along with the Tigon character device.
3526 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag,
3529 struct ti_softc *sc;
3541 struct ti_stats *outstats;
3543 outstats = (struct ti_stats *)addr;
3546 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats,
3547 sizeof(struct ti_stats));
3551 case TIIOCGETPARAMS:
3553 struct ti_params *params;
3555 params = (struct ti_params *)addr;
3558 params->ti_stat_ticks = sc->ti_stat_ticks;
3559 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3560 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3561 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3562 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3563 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3564 params->param_mask = TI_PARAM_ALL;
3571 case TIIOCSETPARAMS:
3573 struct ti_params *params;
3575 params = (struct ti_params *)addr;
3578 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3579 sc->ti_stat_ticks = params->ti_stat_ticks;
3580 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3583 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3584 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3585 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3586 sc->ti_rx_coal_ticks);
3589 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3590 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3591 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3592 sc->ti_tx_coal_ticks);
3595 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3596 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3597 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3598 sc->ti_rx_max_coal_bds);
3601 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3602 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3603 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3604 sc->ti_tx_max_coal_bds);
3607 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3608 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3609 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3610 sc->ti_tx_buf_ratio);
3618 case TIIOCSETTRACE: {
3619 ti_trace_type trace_type;
3621 trace_type = *(ti_trace_type *)addr;
3624 * Set tracing to whatever the user asked for. Setting
3625 * this register to 0 should have the effect of disabling
3628 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3634 case TIIOCGETTRACE: {
3635 struct ti_trace_buf *trace_buf;
3636 uint32_t trace_start, cur_trace_ptr, trace_len;
3638 trace_buf = (struct ti_trace_buf *)addr;
3641 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3642 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3643 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3646 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, "
3647 "trace_len = %d\n", trace_start,
3648 cur_trace_ptr, trace_len);
3649 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n",
3650 trace_buf->buf_len);
3653 error = ti_copy_mem(sc, trace_start, min(trace_len,
3654 trace_buf->buf_len),
3655 (caddr_t)trace_buf->buf, 1, 1);
3658 trace_buf->fill_len = min(trace_len,
3659 trace_buf->buf_len);
3660 if (cur_trace_ptr < trace_start)
3661 trace_buf->cur_trace_ptr =
3662 trace_start - cur_trace_ptr;
3664 trace_buf->cur_trace_ptr =
3665 cur_trace_ptr - trace_start;
3667 trace_buf->fill_len = 0;
3674 * For debugging, five ioctls are needed:
3683 * From what I can tell, Alteon's Solaris Tigon driver
3684 * only has one character device, so you have to attach
3685 * to the Tigon board you're interested in. This seems
3686 * like a not-so-good way to do things, since unless you
3687 * subsequently specify the unit number of the device
3688 * you're interested in every ioctl, you'll only be
3689 * able to debug one board at a time.
3693 case ALT_READ_TG_MEM:
3694 case ALT_WRITE_TG_MEM:
3696 struct tg_mem *mem_param;
3697 uint32_t sram_end, scratch_end;
3699 mem_param = (struct tg_mem *)addr;
3701 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3702 sram_end = TI_END_SRAM_I;
3703 scratch_end = TI_END_SCRATCH_I;
3705 sram_end = TI_END_SRAM_II;
3706 scratch_end = TI_END_SCRATCH_II;
3710 * For now, we'll only handle accessing regular SRAM,
3714 if ((mem_param->tgAddr >= TI_BEG_SRAM)
3715 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) {
3717 * In this instance, we always copy to/from user
3718 * space, so the user space argument is set to 1.
3720 error = ti_copy_mem(sc, mem_param->tgAddr,
3722 mem_param->userAddr, 1,
3723 (cmd == ALT_READ_TG_MEM) ? 1 : 0);
3724 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH)
3725 && (mem_param->tgAddr <= scratch_end)) {
3726 error = ti_copy_scratch(sc, mem_param->tgAddr,
3728 mem_param->userAddr, 1,
3729 (cmd == ALT_READ_TG_MEM) ?
3730 1 : 0, TI_PROCESSOR_A);
3731 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG)
3732 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) {
3733 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3734 if_printf(sc->ti_ifp,
3735 "invalid memory range for Tigon I\n");
3739 error = ti_copy_scratch(sc, mem_param->tgAddr -
3740 TI_SCRATCH_DEBUG_OFF,
3742 mem_param->userAddr, 1,
3743 (cmd == ALT_READ_TG_MEM) ?
3744 1 : 0, TI_PROCESSOR_B);
3746 if_printf(sc->ti_ifp, "memory address %#x len %d is "
3747 "out of supported range\n",
3748 mem_param->tgAddr, mem_param->len);
3755 case ALT_READ_TG_REG:
3756 case ALT_WRITE_TG_REG:
3758 struct tg_reg *regs;
3761 regs = (struct tg_reg *)addr;
3764 * Make sure the address in question isn't out of range.
3766 if (regs->addr > TI_REG_MAX) {
3771 if (cmd == ALT_READ_TG_REG) {
3772 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3773 regs->addr, &tmpval, 1);
3774 regs->data = ntohl(tmpval);
3776 if ((regs->addr == TI_CPU_STATE)
3777 || (regs->addr == TI_CPU_CTL_B)) {
3778 if_printf(sc->ti_ifp, "register %#x = %#x\n",
3779 regs->addr, tmpval);
3783 tmpval = htonl(regs->data);
3784 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3785 regs->addr, &tmpval, 1);
3799 ti_watchdog(void *arg)
3801 struct ti_softc *sc;
3806 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3807 if (sc->ti_timer == 0 || --sc->ti_timer > 0)
3811 * When we're debugging, the chip is often stopped for long periods
3812 * of time, and that would normally cause the watchdog timer to fire.
3813 * Since that impedes debugging, we don't want to do that.
3815 if (sc->ti_flags & TI_FLAG_DEBUGING)
3819 if_printf(ifp, "watchdog timeout -- resetting\n");
3820 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3827 * Stop the adapter and free any mbufs allocated to the
3831 ti_stop(struct ti_softc *sc)
3834 struct ti_cmd_desc cmd;
3840 /* Disable host interrupts. */
3841 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3843 * Tell firmware we're shutting down.
3845 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3847 /* Halt and reinitialize. */
3848 if (ti_chipinit(sc) == 0) {
3849 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
3850 /* XXX ignore init errors. */
3854 /* Free the RX lists. */
3855 ti_free_rx_ring_std(sc);
3857 /* Free jumbo RX list. */
3858 ti_free_rx_ring_jumbo(sc);
3860 /* Free mini RX list. */
3861 ti_free_rx_ring_mini(sc);
3863 /* Free TX buffers. */
3864 ti_free_tx_ring(sc);
3866 sc->ti_ev_prodidx.ti_idx = 0;
3867 sc->ti_return_prodidx.ti_idx = 0;
3868 sc->ti_tx_considx.ti_idx = 0;
3869 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3871 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3872 callout_stop(&sc->ti_watchdog);
3876 * Stop all chip I/O so that the kernel's probe routines don't
3877 * get confused by errant DMAs when rebooting.
3880 ti_shutdown(device_t dev)
3882 struct ti_softc *sc;
3884 sc = device_get_softc(dev);