2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
35 * Manuals, sample driver and firmware source kits are available
36 * from http://www.alteon.com/support/openkits.
38 * Written by Bill Paul <wpaul@ctr.columbia.edu>
39 * Electrical Engineering Department
40 * Columbia University, New York City
44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
48 * filtering and jumbo (9014 byte) frames. The hardware is largely
49 * controlled by firmware, which must be loaded into the NIC during
52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
53 * revision, which supports new features such as extended commands,
54 * extended jumbo receive ring desciptors and a mini receive ring.
56 * Alteon Networks is to be commended for releasing such a vast amount
57 * of development material for the Tigon NIC without requiring an NDA
58 * (although they really should have done it a long time ago). With
59 * any luck, the other vendors will finally wise up and follow Alteon's
62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
63 * this driver by #including it as a C header file. This bloats the
64 * driver somewhat, but it's the easiest method considering that the
65 * driver code and firmware code need to be kept in sync. The source
66 * for the firmware is not provided with the FreeBSD distribution since
67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
69 * The following people deserve special thanks:
70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
72 * - Raymond Lee of Netgear, for providing a pair of Netgear
73 * GA620 Tigon 2 boards for testing
74 * - Ulf Zimmermann, for bringing the GA260 to my attention and
75 * convincing me to write this driver.
76 * - Andrew Gallatin for providing FreeBSD/Alpha support.
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/sockio.h>
88 #include <sys/malloc.h>
89 #include <sys/kernel.h>
90 #include <sys/module.h>
91 #include <sys/socket.h>
92 #include <sys/queue.h>
96 #include <net/if_arp.h>
97 #include <net/ethernet.h>
98 #include <net/if_dl.h>
99 #include <net/if_media.h>
100 #include <net/if_types.h>
101 #include <net/if_vlan_var.h>
105 #include <netinet/in_systm.h>
106 #include <netinet/in.h>
107 #include <netinet/ip.h>
109 #include <vm/vm.h> /* for vtophys */
110 #include <vm/pmap.h> /* for vtophys */
111 #include <machine/bus.h>
112 #include <machine/resource.h>
114 #include <sys/rman.h>
116 /* #define TI_PRIVATE_JUMBOS */
118 #if !defined(TI_PRIVATE_JUMBOS)
119 #include <sys/sockio.h>
121 #include <sys/lock.h>
122 #include <sys/sf_buf.h>
123 #include <vm/vm_extern.h>
125 #include <vm/vm_map.h>
126 #include <vm/vm_map.h>
127 #include <vm/vm_param.h>
128 #include <vm/vm_pageout.h>
129 #include <sys/vmmeter.h>
130 #include <vm/vm_page.h>
131 #include <vm/vm_object.h>
132 #include <vm/vm_kern.h>
133 #include <sys/proc.h>
134 #endif /* !TI_PRIVATE_JUMBOS */
136 #include <dev/pci/pcireg.h>
137 #include <dev/pci/pcivar.h>
139 #include <sys/tiio.h>
140 #include <pci/if_tireg.h>
141 #include <pci/ti_fw.h>
142 #include <pci/ti_fw2.h>
144 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
146 * We can only turn on header splitting if we're using extended receive
149 #if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS)
150 #error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive"
151 #endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */
153 struct ti_softc *tis[8];
162 * Various supported device vendors/types and their names.
165 static struct ti_type ti_devs[] = {
166 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
167 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
168 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
169 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
170 { TC_VENDORID, TC_DEVICEID_3C985,
171 "3Com 3c985-SX Gigabit Ethernet" },
172 { NG_VENDORID, NG_DEVICEID_GA620,
173 "Netgear GA620 1000baseSX Gigabit Ethernet" },
174 { NG_VENDORID, NG_DEVICEID_GA620T,
175 "Netgear GA620 1000baseT Gigabit Ethernet" },
176 { SGI_VENDORID, SGI_DEVICEID_TIGON,
177 "Silicon Graphics Gigabit Ethernet" },
178 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
179 "Farallon PN9000SX Gigabit Ethernet" },
184 static d_open_t ti_open;
185 static d_close_t ti_close;
186 static d_ioctl_t ti_ioctl2;
188 static struct cdevsw ti_cdevsw = {
189 .d_version = D_VERSION,
190 .d_flags = D_NEEDGIANT,
193 .d_ioctl = ti_ioctl2,
197 static int ti_probe(device_t);
198 static int ti_attach(device_t);
199 static int ti_detach(device_t);
200 static void ti_txeof(struct ti_softc *);
201 static void ti_rxeof(struct ti_softc *);
203 static void ti_stats_update(struct ti_softc *);
204 static int ti_encap(struct ti_softc *, struct mbuf *, u_int32_t *);
206 static void ti_intr(void *);
207 static void ti_start(struct ifnet *);
208 static int ti_ioctl(struct ifnet *, u_long, caddr_t);
209 static void ti_init(void *);
210 static void ti_init2(struct ti_softc *);
211 static void ti_stop(struct ti_softc *);
212 static void ti_watchdog(struct ifnet *);
213 static void ti_shutdown(device_t);
214 static int ti_ifmedia_upd(struct ifnet *);
215 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
217 static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int);
218 static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *);
219 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
221 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
222 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
223 static void ti_setmulti(struct ti_softc *);
225 static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t);
226 static int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int);
227 static int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t,
229 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
230 static void ti_loadfw(struct ti_softc *);
231 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
232 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
233 static void ti_handle_events(struct ti_softc *);
234 #ifdef TI_PRIVATE_JUMBOS
235 static int ti_alloc_jumbo_mem(struct ti_softc *);
236 static void *ti_jalloc(struct ti_softc *);
237 static void ti_jfree(void *, void *);
238 #endif /* TI_PRIVATE_JUMBOS */
239 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
240 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
241 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
242 static int ti_init_rx_ring_std(struct ti_softc *);
243 static void ti_free_rx_ring_std(struct ti_softc *);
244 static int ti_init_rx_ring_jumbo(struct ti_softc *);
245 static void ti_free_rx_ring_jumbo(struct ti_softc *);
246 static int ti_init_rx_ring_mini(struct ti_softc *);
247 static void ti_free_rx_ring_mini(struct ti_softc *);
248 static void ti_free_tx_ring(struct ti_softc *);
249 static int ti_init_tx_ring(struct ti_softc *);
251 static int ti_64bitslot_war(struct ti_softc *);
252 static int ti_chipinit(struct ti_softc *);
253 static int ti_gibinit(struct ti_softc *);
255 #ifdef TI_JUMBO_HDRSPLIT
256 static __inline void ti_hdr_split (struct mbuf *top, int hdr_len,
257 int pkt_len, int idx);
258 #endif /* TI_JUMBO_HDRSPLIT */
260 static device_method_t ti_methods[] = {
261 /* Device interface */
262 DEVMETHOD(device_probe, ti_probe),
263 DEVMETHOD(device_attach, ti_attach),
264 DEVMETHOD(device_detach, ti_detach),
265 DEVMETHOD(device_shutdown, ti_shutdown),
269 static driver_t ti_driver = {
272 sizeof(struct ti_softc)
275 static devclass_t ti_devclass;
277 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
278 MODULE_DEPEND(ti, pci, 1, 1, 1);
279 MODULE_DEPEND(ti, ether, 1, 1, 1);
282 * Send an instruction or address to the EEPROM, check for ACK.
284 static u_int32_t ti_eeprom_putbyte(sc, byte)
288 register int i, ack = 0;
291 * Make sure we're in TX mode.
293 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
296 * Feed in each bit and stobe the clock.
298 for (i = 0x80; i; i >>= 1) {
300 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
302 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
305 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
307 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
313 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
318 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
319 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
320 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
326 * Read a byte of data stored in the EEPROM at address 'addr.'
327 * We have to send two address bytes since the EEPROM can hold
328 * more than 256 bytes of data.
330 static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
341 * Send write control code to EEPROM.
343 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
344 printf("ti%d: failed to send write command, status: %x\n",
345 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
350 * Send first byte of address of byte we want to read.
352 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
353 printf("ti%d: failed to send address, status: %x\n",
354 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
358 * Send second byte address of byte we want to read.
360 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
361 printf("ti%d: failed to send address, status: %x\n",
362 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
369 * Send read control code to EEPROM.
371 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
372 printf("ti%d: failed to send read command, status: %x\n",
373 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
378 * Start reading bits from EEPROM.
380 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
381 for (i = 0x80; i; i >>= 1) {
382 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
384 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
386 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
393 * No ACK generated for read, so just return byte.
402 * Read a sequence of bytes from the EEPROM.
405 ti_read_eeprom(sc, dest, off, cnt)
414 for (i = 0; i < cnt; i++) {
415 err = ti_eeprom_getbyte(sc, off + i, &byte);
421 return (err ? 1 : 0);
425 * NIC memory access function. Can be used to either clear a section
426 * of NIC local memory or (if buf is non-NULL) copy data into it.
429 ti_mem(sc, addr, len, buf)
434 int segptr, segsize, cnt;
435 caddr_t ti_winbase, ptr;
439 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
446 segsize = TI_WINLEN - (segptr % TI_WINLEN);
447 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
449 bzero((char *)ti_winbase + (segptr &
450 (TI_WINLEN - 1)), segsize);
452 bcopy((char *)ptr, (char *)ti_winbase +
453 (segptr & (TI_WINLEN - 1)), segsize);
462 ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata)
464 u_int32_t tigon_addr, len;
466 int useraddr, readdata;
468 int segptr, segsize, cnt;
471 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN];
476 * At the moment, we don't handle non-aligned cases, we just bail.
477 * If this proves to be a problem, it will be fixed.
480 && (tigon_addr & 0x3)) {
481 printf("ti%d: ti_copy_mem: tigon address %#x isn't "
482 "word-aligned\n", sc->ti_unit, tigon_addr);
483 printf("ti%d: ti_copy_mem: unaligned writes aren't yet "
484 "supported\n", sc->ti_unit);
488 segptr = tigon_addr & ~0x3;
489 segresid = tigon_addr - segptr;
492 * This is the non-aligned amount left over that we'll need to
497 /* Add in the left over amount at the front of the buffer */
502 * If resid + segresid is >= 4, add multiples of 4 to the count and
503 * decrease the residual by that much.
506 resid -= resid & ~0x3;
513 * Make sure we aren't interrupted while we're changing the window
519 * Save the old window base value.
521 origwin = CSR_READ_4(sc, TI_WINBASE);
524 bus_size_t ti_offset;
529 segsize = TI_WINLEN - (segptr % TI_WINLEN);
530 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
532 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
536 bus_space_read_region_4(sc->ti_btag,
537 sc->ti_bhandle, ti_offset,
538 (u_int32_t *)tmparray,
542 * Yeah, this is a little on the kludgy
543 * side, but at least this code is only
544 * used for debugging.
546 ti_bcopy_swap(tmparray, tmparray2, segsize,
550 copyout(&tmparray2[segresid], ptr,
554 copyout(tmparray2, ptr, segsize);
558 ti_bcopy_swap(tmparray, tmparray2,
559 segsize, TI_SWAP_NTOH);
560 bcopy(&tmparray2[segresid], ptr,
564 ti_bcopy_swap(tmparray, ptr, segsize,
570 copyin(ptr, tmparray2, segsize);
571 ti_bcopy_swap(tmparray2, tmparray, segsize,
574 ti_bcopy_swap(ptr, tmparray, segsize,
577 bus_space_write_region_4(sc->ti_btag,
578 sc->ti_bhandle, ti_offset,
579 (u_int32_t *)tmparray,
588 * Handle leftover, non-word-aligned bytes.
591 u_int32_t tmpval, tmpval2;
592 bus_size_t ti_offset;
595 * Set the segment pointer.
597 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
599 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
602 * First, grab whatever is in our source/destination.
603 * We'll obviously need this for reads, but also for
604 * writes, since we'll be doing read/modify/write.
606 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
607 ti_offset, &tmpval, 1);
610 * Next, translate this from little-endian to big-endian
611 * (at least on i386 boxes).
613 tmpval2 = ntohl(tmpval);
617 * If we're reading, just copy the leftover number
618 * of bytes from the host byte order buffer to
622 copyout(&tmpval2, ptr, resid);
624 bcopy(&tmpval2, ptr, resid);
627 * If we're writing, first copy the bytes to be
628 * written into the network byte order buffer,
629 * leaving the rest of the buffer with whatever was
630 * originally in there. Then, swap the bytes
631 * around into host order and write them out.
633 * XXX KDM the read side of this has been verified
634 * to work, but the write side of it has not been
635 * verified. So user beware.
638 copyin(ptr, &tmpval2, resid);
640 bcopy(ptr, &tmpval2, resid);
642 tmpval = htonl(tmpval2);
644 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
645 ti_offset, &tmpval, 1);
649 CSR_WRITE_4(sc, TI_WINBASE, origwin);
657 ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu)
659 u_int32_t tigon_addr, len;
661 int useraddr, readdata;
666 u_int32_t tmpval, tmpval2;
670 * At the moment, we don't handle non-aligned cases, we just bail.
671 * If this proves to be a problem, it will be fixed.
673 if (tigon_addr & 0x3) {
674 printf("ti%d: ti_copy_scratch: tigon address %#x isn't "
675 "word-aligned\n", sc->ti_unit, tigon_addr);
680 printf("ti%d: ti_copy_scratch: transfer length %d isn't "
681 "word-aligned\n", sc->ti_unit, len);
692 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
695 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
697 tmpval = ntohl(tmpval2);
700 * Note: I've used this debugging interface
701 * extensively with Alteon's 12.3.15 firmware,
702 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
704 * When you compile the firmware without
705 * optimization, which is necessary sometimes in
706 * order to properly step through it, you sometimes
707 * read out a bogus value of 0xc0017c instead of
708 * whatever was supposed to be in that scratchpad
709 * location. That value is on the stack somewhere,
710 * but I've never been able to figure out what was
711 * causing the problem.
713 * The address seems to pop up in random places,
714 * often not in the same place on two subsequent
717 * In any case, the underlying data doesn't seem
718 * to be affected, just the value read out.
723 if (tmpval2 == 0xc0017c)
724 printf("ti%d: found 0xc0017c at %#x "
725 "(tmpval2)\n", sc->ti_unit, segptr);
727 if (tmpval == 0xc0017c)
728 printf("ti%d: found 0xc0017c at %#x "
729 "(tmpval)\n", sc->ti_unit, segptr);
732 copyout(&tmpval, ptr, 4);
734 bcopy(&tmpval, ptr, 4);
737 copyin(ptr, &tmpval2, 4);
739 bcopy(ptr, &tmpval2, 4);
741 tmpval = htonl(tmpval2);
743 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
757 ti_bcopy_swap(src, dst, len, swap_type)
761 ti_swap_type swap_type;
763 const u_int8_t *tmpsrc;
768 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n",
778 if (swap_type == TI_SWAP_NTOH)
779 *(u_int32_t *)tmpdst =
780 ntohl(*(const u_int32_t *)tmpsrc);
782 *(u_int32_t *)tmpdst =
783 htonl(*(const u_int32_t *)tmpsrc);
794 * Load firmware image into the NIC. Check that the firmware revision
795 * is acceptable and see if we want the firmware for the Tigon 1 or
802 switch (sc->ti_hwrev) {
804 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
805 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
806 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
807 printf("ti%d: firmware revision mismatch; want "
808 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
809 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
810 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
811 tigonFwReleaseMinor, tigonFwReleaseFix);
814 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
815 (caddr_t)tigonFwText);
816 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
817 (caddr_t)tigonFwData);
818 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
819 (caddr_t)tigonFwRodata);
820 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
821 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
822 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
824 case TI_HWREV_TIGON_II:
825 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
826 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
827 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
828 printf("ti%d: firmware revision mismatch; want "
829 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
830 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
831 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
832 tigon2FwReleaseMinor, tigon2FwReleaseFix);
835 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
836 (caddr_t)tigon2FwText);
837 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
838 (caddr_t)tigon2FwData);
839 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
840 (caddr_t)tigon2FwRodata);
841 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
842 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
843 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
846 printf("ti%d: can't load firmware: unknown hardware rev\n",
853 * Send the NIC a command via the command ring.
858 struct ti_cmd_desc *cmd;
862 if (sc->ti_rdata->ti_cmd_ring == NULL)
865 index = sc->ti_cmd_saved_prodidx;
866 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
867 TI_INC(index, TI_CMD_RING_CNT);
868 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
869 sc->ti_cmd_saved_prodidx = index;
873 * Send the NIC an extended command. The 'len' parameter specifies the
874 * number of command slots to include after the initial command.
877 ti_cmd_ext(sc, cmd, arg, len)
879 struct ti_cmd_desc *cmd;
886 if (sc->ti_rdata->ti_cmd_ring == NULL)
889 index = sc->ti_cmd_saved_prodidx;
890 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
891 TI_INC(index, TI_CMD_RING_CNT);
892 for (i = 0; i < len; i++) {
893 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
894 *(u_int32_t *)(&arg[i * 4]));
895 TI_INC(index, TI_CMD_RING_CNT);
897 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
898 sc->ti_cmd_saved_prodidx = index;
902 * Handle events that have triggered interrupts.
908 struct ti_event_desc *e;
910 if (sc->ti_rdata->ti_event_ring == NULL)
913 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
914 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
915 switch (e->ti_event) {
916 case TI_EV_LINKSTAT_CHANGED:
917 sc->ti_linkstat = e->ti_code;
918 if (e->ti_code == TI_EV_CODE_LINK_UP)
919 printf("ti%d: 10/100 link up\n", sc->ti_unit);
920 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
921 printf("ti%d: gigabit link up\n", sc->ti_unit);
922 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
923 printf("ti%d: link down\n", sc->ti_unit);
926 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
927 printf("ti%d: invalid command\n", sc->ti_unit);
928 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
929 printf("ti%d: unknown command\n", sc->ti_unit);
930 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
931 printf("ti%d: bad config data\n", sc->ti_unit);
933 case TI_EV_FIRMWARE_UP:
936 case TI_EV_STATS_UPDATED:
939 case TI_EV_RESET_JUMBO_RING:
940 case TI_EV_MCAST_UPDATED:
944 printf("ti%d: unknown event: %d\n",
945 sc->ti_unit, e->ti_event);
948 /* Advance the consumer index. */
949 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
950 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
954 #ifdef TI_PRIVATE_JUMBOS
957 * Memory management for the jumbo receive ring is a pain in the
958 * butt. We need to allocate at least 9018 bytes of space per frame,
959 * _and_ it has to be contiguous (unless you use the extended
960 * jumbo descriptor format). Using malloc() all the time won't
961 * work: malloc() allocates memory in powers of two, which means we
962 * would end up wasting a considerable amount of space by allocating
963 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
964 * to do our own memory management.
966 * The driver needs to allocate a contiguous chunk of memory at boot
967 * time. We then chop this up ourselves into 9K pieces and use them
968 * as external mbuf storage.
970 * One issue here is how much memory to allocate. The jumbo ring has
971 * 256 slots in it, but at 9K per slot than can consume over 2MB of
972 * RAM. This is a bit much, especially considering we also need
973 * RAM for the standard ring and mini ring (on the Tigon 2). To
974 * save space, we only actually allocate enough memory for 64 slots
975 * by default, which works out to between 500 and 600K. This can
976 * be tuned by changing a #define in if_tireg.h.
980 ti_alloc_jumbo_mem(sc)
985 struct ti_jpool_entry *entry;
987 /* Grab a big chunk o' storage. */
988 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
989 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
991 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
992 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
996 SLIST_INIT(&sc->ti_jfree_listhead);
997 SLIST_INIT(&sc->ti_jinuse_listhead);
1000 * Now divide it up into 9K pieces and save the addresses
1003 ptr = sc->ti_cdata.ti_jumbo_buf;
1004 for (i = 0; i < TI_JSLOTS; i++) {
1005 sc->ti_cdata.ti_jslots[i] = ptr;
1007 entry = malloc(sizeof(struct ti_jpool_entry),
1008 M_DEVBUF, M_NOWAIT);
1009 if (entry == NULL) {
1010 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
1012 sc->ti_cdata.ti_jumbo_buf = NULL;
1013 printf("ti%d: no memory for jumbo "
1014 "buffer queue!\n", sc->ti_unit);
1018 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1025 * Allocate a jumbo buffer.
1027 static void *ti_jalloc(sc)
1028 struct ti_softc *sc;
1030 struct ti_jpool_entry *entry;
1032 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
1034 if (entry == NULL) {
1035 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
1039 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
1040 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
1041 return (sc->ti_cdata.ti_jslots[entry->slot]);
1045 * Release a jumbo buffer.
1052 struct ti_softc *sc;
1054 struct ti_jpool_entry *entry;
1056 /* Extract the softc struct pointer. */
1057 sc = (struct ti_softc *)args;
1060 panic("ti_jfree: didn't get softc pointer!");
1062 /* calculate the slot this buffer belongs to */
1063 i = ((vm_offset_t)buf
1064 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
1066 if ((i < 0) || (i >= TI_JSLOTS))
1067 panic("ti_jfree: asked to free buffer that we don't manage!");
1069 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
1071 panic("ti_jfree: buffer not in use!");
1073 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
1074 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1077 #endif /* TI_PRIVATE_JUMBOS */
1080 * Intialize a standard receive ring descriptor.
1083 ti_newbuf_std(sc, i, m)
1084 struct ti_softc *sc;
1088 struct mbuf *m_new = NULL;
1089 struct ti_rx_desc *r;
1092 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1096 MCLGET(m_new, M_DONTWAIT);
1097 if (!(m_new->m_flags & M_EXT)) {
1101 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1104 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1105 m_new->m_data = m_new->m_ext.ext_buf;
1108 m_adj(m_new, ETHER_ALIGN);
1109 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
1110 r = &sc->ti_rdata->ti_rx_std_ring[i];
1111 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
1112 r->ti_type = TI_BDTYPE_RECV_BD;
1114 if (sc->ti_ifp->if_hwassist)
1115 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1116 r->ti_len = m_new->m_len;
1123 * Intialize a mini receive ring descriptor. This only applies to
1127 ti_newbuf_mini(sc, i, m)
1128 struct ti_softc *sc;
1132 struct mbuf *m_new = NULL;
1133 struct ti_rx_desc *r;
1136 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1137 if (m_new == NULL) {
1140 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1143 m_new->m_data = m_new->m_pktdat;
1144 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1147 m_adj(m_new, ETHER_ALIGN);
1148 r = &sc->ti_rdata->ti_rx_mini_ring[i];
1149 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
1150 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
1151 r->ti_type = TI_BDTYPE_RECV_BD;
1152 r->ti_flags = TI_BDFLAG_MINI_RING;
1153 if (sc->ti_ifp->if_hwassist)
1154 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1155 r->ti_len = m_new->m_len;
1161 #ifdef TI_PRIVATE_JUMBOS
1164 * Initialize a jumbo receive ring descriptor. This allocates
1165 * a jumbo buffer from the pool managed internally by the driver.
1168 ti_newbuf_jumbo(sc, i, m)
1169 struct ti_softc *sc;
1173 struct mbuf *m_new = NULL;
1174 struct ti_rx_desc *r;
1177 caddr_t *buf = NULL;
1179 /* Allocate the mbuf. */
1180 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1181 if (m_new == NULL) {
1185 /* Allocate the jumbo buffer */
1186 buf = ti_jalloc(sc);
1189 printf("ti%d: jumbo allocation failed "
1190 "-- packet dropped!\n", sc->ti_unit);
1194 /* Attach the buffer to the mbuf. */
1195 m_new->m_data = (void *) buf;
1196 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
1197 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree,
1198 (struct ti_softc *)sc, 0, EXT_NET_DRV);
1201 m_new->m_data = m_new->m_ext.ext_buf;
1202 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
1205 m_adj(m_new, ETHER_ALIGN);
1206 /* Set up the descriptor. */
1207 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
1208 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
1209 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
1210 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1211 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1212 if (sc->ti_ifp->if_hwassist)
1213 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1214 r->ti_len = m_new->m_len;
1221 #include <vm/vm_page.h>
1223 #if (PAGE_SIZE == 4096)
1229 #define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1230 #define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1231 #define NFS_HDR_LEN (UDP_HDR_LEN)
1232 static int HDR_LEN = TCP_HDR_LEN;
1236 * Initialize a jumbo receive ring descriptor. This allocates
1237 * a jumbo buffer from the pool managed internally by the driver.
1240 ti_newbuf_jumbo(sc, idx, m_old)
1241 struct ti_softc *sc;
1245 struct mbuf *cur, *m_new = NULL;
1246 struct mbuf *m[3] = {NULL, NULL, NULL};
1247 struct ti_rx_desc_ext *r;
1250 /* 1 extra buf to make nobufs easy*/
1251 struct sf_buf *sf[3] = {NULL, NULL, NULL};
1254 if (m_old != NULL) {
1256 cur = m_old->m_next;
1257 for (i = 0; i <= NPAYLOAD; i++){
1262 /* Allocate the mbufs. */
1263 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1264 if (m_new == NULL) {
1265 printf("ti%d: mbuf allocation failed "
1266 "-- packet dropped!\n", sc->ti_unit);
1269 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
1270 if (m[NPAYLOAD] == NULL) {
1271 printf("ti%d: cluster mbuf allocation failed "
1272 "-- packet dropped!\n", sc->ti_unit);
1275 MCLGET(m[NPAYLOAD], M_DONTWAIT);
1276 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1277 printf("ti%d: mbuf allocation failed "
1278 "-- packet dropped!\n", sc->ti_unit);
1281 m[NPAYLOAD]->m_len = MCLBYTES;
1283 for (i = 0; i < NPAYLOAD; i++){
1284 MGET(m[i], M_DONTWAIT, MT_DATA);
1286 printf("ti%d: mbuf allocation failed "
1287 "-- packet dropped!\n", sc->ti_unit);
1290 frame = vm_page_alloc(NULL, color++,
1291 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1293 if (frame == NULL) {
1294 printf("ti%d: buffer allocation failed "
1295 "-- packet dropped!\n", sc->ti_unit);
1296 printf(" index %d page %d\n", idx, i);
1299 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1300 if (sf[i] == NULL) {
1301 vm_page_lock_queues();
1302 vm_page_unwire(frame, 0);
1303 vm_page_free(frame);
1304 vm_page_unlock_queues();
1305 printf("ti%d: buffer allocation failed "
1306 "-- packet dropped!\n", sc->ti_unit);
1307 printf(" index %d page %d\n", idx, i);
1311 for (i = 0; i < NPAYLOAD; i++){
1312 /* Attach the buffer to the mbuf. */
1313 m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1314 m[i]->m_len = PAGE_SIZE;
1315 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1316 sf_buf_mext, sf[i], 0, EXT_DISPOSABLE);
1317 m[i]->m_next = m[i+1];
1319 /* link the buffers to the header */
1320 m_new->m_next = m[0];
1321 m_new->m_data += ETHER_ALIGN;
1322 if (sc->ti_hdrsplit)
1323 m_new->m_len = MHLEN - ETHER_ALIGN;
1325 m_new->m_len = HDR_LEN;
1326 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1329 /* Set up the descriptor. */
1330 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx];
1331 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1332 TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t));
1333 r->ti_len0 = m_new->m_len;
1335 TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t));
1336 r->ti_len1 = PAGE_SIZE;
1338 TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t));
1339 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1341 if (PAGE_SIZE == 4096) {
1342 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t));
1343 r->ti_len3 = MCLBYTES;
1347 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1349 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1351 if (sc->ti_ifp->if_hwassist)
1352 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1362 * This can only be called before the mbufs are strung together.
1363 * If the mbufs are strung together, m_freem() will free the chain,
1364 * so that the later mbufs will be freed multiple times.
1369 for (i = 0; i < 3; i++) {
1373 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
1382 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1383 * that's 1MB or memory, which is a lot. For now, we fill only the first
1384 * 256 ring entries and hope that our CPU is fast enough to keep up with
1388 ti_init_rx_ring_std(sc)
1389 struct ti_softc *sc;
1392 struct ti_cmd_desc cmd;
1394 for (i = 0; i < TI_SSLOTS; i++) {
1395 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
1399 TI_UPDATE_STDPROD(sc, i - 1);
1406 ti_free_rx_ring_std(sc)
1407 struct ti_softc *sc;
1411 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1412 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1413 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1414 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1416 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
1417 sizeof(struct ti_rx_desc));
1422 ti_init_rx_ring_jumbo(sc)
1423 struct ti_softc *sc;
1426 struct ti_cmd_desc cmd;
1428 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1429 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1433 TI_UPDATE_JUMBOPROD(sc, i - 1);
1434 sc->ti_jumbo = i - 1;
1440 ti_free_rx_ring_jumbo(sc)
1441 struct ti_softc *sc;
1445 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1446 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1447 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1448 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1450 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
1451 sizeof(struct ti_rx_desc));
1456 ti_init_rx_ring_mini(sc)
1457 struct ti_softc *sc;
1461 for (i = 0; i < TI_MSLOTS; i++) {
1462 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
1466 TI_UPDATE_MINIPROD(sc, i - 1);
1467 sc->ti_mini = i - 1;
1473 ti_free_rx_ring_mini(sc)
1474 struct ti_softc *sc;
1478 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1479 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1480 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1481 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1483 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1484 sizeof(struct ti_rx_desc));
1490 struct ti_softc *sc;
1494 if (sc->ti_rdata->ti_tx_ring == NULL)
1497 for (i = 0; i < TI_TX_RING_CNT; i++) {
1498 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
1499 m_freem(sc->ti_cdata.ti_tx_chain[i]);
1500 sc->ti_cdata.ti_tx_chain[i] = NULL;
1502 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1503 sizeof(struct ti_tx_desc));
1509 struct ti_softc *sc;
1512 sc->ti_tx_saved_considx = 0;
1513 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1518 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1519 * but we have to support the old way too so that Tigon 1 cards will
1523 ti_add_mcast(sc, addr)
1524 struct ti_softc *sc;
1525 struct ether_addr *addr;
1527 struct ti_cmd_desc cmd;
1529 u_int32_t ext[2] = {0, 0};
1531 m = (u_int16_t *)&addr->octet[0];
1533 switch (sc->ti_hwrev) {
1534 case TI_HWREV_TIGON:
1535 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1536 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1537 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1539 case TI_HWREV_TIGON_II:
1540 ext[0] = htons(m[0]);
1541 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1542 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1545 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1551 ti_del_mcast(sc, addr)
1552 struct ti_softc *sc;
1553 struct ether_addr *addr;
1555 struct ti_cmd_desc cmd;
1557 u_int32_t ext[2] = {0, 0};
1559 m = (u_int16_t *)&addr->octet[0];
1561 switch (sc->ti_hwrev) {
1562 case TI_HWREV_TIGON:
1563 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1564 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1565 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1567 case TI_HWREV_TIGON_II:
1568 ext[0] = htons(m[0]);
1569 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1570 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1573 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1579 * Configure the Tigon's multicast address filter.
1581 * The actual multicast table management is a bit of a pain, thanks to
1582 * slight brain damage on the part of both Alteon and us. With our
1583 * multicast code, we are only alerted when the multicast address table
1584 * changes and at that point we only have the current list of addresses:
1585 * we only know the current state, not the previous state, so we don't
1586 * actually know what addresses were removed or added. The firmware has
1587 * state, but we can't get our grubby mits on it, and there is no 'delete
1588 * all multicast addresses' command. Hence, we have to maintain our own
1589 * state so we know what addresses have been programmed into the NIC at
1594 struct ti_softc *sc;
1597 struct ifmultiaddr *ifma;
1598 struct ti_cmd_desc cmd;
1599 struct ti_mc_entry *mc;
1604 if (ifp->if_flags & IFF_ALLMULTI) {
1605 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1608 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1611 /* Disable interrupts. */
1612 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1613 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1615 /* First, zot all the existing filters. */
1616 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1617 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1618 ti_del_mcast(sc, &mc->mc_addr);
1619 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1623 /* Now program new ones. */
1624 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1625 if (ifma->ifma_addr->sa_family != AF_LINK)
1627 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1629 if_printf(ifp, "no memory for mcast filter entry\n");
1632 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1633 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1634 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1635 ti_add_mcast(sc, &mc->mc_addr);
1638 /* Re-enable interrupts. */
1639 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1643 * Check to see if the BIOS has configured us for a 64 bit slot when
1644 * we aren't actually in one. If we detect this condition, we can work
1645 * around it on the Tigon 2 by setting a bit in the PCI state register,
1646 * but for the Tigon 1 we must give up and abort the interface attach.
1648 static int ti_64bitslot_war(sc)
1649 struct ti_softc *sc;
1651 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1652 CSR_WRITE_4(sc, 0x600, 0);
1653 CSR_WRITE_4(sc, 0x604, 0);
1654 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1655 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1656 if (sc->ti_hwrev == TI_HWREV_TIGON)
1659 TI_SETBIT(sc, TI_PCI_STATE,
1660 TI_PCISTATE_32BIT_BUS);
1670 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1671 * self-test results.
1675 struct ti_softc *sc;
1677 u_int32_t cacheline;
1678 u_int32_t pci_writemax = 0;
1681 /* Initialize link to down state. */
1682 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1684 if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM)
1685 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES;
1687 sc->ti_ifp->if_hwassist = 0;
1689 /* Set endianness before we access any non-PCI registers. */
1690 #if BYTE_ORDER == BIG_ENDIAN
1691 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1692 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1694 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1695 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1698 /* Check the ROM failed bit to see if self-tests passed. */
1699 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1700 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1705 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1707 /* Figure out the hardware revision. */
1708 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1709 case TI_REV_TIGON_I:
1710 sc->ti_hwrev = TI_HWREV_TIGON;
1712 case TI_REV_TIGON_II:
1713 sc->ti_hwrev = TI_HWREV_TIGON_II;
1716 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1720 /* Do special setup for Tigon 2. */
1721 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1722 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1723 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1724 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1728 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
1729 * can't do header splitting.
1731 #ifdef TI_JUMBO_HDRSPLIT
1732 if (sc->ti_hwrev != TI_HWREV_TIGON)
1733 sc->ti_hdrsplit = 1;
1735 printf("ti%d: can't do header splitting on a Tigon I board\n",
1737 #endif /* TI_JUMBO_HDRSPLIT */
1739 /* Set up the PCI state register. */
1740 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1741 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1742 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1745 /* Clear the read/write max DMA parameters. */
1746 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1747 TI_PCISTATE_READ_MAXDMA));
1749 /* Get cache line size. */
1750 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1753 * If the system has set enabled the PCI memory write
1754 * and invalidate command in the command register, set
1755 * the write max parameter accordingly. This is necessary
1756 * to use MWI with the Tigon 2.
1758 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1759 switch (cacheline) {
1768 /* Disable PCI memory write and invalidate. */
1770 printf("ti%d: cache line size %d not "
1771 "supported; disabling PCI MWI\n",
1772 sc->ti_unit, cacheline);
1773 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1774 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1779 #ifdef __brokenalpha__
1781 * From the Alteon sample driver:
1782 * Must insure that we do not cross an 8K (bytes) boundary
1783 * for DMA reads. Our highest limit is 1K bytes. This is a
1784 * restriction on some ALPHA platforms with early revision
1785 * 21174 PCI chipsets, such as the AlphaPC 164lx
1787 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1789 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1792 /* This sets the min dma param all the way up (0xff). */
1793 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1795 if (sc->ti_hdrsplit)
1796 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
1800 /* Configure DMA variables. */
1801 #if BYTE_ORDER == BIG_ENDIAN
1802 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1803 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1804 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1805 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
1806 #else /* BYTE_ORDER */
1807 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1808 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1809 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
1810 #endif /* BYTE_ORDER */
1813 * Only allow 1 DMA channel to be active at a time.
1814 * I don't think this is a good idea, but without it
1815 * the firmware racks up lots of nicDmaReadRingFull
1816 * errors. This is not compatible with hardware checksums.
1818 if (sc->ti_ifp->if_hwassist == 0)
1819 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1821 /* Recommended settings from Tigon manual. */
1822 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1823 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1825 if (ti_64bitslot_war(sc)) {
1826 printf("ti%d: bios thinks we're in a 64 bit slot, "
1827 "but we aren't", sc->ti_unit);
1834 #define TI_RD_OFF(x) offsetof(struct ti_ring_data, x)
1837 * Initialize the general information block and firmware, and
1838 * start the CPU(s) running.
1842 struct ti_softc *sc;
1850 rdphys = sc->ti_rdata_phys;
1852 /* Disable interrupts for now. */
1853 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1856 * Tell the chip where to find the general information block.
1857 * While this struct could go into >4GB memory, we allocate it in a
1858 * single slab with the other descriptors, and those don't seem to
1859 * support being located in a 64-bit region.
1861 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1862 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info));
1864 /* Load the firmware into SRAM. */
1867 /* Set up the contents of the general info and ring control blocks. */
1869 /* Set up the event ring and producer pointer. */
1870 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1872 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring);
1874 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1875 rdphys + TI_RD_OFF(ti_ev_prodidx_r);
1876 sc->ti_ev_prodidx.ti_idx = 0;
1877 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1878 sc->ti_ev_saved_considx = 0;
1880 /* Set up the command ring and producer mailbox. */
1881 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1883 sc->ti_rdata->ti_cmd_ring =
1884 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1885 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1887 rcb->ti_max_len = 0;
1888 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1889 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1891 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1892 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1893 sc->ti_cmd_saved_prodidx = 0;
1896 * Assign the address of the stats refresh buffer.
1897 * We re-use the current stats buffer for this to
1900 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1901 rdphys + TI_RD_OFF(ti_info.ti_stats);
1903 /* Set up the standard receive ring. */
1904 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1905 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring);
1906 rcb->ti_max_len = TI_FRAMELEN;
1908 if (sc->ti_ifp->if_hwassist)
1909 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1910 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1911 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1913 /* Set up the jumbo receive ring. */
1914 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1915 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring);
1917 #ifdef TI_PRIVATE_JUMBOS
1918 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1921 rcb->ti_max_len = PAGE_SIZE;
1922 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
1924 if (sc->ti_ifp->if_hwassist)
1925 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1926 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1927 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1930 * Set up the mini ring. Only activated on the
1931 * Tigon 2 but the slot in the config block is
1932 * still there on the Tigon 1.
1934 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1935 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring);
1936 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1937 if (sc->ti_hwrev == TI_HWREV_TIGON)
1938 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1941 if (sc->ti_ifp->if_hwassist)
1942 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1943 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1944 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1947 * Set up the receive return ring.
1949 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1950 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring);
1952 rcb->ti_max_len = TI_RETURN_RING_CNT;
1953 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1954 rdphys + TI_RD_OFF(ti_return_prodidx_r);
1957 * Set up the tx ring. Note: for the Tigon 2, we have the option
1958 * of putting the transmit ring in the host's address space and
1959 * letting the chip DMA it instead of leaving the ring in the NIC's
1960 * memory and accessing it through the shared memory region. We
1961 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1962 * so we have to revert to the shared memory scheme if we detect
1965 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1966 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1967 sc->ti_rdata->ti_tx_ring_nic =
1968 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1970 bzero((char *)sc->ti_rdata->ti_tx_ring,
1971 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1972 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1973 if (sc->ti_hwrev == TI_HWREV_TIGON)
1976 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1977 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1978 if (sc->ti_ifp->if_hwassist)
1979 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1980 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1981 rcb->ti_max_len = TI_TX_RING_CNT;
1982 if (sc->ti_hwrev == TI_HWREV_TIGON)
1983 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1985 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring);
1986 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1987 rdphys + TI_RD_OFF(ti_tx_considx_r);
1989 /* Set up tuneables */
1991 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1992 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1993 (sc->ti_rx_coal_ticks / 10));
1996 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1997 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1998 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1999 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2000 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2001 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2003 /* Turn interrupts on. */
2004 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2005 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2008 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2014 ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2016 struct ti_softc *sc;
2019 if (error || nseg != 1)
2023 * All of the Tigon data structures need to live at <4GB. This
2024 * cast is fine since busdma was told about this constraint.
2026 sc->ti_rdata_phys = (uint32_t)segs[0].ds_addr;
2031 * Probe for a Tigon chip. Check the PCI vendor and device IDs
2032 * against our list and return its name if we find a match.
2042 while (t->ti_name != NULL) {
2043 if ((pci_get_vendor(dev) == t->ti_vid) &&
2044 (pci_get_device(dev) == t->ti_did)) {
2045 device_set_desc(dev, t->ti_name);
2046 return (BUS_PROBE_DEFAULT);
2059 struct ti_softc *sc;
2060 int unit, error = 0, rid;
2063 sc = device_get_softc(dev);
2064 unit = device_get_unit(dev);
2066 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2067 MTX_DEF | MTX_RECURSE);
2068 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2069 sc->ti_ifp->if_capabilities = IFCAP_HWCSUM |
2070 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2071 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities;
2074 * Map control/status registers.
2076 pci_enable_busmaster(dev);
2079 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2080 RF_ACTIVE|PCI_RF_DENSE);
2082 if (sc->ti_res == NULL) {
2083 printf ("ti%d: couldn't map memory\n", unit);
2088 sc->ti_btag = rman_get_bustag(sc->ti_res);
2089 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2090 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
2092 /* Allocate interrupt */
2095 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2096 RF_SHAREABLE | RF_ACTIVE);
2098 if (sc->ti_irq == NULL) {
2099 printf("ti%d: couldn't map interrupt\n", unit);
2106 if (ti_chipinit(sc)) {
2107 printf("ti%d: chip initialization failed\n", sc->ti_unit);
2112 /* Zero out the NIC's on-board SRAM. */
2113 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2115 /* Init again -- zeroing memory may have clobbered some registers. */
2116 if (ti_chipinit(sc)) {
2117 printf("ti%d: chip initialization failed\n", sc->ti_unit);
2123 * Get station address from the EEPROM. Note: the manual states
2124 * that the MAC address is at offset 0x8c, however the data is
2125 * stored as two longwords (since that's how it's loaded into
2126 * the NIC). This means the MAC address is actually preceded
2127 * by two zero bytes. We need to skip over those.
2129 if (ti_read_eeprom(sc, eaddr,
2130 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2131 printf("ti%d: failed to read station address\n", unit);
2136 /* Allocate the general information block and ring buffers. */
2137 if (bus_dma_tag_create(NULL, /* parent */
2138 1, 0, /* algnmnt, boundary */
2139 BUS_SPACE_MAXADDR, /* lowaddr */
2140 BUS_SPACE_MAXADDR, /* highaddr */
2141 NULL, NULL, /* filter, filterarg */
2142 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
2144 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
2146 NULL, NULL, /* lockfunc, lockarg */
2147 &sc->ti_parent_dmat) != 0) {
2148 printf("ti%d: Failed to allocate parent dmat\n", sc->ti_unit);
2153 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2154 PAGE_SIZE, 0, /* algnmnt, boundary */
2155 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
2156 BUS_SPACE_MAXADDR, /* highaddr */
2157 NULL, NULL, /* filter, filterarg */
2158 sizeof(struct ti_ring_data), /* maxsize */
2160 sizeof(struct ti_ring_data), /* maxsegsize */
2162 NULL, NULL, /* lockfunc, lockarg */
2163 &sc->ti_rdata_dmat) != 0) {
2164 printf("ti%d: Failed to allocate rdata dmat\n", sc->ti_unit);
2169 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata,
2170 BUS_DMA_NOWAIT, &sc->ti_rdata_dmamap) != 0) {
2171 printf("ti%d: Failed to allocate rdata memory\n", sc->ti_unit);
2176 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2177 sc->ti_rdata, sizeof(struct ti_ring_data),
2178 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) {
2179 printf("ti%d: Failed to load rdata segments\n", sc->ti_unit);
2184 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
2186 /* Try to allocate memory for jumbo buffers. */
2187 #ifdef TI_PRIVATE_JUMBOS
2188 if (ti_alloc_jumbo_mem(sc)) {
2189 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
2196 * We really need a better way to tell a 1000baseTX card
2197 * from a 1000baseSX one, since in theory there could be
2198 * OEMed 1000baseTX cards from lame vendors who aren't
2199 * clever enough to change the PCI ID. For the moment
2200 * though, the AceNIC is the only copper card available.
2202 if (pci_get_vendor(dev) == ALT_VENDORID &&
2203 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2205 /* Ok, it's not the only copper card available. */
2206 if (pci_get_vendor(dev) == NG_VENDORID &&
2207 pci_get_device(dev) == NG_DEVICEID_GA620T)
2210 /* Set default tuneable values. */
2211 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
2213 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
2215 sc->ti_rx_coal_ticks = 170;
2216 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
2217 sc->ti_rx_max_coal_bds = 64;
2219 sc->ti_tx_max_coal_bds = 128;
2221 sc->ti_tx_max_coal_bds = 32;
2222 sc->ti_tx_buf_ratio = 21;
2224 /* Set up ifnet structure */
2225 ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
2227 printf("ti%d: can not if_alloc()\n", sc->ti_unit);
2232 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2233 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
2236 ifp->if_ioctl = ti_ioctl;
2237 ifp->if_start = ti_start;
2238 ifp->if_watchdog = ti_watchdog;
2239 ifp->if_init = ti_init;
2240 ifp->if_mtu = ETHERMTU;
2241 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
2243 /* Set up ifmedia support. */
2244 if (sc->ti_copper) {
2246 * Copper cards allow manual 10/100 mode selection,
2247 * but not manual 1000baseTX mode selection. Why?
2248 * Becuase currently there's no way to specify the
2249 * master/slave setting through the firmware interface,
2250 * so Alteon decided to just bag it and handle it
2251 * via autonegotiation.
2253 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2254 ifmedia_add(&sc->ifmedia,
2255 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2256 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2257 ifmedia_add(&sc->ifmedia,
2258 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2259 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2260 ifmedia_add(&sc->ifmedia,
2261 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2263 /* Fiber cards don't support 10/100 modes. */
2264 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2265 ifmedia_add(&sc->ifmedia,
2266 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2268 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2269 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2272 * We're assuming here that card initialization is a sequential
2273 * thing. If it isn't, multiple cards probing at the same time
2274 * could stomp on the list of softcs here.
2277 /* Register the device */
2278 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR,
2279 0600, "ti%d", sc->ti_unit);
2280 sc->dev->si_drv1 = sc;
2283 * Call MI attach routine.
2285 ether_ifattach(ifp, eaddr);
2287 /* Hook interrupt last to avoid having to lock softc */
2288 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
2289 ti_intr, sc, &sc->ti_intrhand);
2292 printf("ti%d: couldn't set up irq\n", unit);
2293 ether_ifdetach(ifp);
2306 * Shutdown hardware and free up resources. This can be called any
2307 * time after the mutex has been initialized. It is called in both
2308 * the error case in attach and the normal detach case so it needs
2309 * to be careful about only freeing resources that have actually been
2316 struct ti_softc *sc;
2319 sc = device_get_softc(dev);
2321 destroy_dev(sc->dev);
2322 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2326 /* These should only be active if attach succeeded */
2327 if (device_is_attached(dev)) {
2329 ether_ifdetach(ifp);
2331 bus_generic_detach(dev);
2333 ifmedia_removeall(&sc->ifmedia);
2336 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata,
2337 sc->ti_rdata_dmamap);
2338 if (sc->ti_rdata_dmat)
2339 bus_dma_tag_destroy(sc->ti_rdata_dmat);
2340 if (sc->ti_parent_dmat)
2341 bus_dma_tag_destroy(sc->ti_parent_dmat);
2342 if (sc->ti_intrhand)
2343 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2345 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2347 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM,
2351 #ifdef TI_PRIVATE_JUMBOS
2352 if (sc->ti_cdata.ti_jumbo_buf)
2353 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
2356 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
2359 mtx_destroy(&sc->ti_mtx);
2364 #ifdef TI_JUMBO_HDRSPLIT
2366 * If hdr_len is 0, that means that header splitting wasn't done on
2367 * this packet for some reason. The two most likely reasons are that
2368 * the protocol isn't a supported protocol for splitting, or this
2369 * packet had a fragment offset that wasn't 0.
2371 * The header length, if it is non-zero, will always be the length of
2372 * the headers on the packet, but that length could be longer than the
2373 * first mbuf. So we take the minimum of the two as the actual
2376 static __inline void
2377 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2380 int lengths[4] = {0, 0, 0, 0};
2381 struct mbuf *m, *mp;
2384 top->m_len = min(hdr_len, top->m_len);
2385 pkt_len -= top->m_len;
2386 lengths[i++] = top->m_len;
2389 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2390 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2391 pkt_len -= m->m_len;
2392 lengths[i++] = m->m_len;
2398 printf("got split packet: ");
2400 printf("got non-split packet: ");
2402 printf("%d,%d,%d,%d = %d\n", lengths[0],
2403 lengths[1], lengths[2], lengths[3],
2404 lengths[0] + lengths[1] + lengths[2] +
2409 panic("header splitting didn't");
2416 if (mp->m_next != NULL)
2417 panic("ti_hdr_split: last mbuf in chain should be null");
2419 #endif /* TI_JUMBO_HDRSPLIT */
2422 * Frame reception handling. This is called if there's a frame
2423 * on the receive return list.
2425 * Note: we have to be able to handle three possibilities here:
2426 * 1) the frame is from the mini receive ring (can only happen)
2427 * on Tigon 2 boards)
2428 * 2) the frame is from the jumbo recieve ring
2429 * 3) the frame is from the standard receive ring
2434 struct ti_softc *sc;
2437 struct ti_cmd_desc cmd;
2443 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2444 struct ti_rx_desc *cur_rx;
2446 struct mbuf *m = NULL;
2447 u_int16_t vlan_tag = 0;
2451 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
2452 rxidx = cur_rx->ti_idx;
2453 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2455 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2457 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
2460 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2462 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2463 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2464 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2465 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2467 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2470 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2472 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2475 #ifdef TI_PRIVATE_JUMBOS
2476 m->m_len = cur_rx->ti_len;
2477 #else /* TI_PRIVATE_JUMBOS */
2478 #ifdef TI_JUMBO_HDRSPLIT
2479 if (sc->ti_hdrsplit)
2480 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2481 cur_rx->ti_len, rxidx);
2483 #endif /* TI_JUMBO_HDRSPLIT */
2484 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len);
2485 #endif /* TI_PRIVATE_JUMBOS */
2486 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2487 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2488 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2489 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
2490 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2492 ti_newbuf_mini(sc, sc->ti_mini, m);
2495 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
2497 ti_newbuf_mini(sc, sc->ti_mini, m);
2500 m->m_len = cur_rx->ti_len;
2502 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2503 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2504 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
2505 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2507 ti_newbuf_std(sc, sc->ti_std, m);
2510 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
2512 ti_newbuf_std(sc, sc->ti_std, m);
2515 m->m_len = cur_rx->ti_len;
2518 m->m_pkthdr.len = cur_rx->ti_len;
2520 m->m_pkthdr.rcvif = ifp;
2522 if (ifp->if_hwassist) {
2523 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
2525 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2526 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2527 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
2531 * If we received a packet with a vlan tag,
2532 * tag it before passing the packet upward.
2535 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue);
2537 (*ifp->if_input)(ifp, m);
2541 /* Only necessary on the Tigon 1. */
2542 if (sc->ti_hwrev == TI_HWREV_TIGON)
2543 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2544 sc->ti_rx_saved_considx);
2546 TI_UPDATE_STDPROD(sc, sc->ti_std);
2547 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2548 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2553 struct ti_softc *sc;
2555 struct ti_tx_desc *cur_tx = NULL;
2561 * Go through our tx ring and free mbufs for those
2562 * frames that have been sent.
2564 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
2567 idx = sc->ti_tx_saved_considx;
2568 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2570 CSR_WRITE_4(sc, TI_WINBASE,
2571 TI_TX_RING_BASE + 6144);
2573 CSR_WRITE_4(sc, TI_WINBASE,
2574 TI_TX_RING_BASE + 4096);
2576 CSR_WRITE_4(sc, TI_WINBASE,
2577 TI_TX_RING_BASE + 2048);
2579 CSR_WRITE_4(sc, TI_WINBASE,
2581 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
2583 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
2584 if (cur_tx->ti_flags & TI_BDFLAG_END)
2586 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
2587 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
2588 sc->ti_cdata.ti_tx_chain[idx] = NULL;
2591 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
2596 ifp->if_flags &= ~IFF_OACTIVE;
2603 struct ti_softc *sc;
2611 /* Avoid this for now -- checking this register is expensive. */
2612 /* Make sure this is really our interrupt. */
2613 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2619 /* Ack interrupt and stop others from occuring. */
2620 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2622 if (ifp->if_flags & IFF_RUNNING) {
2623 /* Check RX return ring producer/consumer */
2626 /* Check TX ring producer/consumer */
2630 ti_handle_events(sc);
2632 /* Re-enable interrupts. */
2633 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2635 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
2643 struct ti_softc *sc;
2649 ifp->if_collisions +=
2650 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2651 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2652 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2653 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2658 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2659 * pointers to descriptors.
2662 ti_encap(sc, m_head, txidx)
2663 struct ti_softc *sc;
2664 struct mbuf *m_head;
2667 struct ti_tx_desc *f = NULL;
2669 u_int32_t frag, cur, cnt = 0;
2670 u_int16_t csum_flags = 0;
2674 cur = frag = *txidx;
2676 if (m_head->m_pkthdr.csum_flags) {
2677 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2678 csum_flags |= TI_BDFLAG_IP_CKSUM;
2679 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2680 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2681 if (m_head->m_flags & M_LASTFRAG)
2682 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2683 else if (m_head->m_flags & M_FRAG)
2684 csum_flags |= TI_BDFLAG_IP_FRAG;
2687 mtag = VLAN_OUTPUT_TAG(sc->ti_ifp, m);
2690 * Start packing the mbufs in this chain into
2691 * the fragment pointers. Stop when we run out
2692 * of fragments or hit the end of the mbuf chain.
2694 for (m = m_head; m != NULL; m = m->m_next) {
2695 if (m->m_len != 0) {
2696 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2698 CSR_WRITE_4(sc, TI_WINBASE,
2699 TI_TX_RING_BASE + 6144);
2700 else if (frag > 255)
2701 CSR_WRITE_4(sc, TI_WINBASE,
2702 TI_TX_RING_BASE + 4096);
2703 else if (frag > 127)
2704 CSR_WRITE_4(sc, TI_WINBASE,
2705 TI_TX_RING_BASE + 2048);
2707 CSR_WRITE_4(sc, TI_WINBASE,
2709 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
2711 f = &sc->ti_rdata->ti_tx_ring[frag];
2712 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2714 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
2715 f->ti_len = m->m_len;
2716 f->ti_flags = csum_flags;
2719 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2720 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff;
2726 * Sanity check: avoid coming within 16 descriptors
2727 * of the end of the ring.
2729 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2732 TI_INC(frag, TI_TX_RING_CNT);
2740 if (frag == sc->ti_tx_saved_considx)
2743 if (sc->ti_hwrev == TI_HWREV_TIGON)
2744 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2747 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2748 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2749 sc->ti_txcnt += cnt;
2757 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2758 * to the mbuf data regions directly in the transmit descriptors.
2764 struct ti_softc *sc;
2765 struct mbuf *m_head = NULL;
2766 u_int32_t prodidx = 0;
2771 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2773 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2774 IF_DEQUEUE(&ifp->if_snd, m_head);
2780 * safety overkill. If this is a fragmented packet chain
2781 * with delayed TCP/UDP checksums, then only encapsulate
2782 * it if we have enough descriptors to handle the entire
2784 * (paranoia -- may not actually be needed)
2786 if (m_head->m_flags & M_FIRSTFRAG &&
2787 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2788 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
2789 m_head->m_pkthdr.csum_data + 16) {
2790 IF_PREPEND(&ifp->if_snd, m_head);
2791 ifp->if_flags |= IFF_OACTIVE;
2797 * Pack the data into the transmit ring. If we
2798 * don't have room, set the OACTIVE flag and wait
2799 * for the NIC to drain the ring.
2801 if (ti_encap(sc, m_head, &prodidx)) {
2802 IF_PREPEND(&ifp->if_snd, m_head);
2803 ifp->if_flags |= IFF_OACTIVE;
2808 * If there's a BPF listener, bounce a copy of this frame
2811 BPF_MTAP(ifp, m_head);
2815 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2818 * Set a timeout in case the chip goes out to lunch.
2828 struct ti_softc *sc = xsc;
2830 /* Cancel pending I/O and flush buffers. */
2834 /* Init the gen info block, ring control blocks and firmware. */
2835 if (ti_gibinit(sc)) {
2836 printf("ti%d: initialization failure\n", sc->ti_unit);
2844 static void ti_init2(sc)
2845 struct ti_softc *sc;
2847 struct ti_cmd_desc cmd;
2850 struct ifmedia *ifm;
2855 /* Specify MTU and interface index. */
2856 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit);
2857 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2858 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
2859 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2861 /* Load our MAC address. */
2862 m = (u_int16_t *)&IFP2ENADDR(sc->ti_ifp)[0];
2863 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2864 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2865 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2867 /* Enable or disable promiscuous mode as needed. */
2868 if (ifp->if_flags & IFF_PROMISC) {
2869 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2871 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2874 /* Program multicast filter. */
2878 * If this is a Tigon 1, we should tell the
2879 * firmware to use software packet filtering.
2881 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2882 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2886 ti_init_rx_ring_std(sc);
2888 /* Init jumbo RX ring. */
2889 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2890 ti_init_rx_ring_jumbo(sc);
2893 * If this is a Tigon 2, we can also configure the
2896 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2897 ti_init_rx_ring_mini(sc);
2899 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2900 sc->ti_rx_saved_considx = 0;
2903 ti_init_tx_ring(sc);
2905 /* Tell firmware we're alive. */
2906 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2908 /* Enable host interrupts. */
2909 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2911 ifp->if_flags |= IFF_RUNNING;
2912 ifp->if_flags &= ~IFF_OACTIVE;
2915 * Make sure to set media properly. We have to do this
2916 * here since we have to issue commands in order to set
2917 * the link negotiation and we can't issue commands until
2918 * the firmware is running.
2921 tmp = ifm->ifm_media;
2922 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2923 ti_ifmedia_upd(ifp);
2924 ifm->ifm_media = tmp;
2928 * Set media options.
2934 struct ti_softc *sc;
2935 struct ifmedia *ifm;
2936 struct ti_cmd_desc cmd;
2942 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2947 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2950 * Transmit flow control doesn't work on the Tigon 1.
2952 flowctl = TI_GLNK_RX_FLOWCTL_Y;
2955 * Transmit flow control can also cause problems on the
2956 * Tigon 2, apparantly with both the copper and fiber
2957 * boards. The symptom is that the interface will just
2958 * hang. This was reproduced with Alteon 180 switches.
2961 if (sc->ti_hwrev != TI_HWREV_TIGON)
2962 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
2965 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2966 TI_GLNK_FULL_DUPLEX| flowctl |
2967 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
2969 flowctl = TI_LNK_RX_FLOWCTL_Y;
2971 if (sc->ti_hwrev != TI_HWREV_TIGON)
2972 flowctl |= TI_LNK_TX_FLOWCTL_Y;
2975 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2976 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
2977 TI_LNK_AUTONEGENB|TI_LNK_ENB);
2978 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2979 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2983 flowctl = TI_GLNK_RX_FLOWCTL_Y;
2985 if (sc->ti_hwrev != TI_HWREV_TIGON)
2986 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
2989 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2990 flowctl |TI_GLNK_ENB);
2991 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2992 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2993 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2995 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2996 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3002 flowctl = TI_LNK_RX_FLOWCTL_Y;
3004 if (sc->ti_hwrev != TI_HWREV_TIGON)
3005 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3008 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3009 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3010 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3011 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3012 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3014 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3016 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3017 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3019 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3021 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3022 TI_CMD_CODE_NEGOTIATE_10_100, 0);
3030 * Report current media status.
3033 ti_ifmedia_sts(ifp, ifmr)
3035 struct ifmediareq *ifmr;
3037 struct ti_softc *sc;
3038 u_int32_t media = 0;
3042 ifmr->ifm_status = IFM_AVALID;
3043 ifmr->ifm_active = IFM_ETHER;
3045 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
3048 ifmr->ifm_status |= IFM_ACTIVE;
3050 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3051 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3053 ifmr->ifm_active |= IFM_1000_T;
3055 ifmr->ifm_active |= IFM_1000_SX;
3056 if (media & TI_GLNK_FULL_DUPLEX)
3057 ifmr->ifm_active |= IFM_FDX;
3059 ifmr->ifm_active |= IFM_HDX;
3060 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3061 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3062 if (sc->ti_copper) {
3063 if (media & TI_LNK_100MB)
3064 ifmr->ifm_active |= IFM_100_TX;
3065 if (media & TI_LNK_10MB)
3066 ifmr->ifm_active |= IFM_10_T;
3068 if (media & TI_LNK_100MB)
3069 ifmr->ifm_active |= IFM_100_FX;
3070 if (media & TI_LNK_10MB)
3071 ifmr->ifm_active |= IFM_10_FL;
3073 if (media & TI_LNK_FULL_DUPLEX)
3074 ifmr->ifm_active |= IFM_FDX;
3075 if (media & TI_LNK_HALF_DUPLEX)
3076 ifmr->ifm_active |= IFM_HDX;
3081 ti_ioctl(ifp, command, data)
3086 struct ti_softc *sc = ifp->if_softc;
3087 struct ifreq *ifr = (struct ifreq *) data;
3088 int mask, error = 0;
3089 struct ti_cmd_desc cmd;
3095 if (ifr->ifr_mtu > TI_JUMBO_MTU)
3098 ifp->if_mtu = ifr->ifr_mtu;
3103 if (ifp->if_flags & IFF_UP) {
3105 * If only the state of the PROMISC flag changed,
3106 * then just use the 'set promisc mode' command
3107 * instead of reinitializing the entire NIC. Doing
3108 * a full re-init means reloading the firmware and
3109 * waiting for it to start up, which may take a
3112 if (ifp->if_flags & IFF_RUNNING &&
3113 ifp->if_flags & IFF_PROMISC &&
3114 !(sc->ti_if_flags & IFF_PROMISC)) {
3115 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3116 TI_CMD_CODE_PROMISC_ENB, 0);
3117 } else if (ifp->if_flags & IFF_RUNNING &&
3118 !(ifp->if_flags & IFF_PROMISC) &&
3119 sc->ti_if_flags & IFF_PROMISC) {
3120 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3121 TI_CMD_CODE_PROMISC_DIS, 0);
3125 if (ifp->if_flags & IFF_RUNNING) {
3129 sc->ti_if_flags = ifp->if_flags;
3134 if (ifp->if_flags & IFF_RUNNING) {
3141 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3144 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3145 if (mask & IFCAP_HWCSUM) {
3146 if (IFCAP_HWCSUM & ifp->if_capenable)
3147 ifp->if_capenable &= ~IFCAP_HWCSUM;
3149 ifp->if_capenable |= IFCAP_HWCSUM;
3150 if (ifp->if_flags & IFF_RUNNING)
3156 error = ether_ioctl(ifp, command, data);
3166 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3168 struct ti_softc *sc;
3175 sc->ti_flags |= TI_FLAG_DEBUGING;
3182 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3184 struct ti_softc *sc;
3191 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3198 * This ioctl routine goes along with the Tigon character device.
3201 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, struct thread *td)
3204 struct ti_softc *sc;
3215 struct ti_stats *outstats;
3217 outstats = (struct ti_stats *)addr;
3219 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats,
3220 sizeof(struct ti_stats));
3223 case TIIOCGETPARAMS:
3225 struct ti_params *params;
3227 params = (struct ti_params *)addr;
3229 params->ti_stat_ticks = sc->ti_stat_ticks;
3230 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3231 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3232 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3233 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3234 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3235 params->param_mask = TI_PARAM_ALL;
3241 case TIIOCSETPARAMS:
3243 struct ti_params *params;
3245 params = (struct ti_params *)addr;
3247 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3248 sc->ti_stat_ticks = params->ti_stat_ticks;
3249 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3252 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3253 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3254 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3255 sc->ti_rx_coal_ticks);
3258 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3259 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3260 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3261 sc->ti_tx_coal_ticks);
3264 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3265 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3266 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3267 sc->ti_rx_max_coal_bds);
3270 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3271 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3272 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3273 sc->ti_tx_max_coal_bds);
3276 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3277 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3278 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3279 sc->ti_tx_buf_ratio);
3286 case TIIOCSETTRACE: {
3287 ti_trace_type trace_type;
3289 trace_type = *(ti_trace_type *)addr;
3292 * Set tracing to whatever the user asked for. Setting
3293 * this register to 0 should have the effect of disabling
3296 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3302 case TIIOCGETTRACE: {
3303 struct ti_trace_buf *trace_buf;
3304 u_int32_t trace_start, cur_trace_ptr, trace_len;
3306 trace_buf = (struct ti_trace_buf *)addr;
3308 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3309 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3310 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3313 printf("ti%d: trace_start = %#x, cur_trace_ptr = %#x, "
3314 "trace_len = %d\n", sc->ti_unit, trace_start,
3315 cur_trace_ptr, trace_len);
3316 printf("ti%d: trace_buf->buf_len = %d\n", sc->ti_unit,
3317 trace_buf->buf_len);
3320 error = ti_copy_mem(sc, trace_start, min(trace_len,
3321 trace_buf->buf_len),
3322 (caddr_t)trace_buf->buf, 1, 1);
3325 trace_buf->fill_len = min(trace_len,
3326 trace_buf->buf_len);
3327 if (cur_trace_ptr < trace_start)
3328 trace_buf->cur_trace_ptr =
3329 trace_start - cur_trace_ptr;
3331 trace_buf->cur_trace_ptr =
3332 cur_trace_ptr - trace_start;
3334 trace_buf->fill_len = 0;
3340 * For debugging, five ioctls are needed:
3349 * From what I can tell, Alteon's Solaris Tigon driver
3350 * only has one character device, so you have to attach
3351 * to the Tigon board you're interested in. This seems
3352 * like a not-so-good way to do things, since unless you
3353 * subsequently specify the unit number of the device
3354 * you're interested in in every ioctl, you'll only be
3355 * able to debug one board at a time.
3359 case ALT_READ_TG_MEM:
3360 case ALT_WRITE_TG_MEM:
3362 struct tg_mem *mem_param;
3363 u_int32_t sram_end, scratch_end;
3365 mem_param = (struct tg_mem *)addr;
3367 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3368 sram_end = TI_END_SRAM_I;
3369 scratch_end = TI_END_SCRATCH_I;
3371 sram_end = TI_END_SRAM_II;
3372 scratch_end = TI_END_SCRATCH_II;
3376 * For now, we'll only handle accessing regular SRAM,
3379 if ((mem_param->tgAddr >= TI_BEG_SRAM)
3380 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) {
3382 * In this instance, we always copy to/from user
3383 * space, so the user space argument is set to 1.
3385 error = ti_copy_mem(sc, mem_param->tgAddr,
3387 mem_param->userAddr, 1,
3388 (cmd == ALT_READ_TG_MEM) ? 1 : 0);
3389 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH)
3390 && (mem_param->tgAddr <= scratch_end)) {
3391 error = ti_copy_scratch(sc, mem_param->tgAddr,
3393 mem_param->userAddr, 1,
3394 (cmd == ALT_READ_TG_MEM) ?
3395 1 : 0, TI_PROCESSOR_A);
3396 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG)
3397 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) {
3398 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3399 printf("ti%d: invalid memory range for "
3400 "Tigon I\n", sc->ti_unit);
3404 error = ti_copy_scratch(sc, mem_param->tgAddr -
3405 TI_SCRATCH_DEBUG_OFF,
3407 mem_param->userAddr, 1,
3408 (cmd == ALT_READ_TG_MEM) ?
3409 1 : 0, TI_PROCESSOR_B);
3411 printf("ti%d: memory address %#x len %d is out of "
3412 "supported range\n", sc->ti_unit,
3413 mem_param->tgAddr, mem_param->len);
3419 case ALT_READ_TG_REG:
3420 case ALT_WRITE_TG_REG:
3422 struct tg_reg *regs;
3425 regs = (struct tg_reg *)addr;
3428 * Make sure the address in question isn't out of range.
3430 if (regs->addr > TI_REG_MAX) {
3434 if (cmd == ALT_READ_TG_REG) {
3435 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3436 regs->addr, &tmpval, 1);
3437 regs->data = ntohl(tmpval);
3439 if ((regs->addr == TI_CPU_STATE)
3440 || (regs->addr == TI_CPU_CTL_B)) {
3441 printf("ti%d: register %#x = %#x\n",
3442 sc->ti_unit, regs->addr, tmpval);
3446 tmpval = htonl(regs->data);
3447 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3448 regs->addr, &tmpval, 1);
3464 struct ti_softc *sc;
3470 * When we're debugging, the chip is often stopped for long periods
3471 * of time, and that would normally cause the watchdog timer to fire.
3472 * Since that impedes debugging, we don't want to do that.
3474 if (sc->ti_flags & TI_FLAG_DEBUGING) {
3479 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
3488 * Stop the adapter and free any mbufs allocated to the
3493 struct ti_softc *sc;
3496 struct ti_cmd_desc cmd;
3502 /* Disable host interrupts. */
3503 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3505 * Tell firmware we're shutting down.
3507 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3509 /* Halt and reinitialize. */
3511 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
3514 /* Free the RX lists. */
3515 ti_free_rx_ring_std(sc);
3517 /* Free jumbo RX list. */
3518 ti_free_rx_ring_jumbo(sc);
3520 /* Free mini RX list. */
3521 ti_free_rx_ring_mini(sc);
3523 /* Free TX buffers. */
3524 ti_free_tx_ring(sc);
3526 sc->ti_ev_prodidx.ti_idx = 0;
3527 sc->ti_return_prodidx.ti_idx = 0;
3528 sc->ti_tx_considx.ti_idx = 0;
3529 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3531 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3536 * Stop all chip I/O so that the kernel's probe routines don't
3537 * get confused by errant DMAs when rebooting.
3543 struct ti_softc *sc;
3545 sc = device_get_softc(dev);