2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
37 * Manuals, sample driver and firmware source kits are available
38 * from http://www.alteon.com/support/openkits.
40 * Written by Bill Paul <wpaul@ctr.columbia.edu>
41 * Electrical Engineering Department
42 * Columbia University, New York City
46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
50 * filtering and jumbo (9014 byte) frames. The hardware is largely
51 * controlled by firmware, which must be loaded into the NIC during
54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
55 * revision, which supports new features such as extended commands,
56 * extended jumbo receive ring desciptors and a mini receive ring.
58 * Alteon Networks is to be commended for releasing such a vast amount
59 * of development material for the Tigon NIC without requiring an NDA
60 * (although they really should have done it a long time ago). With
61 * any luck, the other vendors will finally wise up and follow Alteon's
64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
65 * this driver by #including it as a C header file. This bloats the
66 * driver somewhat, but it's the easiest method considering that the
67 * driver code and firmware code need to be kept in sync. The source
68 * for the firmware is not provided with the FreeBSD distribution since
69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
71 * The following people deserve special thanks:
72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
74 * - Raymond Lee of Netgear, for providing a pair of Netgear
75 * GA620 Tigon 2 boards for testing
76 * - Ulf Zimmermann, for bringing the GA260 to my attention and
77 * convincing me to write this driver.
78 * - Andrew Gallatin for providing FreeBSD/Alpha support.
81 #include <sys/cdefs.h>
82 __FBSDID("$FreeBSD$");
86 #include <sys/param.h>
87 #include <sys/systm.h>
88 #include <sys/sockio.h>
90 #include <sys/malloc.h>
91 #include <sys/kernel.h>
92 #include <sys/module.h>
93 #include <sys/socket.h>
94 #include <sys/queue.h>
96 #include <sys/sf_buf.h>
99 #include <net/if_var.h>
100 #include <net/if_arp.h>
101 #include <net/ethernet.h>
102 #include <net/if_dl.h>
103 #include <net/if_media.h>
104 #include <net/if_types.h>
105 #include <net/if_vlan_var.h>
109 #include <netinet/in_systm.h>
110 #include <netinet/in.h>
111 #include <netinet/ip.h>
113 #include <machine/bus.h>
114 #include <machine/resource.h>
116 #include <sys/rman.h>
118 #ifdef TI_SF_BUF_JUMBO
120 #include <vm/vm_page.h>
123 #include <dev/pci/pcireg.h>
124 #include <dev/pci/pcivar.h>
126 #include <sys/tiio.h>
127 #include <dev/ti/if_tireg.h>
128 #include <dev/ti/ti_fw.h>
129 #include <dev/ti/ti_fw2.h>
131 #include <sys/sysctl.h>
133 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
135 * We can only turn on header splitting if we're using extended receive
138 #if defined(TI_JUMBO_HDRSPLIT) && !defined(TI_SF_BUF_JUMBO)
139 #error "options TI_JUMBO_HDRSPLIT requires TI_SF_BUF_JUMBO"
140 #endif /* TI_JUMBO_HDRSPLIT && !TI_SF_BUF_JUMBO */
148 * Various supported device vendors/types and their names.
151 static const struct ti_type ti_devs[] = {
152 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
153 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
154 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
155 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
156 { TC_VENDORID, TC_DEVICEID_3C985,
157 "3Com 3c985-SX Gigabit Ethernet" },
158 { NG_VENDORID, NG_DEVICEID_GA620,
159 "Netgear GA620 1000baseSX Gigabit Ethernet" },
160 { NG_VENDORID, NG_DEVICEID_GA620T,
161 "Netgear GA620 1000baseT Gigabit Ethernet" },
162 { SGI_VENDORID, SGI_DEVICEID_TIGON,
163 "Silicon Graphics Gigabit Ethernet" },
164 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
165 "Farallon PN9000SX Gigabit Ethernet" },
170 static d_open_t ti_open;
171 static d_close_t ti_close;
172 static d_ioctl_t ti_ioctl2;
174 static struct cdevsw ti_cdevsw = {
175 .d_version = D_VERSION,
179 .d_ioctl = ti_ioctl2,
183 static int ti_probe(device_t);
184 static int ti_attach(device_t);
185 static int ti_detach(device_t);
186 static void ti_txeof(struct ti_softc *);
187 static void ti_rxeof(struct ti_softc *);
189 static int ti_encap(struct ti_softc *, struct mbuf **);
191 static void ti_intr(void *);
192 static void ti_start(struct ifnet *);
193 static void ti_start_locked(struct ifnet *);
194 static int ti_ioctl(struct ifnet *, u_long, caddr_t);
195 static uint64_t ti_get_counter(struct ifnet *, ift_counter);
196 static void ti_init(void *);
197 static void ti_init_locked(void *);
198 static void ti_init2(struct ti_softc *);
199 static void ti_stop(struct ti_softc *);
200 static void ti_watchdog(void *);
201 static int ti_shutdown(device_t);
202 static int ti_ifmedia_upd(struct ifnet *);
203 static int ti_ifmedia_upd_locked(struct ti_softc *);
204 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
206 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
207 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
208 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
210 static u_int ti_add_mcast(void *, struct sockaddr_dl *, u_int);
211 static u_int ti_del_mcast(void *, struct sockaddr_dl *, u_int);
212 static void ti_setmulti(struct ti_softc *);
214 static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *);
215 static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *);
216 static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t);
217 static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int,
219 static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t,
221 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
222 static void ti_loadfw(struct ti_softc *);
223 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
224 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
225 static void ti_handle_events(struct ti_softc *);
226 static void ti_dma_map_addr(void *, bus_dma_segment_t *, int, int);
227 static int ti_dma_alloc(struct ti_softc *);
228 static void ti_dma_free(struct ti_softc *);
229 static int ti_dma_ring_alloc(struct ti_softc *, bus_size_t, bus_size_t,
230 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
231 static void ti_dma_ring_free(struct ti_softc *, bus_dma_tag_t *, uint8_t **,
232 bus_dmamap_t, bus_addr_t *);
233 static int ti_newbuf_std(struct ti_softc *, int);
234 static int ti_newbuf_mini(struct ti_softc *, int);
235 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
236 static int ti_init_rx_ring_std(struct ti_softc *);
237 static void ti_free_rx_ring_std(struct ti_softc *);
238 static int ti_init_rx_ring_jumbo(struct ti_softc *);
239 static void ti_free_rx_ring_jumbo(struct ti_softc *);
240 static int ti_init_rx_ring_mini(struct ti_softc *);
241 static void ti_free_rx_ring_mini(struct ti_softc *);
242 static void ti_free_tx_ring(struct ti_softc *);
243 static int ti_init_tx_ring(struct ti_softc *);
244 static void ti_discard_std(struct ti_softc *, int);
245 #ifndef TI_SF_BUF_JUMBO
246 static void ti_discard_jumbo(struct ti_softc *, int);
248 static void ti_discard_mini(struct ti_softc *, int);
250 static int ti_64bitslot_war(struct ti_softc *);
251 static int ti_chipinit(struct ti_softc *);
252 static int ti_gibinit(struct ti_softc *);
254 #ifdef TI_JUMBO_HDRSPLIT
255 static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len,
257 #endif /* TI_JUMBO_HDRSPLIT */
259 static void ti_sysctl_node(struct ti_softc *);
261 static device_method_t ti_methods[] = {
262 /* Device interface */
263 DEVMETHOD(device_probe, ti_probe),
264 DEVMETHOD(device_attach, ti_attach),
265 DEVMETHOD(device_detach, ti_detach),
266 DEVMETHOD(device_shutdown, ti_shutdown),
270 static driver_t ti_driver = {
273 sizeof(struct ti_softc)
276 static devclass_t ti_devclass;
278 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
279 MODULE_DEPEND(ti, pci, 1, 1, 1);
280 MODULE_DEPEND(ti, ether, 1, 1, 1);
283 * Send an instruction or address to the EEPROM, check for ACK.
286 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
291 * Make sure we're in TX mode.
293 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
296 * Feed in each bit and stobe the clock.
298 for (i = 0x80; i; i >>= 1) {
300 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
302 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
305 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
307 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
313 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
318 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
319 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
320 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
326 * Read a byte of data stored in the EEPROM at address 'addr.'
327 * We have to send two address bytes since the EEPROM can hold
328 * more than 256 bytes of data.
331 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
339 * Send write control code to EEPROM.
341 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
342 device_printf(sc->ti_dev,
343 "failed to send write command, status: %x\n",
344 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
349 * Send first byte of address of byte we want to read.
351 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
352 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
353 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
357 * Send second byte address of byte we want to read.
359 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
360 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
361 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
368 * Send read control code to EEPROM.
370 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
371 device_printf(sc->ti_dev,
372 "failed to send read command, status: %x\n",
373 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
378 * Start reading bits from EEPROM.
380 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
381 for (i = 0x80; i; i >>= 1) {
382 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
384 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
386 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
393 * No ACK generated for read, so just return byte.
402 * Read a sequence of bytes from the EEPROM.
405 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
410 for (i = 0; i < cnt; i++) {
411 err = ti_eeprom_getbyte(sc, off + i, &byte);
417 return (err ? 1 : 0);
421 * NIC memory read function.
422 * Can be used to copy data from NIC local memory.
425 ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
427 int segptr, segsize, cnt;
438 segsize = TI_WINLEN - (segptr % TI_WINLEN);
439 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN));
440 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
441 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
451 * NIC memory write function.
452 * Can be used to copy data into NIC local memory.
455 ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
457 int segptr, segsize, cnt;
468 segsize = TI_WINLEN - (segptr % TI_WINLEN);
469 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN));
470 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
471 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
480 * NIC memory read function.
481 * Can be used to clear a section of NIC local memory.
484 ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len)
486 int segptr, segsize, cnt;
495 segsize = TI_WINLEN - (segptr % TI_WINLEN);
496 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN));
497 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
498 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4);
505 ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
506 caddr_t buf, int useraddr, int readdata)
508 int segptr, segsize, cnt;
517 * At the moment, we don't handle non-aligned cases, we just bail.
518 * If this proves to be a problem, it will be fixed.
520 if (readdata == 0 && (tigon_addr & 0x3) != 0) {
521 device_printf(sc->ti_dev, "%s: tigon address %#x isn't "
522 "word-aligned\n", __func__, tigon_addr);
523 device_printf(sc->ti_dev, "%s: unaligned writes aren't "
524 "yet supported\n", __func__);
528 segptr = tigon_addr & ~0x3;
529 segresid = tigon_addr - segptr;
532 * This is the non-aligned amount left over that we'll need to
537 /* Add in the left over amount at the front of the buffer */
542 * If resid + segresid is >= 4, add multiples of 4 to the count and
543 * decrease the residual by that much.
546 resid -= resid & ~0x3;
553 * Save the old window base value.
555 origwin = CSR_READ_4(sc, TI_WINBASE);
558 bus_size_t ti_offset;
563 segsize = TI_WINLEN - (segptr % TI_WINLEN);
564 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN));
566 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
569 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
570 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2);
573 * Yeah, this is a little on the kludgy
574 * side, but at least this code is only
575 * used for debugging.
577 ti_bcopy_swap(sc->ti_membuf, sc->ti_membuf2,
578 segsize, TI_SWAP_NTOH);
582 copyout(&sc->ti_membuf2[segresid], ptr,
586 copyout(sc->ti_membuf2, ptr, segsize);
591 ti_bcopy_swap(sc->ti_membuf,
592 sc->ti_membuf2, segsize,
595 bcopy(&sc->ti_membuf2[segresid], ptr,
600 ti_bcopy_swap(sc->ti_membuf, ptr,
601 segsize, TI_SWAP_NTOH);
607 copyin(ptr, sc->ti_membuf2, segsize);
609 ti_bcopy_swap(sc->ti_membuf2, sc->ti_membuf,
610 segsize, TI_SWAP_HTON);
612 ti_bcopy_swap(ptr, sc->ti_membuf, segsize,
615 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
616 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2);
624 * Handle leftover, non-word-aligned bytes.
627 uint32_t tmpval, tmpval2;
628 bus_size_t ti_offset;
631 * Set the segment pointer.
633 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN));
635 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
638 * First, grab whatever is in our source/destination.
639 * We'll obviously need this for reads, but also for
640 * writes, since we'll be doing read/modify/write.
642 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
643 ti_offset, &tmpval, 1);
646 * Next, translate this from little-endian to big-endian
647 * (at least on i386 boxes).
649 tmpval2 = ntohl(tmpval);
653 * If we're reading, just copy the leftover number
654 * of bytes from the host byte order buffer to
659 copyout(&tmpval2, ptr, resid);
662 bcopy(&tmpval2, ptr, resid);
665 * If we're writing, first copy the bytes to be
666 * written into the network byte order buffer,
667 * leaving the rest of the buffer with whatever was
668 * originally in there. Then, swap the bytes
669 * around into host order and write them out.
671 * XXX KDM the read side of this has been verified
672 * to work, but the write side of it has not been
673 * verified. So user beware.
677 copyin(ptr, &tmpval2, resid);
680 bcopy(ptr, &tmpval2, resid);
682 tmpval = htonl(tmpval2);
684 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
685 ti_offset, &tmpval, 1);
689 CSR_WRITE_4(sc, TI_WINBASE, origwin);
695 ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
696 caddr_t buf, int useraddr, int readdata, int cpu)
700 uint32_t tmpval, tmpval2;
706 * At the moment, we don't handle non-aligned cases, we just bail.
707 * If this proves to be a problem, it will be fixed.
709 if (tigon_addr & 0x3) {
710 device_printf(sc->ti_dev, "%s: tigon address %#x "
711 "isn't word-aligned\n", __func__, tigon_addr);
716 device_printf(sc->ti_dev, "%s: transfer length %d "
717 "isn't word-aligned\n", __func__, len);
726 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
729 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
731 tmpval = ntohl(tmpval2);
734 * Note: I've used this debugging interface
735 * extensively with Alteon's 12.3.15 firmware,
736 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
738 * When you compile the firmware without
739 * optimization, which is necessary sometimes in
740 * order to properly step through it, you sometimes
741 * read out a bogus value of 0xc0017c instead of
742 * whatever was supposed to be in that scratchpad
743 * location. That value is on the stack somewhere,
744 * but I've never been able to figure out what was
745 * causing the problem.
747 * The address seems to pop up in random places,
748 * often not in the same place on two subsequent
751 * In any case, the underlying data doesn't seem
752 * to be affected, just the value read out.
757 if (tmpval2 == 0xc0017c)
758 device_printf(sc->ti_dev, "found 0xc0017c at "
759 "%#x (tmpval2)\n", segptr);
761 if (tmpval == 0xc0017c)
762 device_printf(sc->ti_dev, "found 0xc0017c at "
763 "%#x (tmpval)\n", segptr);
766 copyout(&tmpval, ptr, 4);
768 bcopy(&tmpval, ptr, 4);
771 copyin(ptr, &tmpval2, 4);
773 bcopy(ptr, &tmpval2, 4);
775 tmpval = htonl(tmpval2);
777 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
789 ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type)
791 const uint8_t *tmpsrc;
796 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", len);
805 if (swap_type == TI_SWAP_NTOH)
806 *(uint32_t *)tmpdst = ntohl(*(const uint32_t *)tmpsrc);
808 *(uint32_t *)tmpdst = htonl(*(const uint32_t *)tmpsrc);
818 * Load firmware image into the NIC. Check that the firmware revision
819 * is acceptable and see if we want the firmware for the Tigon 1 or
823 ti_loadfw(struct ti_softc *sc)
828 switch (sc->ti_hwrev) {
830 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
831 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
832 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
833 device_printf(sc->ti_dev, "firmware revision mismatch; "
834 "want %d.%d.%d, got %d.%d.%d\n",
835 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
836 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
837 tigonFwReleaseMinor, tigonFwReleaseFix);
840 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
841 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
842 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen,
844 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen);
845 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen);
846 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
848 case TI_HWREV_TIGON_II:
849 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
850 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
851 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
852 device_printf(sc->ti_dev, "firmware revision mismatch; "
853 "want %d.%d.%d, got %d.%d.%d\n",
854 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
855 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
856 tigon2FwReleaseMinor, tigon2FwReleaseFix);
859 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen,
861 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen,
863 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
865 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen);
866 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen);
867 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
870 device_printf(sc->ti_dev,
871 "can't load firmware: unknown hardware rev\n");
877 * Send the NIC a command via the command ring.
880 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
884 index = sc->ti_cmd_saved_prodidx;
885 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
886 TI_INC(index, TI_CMD_RING_CNT);
887 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
888 sc->ti_cmd_saved_prodidx = index;
892 * Send the NIC an extended command. The 'len' parameter specifies the
893 * number of command slots to include after the initial command.
896 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len)
901 index = sc->ti_cmd_saved_prodidx;
902 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
903 TI_INC(index, TI_CMD_RING_CNT);
904 for (i = 0; i < len; i++) {
905 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
906 *(uint32_t *)(&arg[i * 4]));
907 TI_INC(index, TI_CMD_RING_CNT);
909 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
910 sc->ti_cmd_saved_prodidx = index;
914 * Handle events that have triggered interrupts.
917 ti_handle_events(struct ti_softc *sc)
919 struct ti_event_desc *e;
921 if (sc->ti_rdata.ti_event_ring == NULL)
924 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag,
925 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_POSTREAD);
926 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
927 e = &sc->ti_rdata.ti_event_ring[sc->ti_ev_saved_considx];
928 switch (TI_EVENT_EVENT(e)) {
929 case TI_EV_LINKSTAT_CHANGED:
930 sc->ti_linkstat = TI_EVENT_CODE(e);
931 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
932 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
933 sc->ti_ifp->if_baudrate = IF_Mbps(100);
935 device_printf(sc->ti_dev,
937 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
938 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
939 sc->ti_ifp->if_baudrate = IF_Gbps(1UL);
941 device_printf(sc->ti_dev,
942 "gigabit link up\n");
943 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
944 if_link_state_change(sc->ti_ifp,
946 sc->ti_ifp->if_baudrate = 0;
948 device_printf(sc->ti_dev,
953 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
954 device_printf(sc->ti_dev, "invalid command\n");
955 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
956 device_printf(sc->ti_dev, "unknown command\n");
957 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
958 device_printf(sc->ti_dev, "bad config data\n");
960 case TI_EV_FIRMWARE_UP:
963 case TI_EV_STATS_UPDATED:
964 case TI_EV_RESET_JUMBO_RING:
965 case TI_EV_MCAST_UPDATED:
969 device_printf(sc->ti_dev, "unknown event: %d\n",
973 /* Advance the consumer index. */
974 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
975 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
977 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag,
978 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_PREREAD);
981 struct ti_dmamap_arg {
982 bus_addr_t ti_busaddr;
986 ti_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
988 struct ti_dmamap_arg *ctx;
993 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
996 ctx->ti_busaddr = segs->ds_addr;
1000 ti_dma_ring_alloc(struct ti_softc *sc, bus_size_t alignment, bus_size_t maxsize,
1001 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr,
1004 struct ti_dmamap_arg ctx;
1007 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag,
1008 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1009 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
1011 device_printf(sc->ti_dev,
1012 "could not create %s dma tag\n", msg);
1015 /* Allocate DMA'able memory for ring. */
1016 error = bus_dmamem_alloc(*tag, (void **)ring,
1017 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
1019 device_printf(sc->ti_dev,
1020 "could not allocate DMA'able memory for %s\n", msg);
1023 /* Load the address of the ring. */
1025 error = bus_dmamap_load(*tag, *map, *ring, maxsize, ti_dma_map_addr,
1026 &ctx, BUS_DMA_NOWAIT);
1028 device_printf(sc->ti_dev,
1029 "could not load DMA'able memory for %s\n", msg);
1032 *paddr = ctx.ti_busaddr;
1037 ti_dma_ring_free(struct ti_softc *sc, bus_dma_tag_t *tag, uint8_t **ring,
1038 bus_dmamap_t map, bus_addr_t *paddr)
1042 bus_dmamap_unload(*tag, map);
1045 if (*ring != NULL) {
1046 bus_dmamem_free(*tag, *ring, map);
1050 bus_dma_tag_destroy(*tag);
1056 ti_dma_alloc(struct ti_softc *sc)
1061 lowaddr = BUS_SPACE_MAXADDR;
1062 if (sc->ti_dac == 0)
1063 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1065 error = bus_dma_tag_create(bus_get_dma_tag(sc->ti_dev), 1, 0, lowaddr,
1066 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
1067 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
1068 &sc->ti_cdata.ti_parent_tag);
1070 device_printf(sc->ti_dev,
1071 "could not allocate parent dma tag\n");
1075 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_gib),
1076 &sc->ti_cdata.ti_gib_tag, (uint8_t **)&sc->ti_rdata.ti_info,
1077 &sc->ti_cdata.ti_gib_map, &sc->ti_rdata.ti_info_paddr, "GIB");
1081 /* Producer/consumer status */
1082 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_status),
1083 &sc->ti_cdata.ti_status_tag, (uint8_t **)&sc->ti_rdata.ti_status,
1084 &sc->ti_cdata.ti_status_map, &sc->ti_rdata.ti_status_paddr,
1090 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_EVENT_RING_SZ,
1091 &sc->ti_cdata.ti_event_ring_tag,
1092 (uint8_t **)&sc->ti_rdata.ti_event_ring,
1093 &sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr,
1098 /* Command ring lives in shared memory so no need to create DMA area. */
1100 /* Standard RX ring */
1101 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_STD_RX_RING_SZ,
1102 &sc->ti_cdata.ti_rx_std_ring_tag,
1103 (uint8_t **)&sc->ti_rdata.ti_rx_std_ring,
1104 &sc->ti_cdata.ti_rx_std_ring_map,
1105 &sc->ti_rdata.ti_rx_std_ring_paddr, "RX ring");
1110 error = ti_dma_ring_alloc(sc, TI_JUMBO_RING_ALIGN, TI_JUMBO_RX_RING_SZ,
1111 &sc->ti_cdata.ti_rx_jumbo_ring_tag,
1112 (uint8_t **)&sc->ti_rdata.ti_rx_jumbo_ring,
1113 &sc->ti_cdata.ti_rx_jumbo_ring_map,
1114 &sc->ti_rdata.ti_rx_jumbo_ring_paddr, "jumbo RX ring");
1118 /* RX return ring */
1119 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_RX_RETURN_RING_SZ,
1120 &sc->ti_cdata.ti_rx_return_ring_tag,
1121 (uint8_t **)&sc->ti_rdata.ti_rx_return_ring,
1122 &sc->ti_cdata.ti_rx_return_ring_map,
1123 &sc->ti_rdata.ti_rx_return_ring_paddr, "RX return ring");
1127 /* Create DMA tag for standard RX mbufs. */
1128 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1129 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1130 MCLBYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_std_tag);
1132 device_printf(sc->ti_dev, "could not allocate RX dma tag\n");
1136 /* Create DMA tag for jumbo RX mbufs. */
1137 #ifdef TI_SF_BUF_JUMBO
1139 * The VM system will take care of providing aligned pages. Alignment
1140 * is set to 1 here so that busdma resources won't be wasted.
1142 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1143 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE * 4, 4,
1144 PAGE_SIZE, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag);
1146 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1147 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MJUM9BYTES, 1,
1148 MJUM9BYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag);
1151 device_printf(sc->ti_dev,
1152 "could not allocate jumbo RX dma tag\n");
1156 /* Create DMA tag for TX mbufs. */
1157 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1,
1158 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1159 MCLBYTES * TI_MAXTXSEGS, TI_MAXTXSEGS, MCLBYTES, 0, NULL, NULL,
1160 &sc->ti_cdata.ti_tx_tag);
1162 device_printf(sc->ti_dev, "could not allocate TX dma tag\n");
1166 /* Create DMA maps for RX buffers. */
1167 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1168 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0,
1169 &sc->ti_cdata.ti_rx_std_maps[i]);
1171 device_printf(sc->ti_dev,
1172 "could not create DMA map for RX\n");
1176 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0,
1177 &sc->ti_cdata.ti_rx_std_sparemap);
1179 device_printf(sc->ti_dev,
1180 "could not create spare DMA map for RX\n");
1184 /* Create DMA maps for jumbo RX buffers. */
1185 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1186 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0,
1187 &sc->ti_cdata.ti_rx_jumbo_maps[i]);
1189 device_printf(sc->ti_dev,
1190 "could not create DMA map for jumbo RX\n");
1194 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0,
1195 &sc->ti_cdata.ti_rx_jumbo_sparemap);
1197 device_printf(sc->ti_dev,
1198 "could not create spare DMA map for jumbo RX\n");
1202 /* Create DMA maps for TX buffers. */
1203 for (i = 0; i < TI_TX_RING_CNT; i++) {
1204 error = bus_dmamap_create(sc->ti_cdata.ti_tx_tag, 0,
1205 &sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1207 device_printf(sc->ti_dev,
1208 "could not create DMA map for TX\n");
1213 /* Mini ring and TX ring is not available on Tigon 1. */
1214 if (sc->ti_hwrev == TI_HWREV_TIGON)
1218 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_TX_RING_SZ,
1219 &sc->ti_cdata.ti_tx_ring_tag, (uint8_t **)&sc->ti_rdata.ti_tx_ring,
1220 &sc->ti_cdata.ti_tx_ring_map, &sc->ti_rdata.ti_tx_ring_paddr,
1226 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_MINI_RX_RING_SZ,
1227 &sc->ti_cdata.ti_rx_mini_ring_tag,
1228 (uint8_t **)&sc->ti_rdata.ti_rx_mini_ring,
1229 &sc->ti_cdata.ti_rx_mini_ring_map,
1230 &sc->ti_rdata.ti_rx_mini_ring_paddr, "mini RX ring");
1234 /* Create DMA tag for mini RX mbufs. */
1235 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1236 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1,
1237 MHLEN, 0, NULL, NULL, &sc->ti_cdata.ti_rx_mini_tag);
1239 device_printf(sc->ti_dev,
1240 "could not allocate mini RX dma tag\n");
1244 /* Create DMA maps for mini RX buffers. */
1245 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1246 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0,
1247 &sc->ti_cdata.ti_rx_mini_maps[i]);
1249 device_printf(sc->ti_dev,
1250 "could not create DMA map for mini RX\n");
1254 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0,
1255 &sc->ti_cdata.ti_rx_mini_sparemap);
1257 device_printf(sc->ti_dev,
1258 "could not create spare DMA map for mini RX\n");
1266 ti_dma_free(struct ti_softc *sc)
1270 /* Destroy DMA maps for RX buffers. */
1271 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1272 if (sc->ti_cdata.ti_rx_std_maps[i]) {
1273 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag,
1274 sc->ti_cdata.ti_rx_std_maps[i]);
1275 sc->ti_cdata.ti_rx_std_maps[i] = NULL;
1278 if (sc->ti_cdata.ti_rx_std_sparemap) {
1279 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag,
1280 sc->ti_cdata.ti_rx_std_sparemap);
1281 sc->ti_cdata.ti_rx_std_sparemap = NULL;
1283 if (sc->ti_cdata.ti_rx_std_tag) {
1284 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_std_tag);
1285 sc->ti_cdata.ti_rx_std_tag = NULL;
1288 /* Destroy DMA maps for jumbo RX buffers. */
1289 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1290 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) {
1291 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag,
1292 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1293 sc->ti_cdata.ti_rx_jumbo_maps[i] = NULL;
1296 if (sc->ti_cdata.ti_rx_jumbo_sparemap) {
1297 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag,
1298 sc->ti_cdata.ti_rx_jumbo_sparemap);
1299 sc->ti_cdata.ti_rx_jumbo_sparemap = NULL;
1301 if (sc->ti_cdata.ti_rx_jumbo_tag) {
1302 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_jumbo_tag);
1303 sc->ti_cdata.ti_rx_jumbo_tag = NULL;
1306 /* Destroy DMA maps for mini RX buffers. */
1307 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1308 if (sc->ti_cdata.ti_rx_mini_maps[i]) {
1309 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag,
1310 sc->ti_cdata.ti_rx_mini_maps[i]);
1311 sc->ti_cdata.ti_rx_mini_maps[i] = NULL;
1314 if (sc->ti_cdata.ti_rx_mini_sparemap) {
1315 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag,
1316 sc->ti_cdata.ti_rx_mini_sparemap);
1317 sc->ti_cdata.ti_rx_mini_sparemap = NULL;
1319 if (sc->ti_cdata.ti_rx_mini_tag) {
1320 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_mini_tag);
1321 sc->ti_cdata.ti_rx_mini_tag = NULL;
1324 /* Destroy DMA maps for TX buffers. */
1325 for (i = 0; i < TI_TX_RING_CNT; i++) {
1326 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) {
1327 bus_dmamap_destroy(sc->ti_cdata.ti_tx_tag,
1328 sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1329 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL;
1332 if (sc->ti_cdata.ti_tx_tag) {
1333 bus_dma_tag_destroy(sc->ti_cdata.ti_tx_tag);
1334 sc->ti_cdata.ti_tx_tag = NULL;
1337 /* Destroy standard RX ring. */
1338 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_std_ring_tag,
1339 (void *)&sc->ti_rdata.ti_rx_std_ring,
1340 sc->ti_cdata.ti_rx_std_ring_map,
1341 &sc->ti_rdata.ti_rx_std_ring_paddr);
1342 /* Destroy jumbo RX ring. */
1343 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_jumbo_ring_tag,
1344 (void *)&sc->ti_rdata.ti_rx_jumbo_ring,
1345 sc->ti_cdata.ti_rx_jumbo_ring_map,
1346 &sc->ti_rdata.ti_rx_jumbo_ring_paddr);
1347 /* Destroy mini RX ring. */
1348 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_mini_ring_tag,
1349 (void *)&sc->ti_rdata.ti_rx_mini_ring,
1350 sc->ti_cdata.ti_rx_mini_ring_map,
1351 &sc->ti_rdata.ti_rx_mini_ring_paddr);
1352 /* Destroy RX return ring. */
1353 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_return_ring_tag,
1354 (void *)&sc->ti_rdata.ti_rx_return_ring,
1355 sc->ti_cdata.ti_rx_return_ring_map,
1356 &sc->ti_rdata.ti_rx_return_ring_paddr);
1357 /* Destroy TX ring. */
1358 ti_dma_ring_free(sc, &sc->ti_cdata.ti_tx_ring_tag,
1359 (void *)&sc->ti_rdata.ti_tx_ring, sc->ti_cdata.ti_tx_ring_map,
1360 &sc->ti_rdata.ti_tx_ring_paddr);
1361 /* Destroy status block. */
1362 ti_dma_ring_free(sc, &sc->ti_cdata.ti_status_tag,
1363 (void *)&sc->ti_rdata.ti_status, sc->ti_cdata.ti_status_map,
1364 &sc->ti_rdata.ti_status_paddr);
1365 /* Destroy event ring. */
1366 ti_dma_ring_free(sc, &sc->ti_cdata.ti_event_ring_tag,
1367 (void *)&sc->ti_rdata.ti_event_ring,
1368 sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr);
1370 ti_dma_ring_free(sc, &sc->ti_cdata.ti_gib_tag,
1371 (void *)&sc->ti_rdata.ti_info, sc->ti_cdata.ti_gib_map,
1372 &sc->ti_rdata.ti_info_paddr);
1374 /* Destroy the parent tag. */
1375 if (sc->ti_cdata.ti_parent_tag) {
1376 bus_dma_tag_destroy(sc->ti_cdata.ti_parent_tag);
1377 sc->ti_cdata.ti_parent_tag = NULL;
1382 * Intialize a standard receive ring descriptor.
1385 ti_newbuf_std(struct ti_softc *sc, int i)
1388 bus_dma_segment_t segs[1];
1390 struct ti_rx_desc *r;
1393 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1396 m->m_len = m->m_pkthdr.len = MCLBYTES;
1397 m_adj(m, ETHER_ALIGN);
1399 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_std_tag,
1400 sc->ti_cdata.ti_rx_std_sparemap, m, segs, &nsegs, 0);
1405 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1407 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1408 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag,
1409 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_POSTREAD);
1410 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag,
1411 sc->ti_cdata.ti_rx_std_maps[i]);
1414 map = sc->ti_cdata.ti_rx_std_maps[i];
1415 sc->ti_cdata.ti_rx_std_maps[i] = sc->ti_cdata.ti_rx_std_sparemap;
1416 sc->ti_cdata.ti_rx_std_sparemap = map;
1417 sc->ti_cdata.ti_rx_std_chain[i] = m;
1419 r = &sc->ti_rdata.ti_rx_std_ring[i];
1420 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1421 r->ti_len = segs[0].ds_len;
1422 r->ti_type = TI_BDTYPE_RECV_BD;
1425 r->ti_tcp_udp_cksum = 0;
1426 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1427 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1430 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag,
1431 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_PREREAD);
1436 * Intialize a mini receive ring descriptor. This only applies to
1440 ti_newbuf_mini(struct ti_softc *sc, int i)
1443 bus_dma_segment_t segs[1];
1445 struct ti_rx_desc *r;
1448 MGETHDR(m, M_NOWAIT, MT_DATA);
1451 m->m_len = m->m_pkthdr.len = MHLEN;
1452 m_adj(m, ETHER_ALIGN);
1454 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_mini_tag,
1455 sc->ti_cdata.ti_rx_mini_sparemap, m, segs, &nsegs, 0);
1460 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1462 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1463 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag,
1464 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_POSTREAD);
1465 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag,
1466 sc->ti_cdata.ti_rx_mini_maps[i]);
1469 map = sc->ti_cdata.ti_rx_mini_maps[i];
1470 sc->ti_cdata.ti_rx_mini_maps[i] = sc->ti_cdata.ti_rx_mini_sparemap;
1471 sc->ti_cdata.ti_rx_mini_sparemap = map;
1472 sc->ti_cdata.ti_rx_mini_chain[i] = m;
1474 r = &sc->ti_rdata.ti_rx_mini_ring[i];
1475 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1476 r->ti_len = segs[0].ds_len;
1477 r->ti_type = TI_BDTYPE_RECV_BD;
1478 r->ti_flags = TI_BDFLAG_MINI_RING;
1480 r->ti_tcp_udp_cksum = 0;
1481 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1482 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1485 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag,
1486 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_PREREAD);
1490 #ifndef TI_SF_BUF_JUMBO
1493 * Initialize a jumbo receive ring descriptor. This allocates
1494 * a jumbo buffer from the pool managed internally by the driver.
1497 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *dummy)
1500 bus_dma_segment_t segs[1];
1502 struct ti_rx_desc *r;
1507 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1510 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1511 m_adj(m, ETHER_ALIGN);
1513 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag,
1514 sc->ti_cdata.ti_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1519 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1521 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1522 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag,
1523 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_POSTREAD);
1524 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag,
1525 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1528 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1529 sc->ti_cdata.ti_rx_jumbo_maps[i] = sc->ti_cdata.ti_rx_jumbo_sparemap;
1530 sc->ti_cdata.ti_rx_jumbo_sparemap = map;
1531 sc->ti_cdata.ti_rx_jumbo_chain[i] = m;
1533 r = &sc->ti_rdata.ti_rx_jumbo_ring[i];
1534 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1535 r->ti_len = segs[0].ds_len;
1536 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1537 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1539 r->ti_tcp_udp_cksum = 0;
1540 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1541 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1544 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag,
1545 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_PREREAD);
1551 #if (PAGE_SIZE == 4096)
1557 #define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1558 #define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1559 #define NFS_HDR_LEN (UDP_HDR_LEN)
1560 static int HDR_LEN = TCP_HDR_LEN;
1563 * Initialize a jumbo receive ring descriptor. This allocates
1564 * a jumbo buffer from the pool managed internally by the driver.
1567 ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old)
1570 struct mbuf *cur, *m_new = NULL;
1571 struct mbuf *m[3] = {NULL, NULL, NULL};
1572 struct ti_rx_desc_ext *r;
1574 /* 1 extra buf to make nobufs easy*/
1575 struct sf_buf *sf[3] = {NULL, NULL, NULL};
1577 bus_dma_segment_t segs[4];
1580 if (m_old != NULL) {
1582 cur = m_old->m_next;
1583 for (i = 0; i <= NPAYLOAD; i++){
1588 /* Allocate the mbufs. */
1589 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1590 if (m_new == NULL) {
1591 device_printf(sc->ti_dev, "mbuf allocation failed "
1592 "-- packet dropped!\n");
1595 MGET(m[NPAYLOAD], M_NOWAIT, MT_DATA);
1596 if (m[NPAYLOAD] == NULL) {
1597 device_printf(sc->ti_dev, "cluster mbuf allocation "
1598 "failed -- packet dropped!\n");
1601 if (!(MCLGET(m[NPAYLOAD], M_NOWAIT))) {
1602 device_printf(sc->ti_dev, "mbuf allocation failed "
1603 "-- packet dropped!\n");
1606 m[NPAYLOAD]->m_len = MCLBYTES;
1608 for (i = 0; i < NPAYLOAD; i++){
1609 MGET(m[i], M_NOWAIT, MT_DATA);
1611 device_printf(sc->ti_dev, "mbuf allocation "
1612 "failed -- packet dropped!\n");
1615 frame = vm_page_alloc(NULL, 0,
1616 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1618 if (frame == NULL) {
1619 device_printf(sc->ti_dev, "buffer allocation "
1620 "failed -- packet dropped!\n");
1621 printf(" index %d page %d\n", idx, i);
1624 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1625 if (sf[i] == NULL) {
1626 vm_page_unwire_noq(frame);
1627 vm_page_free(frame);
1628 device_printf(sc->ti_dev, "buffer allocation "
1629 "failed -- packet dropped!\n");
1630 printf(" index %d page %d\n", idx, i);
1634 for (i = 0; i < NPAYLOAD; i++){
1635 /* Attach the buffer to the mbuf. */
1636 m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1637 m[i]->m_len = PAGE_SIZE;
1638 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1639 sf_mext_free, (void*)sf_buf_kva(sf[i]), sf[i],
1641 m[i]->m_next = m[i+1];
1643 /* link the buffers to the header */
1644 m_new->m_next = m[0];
1645 m_new->m_data += ETHER_ALIGN;
1646 if (sc->ti_hdrsplit)
1647 m_new->m_len = MHLEN - ETHER_ALIGN;
1649 m_new->m_len = HDR_LEN;
1650 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1653 /* Set up the descriptor. */
1654 r = &sc->ti_rdata.ti_rx_jumbo_ring[idx];
1655 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1656 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1657 if (bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, map, m_new,
1660 if ((nsegs < 1) || (nsegs > 4))
1662 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr);
1663 r->ti_len0 = m_new->m_len;
1665 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr);
1666 r->ti_len1 = PAGE_SIZE;
1668 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr);
1669 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1671 if (PAGE_SIZE == 4096) {
1672 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr);
1673 r->ti_len3 = MCLBYTES;
1677 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1679 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1681 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1682 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1686 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, BUS_DMASYNC_PREREAD);
1693 * This can only be called before the mbufs are strung together.
1694 * If the mbufs are strung together, m_freem() will free the chain,
1695 * so that the later mbufs will be freed multiple times.
1700 for (i = 0; i < 3; i++) {
1704 sf_mext_free((void *)sf_buf_kva(sf[i]), sf[i]);
1711 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1712 * that's 1MB or memory, which is a lot. For now, we fill only the first
1713 * 256 ring entries and hope that our CPU is fast enough to keep up with
1717 ti_init_rx_ring_std(struct ti_softc *sc)
1720 struct ti_cmd_desc cmd;
1722 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1723 if (ti_newbuf_std(sc, i) != 0)
1727 sc->ti_std = TI_STD_RX_RING_CNT - 1;
1728 TI_UPDATE_STDPROD(sc, TI_STD_RX_RING_CNT - 1);
1734 ti_free_rx_ring_std(struct ti_softc *sc)
1739 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1740 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1741 map = sc->ti_cdata.ti_rx_std_maps[i];
1742 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, map,
1743 BUS_DMASYNC_POSTREAD);
1744 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, map);
1745 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1746 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1749 bzero(sc->ti_rdata.ti_rx_std_ring, TI_STD_RX_RING_SZ);
1750 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag,
1751 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1755 ti_init_rx_ring_jumbo(struct ti_softc *sc)
1757 struct ti_cmd_desc cmd;
1760 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1761 if (ti_newbuf_jumbo(sc, i, NULL) != 0)
1765 sc->ti_jumbo = TI_JUMBO_RX_RING_CNT - 1;
1766 TI_UPDATE_JUMBOPROD(sc, TI_JUMBO_RX_RING_CNT - 1);
1772 ti_free_rx_ring_jumbo(struct ti_softc *sc)
1777 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1778 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1779 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1780 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map,
1781 BUS_DMASYNC_POSTREAD);
1782 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map);
1783 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1784 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1787 bzero(sc->ti_rdata.ti_rx_jumbo_ring, TI_JUMBO_RX_RING_SZ);
1788 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag,
1789 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1793 ti_init_rx_ring_mini(struct ti_softc *sc)
1797 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1798 if (ti_newbuf_mini(sc, i) != 0)
1802 sc->ti_mini = TI_MINI_RX_RING_CNT - 1;
1803 TI_UPDATE_MINIPROD(sc, TI_MINI_RX_RING_CNT - 1);
1809 ti_free_rx_ring_mini(struct ti_softc *sc)
1814 if (sc->ti_rdata.ti_rx_mini_ring == NULL)
1817 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1818 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1819 map = sc->ti_cdata.ti_rx_mini_maps[i];
1820 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, map,
1821 BUS_DMASYNC_POSTREAD);
1822 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, map);
1823 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1824 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1827 bzero(sc->ti_rdata.ti_rx_mini_ring, TI_MINI_RX_RING_SZ);
1828 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag,
1829 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE);
1833 ti_free_tx_ring(struct ti_softc *sc)
1835 struct ti_txdesc *txd;
1838 if (sc->ti_rdata.ti_tx_ring == NULL)
1841 for (i = 0; i < TI_TX_RING_CNT; i++) {
1842 txd = &sc->ti_cdata.ti_txdesc[i];
1843 if (txd->tx_m != NULL) {
1844 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
1845 BUS_DMASYNC_POSTWRITE);
1846 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag,
1852 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ);
1853 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
1854 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE);
1858 ti_init_tx_ring(struct ti_softc *sc)
1860 struct ti_txdesc *txd;
1863 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq);
1864 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq);
1865 for (i = 0; i < TI_TX_RING_CNT; i++) {
1866 txd = &sc->ti_cdata.ti_txdesc[i];
1867 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
1870 sc->ti_tx_saved_considx = 0;
1871 sc->ti_tx_saved_prodidx = 0;
1872 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1877 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1878 * but we have to support the old way too so that Tigon 1 cards will
1882 ti_add_mcast(void *arg, struct sockaddr_dl *sdl, u_int count)
1884 struct ti_softc *sc = arg;
1885 struct ti_cmd_desc cmd;
1887 uint32_t ext[2] = {0, 0};
1889 m = (uint16_t *)LLADDR(sdl);
1891 switch (sc->ti_hwrev) {
1892 case TI_HWREV_TIGON:
1893 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1894 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1895 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1897 case TI_HWREV_TIGON_II:
1898 ext[0] = htons(m[0]);
1899 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1900 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1903 device_printf(sc->ti_dev, "unknown hwrev\n");
1910 ti_del_mcast(void *arg, struct sockaddr_dl *sdl, u_int count)
1912 struct ti_softc *sc = arg;
1913 struct ti_cmd_desc cmd;
1915 uint32_t ext[2] = {0, 0};
1917 m = (uint16_t *)LLADDR(sdl);
1919 switch (sc->ti_hwrev) {
1920 case TI_HWREV_TIGON:
1921 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1922 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1923 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1925 case TI_HWREV_TIGON_II:
1926 ext[0] = htons(m[0]);
1927 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1928 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1931 device_printf(sc->ti_dev, "unknown hwrev\n");
1939 * Configure the Tigon's multicast address filter.
1941 * The actual multicast table management is a bit of a pain, thanks to
1942 * slight brain damage on the part of both Alteon and us. With our
1943 * multicast code, we are only alerted when the multicast address table
1944 * changes and at that point we only have the current list of addresses:
1945 * we only know the current state, not the previous state, so we don't
1946 * actually know what addresses were removed or added. The firmware has
1947 * state, but we can't get our grubby mits on it, and there is no 'delete
1948 * all multicast addresses' command. Hence, we have to maintain our own
1949 * state so we know what addresses have been programmed into the NIC at
1953 ti_setmulti(struct ti_softc *sc)
1956 struct ti_cmd_desc cmd;
1963 if (ifp->if_flags & IFF_ALLMULTI) {
1964 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1967 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1970 /* Disable interrupts. */
1971 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1972 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1974 /* First, zot all the existing filters. */
1975 if_foreach_llmaddr(ifp, ti_del_mcast, sc);
1977 /* Now program new ones. */
1978 if_foreach_llmaddr(ifp, ti_add_mcast, sc);
1980 /* Re-enable interrupts. */
1981 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1985 * Check to see if the BIOS has configured us for a 64 bit slot when
1986 * we aren't actually in one. If we detect this condition, we can work
1987 * around it on the Tigon 2 by setting a bit in the PCI state register,
1988 * but for the Tigon 1 we must give up and abort the interface attach.
1991 ti_64bitslot_war(struct ti_softc *sc)
1994 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1995 CSR_WRITE_4(sc, 0x600, 0);
1996 CSR_WRITE_4(sc, 0x604, 0);
1997 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1998 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1999 if (sc->ti_hwrev == TI_HWREV_TIGON)
2002 TI_SETBIT(sc, TI_PCI_STATE,
2003 TI_PCISTATE_32BIT_BUS);
2013 * Do endian, PCI and DMA initialization. Also check the on-board ROM
2014 * self-test results.
2017 ti_chipinit(struct ti_softc *sc)
2020 uint32_t pci_writemax = 0;
2023 /* Initialize link to down state. */
2024 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
2026 /* Set endianness before we access any non-PCI registers. */
2027 #if 0 && BYTE_ORDER == BIG_ENDIAN
2028 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
2029 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
2031 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
2032 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
2035 /* Check the ROM failed bit to see if self-tests passed. */
2036 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
2037 device_printf(sc->ti_dev, "board self-diagnostics failed!\n");
2042 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
2044 /* Figure out the hardware revision. */
2045 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
2046 case TI_REV_TIGON_I:
2047 sc->ti_hwrev = TI_HWREV_TIGON;
2049 case TI_REV_TIGON_II:
2050 sc->ti_hwrev = TI_HWREV_TIGON_II;
2053 device_printf(sc->ti_dev, "unsupported chip revision\n");
2057 /* Do special setup for Tigon 2. */
2058 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
2059 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
2060 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
2061 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
2065 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
2066 * can't do header splitting.
2068 #ifdef TI_JUMBO_HDRSPLIT
2069 if (sc->ti_hwrev != TI_HWREV_TIGON)
2070 sc->ti_hdrsplit = 1;
2072 device_printf(sc->ti_dev,
2073 "can't do header splitting on a Tigon I board\n");
2074 #endif /* TI_JUMBO_HDRSPLIT */
2076 /* Set up the PCI state register. */
2077 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
2078 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
2079 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
2082 /* Clear the read/write max DMA parameters. */
2083 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
2084 TI_PCISTATE_READ_MAXDMA));
2086 /* Get cache line size. */
2087 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
2090 * If the system has set enabled the PCI memory write
2091 * and invalidate command in the command register, set
2092 * the write max parameter accordingly. This is necessary
2093 * to use MWI with the Tigon 2.
2095 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
2096 switch (cacheline) {
2105 /* Disable PCI memory write and invalidate. */
2107 device_printf(sc->ti_dev, "cache line size %d"
2108 " not supported; disabling PCI MWI\n",
2110 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
2111 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
2116 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
2118 /* This sets the min dma param all the way up (0xff). */
2119 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
2121 if (sc->ti_hdrsplit)
2122 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
2126 /* Configure DMA variables. */
2127 #if BYTE_ORDER == BIG_ENDIAN
2128 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
2129 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
2130 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
2131 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
2132 #else /* BYTE_ORDER */
2133 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
2134 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
2135 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
2136 #endif /* BYTE_ORDER */
2139 * Only allow 1 DMA channel to be active at a time.
2140 * I don't think this is a good idea, but without it
2141 * the firmware racks up lots of nicDmaReadRingFull
2142 * errors. This is not compatible with hardware checksums.
2144 if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0)
2145 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
2147 /* Recommended settings from Tigon manual. */
2148 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
2149 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
2151 if (ti_64bitslot_war(sc)) {
2152 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, "
2161 * Initialize the general information block and firmware, and
2162 * start the CPU(s) running.
2165 ti_gibinit(struct ti_softc *sc)
2175 /* Disable interrupts for now. */
2176 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2178 /* Tell the chip where to find the general information block. */
2179 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI,
2180 (uint64_t)sc->ti_rdata.ti_info_paddr >> 32);
2181 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO,
2182 sc->ti_rdata.ti_info_paddr & 0xFFFFFFFF);
2184 /* Load the firmware into SRAM. */
2187 /* Set up the contents of the general info and ring control blocks. */
2189 /* Set up the event ring and producer pointer. */
2190 bzero(sc->ti_rdata.ti_event_ring, TI_EVENT_RING_SZ);
2191 rcb = &sc->ti_rdata.ti_info->ti_ev_rcb;
2192 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_event_ring_paddr);
2194 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_ev_prodidx_ptr,
2195 sc->ti_rdata.ti_status_paddr +
2196 offsetof(struct ti_status, ti_ev_prodidx_r));
2197 sc->ti_ev_prodidx.ti_idx = 0;
2198 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
2199 sc->ti_ev_saved_considx = 0;
2201 /* Set up the command ring and producer mailbox. */
2202 rcb = &sc->ti_rdata.ti_info->ti_cmd_rcb;
2203 ti_hostaddr64(&rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING));
2205 rcb->ti_max_len = 0;
2206 for (i = 0; i < TI_CMD_RING_CNT; i++) {
2207 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
2209 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
2210 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
2211 sc->ti_cmd_saved_prodidx = 0;
2214 * Assign the address of the stats refresh buffer.
2215 * We re-use the current stats buffer for this to
2218 bzero(&sc->ti_rdata.ti_info->ti_stats, sizeof(struct ti_stats));
2219 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_refresh_stats_ptr,
2220 sc->ti_rdata.ti_info_paddr + offsetof(struct ti_gib, ti_stats));
2222 /* Set up the standard receive ring. */
2223 rcb = &sc->ti_rdata.ti_info->ti_std_rx_rcb;
2224 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_std_ring_paddr);
2225 rcb->ti_max_len = TI_FRAMELEN;
2227 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2228 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2229 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2230 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2231 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2233 /* Set up the jumbo receive ring. */
2234 rcb = &sc->ti_rdata.ti_info->ti_jumbo_rx_rcb;
2235 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_jumbo_ring_paddr);
2237 #ifndef TI_SF_BUF_JUMBO
2238 rcb->ti_max_len = MJUM9BYTES - ETHER_ALIGN;
2241 rcb->ti_max_len = PAGE_SIZE;
2242 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
2244 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2245 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2246 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2247 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2248 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2251 * Set up the mini ring. Only activated on the
2252 * Tigon 2 but the slot in the config block is
2253 * still there on the Tigon 1.
2255 rcb = &sc->ti_rdata.ti_info->ti_mini_rx_rcb;
2256 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_mini_ring_paddr);
2257 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
2258 if (sc->ti_hwrev == TI_HWREV_TIGON)
2259 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
2262 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2263 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2264 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2265 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2266 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2269 * Set up the receive return ring.
2271 rcb = &sc->ti_rdata.ti_info->ti_return_rcb;
2272 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_return_ring_paddr);
2274 rcb->ti_max_len = TI_RETURN_RING_CNT;
2275 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_return_prodidx_ptr,
2276 sc->ti_rdata.ti_status_paddr +
2277 offsetof(struct ti_status, ti_return_prodidx_r));
2280 * Set up the tx ring. Note: for the Tigon 2, we have the option
2281 * of putting the transmit ring in the host's address space and
2282 * letting the chip DMA it instead of leaving the ring in the NIC's
2283 * memory and accessing it through the shared memory region. We
2284 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
2285 * so we have to revert to the shared memory scheme if we detect
2288 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
2289 if (sc->ti_rdata.ti_tx_ring != NULL)
2290 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ);
2291 rcb = &sc->ti_rdata.ti_info->ti_tx_rcb;
2292 if (sc->ti_hwrev == TI_HWREV_TIGON)
2295 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
2296 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2297 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2298 if (sc->ti_ifp->if_capenable & IFCAP_TXCSUM)
2299 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2300 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2301 rcb->ti_max_len = TI_TX_RING_CNT;
2302 if (sc->ti_hwrev == TI_HWREV_TIGON)
2303 ti_hostaddr64(&rcb->ti_hostaddr, TI_TX_RING_BASE);
2305 ti_hostaddr64(&rcb->ti_hostaddr,
2306 sc->ti_rdata.ti_tx_ring_paddr);
2307 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_tx_considx_ptr,
2308 sc->ti_rdata.ti_status_paddr +
2309 offsetof(struct ti_status, ti_tx_considx_r));
2311 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map,
2312 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2313 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, sc->ti_cdata.ti_status_map,
2314 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2315 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag,
2316 sc->ti_cdata.ti_event_ring_map,
2317 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2318 if (sc->ti_rdata.ti_tx_ring != NULL)
2319 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
2320 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE);
2322 /* Set up tunables */
2324 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN)
2325 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
2326 (sc->ti_rx_coal_ticks / 10));
2329 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2330 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2331 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2332 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2333 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2334 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2336 /* Turn interrupts on. */
2337 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2338 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2341 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2347 * Probe for a Tigon chip. Check the PCI vendor and device IDs
2348 * against our list and return its name if we find a match.
2351 ti_probe(device_t dev)
2353 const struct ti_type *t;
2357 while (t->ti_name != NULL) {
2358 if ((pci_get_vendor(dev) == t->ti_vid) &&
2359 (pci_get_device(dev) == t->ti_did)) {
2360 device_set_desc(dev, t->ti_name);
2361 return (BUS_PROBE_DEFAULT);
2370 ti_attach(device_t dev)
2373 struct ti_softc *sc;
2377 sc = device_get_softc(dev);
2380 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2382 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0);
2383 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2384 ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
2386 device_printf(dev, "can not if_alloc()\n");
2390 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES;
2391 sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
2392 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities;
2395 * Map control/status registers.
2397 pci_enable_busmaster(dev);
2400 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2403 if (sc->ti_res == NULL) {
2404 device_printf(dev, "couldn't map memory\n");
2409 sc->ti_btag = rman_get_bustag(sc->ti_res);
2410 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2412 /* Allocate interrupt */
2415 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2416 RF_SHAREABLE | RF_ACTIVE);
2418 if (sc->ti_irq == NULL) {
2419 device_printf(dev, "couldn't map interrupt\n");
2424 if (ti_chipinit(sc)) {
2425 device_printf(dev, "chip initialization failed\n");
2430 /* Zero out the NIC's on-board SRAM. */
2431 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
2433 /* Init again -- zeroing memory may have clobbered some registers. */
2434 if (ti_chipinit(sc)) {
2435 device_printf(dev, "chip initialization failed\n");
2441 * Get station address from the EEPROM. Note: the manual states
2442 * that the MAC address is at offset 0x8c, however the data is
2443 * stored as two longwords (since that's how it's loaded into
2444 * the NIC). This means the MAC address is actually preceded
2445 * by two zero bytes. We need to skip over those.
2447 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2448 device_printf(dev, "failed to read station address\n");
2453 /* Allocate working area for memory dump. */
2454 sc->ti_membuf = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, M_NOWAIT);
2455 sc->ti_membuf2 = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF,
2457 if (sc->ti_membuf == NULL || sc->ti_membuf2 == NULL) {
2458 device_printf(dev, "cannot allocate memory buffer\n");
2462 if ((error = ti_dma_alloc(sc)) != 0)
2466 * We really need a better way to tell a 1000baseTX card
2467 * from a 1000baseSX one, since in theory there could be
2468 * OEMed 1000baseTX cards from lame vendors who aren't
2469 * clever enough to change the PCI ID. For the moment
2470 * though, the AceNIC is the only copper card available.
2472 if (pci_get_vendor(dev) == ALT_VENDORID &&
2473 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2475 /* Ok, it's not the only copper card available. */
2476 if (pci_get_vendor(dev) == NG_VENDORID &&
2477 pci_get_device(dev) == NG_DEVICEID_GA620T)
2480 /* Set default tunable values. */
2483 /* Set up ifnet structure */
2485 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2486 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2487 ifp->if_ioctl = ti_ioctl;
2488 ifp->if_start = ti_start;
2489 ifp->if_init = ti_init;
2490 ifp->if_get_counter = ti_get_counter;
2491 ifp->if_baudrate = IF_Gbps(1UL);
2492 ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1;
2493 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2494 IFQ_SET_READY(&ifp->if_snd);
2496 /* Set up ifmedia support. */
2497 if (sc->ti_copper) {
2499 * Copper cards allow manual 10/100 mode selection,
2500 * but not manual 1000baseTX mode selection. Why?
2501 * Because currently there's no way to specify the
2502 * master/slave setting through the firmware interface,
2503 * so Alteon decided to just bag it and handle it
2504 * via autonegotiation.
2506 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2507 ifmedia_add(&sc->ifmedia,
2508 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2509 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2510 ifmedia_add(&sc->ifmedia,
2511 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2512 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2513 ifmedia_add(&sc->ifmedia,
2514 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2516 /* Fiber cards don't support 10/100 modes. */
2517 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2518 ifmedia_add(&sc->ifmedia,
2519 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2521 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2522 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2525 * We're assuming here that card initialization is a sequential
2526 * thing. If it isn't, multiple cards probing at the same time
2527 * could stomp on the list of softcs here.
2530 /* Register the device */
2531 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT,
2532 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev));
2533 sc->dev->si_drv1 = sc;
2536 * Call MI attach routine.
2538 ether_ifattach(ifp, eaddr);
2540 /* VLAN capability setup. */
2541 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM |
2542 IFCAP_VLAN_HWTAGGING;
2543 ifp->if_capenable = ifp->if_capabilities;
2544 /* Tell the upper layer we support VLAN over-sized frames. */
2545 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
2547 /* Driver supports link state tracking. */
2548 ifp->if_capabilities |= IFCAP_LINKSTATE;
2549 ifp->if_capenable |= IFCAP_LINKSTATE;
2551 /* Hook interrupt last to avoid having to lock softc */
2552 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE,
2553 NULL, ti_intr, sc, &sc->ti_intrhand);
2556 device_printf(dev, "couldn't set up irq\n");
2568 * Shutdown hardware and free up resources. This can be called any
2569 * time after the mutex has been initialized. It is called in both
2570 * the error case in attach and the normal detach case so it needs
2571 * to be careful about only freeing resources that have actually been
2575 ti_detach(device_t dev)
2577 struct ti_softc *sc;
2580 sc = device_get_softc(dev);
2582 destroy_dev(sc->dev);
2583 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2585 if (device_is_attached(dev)) {
2586 ether_ifdetach(ifp);
2592 /* These should only be active if attach succeeded */
2593 callout_drain(&sc->ti_watchdog);
2594 bus_generic_detach(dev);
2596 ifmedia_removeall(&sc->ifmedia);
2598 if (sc->ti_intrhand)
2599 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2601 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2603 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
2609 free(sc->ti_membuf, M_DEVBUF);
2611 free(sc->ti_membuf2, M_DEVBUF);
2613 mtx_destroy(&sc->ti_mtx);
2618 #ifdef TI_JUMBO_HDRSPLIT
2620 * If hdr_len is 0, that means that header splitting wasn't done on
2621 * this packet for some reason. The two most likely reasons are that
2622 * the protocol isn't a supported protocol for splitting, or this
2623 * packet had a fragment offset that wasn't 0.
2625 * The header length, if it is non-zero, will always be the length of
2626 * the headers on the packet, but that length could be longer than the
2627 * first mbuf. So we take the minimum of the two as the actual
2630 static __inline void
2631 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2634 int lengths[4] = {0, 0, 0, 0};
2635 struct mbuf *m, *mp;
2638 top->m_len = min(hdr_len, top->m_len);
2639 pkt_len -= top->m_len;
2640 lengths[i++] = top->m_len;
2643 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2644 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2645 pkt_len -= m->m_len;
2646 lengths[i++] = m->m_len;
2652 printf("got split packet: ");
2654 printf("got non-split packet: ");
2656 printf("%d,%d,%d,%d = %d\n", lengths[0],
2657 lengths[1], lengths[2], lengths[3],
2658 lengths[0] + lengths[1] + lengths[2] +
2663 panic("header splitting didn't");
2670 if (mp->m_next != NULL)
2671 panic("ti_hdr_split: last mbuf in chain should be null");
2673 #endif /* TI_JUMBO_HDRSPLIT */
2676 ti_discard_std(struct ti_softc *sc, int i)
2679 struct ti_rx_desc *r;
2681 r = &sc->ti_rdata.ti_rx_std_ring[i];
2682 r->ti_len = MCLBYTES - ETHER_ALIGN;
2683 r->ti_type = TI_BDTYPE_RECV_BD;
2686 r->ti_tcp_udp_cksum = 0;
2687 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2688 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2693 ti_discard_mini(struct ti_softc *sc, int i)
2696 struct ti_rx_desc *r;
2698 r = &sc->ti_rdata.ti_rx_mini_ring[i];
2699 r->ti_len = MHLEN - ETHER_ALIGN;
2700 r->ti_type = TI_BDTYPE_RECV_BD;
2701 r->ti_flags = TI_BDFLAG_MINI_RING;
2703 r->ti_tcp_udp_cksum = 0;
2704 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2705 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2709 #ifndef TI_SF_BUF_JUMBO
2711 ti_discard_jumbo(struct ti_softc *sc, int i)
2714 struct ti_rx_desc *r;
2716 r = &sc->ti_rdata.ti_rx_jumbo_ring[i];
2717 r->ti_len = MJUM9BYTES - ETHER_ALIGN;
2718 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
2719 r->ti_flags = TI_BDFLAG_JUMBO_RING;
2721 r->ti_tcp_udp_cksum = 0;
2722 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2723 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2729 * Frame reception handling. This is called if there's a frame
2730 * on the receive return list.
2732 * Note: we have to be able to handle three possibilities here:
2733 * 1) the frame is from the mini receive ring (can only happen)
2734 * on Tigon 2 boards)
2735 * 2) the frame is from the jumbo receive ring
2736 * 3) the frame is from the standard receive ring
2740 ti_rxeof(struct ti_softc *sc)
2743 #ifdef TI_SF_BUF_JUMBO
2746 struct ti_cmd_desc cmd;
2747 int jumbocnt, minicnt, stdcnt, ti_len;
2753 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag,
2754 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
2755 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN)
2756 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag,
2757 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
2758 if (sc->ti_rdata.ti_rx_mini_ring != NULL)
2759 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag,
2760 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_POSTWRITE);
2761 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag,
2762 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
2764 jumbocnt = minicnt = stdcnt = 0;
2765 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2766 struct ti_rx_desc *cur_rx;
2768 struct mbuf *m = NULL;
2769 uint16_t vlan_tag = 0;
2773 &sc->ti_rdata.ti_rx_return_ring[sc->ti_rx_saved_considx];
2774 rxidx = cur_rx->ti_idx;
2775 ti_len = cur_rx->ti_len;
2776 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2778 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2780 vlan_tag = cur_rx->ti_vlan_tag;
2783 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2785 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2786 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2787 #ifndef TI_SF_BUF_JUMBO
2788 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2789 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2790 ti_discard_jumbo(sc, rxidx);
2793 if (ti_newbuf_jumbo(sc, rxidx, NULL) != 0) {
2794 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2795 ti_discard_jumbo(sc, rxidx);
2799 #else /* !TI_SF_BUF_JUMBO */
2800 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2801 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx];
2802 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map,
2803 BUS_DMASYNC_POSTREAD);
2804 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map);
2805 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2806 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2807 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2810 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2811 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2812 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2815 #ifdef TI_JUMBO_HDRSPLIT
2816 if (sc->ti_hdrsplit)
2817 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2820 #endif /* TI_JUMBO_HDRSPLIT */
2821 m_adj(m, ti_len - m->m_pkthdr.len);
2822 #endif /* TI_SF_BUF_JUMBO */
2823 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2825 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2826 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2827 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2828 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2829 ti_discard_mini(sc, rxidx);
2832 if (ti_newbuf_mini(sc, rxidx) != 0) {
2833 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2834 ti_discard_mini(sc, rxidx);
2840 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2841 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2842 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2843 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2844 ti_discard_std(sc, rxidx);
2847 if (ti_newbuf_std(sc, rxidx) != 0) {
2848 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2849 ti_discard_std(sc, rxidx);
2855 m->m_pkthdr.len = ti_len;
2856 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2857 m->m_pkthdr.rcvif = ifp;
2859 if (ifp->if_capenable & IFCAP_RXCSUM) {
2860 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) {
2861 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2862 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2863 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2865 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) {
2866 m->m_pkthdr.csum_data =
2867 cur_rx->ti_tcp_udp_cksum;
2868 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2873 * If we received a packet with a vlan tag,
2874 * tag it before passing the packet upward.
2877 m->m_pkthdr.ether_vtag = vlan_tag;
2878 m->m_flags |= M_VLANTAG;
2881 (*ifp->if_input)(ifp, m);
2885 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag,
2886 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_PREREAD);
2887 /* Only necessary on the Tigon 1. */
2888 if (sc->ti_hwrev == TI_HWREV_TIGON)
2889 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2890 sc->ti_rx_saved_considx);
2893 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag,
2894 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
2895 TI_UPDATE_STDPROD(sc, sc->ti_std);
2898 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag,
2899 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE);
2900 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2903 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag,
2904 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
2905 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2910 ti_txeof(struct ti_softc *sc)
2912 struct ti_txdesc *txd;
2913 struct ti_tx_desc txdesc;
2914 struct ti_tx_desc *cur_tx = NULL;
2920 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2924 if (sc->ti_rdata.ti_tx_ring != NULL)
2925 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
2926 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_POSTWRITE);
2928 * Go through our tx ring and free mbufs for those
2929 * frames that have been sent.
2931 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx;
2932 TI_INC(idx, TI_TX_RING_CNT)) {
2933 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2934 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc),
2935 sizeof(txdesc), &txdesc);
2938 cur_tx = &sc->ti_rdata.ti_tx_ring[idx];
2940 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2941 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0)
2943 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
2944 BUS_DMASYNC_POSTWRITE);
2945 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap);
2947 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2950 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q);
2951 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
2952 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2954 sc->ti_tx_saved_considx = idx;
2955 if (sc->ti_txcnt == 0)
2962 struct ti_softc *sc;
2969 /* Make sure this is really our interrupt. */
2970 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2975 /* Ack interrupt and stop others from occurring. */
2976 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2978 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2979 bus_dmamap_sync(sc->ti_cdata.ti_status_tag,
2980 sc->ti_cdata.ti_status_map, BUS_DMASYNC_POSTREAD);
2981 /* Check RX return ring producer/consumer */
2984 /* Check TX ring producer/consumer */
2986 bus_dmamap_sync(sc->ti_cdata.ti_status_tag,
2987 sc->ti_cdata.ti_status_map, BUS_DMASYNC_PREREAD);
2990 ti_handle_events(sc);
2992 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2993 /* Re-enable interrupts. */
2994 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2995 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2996 ti_start_locked(ifp);
3003 ti_get_counter(struct ifnet *ifp, ift_counter cnt)
3007 case IFCOUNTER_COLLISIONS:
3009 struct ti_softc *sc;
3013 sc = if_getsoftc(ifp);
3014 s = &sc->ti_rdata.ti_info->ti_stats;
3017 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag,
3018 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD);
3019 rv = s->dot3StatsSingleCollisionFrames +
3020 s->dot3StatsMultipleCollisionFrames +
3021 s->dot3StatsExcessiveCollisions +
3022 s->dot3StatsLateCollisions;
3023 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag,
3024 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_PREREAD);
3029 return (if_get_counter_default(ifp, cnt));
3034 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3035 * pointers to descriptors.
3038 ti_encap(struct ti_softc *sc, struct mbuf **m_head)
3040 struct ti_txdesc *txd;
3041 struct ti_tx_desc *f;
3042 struct ti_tx_desc txdesc;
3044 bus_dma_segment_t txsegs[TI_MAXTXSEGS];
3045 uint16_t csum_flags;
3046 int error, frag, i, nseg;
3048 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL)
3051 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
3052 *m_head, txsegs, &nseg, 0);
3053 if (error == EFBIG) {
3054 m = m_defrag(*m_head, M_NOWAIT);
3061 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag,
3062 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
3068 } else if (error != 0)
3076 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) {
3077 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap);
3080 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
3081 BUS_DMASYNC_PREWRITE);
3085 if (m->m_pkthdr.csum_flags & CSUM_IP)
3086 csum_flags |= TI_BDFLAG_IP_CKSUM;
3087 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3088 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
3090 frag = sc->ti_tx_saved_prodidx;
3091 for (i = 0; i < nseg; i++) {
3092 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3093 bzero(&txdesc, sizeof(txdesc));
3096 f = &sc->ti_rdata.ti_tx_ring[frag];
3097 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr);
3098 f->ti_len = txsegs[i].ds_len;
3099 f->ti_flags = csum_flags;
3100 if (m->m_flags & M_VLANTAG) {
3101 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
3102 f->ti_vlan_tag = m->m_pkthdr.ether_vtag;
3107 if (sc->ti_hwrev == TI_HWREV_TIGON)
3108 ti_mem_write(sc, TI_TX_RING_BASE + frag *
3109 sizeof(txdesc), sizeof(txdesc), &txdesc);
3110 TI_INC(frag, TI_TX_RING_CNT);
3113 sc->ti_tx_saved_prodidx = frag;
3114 /* set TI_BDFLAG_END on the last descriptor */
3115 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT;
3116 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3117 txdesc.ti_flags |= TI_BDFLAG_END;
3118 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc),
3119 sizeof(txdesc), &txdesc);
3121 sc->ti_rdata.ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END;
3123 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q);
3124 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q);
3126 sc->ti_txcnt += nseg;
3132 ti_start(struct ifnet *ifp)
3134 struct ti_softc *sc;
3138 ti_start_locked(ifp);
3143 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3144 * to the mbuf data regions directly in the transmit descriptors.
3147 ti_start_locked(struct ifnet *ifp)
3149 struct ti_softc *sc;
3150 struct mbuf *m_head = NULL;
3155 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
3156 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) {
3157 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3162 * Pack the data into the transmit ring. If we
3163 * don't have room, set the OACTIVE flag and wait
3164 * for the NIC to drain the ring.
3166 if (ti_encap(sc, &m_head)) {
3169 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3170 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3176 * If there's a BPF listener, bounce a copy of this frame
3179 ETHER_BPF_MTAP(ifp, m_head);
3183 if (sc->ti_rdata.ti_tx_ring != NULL)
3184 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
3185 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE);
3187 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx);
3190 * Set a timeout in case the chip goes out to lunch.
3199 struct ti_softc *sc;
3208 ti_init_locked(void *xsc)
3210 struct ti_softc *sc = xsc;
3212 if (sc->ti_ifp->if_drv_flags & IFF_DRV_RUNNING)
3215 /* Cancel pending I/O and flush buffers. */
3218 /* Init the gen info block, ring control blocks and firmware. */
3219 if (ti_gibinit(sc)) {
3220 device_printf(sc->ti_dev, "initialization failure\n");
3225 static void ti_init2(struct ti_softc *sc)
3227 struct ti_cmd_desc cmd;
3230 struct ifmedia *ifm;
3237 /* Specify MTU and interface index. */
3238 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev));
3239 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
3240 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
3241 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
3243 /* Load our MAC address. */
3244 ea = IF_LLADDR(sc->ti_ifp);
3245 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]);
3246 CSR_WRITE_4(sc, TI_GCR_PAR1,
3247 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]);
3248 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
3250 /* Enable or disable promiscuous mode as needed. */
3251 if (ifp->if_flags & IFF_PROMISC) {
3252 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
3254 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
3257 /* Program multicast filter. */
3261 * If this is a Tigon 1, we should tell the
3262 * firmware to use software packet filtering.
3264 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3265 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
3269 if (ti_init_rx_ring_std(sc) != 0) {
3271 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n");
3275 /* Init jumbo RX ring. */
3276 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) {
3277 if (ti_init_rx_ring_jumbo(sc) != 0) {
3279 device_printf(sc->ti_dev,
3280 "no memory for jumbo Rx buffers.\n");
3286 * If this is a Tigon 2, we can also configure the
3289 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
3290 if (ti_init_rx_ring_mini(sc) != 0) {
3292 device_printf(sc->ti_dev,
3293 "no memory for mini Rx buffers.\n");
3298 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
3299 sc->ti_rx_saved_considx = 0;
3302 ti_init_tx_ring(sc);
3304 /* Tell firmware we're alive. */
3305 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
3307 /* Enable host interrupts. */
3308 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3310 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3311 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3312 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3315 * Make sure to set media properly. We have to do this
3316 * here since we have to issue commands in order to set
3317 * the link negotiation and we can't issue commands until
3318 * the firmware is running.
3321 tmp = ifm->ifm_media;
3322 ifm->ifm_media = ifm->ifm_cur->ifm_media;
3323 ti_ifmedia_upd_locked(sc);
3324 ifm->ifm_media = tmp;
3328 * Set media options.
3331 ti_ifmedia_upd(struct ifnet *ifp)
3333 struct ti_softc *sc;
3338 error = ti_ifmedia_upd_locked(sc);
3345 ti_ifmedia_upd_locked(struct ti_softc *sc)
3347 struct ifmedia *ifm;
3348 struct ti_cmd_desc cmd;
3353 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3358 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3361 * Transmit flow control doesn't work on the Tigon 1.
3363 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3366 * Transmit flow control can also cause problems on the
3367 * Tigon 2, apparently with both the copper and fiber
3368 * boards. The symptom is that the interface will just
3369 * hang. This was reproduced with Alteon 180 switches.
3372 if (sc->ti_hwrev != TI_HWREV_TIGON)
3373 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3376 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3377 TI_GLNK_FULL_DUPLEX| flowctl |
3378 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
3380 flowctl = TI_LNK_RX_FLOWCTL_Y;
3382 if (sc->ti_hwrev != TI_HWREV_TIGON)
3383 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3386 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
3387 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
3388 TI_LNK_AUTONEGENB|TI_LNK_ENB);
3389 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3390 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
3394 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3396 if (sc->ti_hwrev != TI_HWREV_TIGON)
3397 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3400 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3401 flowctl |TI_GLNK_ENB);
3402 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
3403 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3404 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
3406 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3407 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3413 flowctl = TI_LNK_RX_FLOWCTL_Y;
3415 if (sc->ti_hwrev != TI_HWREV_TIGON)
3416 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3419 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3420 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3421 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3422 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3423 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3425 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3427 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3428 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3430 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3432 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3433 TI_CMD_CODE_NEGOTIATE_10_100, 0);
3441 * Report current media status.
3444 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3446 struct ti_softc *sc;
3453 ifmr->ifm_status = IFM_AVALID;
3454 ifmr->ifm_active = IFM_ETHER;
3456 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
3461 ifmr->ifm_status |= IFM_ACTIVE;
3463 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3464 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3466 ifmr->ifm_active |= IFM_1000_T;
3468 ifmr->ifm_active |= IFM_1000_SX;
3469 if (media & TI_GLNK_FULL_DUPLEX)
3470 ifmr->ifm_active |= IFM_FDX;
3472 ifmr->ifm_active |= IFM_HDX;
3473 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3474 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3475 if (sc->ti_copper) {
3476 if (media & TI_LNK_100MB)
3477 ifmr->ifm_active |= IFM_100_TX;
3478 if (media & TI_LNK_10MB)
3479 ifmr->ifm_active |= IFM_10_T;
3481 if (media & TI_LNK_100MB)
3482 ifmr->ifm_active |= IFM_100_FX;
3483 if (media & TI_LNK_10MB)
3484 ifmr->ifm_active |= IFM_10_FL;
3486 if (media & TI_LNK_FULL_DUPLEX)
3487 ifmr->ifm_active |= IFM_FDX;
3488 if (media & TI_LNK_HALF_DUPLEX)
3489 ifmr->ifm_active |= IFM_HDX;
3495 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3497 struct ti_softc *sc = ifp->if_softc;
3498 struct ifreq *ifr = (struct ifreq *) data;
3499 struct ti_cmd_desc cmd;
3500 int mask, error = 0;
3505 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU)
3508 ifp->if_mtu = ifr->ifr_mtu;
3509 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3510 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3518 if (ifp->if_flags & IFF_UP) {
3520 * If only the state of the PROMISC flag changed,
3521 * then just use the 'set promisc mode' command
3522 * instead of reinitializing the entire NIC. Doing
3523 * a full re-init means reloading the firmware and
3524 * waiting for it to start up, which may take a
3527 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3528 ifp->if_flags & IFF_PROMISC &&
3529 !(sc->ti_if_flags & IFF_PROMISC)) {
3530 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3531 TI_CMD_CODE_PROMISC_ENB, 0);
3532 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3533 !(ifp->if_flags & IFF_PROMISC) &&
3534 sc->ti_if_flags & IFF_PROMISC) {
3535 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3536 TI_CMD_CODE_PROMISC_DIS, 0);
3540 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3544 sc->ti_if_flags = ifp->if_flags;
3550 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3556 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3560 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3561 if ((mask & IFCAP_TXCSUM) != 0 &&
3562 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3563 ifp->if_capenable ^= IFCAP_TXCSUM;
3564 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3565 ifp->if_hwassist |= TI_CSUM_FEATURES;
3567 ifp->if_hwassist &= ~TI_CSUM_FEATURES;
3569 if ((mask & IFCAP_RXCSUM) != 0 &&
3570 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3571 ifp->if_capenable ^= IFCAP_RXCSUM;
3572 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3573 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0)
3574 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3575 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
3576 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
3577 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
3578 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM |
3579 IFCAP_VLAN_HWTAGGING)) != 0) {
3580 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3581 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3586 VLAN_CAPABILITIES(ifp);
3589 error = ether_ioctl(ifp, command, data);
3597 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3599 struct ti_softc *sc;
3606 sc->ti_flags |= TI_FLAG_DEBUGING;
3613 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3615 struct ti_softc *sc;
3622 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3629 * This ioctl routine goes along with the Tigon character device.
3632 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag,
3635 struct ti_softc *sc;
3647 struct ti_stats *outstats;
3649 outstats = (struct ti_stats *)addr;
3652 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag,
3653 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD);
3654 bcopy(&sc->ti_rdata.ti_info->ti_stats, outstats,
3655 sizeof(struct ti_stats));
3656 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag,
3657 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_PREREAD);
3661 case TIIOCGETPARAMS:
3663 struct ti_params *params;
3665 params = (struct ti_params *)addr;
3668 params->ti_stat_ticks = sc->ti_stat_ticks;
3669 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3670 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3671 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3672 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3673 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3674 params->param_mask = TI_PARAM_ALL;
3678 case TIIOCSETPARAMS:
3680 struct ti_params *params;
3682 params = (struct ti_params *)addr;
3685 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3686 sc->ti_stat_ticks = params->ti_stat_ticks;
3687 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3690 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3691 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3692 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3693 sc->ti_rx_coal_ticks);
3696 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3697 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3698 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3699 sc->ti_tx_coal_ticks);
3702 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3703 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3704 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3705 sc->ti_rx_max_coal_bds);
3708 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3709 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3710 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3711 sc->ti_tx_max_coal_bds);
3714 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3715 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3716 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3717 sc->ti_tx_buf_ratio);
3722 case TIIOCSETTRACE: {
3723 ti_trace_type trace_type;
3725 trace_type = *(ti_trace_type *)addr;
3728 * Set tracing to whatever the user asked for. Setting
3729 * this register to 0 should have the effect of disabling
3733 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3737 case TIIOCGETTRACE: {
3738 struct ti_trace_buf *trace_buf;
3739 uint32_t trace_start, cur_trace_ptr, trace_len;
3741 trace_buf = (struct ti_trace_buf *)addr;
3744 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3745 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3746 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3748 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, "
3749 "trace_len = %d\n", trace_start,
3750 cur_trace_ptr, trace_len);
3751 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n",
3752 trace_buf->buf_len);
3754 error = ti_copy_mem(sc, trace_start, min(trace_len,
3755 trace_buf->buf_len), (caddr_t)trace_buf->buf, 1, 1);
3757 trace_buf->fill_len = min(trace_len,
3758 trace_buf->buf_len);
3759 if (cur_trace_ptr < trace_start)
3760 trace_buf->cur_trace_ptr =
3761 trace_start - cur_trace_ptr;
3763 trace_buf->cur_trace_ptr =
3764 cur_trace_ptr - trace_start;
3766 trace_buf->fill_len = 0;
3772 * For debugging, five ioctls are needed:
3781 * From what I can tell, Alteon's Solaris Tigon driver
3782 * only has one character device, so you have to attach
3783 * to the Tigon board you're interested in. This seems
3784 * like a not-so-good way to do things, since unless you
3785 * subsequently specify the unit number of the device
3786 * you're interested in every ioctl, you'll only be
3787 * able to debug one board at a time.
3790 case ALT_READ_TG_MEM:
3791 case ALT_WRITE_TG_MEM:
3793 struct tg_mem *mem_param;
3794 uint32_t sram_end, scratch_end;
3796 mem_param = (struct tg_mem *)addr;
3798 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3799 sram_end = TI_END_SRAM_I;
3800 scratch_end = TI_END_SCRATCH_I;
3802 sram_end = TI_END_SRAM_II;
3803 scratch_end = TI_END_SCRATCH_II;
3807 * For now, we'll only handle accessing regular SRAM,
3811 if (mem_param->tgAddr >= TI_BEG_SRAM &&
3812 mem_param->tgAddr + mem_param->len <= sram_end) {
3814 * In this instance, we always copy to/from user
3815 * space, so the user space argument is set to 1.
3817 error = ti_copy_mem(sc, mem_param->tgAddr,
3818 mem_param->len, mem_param->userAddr, 1,
3819 cmd == ALT_READ_TG_MEM ? 1 : 0);
3820 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH &&
3821 mem_param->tgAddr <= scratch_end) {
3822 error = ti_copy_scratch(sc, mem_param->tgAddr,
3823 mem_param->len, mem_param->userAddr, 1,
3824 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_A);
3825 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG &&
3826 mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG) {
3827 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3828 if_printf(sc->ti_ifp,
3829 "invalid memory range for Tigon I\n");
3833 error = ti_copy_scratch(sc, mem_param->tgAddr -
3834 TI_SCRATCH_DEBUG_OFF, mem_param->len,
3835 mem_param->userAddr, 1,
3836 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_B);
3838 if_printf(sc->ti_ifp, "memory address %#x len %d is "
3839 "out of supported range\n",
3840 mem_param->tgAddr, mem_param->len);
3846 case ALT_READ_TG_REG:
3847 case ALT_WRITE_TG_REG:
3849 struct tg_reg *regs;
3852 regs = (struct tg_reg *)addr;
3855 * Make sure the address in question isn't out of range.
3857 if (regs->addr > TI_REG_MAX) {
3862 if (cmd == ALT_READ_TG_REG) {
3863 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3864 regs->addr, &tmpval, 1);
3865 regs->data = ntohl(tmpval);
3867 if ((regs->addr == TI_CPU_STATE)
3868 || (regs->addr == TI_CPU_CTL_B)) {
3869 if_printf(sc->ti_ifp, "register %#x = %#x\n",
3870 regs->addr, tmpval);
3874 tmpval = htonl(regs->data);
3875 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3876 regs->addr, &tmpval, 1);
3889 ti_watchdog(void *arg)
3891 struct ti_softc *sc;
3896 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3897 if (sc->ti_timer == 0 || --sc->ti_timer > 0)
3901 * When we're debugging, the chip is often stopped for long periods
3902 * of time, and that would normally cause the watchdog timer to fire.
3903 * Since that impedes debugging, we don't want to do that.
3905 if (sc->ti_flags & TI_FLAG_DEBUGING)
3909 if_printf(ifp, "watchdog timeout -- resetting\n");
3910 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3913 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3917 * Stop the adapter and free any mbufs allocated to the
3921 ti_stop(struct ti_softc *sc)
3924 struct ti_cmd_desc cmd;
3930 /* Disable host interrupts. */
3931 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3933 * Tell firmware we're shutting down.
3935 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3937 /* Halt and reinitialize. */
3938 if (ti_chipinit(sc) == 0) {
3939 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
3940 /* XXX ignore init errors. */
3944 /* Free the RX lists. */
3945 ti_free_rx_ring_std(sc);
3947 /* Free jumbo RX list. */
3948 ti_free_rx_ring_jumbo(sc);
3950 /* Free mini RX list. */
3951 ti_free_rx_ring_mini(sc);
3953 /* Free TX buffers. */
3954 ti_free_tx_ring(sc);
3956 sc->ti_ev_prodidx.ti_idx = 0;
3957 sc->ti_return_prodidx.ti_idx = 0;
3958 sc->ti_tx_considx.ti_idx = 0;
3959 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3961 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3962 callout_stop(&sc->ti_watchdog);
3966 * Stop all chip I/O so that the kernel's probe routines don't
3967 * get confused by errant DMAs when rebooting.
3970 ti_shutdown(device_t dev)
3972 struct ti_softc *sc;
3974 sc = device_get_softc(dev);
3983 ti_sysctl_node(struct ti_softc *sc)
3985 struct sysctl_ctx_list *ctx;
3986 struct sysctl_oid_list *child;
3989 ctx = device_get_sysctl_ctx(sc->ti_dev);
3990 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ti_dev));
3994 snprintf(tname, sizeof(tname), "dev.ti.%d.dac",
3995 device_get_unit(sc->ti_dev));
3996 TUNABLE_INT_FETCH(tname, &sc->ti_dac);
3998 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_coal_ticks", CTLFLAG_RW,
3999 &sc->ti_rx_coal_ticks, 0, "Receive coalcesced ticks");
4000 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_max_coal_bds", CTLFLAG_RW,
4001 &sc->ti_rx_max_coal_bds, 0, "Receive max coalcesced BDs");
4003 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_coal_ticks", CTLFLAG_RW,
4004 &sc->ti_tx_coal_ticks, 0, "Send coalcesced ticks");
4005 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_max_coal_bds", CTLFLAG_RW,
4006 &sc->ti_tx_max_coal_bds, 0, "Send max coalcesced BDs");
4007 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_buf_ratio", CTLFLAG_RW,
4008 &sc->ti_tx_buf_ratio, 0,
4009 "Ratio of NIC memory devoted to TX buffer");
4011 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stat_ticks", CTLFLAG_RW,
4012 &sc->ti_stat_ticks, 0,
4013 "Number of clock ticks for statistics update interval");
4015 /* Pull in device tunables. */
4016 sc->ti_rx_coal_ticks = 170;
4017 resource_int_value(device_get_name(sc->ti_dev),
4018 device_get_unit(sc->ti_dev), "rx_coal_ticks",
4019 &sc->ti_rx_coal_ticks);
4020 sc->ti_rx_max_coal_bds = 64;
4021 resource_int_value(device_get_name(sc->ti_dev),
4022 device_get_unit(sc->ti_dev), "rx_max_coal_bds",
4023 &sc->ti_rx_max_coal_bds);
4025 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
4026 resource_int_value(device_get_name(sc->ti_dev),
4027 device_get_unit(sc->ti_dev), "tx_coal_ticks",
4028 &sc->ti_tx_coal_ticks);
4029 sc->ti_tx_max_coal_bds = 32;
4030 resource_int_value(device_get_name(sc->ti_dev),
4031 device_get_unit(sc->ti_dev), "tx_max_coal_bds",
4032 &sc->ti_tx_max_coal_bds);
4033 sc->ti_tx_buf_ratio = 21;
4034 resource_int_value(device_get_name(sc->ti_dev),
4035 device_get_unit(sc->ti_dev), "tx_buf_ratio",
4036 &sc->ti_tx_buf_ratio);
4038 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
4039 resource_int_value(device_get_name(sc->ti_dev),
4040 device_get_unit(sc->ti_dev), "stat_ticks",
4041 &sc->ti_stat_ticks);