2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
35 * Manuals, sample driver and firmware source kits are available
36 * from http://www.alteon.com/support/openkits.
38 * Written by Bill Paul <wpaul@ctr.columbia.edu>
39 * Electrical Engineering Department
40 * Columbia University, New York City
44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
48 * filtering and jumbo (9014 byte) frames. The hardware is largely
49 * controlled by firmware, which must be loaded into the NIC during
52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
53 * revision, which supports new features such as extended commands,
54 * extended jumbo receive ring desciptors and a mini receive ring.
56 * Alteon Networks is to be commended for releasing such a vast amount
57 * of development material for the Tigon NIC without requiring an NDA
58 * (although they really should have done it a long time ago). With
59 * any luck, the other vendors will finally wise up and follow Alteon's
62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
63 * this driver by #including it as a C header file. This bloats the
64 * driver somewhat, but it's the easiest method considering that the
65 * driver code and firmware code need to be kept in sync. The source
66 * for the firmware is not provided with the FreeBSD distribution since
67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
69 * The following people deserve special thanks:
70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
72 * - Raymond Lee of Netgear, for providing a pair of Netgear
73 * GA620 Tigon 2 boards for testing
74 * - Ulf Zimmermann, for bringing the GA260 to my attention and
75 * convincing me to write this driver.
76 * - Andrew Gallatin for providing FreeBSD/Alpha support.
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/sockio.h>
88 #include <sys/malloc.h>
89 #include <sys/kernel.h>
90 #include <sys/module.h>
91 #include <sys/socket.h>
92 #include <sys/queue.h>
94 #include <sys/sf_buf.h>
97 #include <net/if_var.h>
98 #include <net/if_arp.h>
99 #include <net/ethernet.h>
100 #include <net/if_dl.h>
101 #include <net/if_media.h>
102 #include <net/if_types.h>
103 #include <net/if_vlan_var.h>
107 #include <netinet/in_systm.h>
108 #include <netinet/in.h>
109 #include <netinet/ip.h>
111 #include <machine/bus.h>
112 #include <machine/resource.h>
114 #include <sys/rman.h>
116 #ifdef TI_SF_BUF_JUMBO
118 #include <vm/vm_page.h>
121 #include <dev/pci/pcireg.h>
122 #include <dev/pci/pcivar.h>
124 #include <sys/tiio.h>
125 #include <dev/ti/if_tireg.h>
126 #include <dev/ti/ti_fw.h>
127 #include <dev/ti/ti_fw2.h>
129 #include <sys/sysctl.h>
131 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
133 * We can only turn on header splitting if we're using extended receive
136 #if defined(TI_JUMBO_HDRSPLIT) && !defined(TI_SF_BUF_JUMBO)
137 #error "options TI_JUMBO_HDRSPLIT requires TI_SF_BUF_JUMBO"
138 #endif /* TI_JUMBO_HDRSPLIT && !TI_SF_BUF_JUMBO */
146 * Various supported device vendors/types and their names.
149 static const struct ti_type ti_devs[] = {
150 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
151 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
152 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
153 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
154 { TC_VENDORID, TC_DEVICEID_3C985,
155 "3Com 3c985-SX Gigabit Ethernet" },
156 { NG_VENDORID, NG_DEVICEID_GA620,
157 "Netgear GA620 1000baseSX Gigabit Ethernet" },
158 { NG_VENDORID, NG_DEVICEID_GA620T,
159 "Netgear GA620 1000baseT Gigabit Ethernet" },
160 { SGI_VENDORID, SGI_DEVICEID_TIGON,
161 "Silicon Graphics Gigabit Ethernet" },
162 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
163 "Farallon PN9000SX Gigabit Ethernet" },
168 static d_open_t ti_open;
169 static d_close_t ti_close;
170 static d_ioctl_t ti_ioctl2;
172 static struct cdevsw ti_cdevsw = {
173 .d_version = D_VERSION,
177 .d_ioctl = ti_ioctl2,
181 static int ti_probe(device_t);
182 static int ti_attach(device_t);
183 static int ti_detach(device_t);
184 static void ti_txeof(struct ti_softc *);
185 static void ti_rxeof(struct ti_softc *);
187 static void ti_stats_update(struct ti_softc *);
188 static int ti_encap(struct ti_softc *, struct mbuf **);
190 static void ti_intr(void *);
191 static void ti_start(struct ifnet *);
192 static void ti_start_locked(struct ifnet *);
193 static int ti_ioctl(struct ifnet *, u_long, caddr_t);
194 static void ti_init(void *);
195 static void ti_init_locked(void *);
196 static void ti_init2(struct ti_softc *);
197 static void ti_stop(struct ti_softc *);
198 static void ti_watchdog(void *);
199 static int ti_shutdown(device_t);
200 static int ti_ifmedia_upd(struct ifnet *);
201 static int ti_ifmedia_upd_locked(struct ti_softc *);
202 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
204 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
205 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
206 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
208 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
209 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
210 static void ti_setmulti(struct ti_softc *);
212 static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *);
213 static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *);
214 static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t);
215 static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int,
217 static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t,
219 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
220 static void ti_loadfw(struct ti_softc *);
221 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
222 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
223 static void ti_handle_events(struct ti_softc *);
224 static void ti_dma_map_addr(void *, bus_dma_segment_t *, int, int);
225 static int ti_dma_alloc(struct ti_softc *);
226 static void ti_dma_free(struct ti_softc *);
227 static int ti_dma_ring_alloc(struct ti_softc *, bus_size_t, bus_size_t,
228 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
229 static void ti_dma_ring_free(struct ti_softc *, bus_dma_tag_t *, uint8_t **,
230 bus_dmamap_t, bus_addr_t *);
231 static int ti_newbuf_std(struct ti_softc *, int);
232 static int ti_newbuf_mini(struct ti_softc *, int);
233 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
234 static int ti_init_rx_ring_std(struct ti_softc *);
235 static void ti_free_rx_ring_std(struct ti_softc *);
236 static int ti_init_rx_ring_jumbo(struct ti_softc *);
237 static void ti_free_rx_ring_jumbo(struct ti_softc *);
238 static int ti_init_rx_ring_mini(struct ti_softc *);
239 static void ti_free_rx_ring_mini(struct ti_softc *);
240 static void ti_free_tx_ring(struct ti_softc *);
241 static int ti_init_tx_ring(struct ti_softc *);
242 static void ti_discard_std(struct ti_softc *, int);
243 #ifndef TI_SF_BUF_JUMBO
244 static void ti_discard_jumbo(struct ti_softc *, int);
246 static void ti_discard_mini(struct ti_softc *, int);
248 static int ti_64bitslot_war(struct ti_softc *);
249 static int ti_chipinit(struct ti_softc *);
250 static int ti_gibinit(struct ti_softc *);
252 #ifdef TI_JUMBO_HDRSPLIT
253 static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len,
255 #endif /* TI_JUMBO_HDRSPLIT */
257 static void ti_sysctl_node(struct ti_softc *);
259 static device_method_t ti_methods[] = {
260 /* Device interface */
261 DEVMETHOD(device_probe, ti_probe),
262 DEVMETHOD(device_attach, ti_attach),
263 DEVMETHOD(device_detach, ti_detach),
264 DEVMETHOD(device_shutdown, ti_shutdown),
268 static driver_t ti_driver = {
271 sizeof(struct ti_softc)
274 static devclass_t ti_devclass;
276 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
277 MODULE_DEPEND(ti, pci, 1, 1, 1);
278 MODULE_DEPEND(ti, ether, 1, 1, 1);
281 * Send an instruction or address to the EEPROM, check for ACK.
284 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
289 * Make sure we're in TX mode.
291 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
294 * Feed in each bit and stobe the clock.
296 for (i = 0x80; i; i >>= 1) {
298 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
300 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
303 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
305 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
311 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
316 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
317 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
318 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
324 * Read a byte of data stored in the EEPROM at address 'addr.'
325 * We have to send two address bytes since the EEPROM can hold
326 * more than 256 bytes of data.
329 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
337 * Send write control code to EEPROM.
339 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
340 device_printf(sc->ti_dev,
341 "failed to send write command, status: %x\n",
342 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
347 * Send first byte of address of byte we want to read.
349 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
350 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
351 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
355 * Send second byte address of byte we want to read.
357 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
358 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
359 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
366 * Send read control code to EEPROM.
368 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
369 device_printf(sc->ti_dev,
370 "failed to send read command, status: %x\n",
371 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
376 * Start reading bits from EEPROM.
378 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
379 for (i = 0x80; i; i >>= 1) {
380 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
382 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
384 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
391 * No ACK generated for read, so just return byte.
400 * Read a sequence of bytes from the EEPROM.
403 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
408 for (i = 0; i < cnt; i++) {
409 err = ti_eeprom_getbyte(sc, off + i, &byte);
415 return (err ? 1 : 0);
419 * NIC memory read function.
420 * Can be used to copy data from NIC local memory.
423 ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
425 int segptr, segsize, cnt;
436 segsize = TI_WINLEN - (segptr % TI_WINLEN);
437 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
438 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
439 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
449 * NIC memory write function.
450 * Can be used to copy data into NIC local memory.
453 ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
455 int segptr, segsize, cnt;
466 segsize = TI_WINLEN - (segptr % TI_WINLEN);
467 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
468 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
469 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
478 * NIC memory read function.
479 * Can be used to clear a section of NIC local memory.
482 ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len)
484 int segptr, segsize, cnt;
493 segsize = TI_WINLEN - (segptr % TI_WINLEN);
494 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
495 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
496 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4);
503 ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
504 caddr_t buf, int useraddr, int readdata)
506 int segptr, segsize, cnt;
515 * At the moment, we don't handle non-aligned cases, we just bail.
516 * If this proves to be a problem, it will be fixed.
518 if (readdata == 0 && (tigon_addr & 0x3) != 0) {
519 device_printf(sc->ti_dev, "%s: tigon address %#x isn't "
520 "word-aligned\n", __func__, tigon_addr);
521 device_printf(sc->ti_dev, "%s: unaligned writes aren't "
522 "yet supported\n", __func__);
526 segptr = tigon_addr & ~0x3;
527 segresid = tigon_addr - segptr;
530 * This is the non-aligned amount left over that we'll need to
535 /* Add in the left over amount at the front of the buffer */
540 * If resid + segresid is >= 4, add multiples of 4 to the count and
541 * decrease the residual by that much.
544 resid -= resid & ~0x3;
551 * Save the old window base value.
553 origwin = CSR_READ_4(sc, TI_WINBASE);
556 bus_size_t ti_offset;
561 segsize = TI_WINLEN - (segptr % TI_WINLEN);
562 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
564 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
567 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
568 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2);
571 * Yeah, this is a little on the kludgy
572 * side, but at least this code is only
573 * used for debugging.
575 ti_bcopy_swap(sc->ti_membuf, sc->ti_membuf2,
576 segsize, TI_SWAP_NTOH);
580 copyout(&sc->ti_membuf2[segresid], ptr,
584 copyout(sc->ti_membuf2, ptr, segsize);
589 ti_bcopy_swap(sc->ti_membuf,
590 sc->ti_membuf2, segsize,
593 bcopy(&sc->ti_membuf2[segresid], ptr,
598 ti_bcopy_swap(sc->ti_membuf, ptr,
599 segsize, TI_SWAP_NTOH);
605 copyin(ptr, sc->ti_membuf2, segsize);
607 ti_bcopy_swap(sc->ti_membuf2, sc->ti_membuf,
608 segsize, TI_SWAP_HTON);
610 ti_bcopy_swap(ptr, sc->ti_membuf, segsize,
613 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
614 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2);
622 * Handle leftover, non-word-aligned bytes.
625 uint32_t tmpval, tmpval2;
626 bus_size_t ti_offset;
629 * Set the segment pointer.
631 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
633 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
636 * First, grab whatever is in our source/destination.
637 * We'll obviously need this for reads, but also for
638 * writes, since we'll be doing read/modify/write.
640 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
641 ti_offset, &tmpval, 1);
644 * Next, translate this from little-endian to big-endian
645 * (at least on i386 boxes).
647 tmpval2 = ntohl(tmpval);
651 * If we're reading, just copy the leftover number
652 * of bytes from the host byte order buffer to
657 copyout(&tmpval2, ptr, resid);
660 bcopy(&tmpval2, ptr, resid);
663 * If we're writing, first copy the bytes to be
664 * written into the network byte order buffer,
665 * leaving the rest of the buffer with whatever was
666 * originally in there. Then, swap the bytes
667 * around into host order and write them out.
669 * XXX KDM the read side of this has been verified
670 * to work, but the write side of it has not been
671 * verified. So user beware.
675 copyin(ptr, &tmpval2, resid);
678 bcopy(ptr, &tmpval2, resid);
680 tmpval = htonl(tmpval2);
682 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
683 ti_offset, &tmpval, 1);
687 CSR_WRITE_4(sc, TI_WINBASE, origwin);
693 ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
694 caddr_t buf, int useraddr, int readdata, int cpu)
698 uint32_t tmpval, tmpval2;
704 * At the moment, we don't handle non-aligned cases, we just bail.
705 * If this proves to be a problem, it will be fixed.
707 if (tigon_addr & 0x3) {
708 device_printf(sc->ti_dev, "%s: tigon address %#x "
709 "isn't word-aligned\n", __func__, tigon_addr);
714 device_printf(sc->ti_dev, "%s: transfer length %d "
715 "isn't word-aligned\n", __func__, len);
724 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
727 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
729 tmpval = ntohl(tmpval2);
732 * Note: I've used this debugging interface
733 * extensively with Alteon's 12.3.15 firmware,
734 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
736 * When you compile the firmware without
737 * optimization, which is necessary sometimes in
738 * order to properly step through it, you sometimes
739 * read out a bogus value of 0xc0017c instead of
740 * whatever was supposed to be in that scratchpad
741 * location. That value is on the stack somewhere,
742 * but I've never been able to figure out what was
743 * causing the problem.
745 * The address seems to pop up in random places,
746 * often not in the same place on two subsequent
749 * In any case, the underlying data doesn't seem
750 * to be affected, just the value read out.
755 if (tmpval2 == 0xc0017c)
756 device_printf(sc->ti_dev, "found 0xc0017c at "
757 "%#x (tmpval2)\n", segptr);
759 if (tmpval == 0xc0017c)
760 device_printf(sc->ti_dev, "found 0xc0017c at "
761 "%#x (tmpval)\n", segptr);
764 copyout(&tmpval, ptr, 4);
766 bcopy(&tmpval, ptr, 4);
769 copyin(ptr, &tmpval2, 4);
771 bcopy(ptr, &tmpval2, 4);
773 tmpval = htonl(tmpval2);
775 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
787 ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type)
789 const uint8_t *tmpsrc;
794 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", len);
803 if (swap_type == TI_SWAP_NTOH)
804 *(uint32_t *)tmpdst = ntohl(*(const uint32_t *)tmpsrc);
806 *(uint32_t *)tmpdst = htonl(*(const uint32_t *)tmpsrc);
816 * Load firmware image into the NIC. Check that the firmware revision
817 * is acceptable and see if we want the firmware for the Tigon 1 or
821 ti_loadfw(struct ti_softc *sc)
826 switch (sc->ti_hwrev) {
828 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
829 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
830 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
831 device_printf(sc->ti_dev, "firmware revision mismatch; "
832 "want %d.%d.%d, got %d.%d.%d\n",
833 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
834 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
835 tigonFwReleaseMinor, tigonFwReleaseFix);
838 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
839 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
840 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen,
842 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen);
843 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen);
844 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
846 case TI_HWREV_TIGON_II:
847 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
848 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
849 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
850 device_printf(sc->ti_dev, "firmware revision mismatch; "
851 "want %d.%d.%d, got %d.%d.%d\n",
852 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
853 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
854 tigon2FwReleaseMinor, tigon2FwReleaseFix);
857 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen,
859 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen,
861 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
863 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen);
864 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen);
865 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
868 device_printf(sc->ti_dev,
869 "can't load firmware: unknown hardware rev\n");
875 * Send the NIC a command via the command ring.
878 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
882 index = sc->ti_cmd_saved_prodidx;
883 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
884 TI_INC(index, TI_CMD_RING_CNT);
885 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
886 sc->ti_cmd_saved_prodidx = index;
890 * Send the NIC an extended command. The 'len' parameter specifies the
891 * number of command slots to include after the initial command.
894 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len)
899 index = sc->ti_cmd_saved_prodidx;
900 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
901 TI_INC(index, TI_CMD_RING_CNT);
902 for (i = 0; i < len; i++) {
903 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
904 *(uint32_t *)(&arg[i * 4]));
905 TI_INC(index, TI_CMD_RING_CNT);
907 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
908 sc->ti_cmd_saved_prodidx = index;
912 * Handle events that have triggered interrupts.
915 ti_handle_events(struct ti_softc *sc)
917 struct ti_event_desc *e;
919 if (sc->ti_rdata.ti_event_ring == NULL)
922 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag,
923 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_POSTREAD);
924 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
925 e = &sc->ti_rdata.ti_event_ring[sc->ti_ev_saved_considx];
926 switch (TI_EVENT_EVENT(e)) {
927 case TI_EV_LINKSTAT_CHANGED:
928 sc->ti_linkstat = TI_EVENT_CODE(e);
929 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
930 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
931 sc->ti_ifp->if_baudrate = IF_Mbps(100);
933 device_printf(sc->ti_dev,
935 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
936 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
937 sc->ti_ifp->if_baudrate = IF_Gbps(1UL);
939 device_printf(sc->ti_dev,
940 "gigabit link up\n");
941 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
942 if_link_state_change(sc->ti_ifp,
944 sc->ti_ifp->if_baudrate = 0;
946 device_printf(sc->ti_dev,
951 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
952 device_printf(sc->ti_dev, "invalid command\n");
953 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
954 device_printf(sc->ti_dev, "unknown command\n");
955 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
956 device_printf(sc->ti_dev, "bad config data\n");
958 case TI_EV_FIRMWARE_UP:
961 case TI_EV_STATS_UPDATED:
964 case TI_EV_RESET_JUMBO_RING:
965 case TI_EV_MCAST_UPDATED:
969 device_printf(sc->ti_dev, "unknown event: %d\n",
973 /* Advance the consumer index. */
974 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
975 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
977 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag,
978 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_PREREAD);
981 struct ti_dmamap_arg {
982 bus_addr_t ti_busaddr;
986 ti_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
988 struct ti_dmamap_arg *ctx;
993 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
996 ctx->ti_busaddr = segs->ds_addr;
1000 ti_dma_ring_alloc(struct ti_softc *sc, bus_size_t alignment, bus_size_t maxsize,
1001 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr,
1004 struct ti_dmamap_arg ctx;
1007 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag,
1008 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1009 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
1011 device_printf(sc->ti_dev,
1012 "could not create %s dma tag\n", msg);
1015 /* Allocate DMA'able memory for ring. */
1016 error = bus_dmamem_alloc(*tag, (void **)ring,
1017 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
1019 device_printf(sc->ti_dev,
1020 "could not allocate DMA'able memory for %s\n", msg);
1023 /* Load the address of the ring. */
1025 error = bus_dmamap_load(*tag, *map, *ring, maxsize, ti_dma_map_addr,
1026 &ctx, BUS_DMA_NOWAIT);
1028 device_printf(sc->ti_dev,
1029 "could not load DMA'able memory for %s\n", msg);
1032 *paddr = ctx.ti_busaddr;
1037 ti_dma_ring_free(struct ti_softc *sc, bus_dma_tag_t *tag, uint8_t **ring,
1038 bus_dmamap_t map, bus_addr_t *paddr)
1042 bus_dmamap_unload(*tag, map);
1045 if (*ring != NULL) {
1046 bus_dmamem_free(*tag, *ring, map);
1050 bus_dma_tag_destroy(*tag);
1056 ti_dma_alloc(struct ti_softc *sc)
1061 lowaddr = BUS_SPACE_MAXADDR;
1062 if (sc->ti_dac == 0)
1063 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1065 error = bus_dma_tag_create(bus_get_dma_tag(sc->ti_dev), 1, 0, lowaddr,
1066 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
1067 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
1068 &sc->ti_cdata.ti_parent_tag);
1070 device_printf(sc->ti_dev,
1071 "could not allocate parent dma tag\n");
1075 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_gib),
1076 &sc->ti_cdata.ti_gib_tag, (uint8_t **)&sc->ti_rdata.ti_info,
1077 &sc->ti_cdata.ti_gib_map, &sc->ti_rdata.ti_info_paddr, "GIB");
1081 /* Producer/consumer status */
1082 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_status),
1083 &sc->ti_cdata.ti_status_tag, (uint8_t **)&sc->ti_rdata.ti_status,
1084 &sc->ti_cdata.ti_status_map, &sc->ti_rdata.ti_status_paddr,
1090 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_EVENT_RING_SZ,
1091 &sc->ti_cdata.ti_event_ring_tag,
1092 (uint8_t **)&sc->ti_rdata.ti_event_ring,
1093 &sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr,
1098 /* Command ring lives in shared memory so no need to create DMA area. */
1100 /* Standard RX ring */
1101 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_STD_RX_RING_SZ,
1102 &sc->ti_cdata.ti_rx_std_ring_tag,
1103 (uint8_t **)&sc->ti_rdata.ti_rx_std_ring,
1104 &sc->ti_cdata.ti_rx_std_ring_map,
1105 &sc->ti_rdata.ti_rx_std_ring_paddr, "RX ring");
1110 error = ti_dma_ring_alloc(sc, TI_JUMBO_RING_ALIGN, TI_JUMBO_RX_RING_SZ,
1111 &sc->ti_cdata.ti_rx_jumbo_ring_tag,
1112 (uint8_t **)&sc->ti_rdata.ti_rx_jumbo_ring,
1113 &sc->ti_cdata.ti_rx_jumbo_ring_map,
1114 &sc->ti_rdata.ti_rx_jumbo_ring_paddr, "jumbo RX ring");
1118 /* RX return ring */
1119 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_RX_RETURN_RING_SZ,
1120 &sc->ti_cdata.ti_rx_return_ring_tag,
1121 (uint8_t **)&sc->ti_rdata.ti_rx_return_ring,
1122 &sc->ti_cdata.ti_rx_return_ring_map,
1123 &sc->ti_rdata.ti_rx_return_ring_paddr, "RX return ring");
1127 /* Create DMA tag for standard RX mbufs. */
1128 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1129 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1130 MCLBYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_std_tag);
1132 device_printf(sc->ti_dev, "could not allocate RX dma tag\n");
1136 /* Create DMA tag for jumbo RX mbufs. */
1137 #ifdef TI_SF_BUF_JUMBO
1139 * The VM system will take care of providing aligned pages. Alignment
1140 * is set to 1 here so that busdma resources won't be wasted.
1142 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1143 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE * 4, 4,
1144 PAGE_SIZE, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag);
1146 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1147 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MJUM9BYTES, 1,
1148 MJUM9BYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag);
1151 device_printf(sc->ti_dev,
1152 "could not allocate jumbo RX dma tag\n");
1156 /* Create DMA tag for TX mbufs. */
1157 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1,
1158 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1159 MCLBYTES * TI_MAXTXSEGS, TI_MAXTXSEGS, MCLBYTES, 0, NULL, NULL,
1160 &sc->ti_cdata.ti_tx_tag);
1162 device_printf(sc->ti_dev, "could not allocate TX dma tag\n");
1166 /* Create DMA maps for RX buffers. */
1167 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1168 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0,
1169 &sc->ti_cdata.ti_rx_std_maps[i]);
1171 device_printf(sc->ti_dev,
1172 "could not create DMA map for RX\n");
1176 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0,
1177 &sc->ti_cdata.ti_rx_std_sparemap);
1179 device_printf(sc->ti_dev,
1180 "could not create spare DMA map for RX\n");
1184 /* Create DMA maps for jumbo RX buffers. */
1185 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1186 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0,
1187 &sc->ti_cdata.ti_rx_jumbo_maps[i]);
1189 device_printf(sc->ti_dev,
1190 "could not create DMA map for jumbo RX\n");
1194 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0,
1195 &sc->ti_cdata.ti_rx_jumbo_sparemap);
1197 device_printf(sc->ti_dev,
1198 "could not create spare DMA map for jumbo RX\n");
1202 /* Create DMA maps for TX buffers. */
1203 for (i = 0; i < TI_TX_RING_CNT; i++) {
1204 error = bus_dmamap_create(sc->ti_cdata.ti_tx_tag, 0,
1205 &sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1207 device_printf(sc->ti_dev,
1208 "could not create DMA map for TX\n");
1213 /* Mini ring and TX ring is not available on Tigon 1. */
1214 if (sc->ti_hwrev == TI_HWREV_TIGON)
1218 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_TX_RING_SZ,
1219 &sc->ti_cdata.ti_tx_ring_tag, (uint8_t **)&sc->ti_rdata.ti_tx_ring,
1220 &sc->ti_cdata.ti_tx_ring_map, &sc->ti_rdata.ti_tx_ring_paddr,
1226 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_MINI_RX_RING_SZ,
1227 &sc->ti_cdata.ti_rx_mini_ring_tag,
1228 (uint8_t **)&sc->ti_rdata.ti_rx_mini_ring,
1229 &sc->ti_cdata.ti_rx_mini_ring_map,
1230 &sc->ti_rdata.ti_rx_mini_ring_paddr, "mini RX ring");
1234 /* Create DMA tag for mini RX mbufs. */
1235 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1236 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1,
1237 MHLEN, 0, NULL, NULL, &sc->ti_cdata.ti_rx_mini_tag);
1239 device_printf(sc->ti_dev,
1240 "could not allocate mini RX dma tag\n");
1244 /* Create DMA maps for mini RX buffers. */
1245 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1246 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0,
1247 &sc->ti_cdata.ti_rx_mini_maps[i]);
1249 device_printf(sc->ti_dev,
1250 "could not create DMA map for mini RX\n");
1254 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0,
1255 &sc->ti_cdata.ti_rx_mini_sparemap);
1257 device_printf(sc->ti_dev,
1258 "could not create spare DMA map for mini RX\n");
1266 ti_dma_free(struct ti_softc *sc)
1270 /* Destroy DMA maps for RX buffers. */
1271 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1272 if (sc->ti_cdata.ti_rx_std_maps[i]) {
1273 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag,
1274 sc->ti_cdata.ti_rx_std_maps[i]);
1275 sc->ti_cdata.ti_rx_std_maps[i] = NULL;
1278 if (sc->ti_cdata.ti_rx_std_sparemap) {
1279 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag,
1280 sc->ti_cdata.ti_rx_std_sparemap);
1281 sc->ti_cdata.ti_rx_std_sparemap = NULL;
1283 if (sc->ti_cdata.ti_rx_std_tag) {
1284 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_std_tag);
1285 sc->ti_cdata.ti_rx_std_tag = NULL;
1288 /* Destroy DMA maps for jumbo RX buffers. */
1289 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1290 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) {
1291 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag,
1292 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1293 sc->ti_cdata.ti_rx_jumbo_maps[i] = NULL;
1296 if (sc->ti_cdata.ti_rx_jumbo_sparemap) {
1297 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag,
1298 sc->ti_cdata.ti_rx_jumbo_sparemap);
1299 sc->ti_cdata.ti_rx_jumbo_sparemap = NULL;
1301 if (sc->ti_cdata.ti_rx_jumbo_tag) {
1302 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_jumbo_tag);
1303 sc->ti_cdata.ti_rx_jumbo_tag = NULL;
1306 /* Destroy DMA maps for mini RX buffers. */
1307 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1308 if (sc->ti_cdata.ti_rx_mini_maps[i]) {
1309 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag,
1310 sc->ti_cdata.ti_rx_mini_maps[i]);
1311 sc->ti_cdata.ti_rx_mini_maps[i] = NULL;
1314 if (sc->ti_cdata.ti_rx_mini_sparemap) {
1315 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag,
1316 sc->ti_cdata.ti_rx_mini_sparemap);
1317 sc->ti_cdata.ti_rx_mini_sparemap = NULL;
1319 if (sc->ti_cdata.ti_rx_mini_tag) {
1320 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_mini_tag);
1321 sc->ti_cdata.ti_rx_mini_tag = NULL;
1324 /* Destroy DMA maps for TX buffers. */
1325 for (i = 0; i < TI_TX_RING_CNT; i++) {
1326 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) {
1327 bus_dmamap_destroy(sc->ti_cdata.ti_tx_tag,
1328 sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1329 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL;
1332 if (sc->ti_cdata.ti_tx_tag) {
1333 bus_dma_tag_destroy(sc->ti_cdata.ti_tx_tag);
1334 sc->ti_cdata.ti_tx_tag = NULL;
1337 /* Destroy standard RX ring. */
1338 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_std_ring_tag,
1339 (void *)&sc->ti_rdata.ti_rx_std_ring,
1340 sc->ti_cdata.ti_rx_std_ring_map,
1341 &sc->ti_rdata.ti_rx_std_ring_paddr);
1342 /* Destroy jumbo RX ring. */
1343 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_jumbo_ring_tag,
1344 (void *)&sc->ti_rdata.ti_rx_jumbo_ring,
1345 sc->ti_cdata.ti_rx_jumbo_ring_map,
1346 &sc->ti_rdata.ti_rx_jumbo_ring_paddr);
1347 /* Destroy mini RX ring. */
1348 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_mini_ring_tag,
1349 (void *)&sc->ti_rdata.ti_rx_mini_ring,
1350 sc->ti_cdata.ti_rx_mini_ring_map,
1351 &sc->ti_rdata.ti_rx_mini_ring_paddr);
1352 /* Destroy RX return ring. */
1353 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_return_ring_tag,
1354 (void *)&sc->ti_rdata.ti_rx_return_ring,
1355 sc->ti_cdata.ti_rx_return_ring_map,
1356 &sc->ti_rdata.ti_rx_return_ring_paddr);
1357 /* Destroy TX ring. */
1358 ti_dma_ring_free(sc, &sc->ti_cdata.ti_tx_ring_tag,
1359 (void *)&sc->ti_rdata.ti_tx_ring, sc->ti_cdata.ti_tx_ring_map,
1360 &sc->ti_rdata.ti_tx_ring_paddr);
1361 /* Destroy status block. */
1362 ti_dma_ring_free(sc, &sc->ti_cdata.ti_status_tag,
1363 (void *)&sc->ti_rdata.ti_status, sc->ti_cdata.ti_status_map,
1364 &sc->ti_rdata.ti_status_paddr);
1365 /* Destroy event ring. */
1366 ti_dma_ring_free(sc, &sc->ti_cdata.ti_event_ring_tag,
1367 (void *)&sc->ti_rdata.ti_event_ring,
1368 sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr);
1370 ti_dma_ring_free(sc, &sc->ti_cdata.ti_gib_tag,
1371 (void *)&sc->ti_rdata.ti_info, sc->ti_cdata.ti_gib_map,
1372 &sc->ti_rdata.ti_info_paddr);
1374 /* Destroy the parent tag. */
1375 if (sc->ti_cdata.ti_parent_tag) {
1376 bus_dma_tag_destroy(sc->ti_cdata.ti_parent_tag);
1377 sc->ti_cdata.ti_parent_tag = NULL;
1382 * Intialize a standard receive ring descriptor.
1385 ti_newbuf_std(struct ti_softc *sc, int i)
1388 bus_dma_segment_t segs[1];
1390 struct ti_rx_desc *r;
1393 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1396 m->m_len = m->m_pkthdr.len = MCLBYTES;
1397 m_adj(m, ETHER_ALIGN);
1399 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_std_tag,
1400 sc->ti_cdata.ti_rx_std_sparemap, m, segs, &nsegs, 0);
1405 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1407 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1408 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag,
1409 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_POSTREAD);
1410 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag,
1411 sc->ti_cdata.ti_rx_std_maps[i]);
1414 map = sc->ti_cdata.ti_rx_std_maps[i];
1415 sc->ti_cdata.ti_rx_std_maps[i] = sc->ti_cdata.ti_rx_std_sparemap;
1416 sc->ti_cdata.ti_rx_std_sparemap = map;
1417 sc->ti_cdata.ti_rx_std_chain[i] = m;
1419 r = &sc->ti_rdata.ti_rx_std_ring[i];
1420 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1421 r->ti_len = segs[0].ds_len;
1422 r->ti_type = TI_BDTYPE_RECV_BD;
1425 r->ti_tcp_udp_cksum = 0;
1426 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1427 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1430 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag,
1431 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_PREREAD);
1436 * Intialize a mini receive ring descriptor. This only applies to
1440 ti_newbuf_mini(struct ti_softc *sc, int i)
1443 bus_dma_segment_t segs[1];
1445 struct ti_rx_desc *r;
1448 MGETHDR(m, M_NOWAIT, MT_DATA);
1451 m->m_len = m->m_pkthdr.len = MHLEN;
1452 m_adj(m, ETHER_ALIGN);
1454 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_mini_tag,
1455 sc->ti_cdata.ti_rx_mini_sparemap, m, segs, &nsegs, 0);
1460 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1462 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1463 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag,
1464 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_POSTREAD);
1465 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag,
1466 sc->ti_cdata.ti_rx_mini_maps[i]);
1469 map = sc->ti_cdata.ti_rx_mini_maps[i];
1470 sc->ti_cdata.ti_rx_mini_maps[i] = sc->ti_cdata.ti_rx_mini_sparemap;
1471 sc->ti_cdata.ti_rx_mini_sparemap = map;
1472 sc->ti_cdata.ti_rx_mini_chain[i] = m;
1474 r = &sc->ti_rdata.ti_rx_mini_ring[i];
1475 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1476 r->ti_len = segs[0].ds_len;
1477 r->ti_type = TI_BDTYPE_RECV_BD;
1478 r->ti_flags = TI_BDFLAG_MINI_RING;
1480 r->ti_tcp_udp_cksum = 0;
1481 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1482 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1485 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag,
1486 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_PREREAD);
1490 #ifndef TI_SF_BUF_JUMBO
1493 * Initialize a jumbo receive ring descriptor. This allocates
1494 * a jumbo buffer from the pool managed internally by the driver.
1497 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *dummy)
1500 bus_dma_segment_t segs[1];
1502 struct ti_rx_desc *r;
1507 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1510 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1511 m_adj(m, ETHER_ALIGN);
1513 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag,
1514 sc->ti_cdata.ti_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1519 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1521 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1522 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag,
1523 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_POSTREAD);
1524 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag,
1525 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1528 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1529 sc->ti_cdata.ti_rx_jumbo_maps[i] = sc->ti_cdata.ti_rx_jumbo_sparemap;
1530 sc->ti_cdata.ti_rx_jumbo_sparemap = map;
1531 sc->ti_cdata.ti_rx_jumbo_chain[i] = m;
1533 r = &sc->ti_rdata.ti_rx_jumbo_ring[i];
1534 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1535 r->ti_len = segs[0].ds_len;
1536 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1537 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1539 r->ti_tcp_udp_cksum = 0;
1540 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1541 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1544 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag,
1545 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_PREREAD);
1551 #if (PAGE_SIZE == 4096)
1557 #define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1558 #define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1559 #define NFS_HDR_LEN (UDP_HDR_LEN)
1560 static int HDR_LEN = TCP_HDR_LEN;
1563 * Initialize a jumbo receive ring descriptor. This allocates
1564 * a jumbo buffer from the pool managed internally by the driver.
1567 ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old)
1570 struct mbuf *cur, *m_new = NULL;
1571 struct mbuf *m[3] = {NULL, NULL, NULL};
1572 struct ti_rx_desc_ext *r;
1574 /* 1 extra buf to make nobufs easy*/
1575 struct sf_buf *sf[3] = {NULL, NULL, NULL};
1577 bus_dma_segment_t segs[4];
1580 if (m_old != NULL) {
1582 cur = m_old->m_next;
1583 for (i = 0; i <= NPAYLOAD; i++){
1588 /* Allocate the mbufs. */
1589 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1590 if (m_new == NULL) {
1591 device_printf(sc->ti_dev, "mbuf allocation failed "
1592 "-- packet dropped!\n");
1595 MGET(m[NPAYLOAD], M_NOWAIT, MT_DATA);
1596 if (m[NPAYLOAD] == NULL) {
1597 device_printf(sc->ti_dev, "cluster mbuf allocation "
1598 "failed -- packet dropped!\n");
1601 MCLGET(m[NPAYLOAD], M_NOWAIT);
1602 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1603 device_printf(sc->ti_dev, "mbuf allocation failed "
1604 "-- packet dropped!\n");
1607 m[NPAYLOAD]->m_len = MCLBYTES;
1609 for (i = 0; i < NPAYLOAD; i++){
1610 MGET(m[i], M_NOWAIT, MT_DATA);
1612 device_printf(sc->ti_dev, "mbuf allocation "
1613 "failed -- packet dropped!\n");
1616 frame = vm_page_alloc(NULL, 0,
1617 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1619 if (frame == NULL) {
1620 device_printf(sc->ti_dev, "buffer allocation "
1621 "failed -- packet dropped!\n");
1622 printf(" index %d page %d\n", idx, i);
1625 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1626 if (sf[i] == NULL) {
1627 vm_page_unwire(frame, PQ_INACTIVE);
1628 vm_page_free(frame);
1629 device_printf(sc->ti_dev, "buffer allocation "
1630 "failed -- packet dropped!\n");
1631 printf(" index %d page %d\n", idx, i);
1635 for (i = 0; i < NPAYLOAD; i++){
1636 /* Attach the buffer to the mbuf. */
1637 m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1638 m[i]->m_len = PAGE_SIZE;
1639 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1640 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i],
1642 m[i]->m_next = m[i+1];
1644 /* link the buffers to the header */
1645 m_new->m_next = m[0];
1646 m_new->m_data += ETHER_ALIGN;
1647 if (sc->ti_hdrsplit)
1648 m_new->m_len = MHLEN - ETHER_ALIGN;
1650 m_new->m_len = HDR_LEN;
1651 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1654 /* Set up the descriptor. */
1655 r = &sc->ti_rdata.ti_rx_jumbo_ring[idx];
1656 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1657 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1658 if (bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, map, m_new,
1661 if ((nsegs < 1) || (nsegs > 4))
1663 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr);
1664 r->ti_len0 = m_new->m_len;
1666 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr);
1667 r->ti_len1 = PAGE_SIZE;
1669 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr);
1670 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1672 if (PAGE_SIZE == 4096) {
1673 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr);
1674 r->ti_len3 = MCLBYTES;
1678 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1680 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1682 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1683 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1687 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, BUS_DMASYNC_PREREAD);
1694 * This can only be called before the mbufs are strung together.
1695 * If the mbufs are strung together, m_freem() will free the chain,
1696 * so that the later mbufs will be freed multiple times.
1701 for (i = 0; i < 3; i++) {
1705 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
1712 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1713 * that's 1MB or memory, which is a lot. For now, we fill only the first
1714 * 256 ring entries and hope that our CPU is fast enough to keep up with
1718 ti_init_rx_ring_std(struct ti_softc *sc)
1721 struct ti_cmd_desc cmd;
1723 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1724 if (ti_newbuf_std(sc, i) != 0)
1728 sc->ti_std = TI_STD_RX_RING_CNT - 1;
1729 TI_UPDATE_STDPROD(sc, TI_STD_RX_RING_CNT - 1);
1735 ti_free_rx_ring_std(struct ti_softc *sc)
1740 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1741 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1742 map = sc->ti_cdata.ti_rx_std_maps[i];
1743 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, map,
1744 BUS_DMASYNC_POSTREAD);
1745 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, map);
1746 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1747 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1750 bzero(sc->ti_rdata.ti_rx_std_ring, TI_STD_RX_RING_SZ);
1751 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag,
1752 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1756 ti_init_rx_ring_jumbo(struct ti_softc *sc)
1758 struct ti_cmd_desc cmd;
1761 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1762 if (ti_newbuf_jumbo(sc, i, NULL) != 0)
1766 sc->ti_jumbo = TI_JUMBO_RX_RING_CNT - 1;
1767 TI_UPDATE_JUMBOPROD(sc, TI_JUMBO_RX_RING_CNT - 1);
1773 ti_free_rx_ring_jumbo(struct ti_softc *sc)
1778 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1779 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1780 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1781 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map,
1782 BUS_DMASYNC_POSTREAD);
1783 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map);
1784 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1785 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1788 bzero(sc->ti_rdata.ti_rx_jumbo_ring, TI_JUMBO_RX_RING_SZ);
1789 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag,
1790 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1794 ti_init_rx_ring_mini(struct ti_softc *sc)
1798 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1799 if (ti_newbuf_mini(sc, i) != 0)
1803 sc->ti_mini = TI_MINI_RX_RING_CNT - 1;
1804 TI_UPDATE_MINIPROD(sc, TI_MINI_RX_RING_CNT - 1);
1810 ti_free_rx_ring_mini(struct ti_softc *sc)
1815 if (sc->ti_rdata.ti_rx_mini_ring == NULL)
1818 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1819 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1820 map = sc->ti_cdata.ti_rx_mini_maps[i];
1821 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, map,
1822 BUS_DMASYNC_POSTREAD);
1823 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, map);
1824 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1825 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1828 bzero(sc->ti_rdata.ti_rx_mini_ring, TI_MINI_RX_RING_SZ);
1829 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag,
1830 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE);
1834 ti_free_tx_ring(struct ti_softc *sc)
1836 struct ti_txdesc *txd;
1839 if (sc->ti_rdata.ti_tx_ring == NULL)
1842 for (i = 0; i < TI_TX_RING_CNT; i++) {
1843 txd = &sc->ti_cdata.ti_txdesc[i];
1844 if (txd->tx_m != NULL) {
1845 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
1846 BUS_DMASYNC_POSTWRITE);
1847 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag,
1853 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ);
1854 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
1855 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE);
1859 ti_init_tx_ring(struct ti_softc *sc)
1861 struct ti_txdesc *txd;
1864 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq);
1865 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq);
1866 for (i = 0; i < TI_TX_RING_CNT; i++) {
1867 txd = &sc->ti_cdata.ti_txdesc[i];
1868 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
1871 sc->ti_tx_saved_considx = 0;
1872 sc->ti_tx_saved_prodidx = 0;
1873 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1878 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1879 * but we have to support the old way too so that Tigon 1 cards will
1883 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
1885 struct ti_cmd_desc cmd;
1887 uint32_t ext[2] = {0, 0};
1889 m = (uint16_t *)&addr->octet[0];
1891 switch (sc->ti_hwrev) {
1892 case TI_HWREV_TIGON:
1893 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1894 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1895 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1897 case TI_HWREV_TIGON_II:
1898 ext[0] = htons(m[0]);
1899 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1900 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1903 device_printf(sc->ti_dev, "unknown hwrev\n");
1909 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
1911 struct ti_cmd_desc cmd;
1913 uint32_t ext[2] = {0, 0};
1915 m = (uint16_t *)&addr->octet[0];
1917 switch (sc->ti_hwrev) {
1918 case TI_HWREV_TIGON:
1919 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1920 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1921 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1923 case TI_HWREV_TIGON_II:
1924 ext[0] = htons(m[0]);
1925 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1926 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1929 device_printf(sc->ti_dev, "unknown hwrev\n");
1935 * Configure the Tigon's multicast address filter.
1937 * The actual multicast table management is a bit of a pain, thanks to
1938 * slight brain damage on the part of both Alteon and us. With our
1939 * multicast code, we are only alerted when the multicast address table
1940 * changes and at that point we only have the current list of addresses:
1941 * we only know the current state, not the previous state, so we don't
1942 * actually know what addresses were removed or added. The firmware has
1943 * state, but we can't get our grubby mits on it, and there is no 'delete
1944 * all multicast addresses' command. Hence, we have to maintain our own
1945 * state so we know what addresses have been programmed into the NIC at
1949 ti_setmulti(struct ti_softc *sc)
1952 struct ifmultiaddr *ifma;
1953 struct ti_cmd_desc cmd;
1954 struct ti_mc_entry *mc;
1961 if (ifp->if_flags & IFF_ALLMULTI) {
1962 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1965 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1968 /* Disable interrupts. */
1969 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1970 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1972 /* First, zot all the existing filters. */
1973 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1974 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1975 ti_del_mcast(sc, &mc->mc_addr);
1976 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1980 /* Now program new ones. */
1981 if_maddr_rlock(ifp);
1982 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1983 if (ifma->ifma_addr->sa_family != AF_LINK)
1985 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1987 device_printf(sc->ti_dev,
1988 "no memory for mcast filter entry\n");
1991 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1992 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1993 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1994 ti_add_mcast(sc, &mc->mc_addr);
1996 if_maddr_runlock(ifp);
1998 /* Re-enable interrupts. */
1999 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
2003 * Check to see if the BIOS has configured us for a 64 bit slot when
2004 * we aren't actually in one. If we detect this condition, we can work
2005 * around it on the Tigon 2 by setting a bit in the PCI state register,
2006 * but for the Tigon 1 we must give up and abort the interface attach.
2009 ti_64bitslot_war(struct ti_softc *sc)
2012 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
2013 CSR_WRITE_4(sc, 0x600, 0);
2014 CSR_WRITE_4(sc, 0x604, 0);
2015 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
2016 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
2017 if (sc->ti_hwrev == TI_HWREV_TIGON)
2020 TI_SETBIT(sc, TI_PCI_STATE,
2021 TI_PCISTATE_32BIT_BUS);
2031 * Do endian, PCI and DMA initialization. Also check the on-board ROM
2032 * self-test results.
2035 ti_chipinit(struct ti_softc *sc)
2038 uint32_t pci_writemax = 0;
2041 /* Initialize link to down state. */
2042 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
2044 /* Set endianness before we access any non-PCI registers. */
2045 #if 0 && BYTE_ORDER == BIG_ENDIAN
2046 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
2047 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
2049 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
2050 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
2053 /* Check the ROM failed bit to see if self-tests passed. */
2054 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
2055 device_printf(sc->ti_dev, "board self-diagnostics failed!\n");
2060 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
2062 /* Figure out the hardware revision. */
2063 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
2064 case TI_REV_TIGON_I:
2065 sc->ti_hwrev = TI_HWREV_TIGON;
2067 case TI_REV_TIGON_II:
2068 sc->ti_hwrev = TI_HWREV_TIGON_II;
2071 device_printf(sc->ti_dev, "unsupported chip revision\n");
2075 /* Do special setup for Tigon 2. */
2076 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
2077 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
2078 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
2079 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
2083 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
2084 * can't do header splitting.
2086 #ifdef TI_JUMBO_HDRSPLIT
2087 if (sc->ti_hwrev != TI_HWREV_TIGON)
2088 sc->ti_hdrsplit = 1;
2090 device_printf(sc->ti_dev,
2091 "can't do header splitting on a Tigon I board\n");
2092 #endif /* TI_JUMBO_HDRSPLIT */
2094 /* Set up the PCI state register. */
2095 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
2096 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
2097 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
2100 /* Clear the read/write max DMA parameters. */
2101 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
2102 TI_PCISTATE_READ_MAXDMA));
2104 /* Get cache line size. */
2105 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
2108 * If the system has set enabled the PCI memory write
2109 * and invalidate command in the command register, set
2110 * the write max parameter accordingly. This is necessary
2111 * to use MWI with the Tigon 2.
2113 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
2114 switch (cacheline) {
2123 /* Disable PCI memory write and invalidate. */
2125 device_printf(sc->ti_dev, "cache line size %d"
2126 " not supported; disabling PCI MWI\n",
2128 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
2129 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
2134 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
2136 /* This sets the min dma param all the way up (0xff). */
2137 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
2139 if (sc->ti_hdrsplit)
2140 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
2144 /* Configure DMA variables. */
2145 #if BYTE_ORDER == BIG_ENDIAN
2146 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
2147 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
2148 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
2149 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
2150 #else /* BYTE_ORDER */
2151 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
2152 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
2153 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
2154 #endif /* BYTE_ORDER */
2157 * Only allow 1 DMA channel to be active at a time.
2158 * I don't think this is a good idea, but without it
2159 * the firmware racks up lots of nicDmaReadRingFull
2160 * errors. This is not compatible with hardware checksums.
2162 if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0)
2163 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
2165 /* Recommended settings from Tigon manual. */
2166 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
2167 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
2169 if (ti_64bitslot_war(sc)) {
2170 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, "
2179 * Initialize the general information block and firmware, and
2180 * start the CPU(s) running.
2183 ti_gibinit(struct ti_softc *sc)
2193 /* Disable interrupts for now. */
2194 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2196 /* Tell the chip where to find the general information block. */
2197 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI,
2198 (uint64_t)sc->ti_rdata.ti_info_paddr >> 32);
2199 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO,
2200 sc->ti_rdata.ti_info_paddr & 0xFFFFFFFF);
2202 /* Load the firmware into SRAM. */
2205 /* Set up the contents of the general info and ring control blocks. */
2207 /* Set up the event ring and producer pointer. */
2208 bzero(sc->ti_rdata.ti_event_ring, TI_EVENT_RING_SZ);
2209 rcb = &sc->ti_rdata.ti_info->ti_ev_rcb;
2210 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_event_ring_paddr);
2212 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_ev_prodidx_ptr,
2213 sc->ti_rdata.ti_status_paddr +
2214 offsetof(struct ti_status, ti_ev_prodidx_r));
2215 sc->ti_ev_prodidx.ti_idx = 0;
2216 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
2217 sc->ti_ev_saved_considx = 0;
2219 /* Set up the command ring and producer mailbox. */
2220 rcb = &sc->ti_rdata.ti_info->ti_cmd_rcb;
2221 ti_hostaddr64(&rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING));
2223 rcb->ti_max_len = 0;
2224 for (i = 0; i < TI_CMD_RING_CNT; i++) {
2225 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
2227 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
2228 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
2229 sc->ti_cmd_saved_prodidx = 0;
2232 * Assign the address of the stats refresh buffer.
2233 * We re-use the current stats buffer for this to
2236 bzero(&sc->ti_rdata.ti_info->ti_stats, sizeof(struct ti_stats));
2237 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_refresh_stats_ptr,
2238 sc->ti_rdata.ti_info_paddr + offsetof(struct ti_gib, ti_stats));
2240 /* Set up the standard receive ring. */
2241 rcb = &sc->ti_rdata.ti_info->ti_std_rx_rcb;
2242 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_std_ring_paddr);
2243 rcb->ti_max_len = TI_FRAMELEN;
2245 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2246 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2247 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2248 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2249 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2251 /* Set up the jumbo receive ring. */
2252 rcb = &sc->ti_rdata.ti_info->ti_jumbo_rx_rcb;
2253 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_jumbo_ring_paddr);
2255 #ifndef TI_SF_BUF_JUMBO
2256 rcb->ti_max_len = MJUM9BYTES - ETHER_ALIGN;
2259 rcb->ti_max_len = PAGE_SIZE;
2260 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
2262 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2263 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2264 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2265 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2266 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2269 * Set up the mini ring. Only activated on the
2270 * Tigon 2 but the slot in the config block is
2271 * still there on the Tigon 1.
2273 rcb = &sc->ti_rdata.ti_info->ti_mini_rx_rcb;
2274 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_mini_ring_paddr);
2275 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
2276 if (sc->ti_hwrev == TI_HWREV_TIGON)
2277 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
2280 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2281 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2282 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2283 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2284 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2287 * Set up the receive return ring.
2289 rcb = &sc->ti_rdata.ti_info->ti_return_rcb;
2290 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_return_ring_paddr);
2292 rcb->ti_max_len = TI_RETURN_RING_CNT;
2293 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_return_prodidx_ptr,
2294 sc->ti_rdata.ti_status_paddr +
2295 offsetof(struct ti_status, ti_return_prodidx_r));
2298 * Set up the tx ring. Note: for the Tigon 2, we have the option
2299 * of putting the transmit ring in the host's address space and
2300 * letting the chip DMA it instead of leaving the ring in the NIC's
2301 * memory and accessing it through the shared memory region. We
2302 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
2303 * so we have to revert to the shared memory scheme if we detect
2306 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
2307 if (sc->ti_rdata.ti_tx_ring != NULL)
2308 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ);
2309 rcb = &sc->ti_rdata.ti_info->ti_tx_rcb;
2310 if (sc->ti_hwrev == TI_HWREV_TIGON)
2313 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
2314 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2315 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2316 if (sc->ti_ifp->if_capenable & IFCAP_TXCSUM)
2317 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2318 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2319 rcb->ti_max_len = TI_TX_RING_CNT;
2320 if (sc->ti_hwrev == TI_HWREV_TIGON)
2321 ti_hostaddr64(&rcb->ti_hostaddr, TI_TX_RING_BASE);
2323 ti_hostaddr64(&rcb->ti_hostaddr,
2324 sc->ti_rdata.ti_tx_ring_paddr);
2325 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_tx_considx_ptr,
2326 sc->ti_rdata.ti_status_paddr +
2327 offsetof(struct ti_status, ti_tx_considx_r));
2329 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map,
2330 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2331 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, sc->ti_cdata.ti_status_map,
2332 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2333 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag,
2334 sc->ti_cdata.ti_event_ring_map,
2335 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2336 if (sc->ti_rdata.ti_tx_ring != NULL)
2337 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
2338 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE);
2340 /* Set up tunables */
2342 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN)
2343 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
2344 (sc->ti_rx_coal_ticks / 10));
2347 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2348 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2349 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2350 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2351 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2352 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2354 /* Turn interrupts on. */
2355 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2356 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2359 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2365 * Probe for a Tigon chip. Check the PCI vendor and device IDs
2366 * against our list and return its name if we find a match.
2369 ti_probe(device_t dev)
2371 const struct ti_type *t;
2375 while (t->ti_name != NULL) {
2376 if ((pci_get_vendor(dev) == t->ti_vid) &&
2377 (pci_get_device(dev) == t->ti_did)) {
2378 device_set_desc(dev, t->ti_name);
2379 return (BUS_PROBE_DEFAULT);
2388 ti_attach(device_t dev)
2391 struct ti_softc *sc;
2395 sc = device_get_softc(dev);
2398 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2400 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0);
2401 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2402 ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
2404 device_printf(dev, "can not if_alloc()\n");
2408 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES;
2409 sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
2410 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities;
2413 * Map control/status registers.
2415 pci_enable_busmaster(dev);
2418 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2421 if (sc->ti_res == NULL) {
2422 device_printf(dev, "couldn't map memory\n");
2427 sc->ti_btag = rman_get_bustag(sc->ti_res);
2428 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2430 /* Allocate interrupt */
2433 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2434 RF_SHAREABLE | RF_ACTIVE);
2436 if (sc->ti_irq == NULL) {
2437 device_printf(dev, "couldn't map interrupt\n");
2442 if (ti_chipinit(sc)) {
2443 device_printf(dev, "chip initialization failed\n");
2448 /* Zero out the NIC's on-board SRAM. */
2449 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
2451 /* Init again -- zeroing memory may have clobbered some registers. */
2452 if (ti_chipinit(sc)) {
2453 device_printf(dev, "chip initialization failed\n");
2459 * Get station address from the EEPROM. Note: the manual states
2460 * that the MAC address is at offset 0x8c, however the data is
2461 * stored as two longwords (since that's how it's loaded into
2462 * the NIC). This means the MAC address is actually preceded
2463 * by two zero bytes. We need to skip over those.
2465 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2466 device_printf(dev, "failed to read station address\n");
2471 /* Allocate working area for memory dump. */
2472 sc->ti_membuf = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, M_NOWAIT);
2473 sc->ti_membuf2 = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF,
2475 if (sc->ti_membuf == NULL || sc->ti_membuf2 == NULL) {
2476 device_printf(dev, "cannot allocate memory buffer\n");
2480 if ((error = ti_dma_alloc(sc)) != 0)
2484 * We really need a better way to tell a 1000baseTX card
2485 * from a 1000baseSX one, since in theory there could be
2486 * OEMed 1000baseTX cards from lame vendors who aren't
2487 * clever enough to change the PCI ID. For the moment
2488 * though, the AceNIC is the only copper card available.
2490 if (pci_get_vendor(dev) == ALT_VENDORID &&
2491 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2493 /* Ok, it's not the only copper card available. */
2494 if (pci_get_vendor(dev) == NG_VENDORID &&
2495 pci_get_device(dev) == NG_DEVICEID_GA620T)
2498 /* Set default tunable values. */
2501 /* Set up ifnet structure */
2503 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2504 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2505 ifp->if_ioctl = ti_ioctl;
2506 ifp->if_start = ti_start;
2507 ifp->if_init = ti_init;
2508 ifp->if_baudrate = IF_Gbps(1UL);
2509 ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1;
2510 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2511 IFQ_SET_READY(&ifp->if_snd);
2513 /* Set up ifmedia support. */
2514 if (sc->ti_copper) {
2516 * Copper cards allow manual 10/100 mode selection,
2517 * but not manual 1000baseTX mode selection. Why?
2518 * Becuase currently there's no way to specify the
2519 * master/slave setting through the firmware interface,
2520 * so Alteon decided to just bag it and handle it
2521 * via autonegotiation.
2523 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2524 ifmedia_add(&sc->ifmedia,
2525 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2526 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2527 ifmedia_add(&sc->ifmedia,
2528 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2529 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2530 ifmedia_add(&sc->ifmedia,
2531 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2533 /* Fiber cards don't support 10/100 modes. */
2534 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2535 ifmedia_add(&sc->ifmedia,
2536 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2538 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2539 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2542 * We're assuming here that card initialization is a sequential
2543 * thing. If it isn't, multiple cards probing at the same time
2544 * could stomp on the list of softcs here.
2547 /* Register the device */
2548 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT,
2549 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev));
2550 sc->dev->si_drv1 = sc;
2553 * Call MI attach routine.
2555 ether_ifattach(ifp, eaddr);
2557 /* VLAN capability setup. */
2558 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM |
2559 IFCAP_VLAN_HWTAGGING;
2560 ifp->if_capenable = ifp->if_capabilities;
2561 /* Tell the upper layer we support VLAN over-sized frames. */
2562 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
2564 /* Driver supports link state tracking. */
2565 ifp->if_capabilities |= IFCAP_LINKSTATE;
2566 ifp->if_capenable |= IFCAP_LINKSTATE;
2568 /* Hook interrupt last to avoid having to lock softc */
2569 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE,
2570 NULL, ti_intr, sc, &sc->ti_intrhand);
2573 device_printf(dev, "couldn't set up irq\n");
2585 * Shutdown hardware and free up resources. This can be called any
2586 * time after the mutex has been initialized. It is called in both
2587 * the error case in attach and the normal detach case so it needs
2588 * to be careful about only freeing resources that have actually been
2592 ti_detach(device_t dev)
2594 struct ti_softc *sc;
2597 sc = device_get_softc(dev);
2599 destroy_dev(sc->dev);
2600 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2602 if (device_is_attached(dev)) {
2603 ether_ifdetach(ifp);
2609 /* These should only be active if attach succeeded */
2610 callout_drain(&sc->ti_watchdog);
2611 bus_generic_detach(dev);
2613 ifmedia_removeall(&sc->ifmedia);
2615 if (sc->ti_intrhand)
2616 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2618 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2620 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
2626 free(sc->ti_membuf, M_DEVBUF);
2628 free(sc->ti_membuf2, M_DEVBUF);
2630 mtx_destroy(&sc->ti_mtx);
2635 #ifdef TI_JUMBO_HDRSPLIT
2637 * If hdr_len is 0, that means that header splitting wasn't done on
2638 * this packet for some reason. The two most likely reasons are that
2639 * the protocol isn't a supported protocol for splitting, or this
2640 * packet had a fragment offset that wasn't 0.
2642 * The header length, if it is non-zero, will always be the length of
2643 * the headers on the packet, but that length could be longer than the
2644 * first mbuf. So we take the minimum of the two as the actual
2647 static __inline void
2648 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2651 int lengths[4] = {0, 0, 0, 0};
2652 struct mbuf *m, *mp;
2655 top->m_len = min(hdr_len, top->m_len);
2656 pkt_len -= top->m_len;
2657 lengths[i++] = top->m_len;
2660 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2661 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2662 pkt_len -= m->m_len;
2663 lengths[i++] = m->m_len;
2669 printf("got split packet: ");
2671 printf("got non-split packet: ");
2673 printf("%d,%d,%d,%d = %d\n", lengths[0],
2674 lengths[1], lengths[2], lengths[3],
2675 lengths[0] + lengths[1] + lengths[2] +
2680 panic("header splitting didn't");
2687 if (mp->m_next != NULL)
2688 panic("ti_hdr_split: last mbuf in chain should be null");
2690 #endif /* TI_JUMBO_HDRSPLIT */
2693 ti_discard_std(struct ti_softc *sc, int i)
2696 struct ti_rx_desc *r;
2698 r = &sc->ti_rdata.ti_rx_std_ring[i];
2699 r->ti_len = MCLBYTES - ETHER_ALIGN;
2700 r->ti_type = TI_BDTYPE_RECV_BD;
2703 r->ti_tcp_udp_cksum = 0;
2704 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2705 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2710 ti_discard_mini(struct ti_softc *sc, int i)
2713 struct ti_rx_desc *r;
2715 r = &sc->ti_rdata.ti_rx_mini_ring[i];
2716 r->ti_len = MHLEN - ETHER_ALIGN;
2717 r->ti_type = TI_BDTYPE_RECV_BD;
2718 r->ti_flags = TI_BDFLAG_MINI_RING;
2720 r->ti_tcp_udp_cksum = 0;
2721 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2722 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2726 #ifndef TI_SF_BUF_JUMBO
2728 ti_discard_jumbo(struct ti_softc *sc, int i)
2731 struct ti_rx_desc *r;
2733 r = &sc->ti_rdata.ti_rx_jumbo_ring[i];
2734 r->ti_len = MJUM9BYTES - ETHER_ALIGN;
2735 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
2736 r->ti_flags = TI_BDFLAG_JUMBO_RING;
2738 r->ti_tcp_udp_cksum = 0;
2739 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2740 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2746 * Frame reception handling. This is called if there's a frame
2747 * on the receive return list.
2749 * Note: we have to be able to handle three possibilities here:
2750 * 1) the frame is from the mini receive ring (can only happen)
2751 * on Tigon 2 boards)
2752 * 2) the frame is from the jumbo recieve ring
2753 * 3) the frame is from the standard receive ring
2757 ti_rxeof(struct ti_softc *sc)
2760 #ifdef TI_SF_BUF_JUMBO
2763 struct ti_cmd_desc cmd;
2764 int jumbocnt, minicnt, stdcnt, ti_len;
2770 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag,
2771 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
2772 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN)
2773 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag,
2774 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
2775 if (sc->ti_rdata.ti_rx_mini_ring != NULL)
2776 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag,
2777 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_POSTWRITE);
2778 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag,
2779 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
2781 jumbocnt = minicnt = stdcnt = 0;
2782 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2783 struct ti_rx_desc *cur_rx;
2785 struct mbuf *m = NULL;
2786 uint16_t vlan_tag = 0;
2790 &sc->ti_rdata.ti_rx_return_ring[sc->ti_rx_saved_considx];
2791 rxidx = cur_rx->ti_idx;
2792 ti_len = cur_rx->ti_len;
2793 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2795 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2797 vlan_tag = cur_rx->ti_vlan_tag;
2800 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2802 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2803 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2804 #ifndef TI_SF_BUF_JUMBO
2805 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2807 ti_discard_jumbo(sc, rxidx);
2810 if (ti_newbuf_jumbo(sc, rxidx, NULL) != 0) {
2812 ti_discard_jumbo(sc, rxidx);
2816 #else /* !TI_SF_BUF_JUMBO */
2817 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2818 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx];
2819 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map,
2820 BUS_DMASYNC_POSTREAD);
2821 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map);
2822 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2824 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2827 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2829 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2832 #ifdef TI_JUMBO_HDRSPLIT
2833 if (sc->ti_hdrsplit)
2834 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2837 #endif /* TI_JUMBO_HDRSPLIT */
2838 m_adj(m, ti_len - m->m_pkthdr.len);
2839 #endif /* TI_SF_BUF_JUMBO */
2840 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2842 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2843 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2844 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2846 ti_discard_mini(sc, rxidx);
2849 if (ti_newbuf_mini(sc, rxidx) != 0) {
2851 ti_discard_mini(sc, rxidx);
2857 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2858 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2859 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2861 ti_discard_std(sc, rxidx);
2864 if (ti_newbuf_std(sc, rxidx) != 0) {
2866 ti_discard_std(sc, rxidx);
2872 m->m_pkthdr.len = ti_len;
2874 m->m_pkthdr.rcvif = ifp;
2876 if (ifp->if_capenable & IFCAP_RXCSUM) {
2877 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) {
2878 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2879 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2880 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2882 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) {
2883 m->m_pkthdr.csum_data =
2884 cur_rx->ti_tcp_udp_cksum;
2885 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2890 * If we received a packet with a vlan tag,
2891 * tag it before passing the packet upward.
2894 m->m_pkthdr.ether_vtag = vlan_tag;
2895 m->m_flags |= M_VLANTAG;
2898 (*ifp->if_input)(ifp, m);
2902 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag,
2903 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_PREREAD);
2904 /* Only necessary on the Tigon 1. */
2905 if (sc->ti_hwrev == TI_HWREV_TIGON)
2906 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2907 sc->ti_rx_saved_considx);
2910 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag,
2911 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
2912 TI_UPDATE_STDPROD(sc, sc->ti_std);
2915 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag,
2916 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE);
2917 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2920 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag,
2921 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
2922 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2927 ti_txeof(struct ti_softc *sc)
2929 struct ti_txdesc *txd;
2930 struct ti_tx_desc txdesc;
2931 struct ti_tx_desc *cur_tx = NULL;
2937 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2941 if (sc->ti_rdata.ti_tx_ring != NULL)
2942 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
2943 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_POSTWRITE);
2945 * Go through our tx ring and free mbufs for those
2946 * frames that have been sent.
2948 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx;
2949 TI_INC(idx, TI_TX_RING_CNT)) {
2950 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2951 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc),
2952 sizeof(txdesc), &txdesc);
2955 cur_tx = &sc->ti_rdata.ti_tx_ring[idx];
2957 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2958 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0)
2960 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
2961 BUS_DMASYNC_POSTWRITE);
2962 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap);
2967 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q);
2968 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
2969 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2971 sc->ti_tx_saved_considx = idx;
2972 if (sc->ti_txcnt == 0)
2979 struct ti_softc *sc;
2986 /* Make sure this is really our interrupt. */
2987 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2992 /* Ack interrupt and stop others from occuring. */
2993 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2995 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2996 bus_dmamap_sync(sc->ti_cdata.ti_status_tag,
2997 sc->ti_cdata.ti_status_map, BUS_DMASYNC_POSTREAD);
2998 /* Check RX return ring producer/consumer */
3001 /* Check TX ring producer/consumer */
3003 bus_dmamap_sync(sc->ti_cdata.ti_status_tag,
3004 sc->ti_cdata.ti_status_map, BUS_DMASYNC_PREREAD);
3007 ti_handle_events(sc);
3009 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3010 /* Re-enable interrupts. */
3011 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3012 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3013 ti_start_locked(ifp);
3020 ti_stats_update(struct ti_softc *sc)
3027 if (sc->ti_stat_ticks == 0)
3029 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map,
3030 BUS_DMASYNC_POSTREAD);
3032 s = &sc->ti_rdata.ti_info->ti_stats;
3033 ifp->if_collisions += (s->dot3StatsSingleCollisionFrames +
3034 s->dot3StatsMultipleCollisionFrames +
3035 s->dot3StatsExcessiveCollisions + s->dot3StatsLateCollisions) -
3038 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map,
3039 BUS_DMASYNC_PREREAD);
3043 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3044 * pointers to descriptors.
3047 ti_encap(struct ti_softc *sc, struct mbuf **m_head)
3049 struct ti_txdesc *txd;
3050 struct ti_tx_desc *f;
3051 struct ti_tx_desc txdesc;
3053 bus_dma_segment_t txsegs[TI_MAXTXSEGS];
3054 uint16_t csum_flags;
3055 int error, frag, i, nseg;
3057 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL)
3060 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
3061 *m_head, txsegs, &nseg, 0);
3062 if (error == EFBIG) {
3063 m = m_defrag(*m_head, M_NOWAIT);
3070 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag,
3071 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
3077 } else if (error != 0)
3085 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) {
3086 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap);
3089 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
3090 BUS_DMASYNC_PREWRITE);
3094 if (m->m_pkthdr.csum_flags & CSUM_IP)
3095 csum_flags |= TI_BDFLAG_IP_CKSUM;
3096 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3097 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
3099 frag = sc->ti_tx_saved_prodidx;
3100 for (i = 0; i < nseg; i++) {
3101 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3102 bzero(&txdesc, sizeof(txdesc));
3105 f = &sc->ti_rdata.ti_tx_ring[frag];
3106 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr);
3107 f->ti_len = txsegs[i].ds_len;
3108 f->ti_flags = csum_flags;
3109 if (m->m_flags & M_VLANTAG) {
3110 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
3111 f->ti_vlan_tag = m->m_pkthdr.ether_vtag;
3116 if (sc->ti_hwrev == TI_HWREV_TIGON)
3117 ti_mem_write(sc, TI_TX_RING_BASE + frag *
3118 sizeof(txdesc), sizeof(txdesc), &txdesc);
3119 TI_INC(frag, TI_TX_RING_CNT);
3122 sc->ti_tx_saved_prodidx = frag;
3123 /* set TI_BDFLAG_END on the last descriptor */
3124 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT;
3125 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3126 txdesc.ti_flags |= TI_BDFLAG_END;
3127 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc),
3128 sizeof(txdesc), &txdesc);
3130 sc->ti_rdata.ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END;
3132 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q);
3133 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q);
3135 sc->ti_txcnt += nseg;
3141 ti_start(struct ifnet *ifp)
3143 struct ti_softc *sc;
3147 ti_start_locked(ifp);
3152 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3153 * to the mbuf data regions directly in the transmit descriptors.
3156 ti_start_locked(struct ifnet *ifp)
3158 struct ti_softc *sc;
3159 struct mbuf *m_head = NULL;
3164 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
3165 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) {
3166 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3171 * Pack the data into the transmit ring. If we
3172 * don't have room, set the OACTIVE flag and wait
3173 * for the NIC to drain the ring.
3175 if (ti_encap(sc, &m_head)) {
3178 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3179 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3185 * If there's a BPF listener, bounce a copy of this frame
3188 ETHER_BPF_MTAP(ifp, m_head);
3192 if (sc->ti_rdata.ti_tx_ring != NULL)
3193 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
3194 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE);
3196 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx);
3199 * Set a timeout in case the chip goes out to lunch.
3208 struct ti_softc *sc;
3217 ti_init_locked(void *xsc)
3219 struct ti_softc *sc = xsc;
3221 if (sc->ti_ifp->if_drv_flags & IFF_DRV_RUNNING)
3224 /* Cancel pending I/O and flush buffers. */
3227 /* Init the gen info block, ring control blocks and firmware. */
3228 if (ti_gibinit(sc)) {
3229 device_printf(sc->ti_dev, "initialization failure\n");
3234 static void ti_init2(struct ti_softc *sc)
3236 struct ti_cmd_desc cmd;
3239 struct ifmedia *ifm;
3246 /* Specify MTU and interface index. */
3247 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev));
3248 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
3249 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
3250 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
3252 /* Load our MAC address. */
3253 ea = IF_LLADDR(sc->ti_ifp);
3254 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]);
3255 CSR_WRITE_4(sc, TI_GCR_PAR1,
3256 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]);
3257 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
3259 /* Enable or disable promiscuous mode as needed. */
3260 if (ifp->if_flags & IFF_PROMISC) {
3261 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
3263 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
3266 /* Program multicast filter. */
3270 * If this is a Tigon 1, we should tell the
3271 * firmware to use software packet filtering.
3273 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3274 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
3278 if (ti_init_rx_ring_std(sc) != 0) {
3280 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n");
3284 /* Init jumbo RX ring. */
3285 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) {
3286 if (ti_init_rx_ring_jumbo(sc) != 0) {
3288 device_printf(sc->ti_dev,
3289 "no memory for jumbo Rx buffers.\n");
3295 * If this is a Tigon 2, we can also configure the
3298 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
3299 if (ti_init_rx_ring_mini(sc) != 0) {
3301 device_printf(sc->ti_dev,
3302 "no memory for mini Rx buffers.\n");
3307 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
3308 sc->ti_rx_saved_considx = 0;
3311 ti_init_tx_ring(sc);
3313 /* Tell firmware we're alive. */
3314 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
3316 /* Enable host interrupts. */
3317 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3319 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3320 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3321 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3324 * Make sure to set media properly. We have to do this
3325 * here since we have to issue commands in order to set
3326 * the link negotiation and we can't issue commands until
3327 * the firmware is running.
3330 tmp = ifm->ifm_media;
3331 ifm->ifm_media = ifm->ifm_cur->ifm_media;
3332 ti_ifmedia_upd_locked(sc);
3333 ifm->ifm_media = tmp;
3337 * Set media options.
3340 ti_ifmedia_upd(struct ifnet *ifp)
3342 struct ti_softc *sc;
3347 error = ti_ifmedia_upd(ifp);
3354 ti_ifmedia_upd_locked(struct ti_softc *sc)
3356 struct ifmedia *ifm;
3357 struct ti_cmd_desc cmd;
3362 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3367 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3370 * Transmit flow control doesn't work on the Tigon 1.
3372 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3375 * Transmit flow control can also cause problems on the
3376 * Tigon 2, apparantly with both the copper and fiber
3377 * boards. The symptom is that the interface will just
3378 * hang. This was reproduced with Alteon 180 switches.
3381 if (sc->ti_hwrev != TI_HWREV_TIGON)
3382 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3385 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3386 TI_GLNK_FULL_DUPLEX| flowctl |
3387 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
3389 flowctl = TI_LNK_RX_FLOWCTL_Y;
3391 if (sc->ti_hwrev != TI_HWREV_TIGON)
3392 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3395 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
3396 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
3397 TI_LNK_AUTONEGENB|TI_LNK_ENB);
3398 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3399 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
3403 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3405 if (sc->ti_hwrev != TI_HWREV_TIGON)
3406 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3409 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3410 flowctl |TI_GLNK_ENB);
3411 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
3412 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3413 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
3415 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3416 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3422 flowctl = TI_LNK_RX_FLOWCTL_Y;
3424 if (sc->ti_hwrev != TI_HWREV_TIGON)
3425 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3428 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3429 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3430 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3431 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3432 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3434 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3436 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3437 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3439 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3441 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3442 TI_CMD_CODE_NEGOTIATE_10_100, 0);
3450 * Report current media status.
3453 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3455 struct ti_softc *sc;
3462 ifmr->ifm_status = IFM_AVALID;
3463 ifmr->ifm_active = IFM_ETHER;
3465 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
3470 ifmr->ifm_status |= IFM_ACTIVE;
3472 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3473 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3475 ifmr->ifm_active |= IFM_1000_T;
3477 ifmr->ifm_active |= IFM_1000_SX;
3478 if (media & TI_GLNK_FULL_DUPLEX)
3479 ifmr->ifm_active |= IFM_FDX;
3481 ifmr->ifm_active |= IFM_HDX;
3482 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3483 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3484 if (sc->ti_copper) {
3485 if (media & TI_LNK_100MB)
3486 ifmr->ifm_active |= IFM_100_TX;
3487 if (media & TI_LNK_10MB)
3488 ifmr->ifm_active |= IFM_10_T;
3490 if (media & TI_LNK_100MB)
3491 ifmr->ifm_active |= IFM_100_FX;
3492 if (media & TI_LNK_10MB)
3493 ifmr->ifm_active |= IFM_10_FL;
3495 if (media & TI_LNK_FULL_DUPLEX)
3496 ifmr->ifm_active |= IFM_FDX;
3497 if (media & TI_LNK_HALF_DUPLEX)
3498 ifmr->ifm_active |= IFM_HDX;
3504 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3506 struct ti_softc *sc = ifp->if_softc;
3507 struct ifreq *ifr = (struct ifreq *) data;
3508 struct ti_cmd_desc cmd;
3509 int mask, error = 0;
3514 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU)
3517 ifp->if_mtu = ifr->ifr_mtu;
3518 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3519 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3527 if (ifp->if_flags & IFF_UP) {
3529 * If only the state of the PROMISC flag changed,
3530 * then just use the 'set promisc mode' command
3531 * instead of reinitializing the entire NIC. Doing
3532 * a full re-init means reloading the firmware and
3533 * waiting for it to start up, which may take a
3536 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3537 ifp->if_flags & IFF_PROMISC &&
3538 !(sc->ti_if_flags & IFF_PROMISC)) {
3539 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3540 TI_CMD_CODE_PROMISC_ENB, 0);
3541 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3542 !(ifp->if_flags & IFF_PROMISC) &&
3543 sc->ti_if_flags & IFF_PROMISC) {
3544 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3545 TI_CMD_CODE_PROMISC_DIS, 0);
3549 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3553 sc->ti_if_flags = ifp->if_flags;
3559 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3565 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3569 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3570 if ((mask & IFCAP_TXCSUM) != 0 &&
3571 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3572 ifp->if_capenable ^= IFCAP_TXCSUM;
3573 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3574 ifp->if_hwassist |= TI_CSUM_FEATURES;
3576 ifp->if_hwassist &= ~TI_CSUM_FEATURES;
3578 if ((mask & IFCAP_RXCSUM) != 0 &&
3579 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3580 ifp->if_capenable ^= IFCAP_RXCSUM;
3581 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3582 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0)
3583 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3584 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
3585 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
3586 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
3587 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM |
3588 IFCAP_VLAN_HWTAGGING)) != 0) {
3589 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3590 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3595 VLAN_CAPABILITIES(ifp);
3598 error = ether_ioctl(ifp, command, data);
3606 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3608 struct ti_softc *sc;
3615 sc->ti_flags |= TI_FLAG_DEBUGING;
3622 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3624 struct ti_softc *sc;
3631 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3638 * This ioctl routine goes along with the Tigon character device.
3641 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag,
3644 struct ti_softc *sc;
3656 struct ti_stats *outstats;
3658 outstats = (struct ti_stats *)addr;
3661 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag,
3662 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD);
3663 bcopy(&sc->ti_rdata.ti_info->ti_stats, outstats,
3664 sizeof(struct ti_stats));
3668 case TIIOCGETPARAMS:
3670 struct ti_params *params;
3672 params = (struct ti_params *)addr;
3675 params->ti_stat_ticks = sc->ti_stat_ticks;
3676 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3677 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3678 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3679 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3680 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3681 params->param_mask = TI_PARAM_ALL;
3685 case TIIOCSETPARAMS:
3687 struct ti_params *params;
3689 params = (struct ti_params *)addr;
3692 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3693 sc->ti_stat_ticks = params->ti_stat_ticks;
3694 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3697 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3698 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3699 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3700 sc->ti_rx_coal_ticks);
3703 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3704 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3705 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3706 sc->ti_tx_coal_ticks);
3709 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3710 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3711 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3712 sc->ti_rx_max_coal_bds);
3715 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3716 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3717 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3718 sc->ti_tx_max_coal_bds);
3721 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3722 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3723 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3724 sc->ti_tx_buf_ratio);
3729 case TIIOCSETTRACE: {
3730 ti_trace_type trace_type;
3732 trace_type = *(ti_trace_type *)addr;
3735 * Set tracing to whatever the user asked for. Setting
3736 * this register to 0 should have the effect of disabling
3740 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3744 case TIIOCGETTRACE: {
3745 struct ti_trace_buf *trace_buf;
3746 uint32_t trace_start, cur_trace_ptr, trace_len;
3748 trace_buf = (struct ti_trace_buf *)addr;
3751 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3752 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3753 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3755 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, "
3756 "trace_len = %d\n", trace_start,
3757 cur_trace_ptr, trace_len);
3758 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n",
3759 trace_buf->buf_len);
3761 error = ti_copy_mem(sc, trace_start, min(trace_len,
3762 trace_buf->buf_len), (caddr_t)trace_buf->buf, 1, 1);
3764 trace_buf->fill_len = min(trace_len,
3765 trace_buf->buf_len);
3766 if (cur_trace_ptr < trace_start)
3767 trace_buf->cur_trace_ptr =
3768 trace_start - cur_trace_ptr;
3770 trace_buf->cur_trace_ptr =
3771 cur_trace_ptr - trace_start;
3773 trace_buf->fill_len = 0;
3779 * For debugging, five ioctls are needed:
3788 * From what I can tell, Alteon's Solaris Tigon driver
3789 * only has one character device, so you have to attach
3790 * to the Tigon board you're interested in. This seems
3791 * like a not-so-good way to do things, since unless you
3792 * subsequently specify the unit number of the device
3793 * you're interested in every ioctl, you'll only be
3794 * able to debug one board at a time.
3797 case ALT_READ_TG_MEM:
3798 case ALT_WRITE_TG_MEM:
3800 struct tg_mem *mem_param;
3801 uint32_t sram_end, scratch_end;
3803 mem_param = (struct tg_mem *)addr;
3805 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3806 sram_end = TI_END_SRAM_I;
3807 scratch_end = TI_END_SCRATCH_I;
3809 sram_end = TI_END_SRAM_II;
3810 scratch_end = TI_END_SCRATCH_II;
3814 * For now, we'll only handle accessing regular SRAM,
3818 if (mem_param->tgAddr >= TI_BEG_SRAM &&
3819 mem_param->tgAddr + mem_param->len <= sram_end) {
3821 * In this instance, we always copy to/from user
3822 * space, so the user space argument is set to 1.
3824 error = ti_copy_mem(sc, mem_param->tgAddr,
3825 mem_param->len, mem_param->userAddr, 1,
3826 cmd == ALT_READ_TG_MEM ? 1 : 0);
3827 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH &&
3828 mem_param->tgAddr <= scratch_end) {
3829 error = ti_copy_scratch(sc, mem_param->tgAddr,
3830 mem_param->len, mem_param->userAddr, 1,
3831 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_A);
3832 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG &&
3833 mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG) {
3834 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3835 if_printf(sc->ti_ifp,
3836 "invalid memory range for Tigon I\n");
3840 error = ti_copy_scratch(sc, mem_param->tgAddr -
3841 TI_SCRATCH_DEBUG_OFF, mem_param->len,
3842 mem_param->userAddr, 1,
3843 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_B);
3845 if_printf(sc->ti_ifp, "memory address %#x len %d is "
3846 "out of supported range\n",
3847 mem_param->tgAddr, mem_param->len);
3853 case ALT_READ_TG_REG:
3854 case ALT_WRITE_TG_REG:
3856 struct tg_reg *regs;
3859 regs = (struct tg_reg *)addr;
3862 * Make sure the address in question isn't out of range.
3864 if (regs->addr > TI_REG_MAX) {
3869 if (cmd == ALT_READ_TG_REG) {
3870 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3871 regs->addr, &tmpval, 1);
3872 regs->data = ntohl(tmpval);
3874 if ((regs->addr == TI_CPU_STATE)
3875 || (regs->addr == TI_CPU_CTL_B)) {
3876 if_printf(sc->ti_ifp, "register %#x = %#x\n",
3877 regs->addr, tmpval);
3881 tmpval = htonl(regs->data);
3882 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3883 regs->addr, &tmpval, 1);
3896 ti_watchdog(void *arg)
3898 struct ti_softc *sc;
3903 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3904 if (sc->ti_timer == 0 || --sc->ti_timer > 0)
3908 * When we're debugging, the chip is often stopped for long periods
3909 * of time, and that would normally cause the watchdog timer to fire.
3910 * Since that impedes debugging, we don't want to do that.
3912 if (sc->ti_flags & TI_FLAG_DEBUGING)
3916 if_printf(ifp, "watchdog timeout -- resetting\n");
3917 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3924 * Stop the adapter and free any mbufs allocated to the
3928 ti_stop(struct ti_softc *sc)
3931 struct ti_cmd_desc cmd;
3937 /* Disable host interrupts. */
3938 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3940 * Tell firmware we're shutting down.
3942 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3944 /* Halt and reinitialize. */
3945 if (ti_chipinit(sc) == 0) {
3946 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
3947 /* XXX ignore init errors. */
3951 /* Free the RX lists. */
3952 ti_free_rx_ring_std(sc);
3954 /* Free jumbo RX list. */
3955 ti_free_rx_ring_jumbo(sc);
3957 /* Free mini RX list. */
3958 ti_free_rx_ring_mini(sc);
3960 /* Free TX buffers. */
3961 ti_free_tx_ring(sc);
3963 sc->ti_ev_prodidx.ti_idx = 0;
3964 sc->ti_return_prodidx.ti_idx = 0;
3965 sc->ti_tx_considx.ti_idx = 0;
3966 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3968 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3969 callout_stop(&sc->ti_watchdog);
3973 * Stop all chip I/O so that the kernel's probe routines don't
3974 * get confused by errant DMAs when rebooting.
3977 ti_shutdown(device_t dev)
3979 struct ti_softc *sc;
3981 sc = device_get_softc(dev);
3990 ti_sysctl_node(struct ti_softc *sc)
3992 struct sysctl_ctx_list *ctx;
3993 struct sysctl_oid_list *child;
3996 ctx = device_get_sysctl_ctx(sc->ti_dev);
3997 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ti_dev));
4001 snprintf(tname, sizeof(tname), "dev.ti.%d.dac",
4002 device_get_unit(sc->ti_dev));
4003 TUNABLE_INT_FETCH(tname, &sc->ti_dac);
4005 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_coal_ticks", CTLFLAG_RW,
4006 &sc->ti_rx_coal_ticks, 0, "Receive coalcesced ticks");
4007 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_max_coal_bds", CTLFLAG_RW,
4008 &sc->ti_rx_max_coal_bds, 0, "Receive max coalcesced BDs");
4010 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_coal_ticks", CTLFLAG_RW,
4011 &sc->ti_tx_coal_ticks, 0, "Send coalcesced ticks");
4012 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_max_coal_bds", CTLFLAG_RW,
4013 &sc->ti_tx_max_coal_bds, 0, "Send max coalcesced BDs");
4014 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_buf_ratio", CTLFLAG_RW,
4015 &sc->ti_tx_buf_ratio, 0,
4016 "Ratio of NIC memory devoted to TX buffer");
4018 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stat_ticks", CTLFLAG_RW,
4019 &sc->ti_stat_ticks, 0,
4020 "Number of clock ticks for statistics update interval");
4022 /* Pull in device tunables. */
4023 sc->ti_rx_coal_ticks = 170;
4024 resource_int_value(device_get_name(sc->ti_dev),
4025 device_get_unit(sc->ti_dev), "rx_coal_ticks",
4026 &sc->ti_rx_coal_ticks);
4027 sc->ti_rx_max_coal_bds = 64;
4028 resource_int_value(device_get_name(sc->ti_dev),
4029 device_get_unit(sc->ti_dev), "rx_max_coal_bds",
4030 &sc->ti_rx_max_coal_bds);
4032 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
4033 resource_int_value(device_get_name(sc->ti_dev),
4034 device_get_unit(sc->ti_dev), "tx_coal_ticks",
4035 &sc->ti_tx_coal_ticks);
4036 sc->ti_tx_max_coal_bds = 32;
4037 resource_int_value(device_get_name(sc->ti_dev),
4038 device_get_unit(sc->ti_dev), "tx_max_coal_bds",
4039 &sc->ti_tx_max_coal_bds);
4040 sc->ti_tx_buf_ratio = 21;
4041 resource_int_value(device_get_name(sc->ti_dev),
4042 device_get_unit(sc->ti_dev), "tx_buf_ratio",
4043 &sc->ti_tx_buf_ratio);
4045 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
4046 resource_int_value(device_get_name(sc->ti_dev),
4047 device_get_unit(sc->ti_dev), "stat_ticks",
4048 &sc->ti_stat_ticks);