2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
37 * Manuals, sample driver and firmware source kits are available
38 * from http://www.alteon.com/support/openkits.
40 * Written by Bill Paul <wpaul@ctr.columbia.edu>
41 * Electrical Engineering Department
42 * Columbia University, New York City
46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
50 * filtering and jumbo (9014 byte) frames. The hardware is largely
51 * controlled by firmware, which must be loaded into the NIC during
54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
55 * revision, which supports new features such as extended commands,
56 * extended jumbo receive ring descriptors and a mini receive ring.
58 * Alteon Networks is to be commended for releasing such a vast amount
59 * of development material for the Tigon NIC without requiring an NDA
60 * (although they really should have done it a long time ago). With
61 * any luck, the other vendors will finally wise up and follow Alteon's
64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
65 * this driver by #including it as a C header file. This bloats the
66 * driver somewhat, but it's the easiest method considering that the
67 * driver code and firmware code need to be kept in sync. The source
68 * for the firmware is not provided with the FreeBSD distribution since
69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
71 * The following people deserve special thanks:
72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
74 * - Raymond Lee of Netgear, for providing a pair of Netgear
75 * GA620 Tigon 2 boards for testing
76 * - Ulf Zimmermann, for bringing the GA260 to my attention and
77 * convincing me to write this driver.
78 * - Andrew Gallatin for providing FreeBSD/Alpha support.
81 #include <sys/cdefs.h>
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/sockio.h>
88 #include <sys/malloc.h>
89 #include <sys/kernel.h>
90 #include <sys/module.h>
91 #include <sys/socket.h>
92 #include <sys/queue.h>
94 #include <sys/sf_buf.h>
97 #include <net/if_var.h>
98 #include <net/if_arp.h>
99 #include <net/ethernet.h>
100 #include <net/if_dl.h>
101 #include <net/if_media.h>
102 #include <net/if_types.h>
103 #include <net/if_vlan_var.h>
107 #include <netinet/in_systm.h>
108 #include <netinet/in.h>
109 #include <netinet/ip.h>
111 #include <machine/bus.h>
112 #include <machine/resource.h>
114 #include <sys/rman.h>
116 #ifdef TI_SF_BUF_JUMBO
118 #include <vm/vm_page.h>
121 #include <dev/pci/pcireg.h>
122 #include <dev/pci/pcivar.h>
124 #include <sys/tiio.h>
125 #include <dev/ti/if_tireg.h>
126 #include <dev/ti/ti_fw.h>
127 #include <dev/ti/ti_fw2.h>
129 #include <sys/sysctl.h>
131 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
133 * We can only turn on header splitting if we're using extended receive
136 #if defined(TI_JUMBO_HDRSPLIT) && !defined(TI_SF_BUF_JUMBO)
137 #error "options TI_JUMBO_HDRSPLIT requires TI_SF_BUF_JUMBO"
138 #endif /* TI_JUMBO_HDRSPLIT && !TI_SF_BUF_JUMBO */
146 * Various supported device vendors/types and their names.
149 static const struct ti_type ti_devs[] = {
150 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
151 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
152 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
153 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
154 { TC_VENDORID, TC_DEVICEID_3C985,
155 "3Com 3c985-SX Gigabit Ethernet" },
156 { NG_VENDORID, NG_DEVICEID_GA620,
157 "Netgear GA620 1000baseSX Gigabit Ethernet" },
158 { NG_VENDORID, NG_DEVICEID_GA620T,
159 "Netgear GA620 1000baseT Gigabit Ethernet" },
160 { SGI_VENDORID, SGI_DEVICEID_TIGON,
161 "Silicon Graphics Gigabit Ethernet" },
162 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
163 "Farallon PN9000SX Gigabit Ethernet" },
167 static d_open_t ti_open;
168 static d_close_t ti_close;
169 static d_ioctl_t ti_ioctl2;
171 static struct cdevsw ti_cdevsw = {
172 .d_version = D_VERSION,
176 .d_ioctl = ti_ioctl2,
180 static int ti_probe(device_t);
181 static int ti_attach(device_t);
182 static int ti_detach(device_t);
183 static void ti_txeof(struct ti_softc *);
184 static void ti_rxeof(struct ti_softc *);
186 static int ti_encap(struct ti_softc *, struct mbuf **);
188 static void ti_intr(void *);
189 static void ti_start(if_t);
190 static void ti_start_locked(if_t);
191 static int ti_ioctl(if_t, u_long, caddr_t);
192 static uint64_t ti_get_counter(if_t, ift_counter);
193 static void ti_init(void *);
194 static void ti_init_locked(void *);
195 static void ti_init2(struct ti_softc *);
196 static void ti_stop(struct ti_softc *);
197 static void ti_watchdog(void *);
198 static int ti_shutdown(device_t);
199 static int ti_ifmedia_upd(if_t);
200 static int ti_ifmedia_upd_locked(struct ti_softc *);
201 static void ti_ifmedia_sts(if_t, struct ifmediareq *);
203 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
204 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
205 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
207 static u_int ti_add_mcast(void *, struct sockaddr_dl *, u_int);
208 static u_int ti_del_mcast(void *, struct sockaddr_dl *, u_int);
209 static void ti_setmulti(struct ti_softc *);
211 static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *);
212 static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *);
213 static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t);
214 static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int,
216 static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t,
218 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
219 static void ti_loadfw(struct ti_softc *);
220 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
221 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
222 static void ti_handle_events(struct ti_softc *);
223 static void ti_dma_map_addr(void *, bus_dma_segment_t *, int, int);
224 static int ti_dma_alloc(struct ti_softc *);
225 static void ti_dma_free(struct ti_softc *);
226 static int ti_dma_ring_alloc(struct ti_softc *, bus_size_t, bus_size_t,
227 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
228 static void ti_dma_ring_free(struct ti_softc *, bus_dma_tag_t *, uint8_t **,
229 bus_dmamap_t, bus_addr_t *);
230 static int ti_newbuf_std(struct ti_softc *, int);
231 static int ti_newbuf_mini(struct ti_softc *, int);
232 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
233 static int ti_init_rx_ring_std(struct ti_softc *);
234 static void ti_free_rx_ring_std(struct ti_softc *);
235 static int ti_init_rx_ring_jumbo(struct ti_softc *);
236 static void ti_free_rx_ring_jumbo(struct ti_softc *);
237 static int ti_init_rx_ring_mini(struct ti_softc *);
238 static void ti_free_rx_ring_mini(struct ti_softc *);
239 static void ti_free_tx_ring(struct ti_softc *);
240 static int ti_init_tx_ring(struct ti_softc *);
241 static void ti_discard_std(struct ti_softc *, int);
242 #ifndef TI_SF_BUF_JUMBO
243 static void ti_discard_jumbo(struct ti_softc *, int);
245 static void ti_discard_mini(struct ti_softc *, int);
247 static int ti_64bitslot_war(struct ti_softc *);
248 static int ti_chipinit(struct ti_softc *);
249 static int ti_gibinit(struct ti_softc *);
251 #ifdef TI_JUMBO_HDRSPLIT
252 static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len,
254 #endif /* TI_JUMBO_HDRSPLIT */
256 static void ti_sysctl_node(struct ti_softc *);
258 static device_method_t ti_methods[] = {
259 /* Device interface */
260 DEVMETHOD(device_probe, ti_probe),
261 DEVMETHOD(device_attach, ti_attach),
262 DEVMETHOD(device_detach, ti_detach),
263 DEVMETHOD(device_shutdown, ti_shutdown),
267 static driver_t ti_driver = {
270 sizeof(struct ti_softc)
273 DRIVER_MODULE(ti, pci, ti_driver, 0, 0);
274 MODULE_DEPEND(ti, pci, 1, 1, 1);
275 MODULE_DEPEND(ti, ether, 1, 1, 1);
278 * Send an instruction or address to the EEPROM, check for ACK.
281 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
286 * Make sure we're in TX mode.
288 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
291 * Feed in each bit and stobe the clock.
293 for (i = 0x80; i; i >>= 1) {
295 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
297 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
300 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
302 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
308 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
313 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
314 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
315 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
321 * Read a byte of data stored in the EEPROM at address 'addr.'
322 * We have to send two address bytes since the EEPROM can hold
323 * more than 256 bytes of data.
326 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
334 * Send write control code to EEPROM.
336 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
337 device_printf(sc->ti_dev,
338 "failed to send write command, status: %x\n",
339 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
344 * Send first byte of address of byte we want to read.
346 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
347 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
348 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
352 * Send second byte address of byte we want to read.
354 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
355 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
356 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
363 * Send read control code to EEPROM.
365 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
366 device_printf(sc->ti_dev,
367 "failed to send read command, status: %x\n",
368 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
373 * Start reading bits from EEPROM.
375 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
376 for (i = 0x80; i; i >>= 1) {
377 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
379 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
381 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
388 * No ACK generated for read, so just return byte.
397 * Read a sequence of bytes from the EEPROM.
400 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
405 for (i = 0; i < cnt; i++) {
406 err = ti_eeprom_getbyte(sc, off + i, &byte);
412 return (err ? 1 : 0);
416 * NIC memory read function.
417 * Can be used to copy data from NIC local memory.
420 ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
422 int segptr, segsize, cnt;
433 segsize = TI_WINLEN - (segptr % TI_WINLEN);
434 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN));
435 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
436 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
445 * NIC memory write function.
446 * Can be used to copy data into NIC local memory.
449 ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
451 int segptr, segsize, cnt;
462 segsize = TI_WINLEN - (segptr % TI_WINLEN);
463 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN));
464 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
465 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
474 * NIC memory read function.
475 * Can be used to clear a section of NIC local memory.
478 ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len)
480 int segptr, segsize, cnt;
489 segsize = TI_WINLEN - (segptr % TI_WINLEN);
490 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN));
491 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
492 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4);
499 ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
500 caddr_t buf, int useraddr, int readdata)
502 int segptr, segsize, cnt;
511 * At the moment, we don't handle non-aligned cases, we just bail.
512 * If this proves to be a problem, it will be fixed.
514 if (readdata == 0 && (tigon_addr & 0x3) != 0) {
515 device_printf(sc->ti_dev, "%s: tigon address %#x isn't "
516 "word-aligned\n", __func__, tigon_addr);
517 device_printf(sc->ti_dev, "%s: unaligned writes aren't "
518 "yet supported\n", __func__);
522 segptr = tigon_addr & ~0x3;
523 segresid = tigon_addr - segptr;
526 * This is the non-aligned amount left over that we'll need to
531 /* Add in the left over amount at the front of the buffer */
536 * If resid + segresid is >= 4, add multiples of 4 to the count and
537 * decrease the residual by that much.
540 resid -= resid & ~0x3;
547 * Save the old window base value.
549 origwin = CSR_READ_4(sc, TI_WINBASE);
552 bus_size_t ti_offset;
557 segsize = TI_WINLEN - (segptr % TI_WINLEN);
558 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN));
560 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
563 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
564 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2);
567 * Yeah, this is a little on the kludgy
568 * side, but at least this code is only
569 * used for debugging.
571 ti_bcopy_swap(sc->ti_membuf, sc->ti_membuf2,
572 segsize, TI_SWAP_NTOH);
576 copyout(&sc->ti_membuf2[segresid], ptr,
580 copyout(sc->ti_membuf2, ptr, segsize);
584 ti_bcopy_swap(sc->ti_membuf,
585 sc->ti_membuf2, segsize,
588 bcopy(&sc->ti_membuf2[segresid], ptr,
593 ti_bcopy_swap(sc->ti_membuf, ptr,
594 segsize, TI_SWAP_NTOH);
600 copyin(ptr, sc->ti_membuf2, segsize);
602 ti_bcopy_swap(sc->ti_membuf2, sc->ti_membuf,
603 segsize, TI_SWAP_HTON);
605 ti_bcopy_swap(ptr, sc->ti_membuf, segsize,
608 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
609 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2);
617 * Handle leftover, non-word-aligned bytes.
620 uint32_t tmpval, tmpval2;
621 bus_size_t ti_offset;
624 * Set the segment pointer.
626 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN));
628 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
631 * First, grab whatever is in our source/destination.
632 * We'll obviously need this for reads, but also for
633 * writes, since we'll be doing read/modify/write.
635 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
636 ti_offset, &tmpval, 1);
639 * Next, translate this from little-endian to big-endian
640 * (at least on i386 boxes).
642 tmpval2 = ntohl(tmpval);
646 * If we're reading, just copy the leftover number
647 * of bytes from the host byte order buffer to
652 copyout(&tmpval2, ptr, resid);
655 bcopy(&tmpval2, ptr, resid);
658 * If we're writing, first copy the bytes to be
659 * written into the network byte order buffer,
660 * leaving the rest of the buffer with whatever was
661 * originally in there. Then, swap the bytes
662 * around into host order and write them out.
664 * XXX KDM the read side of this has been verified
665 * to work, but the write side of it has not been
666 * verified. So user beware.
670 copyin(ptr, &tmpval2, resid);
673 bcopy(ptr, &tmpval2, resid);
675 tmpval = htonl(tmpval2);
677 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
678 ti_offset, &tmpval, 1);
682 CSR_WRITE_4(sc, TI_WINBASE, origwin);
688 ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
689 caddr_t buf, int useraddr, int readdata, int cpu)
693 uint32_t tmpval, tmpval2;
699 * At the moment, we don't handle non-aligned cases, we just bail.
700 * If this proves to be a problem, it will be fixed.
702 if (tigon_addr & 0x3) {
703 device_printf(sc->ti_dev, "%s: tigon address %#x "
704 "isn't word-aligned\n", __func__, tigon_addr);
709 device_printf(sc->ti_dev, "%s: transfer length %d "
710 "isn't word-aligned\n", __func__, len);
719 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
722 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
724 tmpval = ntohl(tmpval2);
727 * Note: I've used this debugging interface
728 * extensively with Alteon's 12.3.15 firmware,
729 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
731 * When you compile the firmware without
732 * optimization, which is necessary sometimes in
733 * order to properly step through it, you sometimes
734 * read out a bogus value of 0xc0017c instead of
735 * whatever was supposed to be in that scratchpad
736 * location. That value is on the stack somewhere,
737 * but I've never been able to figure out what was
738 * causing the problem.
740 * The address seems to pop up in random places,
741 * often not in the same place on two subsequent
744 * In any case, the underlying data doesn't seem
745 * to be affected, just the value read out.
750 if (tmpval2 == 0xc0017c)
751 device_printf(sc->ti_dev, "found 0xc0017c at "
752 "%#x (tmpval2)\n", segptr);
754 if (tmpval == 0xc0017c)
755 device_printf(sc->ti_dev, "found 0xc0017c at "
756 "%#x (tmpval)\n", segptr);
759 copyout(&tmpval, ptr, 4);
761 bcopy(&tmpval, ptr, 4);
764 copyin(ptr, &tmpval2, 4);
766 bcopy(ptr, &tmpval2, 4);
768 tmpval = htonl(tmpval2);
770 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
782 ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type)
784 const uint8_t *tmpsrc;
789 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", len);
798 if (swap_type == TI_SWAP_NTOH)
799 *(uint32_t *)tmpdst = ntohl(*(const uint32_t *)tmpsrc);
801 *(uint32_t *)tmpdst = htonl(*(const uint32_t *)tmpsrc);
811 * Load firmware image into the NIC. Check that the firmware revision
812 * is acceptable and see if we want the firmware for the Tigon 1 or
816 ti_loadfw(struct ti_softc *sc)
821 switch (sc->ti_hwrev) {
823 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
824 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
825 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
826 device_printf(sc->ti_dev, "firmware revision mismatch; "
827 "want %d.%d.%d, got %d.%d.%d\n",
828 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
829 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
830 tigonFwReleaseMinor, tigonFwReleaseFix);
833 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
834 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
835 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen,
837 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen);
838 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen);
839 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
841 case TI_HWREV_TIGON_II:
842 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
843 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
844 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
845 device_printf(sc->ti_dev, "firmware revision mismatch; "
846 "want %d.%d.%d, got %d.%d.%d\n",
847 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
848 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
849 tigon2FwReleaseMinor, tigon2FwReleaseFix);
852 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen,
854 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen,
856 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
858 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen);
859 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen);
860 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
863 device_printf(sc->ti_dev,
864 "can't load firmware: unknown hardware rev\n");
870 * Send the NIC a command via the command ring.
873 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
877 index = sc->ti_cmd_saved_prodidx;
878 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
879 TI_INC(index, TI_CMD_RING_CNT);
880 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
881 sc->ti_cmd_saved_prodidx = index;
885 * Send the NIC an extended command. The 'len' parameter specifies the
886 * number of command slots to include after the initial command.
889 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len)
894 index = sc->ti_cmd_saved_prodidx;
895 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
896 TI_INC(index, TI_CMD_RING_CNT);
897 for (i = 0; i < len; i++) {
898 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
899 *(uint32_t *)(&arg[i * 4]));
900 TI_INC(index, TI_CMD_RING_CNT);
902 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
903 sc->ti_cmd_saved_prodidx = index;
907 * Handle events that have triggered interrupts.
910 ti_handle_events(struct ti_softc *sc)
912 struct ti_event_desc *e;
914 if (sc->ti_rdata.ti_event_ring == NULL)
917 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag,
918 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_POSTREAD);
919 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
920 e = &sc->ti_rdata.ti_event_ring[sc->ti_ev_saved_considx];
921 switch (TI_EVENT_EVENT(e)) {
922 case TI_EV_LINKSTAT_CHANGED:
923 sc->ti_linkstat = TI_EVENT_CODE(e);
924 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
925 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
926 if_setbaudrate(sc->ti_ifp, IF_Mbps(100));
928 device_printf(sc->ti_dev,
930 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
931 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
932 if_setbaudrate(sc->ti_ifp, IF_Gbps(1UL));
934 device_printf(sc->ti_dev,
935 "gigabit link up\n");
936 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
937 if_link_state_change(sc->ti_ifp,
939 if_setbaudrate(sc->ti_ifp, 0);
941 device_printf(sc->ti_dev,
946 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
947 device_printf(sc->ti_dev, "invalid command\n");
948 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
949 device_printf(sc->ti_dev, "unknown command\n");
950 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
951 device_printf(sc->ti_dev, "bad config data\n");
953 case TI_EV_FIRMWARE_UP:
956 case TI_EV_STATS_UPDATED:
957 case TI_EV_RESET_JUMBO_RING:
958 case TI_EV_MCAST_UPDATED:
962 device_printf(sc->ti_dev, "unknown event: %d\n",
966 /* Advance the consumer index. */
967 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
968 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
970 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag,
971 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_PREREAD);
974 struct ti_dmamap_arg {
975 bus_addr_t ti_busaddr;
979 ti_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
981 struct ti_dmamap_arg *ctx;
986 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
989 ctx->ti_busaddr = segs->ds_addr;
993 ti_dma_ring_alloc(struct ti_softc *sc, bus_size_t alignment, bus_size_t maxsize,
994 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr,
997 struct ti_dmamap_arg ctx;
1000 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag,
1001 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1002 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
1004 device_printf(sc->ti_dev,
1005 "could not create %s dma tag\n", msg);
1008 /* Allocate DMA'able memory for ring. */
1009 error = bus_dmamem_alloc(*tag, (void **)ring,
1010 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
1012 device_printf(sc->ti_dev,
1013 "could not allocate DMA'able memory for %s\n", msg);
1016 /* Load the address of the ring. */
1018 error = bus_dmamap_load(*tag, *map, *ring, maxsize, ti_dma_map_addr,
1019 &ctx, BUS_DMA_NOWAIT);
1021 device_printf(sc->ti_dev,
1022 "could not load DMA'able memory for %s\n", msg);
1025 *paddr = ctx.ti_busaddr;
1030 ti_dma_ring_free(struct ti_softc *sc, bus_dma_tag_t *tag, uint8_t **ring,
1031 bus_dmamap_t map, bus_addr_t *paddr)
1035 bus_dmamap_unload(*tag, map);
1038 if (*ring != NULL) {
1039 bus_dmamem_free(*tag, *ring, map);
1043 bus_dma_tag_destroy(*tag);
1049 ti_dma_alloc(struct ti_softc *sc)
1054 lowaddr = BUS_SPACE_MAXADDR;
1055 if (sc->ti_dac == 0)
1056 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1058 error = bus_dma_tag_create(bus_get_dma_tag(sc->ti_dev), 1, 0, lowaddr,
1059 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
1060 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
1061 &sc->ti_cdata.ti_parent_tag);
1063 device_printf(sc->ti_dev,
1064 "could not allocate parent dma tag\n");
1068 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_gib),
1069 &sc->ti_cdata.ti_gib_tag, (uint8_t **)&sc->ti_rdata.ti_info,
1070 &sc->ti_cdata.ti_gib_map, &sc->ti_rdata.ti_info_paddr, "GIB");
1074 /* Producer/consumer status */
1075 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_status),
1076 &sc->ti_cdata.ti_status_tag, (uint8_t **)&sc->ti_rdata.ti_status,
1077 &sc->ti_cdata.ti_status_map, &sc->ti_rdata.ti_status_paddr,
1083 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_EVENT_RING_SZ,
1084 &sc->ti_cdata.ti_event_ring_tag,
1085 (uint8_t **)&sc->ti_rdata.ti_event_ring,
1086 &sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr,
1091 /* Command ring lives in shared memory so no need to create DMA area. */
1093 /* Standard RX ring */
1094 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_STD_RX_RING_SZ,
1095 &sc->ti_cdata.ti_rx_std_ring_tag,
1096 (uint8_t **)&sc->ti_rdata.ti_rx_std_ring,
1097 &sc->ti_cdata.ti_rx_std_ring_map,
1098 &sc->ti_rdata.ti_rx_std_ring_paddr, "RX ring");
1103 error = ti_dma_ring_alloc(sc, TI_JUMBO_RING_ALIGN, TI_JUMBO_RX_RING_SZ,
1104 &sc->ti_cdata.ti_rx_jumbo_ring_tag,
1105 (uint8_t **)&sc->ti_rdata.ti_rx_jumbo_ring,
1106 &sc->ti_cdata.ti_rx_jumbo_ring_map,
1107 &sc->ti_rdata.ti_rx_jumbo_ring_paddr, "jumbo RX ring");
1111 /* RX return ring */
1112 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_RX_RETURN_RING_SZ,
1113 &sc->ti_cdata.ti_rx_return_ring_tag,
1114 (uint8_t **)&sc->ti_rdata.ti_rx_return_ring,
1115 &sc->ti_cdata.ti_rx_return_ring_map,
1116 &sc->ti_rdata.ti_rx_return_ring_paddr, "RX return ring");
1120 /* Create DMA tag for standard RX mbufs. */
1121 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1122 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1123 MCLBYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_std_tag);
1125 device_printf(sc->ti_dev, "could not allocate RX dma tag\n");
1129 /* Create DMA tag for jumbo RX mbufs. */
1130 #ifdef TI_SF_BUF_JUMBO
1132 * The VM system will take care of providing aligned pages. Alignment
1133 * is set to 1 here so that busdma resources won't be wasted.
1135 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1136 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE * 4, 4,
1137 PAGE_SIZE, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag);
1139 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1140 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MJUM9BYTES, 1,
1141 MJUM9BYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag);
1144 device_printf(sc->ti_dev,
1145 "could not allocate jumbo RX dma tag\n");
1149 /* Create DMA tag for TX mbufs. */
1150 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1,
1151 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1152 MCLBYTES * TI_MAXTXSEGS, TI_MAXTXSEGS, MCLBYTES, 0, NULL, NULL,
1153 &sc->ti_cdata.ti_tx_tag);
1155 device_printf(sc->ti_dev, "could not allocate TX dma tag\n");
1159 /* Create DMA maps for RX buffers. */
1160 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1161 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0,
1162 &sc->ti_cdata.ti_rx_std_maps[i]);
1164 device_printf(sc->ti_dev,
1165 "could not create DMA map for RX\n");
1169 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0,
1170 &sc->ti_cdata.ti_rx_std_sparemap);
1172 device_printf(sc->ti_dev,
1173 "could not create spare DMA map for RX\n");
1177 /* Create DMA maps for jumbo RX buffers. */
1178 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1179 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0,
1180 &sc->ti_cdata.ti_rx_jumbo_maps[i]);
1182 device_printf(sc->ti_dev,
1183 "could not create DMA map for jumbo RX\n");
1187 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0,
1188 &sc->ti_cdata.ti_rx_jumbo_sparemap);
1190 device_printf(sc->ti_dev,
1191 "could not create spare DMA map for jumbo RX\n");
1195 /* Create DMA maps for TX buffers. */
1196 for (i = 0; i < TI_TX_RING_CNT; i++) {
1197 error = bus_dmamap_create(sc->ti_cdata.ti_tx_tag, 0,
1198 &sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1200 device_printf(sc->ti_dev,
1201 "could not create DMA map for TX\n");
1206 /* Mini ring and TX ring is not available on Tigon 1. */
1207 if (sc->ti_hwrev == TI_HWREV_TIGON)
1211 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_TX_RING_SZ,
1212 &sc->ti_cdata.ti_tx_ring_tag, (uint8_t **)&sc->ti_rdata.ti_tx_ring,
1213 &sc->ti_cdata.ti_tx_ring_map, &sc->ti_rdata.ti_tx_ring_paddr,
1219 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_MINI_RX_RING_SZ,
1220 &sc->ti_cdata.ti_rx_mini_ring_tag,
1221 (uint8_t **)&sc->ti_rdata.ti_rx_mini_ring,
1222 &sc->ti_cdata.ti_rx_mini_ring_map,
1223 &sc->ti_rdata.ti_rx_mini_ring_paddr, "mini RX ring");
1227 /* Create DMA tag for mini RX mbufs. */
1228 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1229 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1,
1230 MHLEN, 0, NULL, NULL, &sc->ti_cdata.ti_rx_mini_tag);
1232 device_printf(sc->ti_dev,
1233 "could not allocate mini RX dma tag\n");
1237 /* Create DMA maps for mini RX buffers. */
1238 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1239 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0,
1240 &sc->ti_cdata.ti_rx_mini_maps[i]);
1242 device_printf(sc->ti_dev,
1243 "could not create DMA map for mini RX\n");
1247 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0,
1248 &sc->ti_cdata.ti_rx_mini_sparemap);
1250 device_printf(sc->ti_dev,
1251 "could not create spare DMA map for mini RX\n");
1259 ti_dma_free(struct ti_softc *sc)
1263 /* Destroy DMA maps for RX buffers. */
1264 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1265 if (sc->ti_cdata.ti_rx_std_maps[i]) {
1266 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag,
1267 sc->ti_cdata.ti_rx_std_maps[i]);
1268 sc->ti_cdata.ti_rx_std_maps[i] = NULL;
1271 if (sc->ti_cdata.ti_rx_std_sparemap) {
1272 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag,
1273 sc->ti_cdata.ti_rx_std_sparemap);
1274 sc->ti_cdata.ti_rx_std_sparemap = NULL;
1276 if (sc->ti_cdata.ti_rx_std_tag) {
1277 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_std_tag);
1278 sc->ti_cdata.ti_rx_std_tag = NULL;
1281 /* Destroy DMA maps for jumbo RX buffers. */
1282 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1283 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) {
1284 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag,
1285 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1286 sc->ti_cdata.ti_rx_jumbo_maps[i] = NULL;
1289 if (sc->ti_cdata.ti_rx_jumbo_sparemap) {
1290 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag,
1291 sc->ti_cdata.ti_rx_jumbo_sparemap);
1292 sc->ti_cdata.ti_rx_jumbo_sparemap = NULL;
1294 if (sc->ti_cdata.ti_rx_jumbo_tag) {
1295 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_jumbo_tag);
1296 sc->ti_cdata.ti_rx_jumbo_tag = NULL;
1299 /* Destroy DMA maps for mini RX buffers. */
1300 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1301 if (sc->ti_cdata.ti_rx_mini_maps[i]) {
1302 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag,
1303 sc->ti_cdata.ti_rx_mini_maps[i]);
1304 sc->ti_cdata.ti_rx_mini_maps[i] = NULL;
1307 if (sc->ti_cdata.ti_rx_mini_sparemap) {
1308 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag,
1309 sc->ti_cdata.ti_rx_mini_sparemap);
1310 sc->ti_cdata.ti_rx_mini_sparemap = NULL;
1312 if (sc->ti_cdata.ti_rx_mini_tag) {
1313 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_mini_tag);
1314 sc->ti_cdata.ti_rx_mini_tag = NULL;
1317 /* Destroy DMA maps for TX buffers. */
1318 for (i = 0; i < TI_TX_RING_CNT; i++) {
1319 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) {
1320 bus_dmamap_destroy(sc->ti_cdata.ti_tx_tag,
1321 sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1322 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL;
1325 if (sc->ti_cdata.ti_tx_tag) {
1326 bus_dma_tag_destroy(sc->ti_cdata.ti_tx_tag);
1327 sc->ti_cdata.ti_tx_tag = NULL;
1330 /* Destroy standard RX ring. */
1331 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_std_ring_tag,
1332 (void *)&sc->ti_rdata.ti_rx_std_ring,
1333 sc->ti_cdata.ti_rx_std_ring_map,
1334 &sc->ti_rdata.ti_rx_std_ring_paddr);
1335 /* Destroy jumbo RX ring. */
1336 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_jumbo_ring_tag,
1337 (void *)&sc->ti_rdata.ti_rx_jumbo_ring,
1338 sc->ti_cdata.ti_rx_jumbo_ring_map,
1339 &sc->ti_rdata.ti_rx_jumbo_ring_paddr);
1340 /* Destroy mini RX ring. */
1341 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_mini_ring_tag,
1342 (void *)&sc->ti_rdata.ti_rx_mini_ring,
1343 sc->ti_cdata.ti_rx_mini_ring_map,
1344 &sc->ti_rdata.ti_rx_mini_ring_paddr);
1345 /* Destroy RX return ring. */
1346 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_return_ring_tag,
1347 (void *)&sc->ti_rdata.ti_rx_return_ring,
1348 sc->ti_cdata.ti_rx_return_ring_map,
1349 &sc->ti_rdata.ti_rx_return_ring_paddr);
1350 /* Destroy TX ring. */
1351 ti_dma_ring_free(sc, &sc->ti_cdata.ti_tx_ring_tag,
1352 (void *)&sc->ti_rdata.ti_tx_ring, sc->ti_cdata.ti_tx_ring_map,
1353 &sc->ti_rdata.ti_tx_ring_paddr);
1354 /* Destroy status block. */
1355 ti_dma_ring_free(sc, &sc->ti_cdata.ti_status_tag,
1356 (void *)&sc->ti_rdata.ti_status, sc->ti_cdata.ti_status_map,
1357 &sc->ti_rdata.ti_status_paddr);
1358 /* Destroy event ring. */
1359 ti_dma_ring_free(sc, &sc->ti_cdata.ti_event_ring_tag,
1360 (void *)&sc->ti_rdata.ti_event_ring,
1361 sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr);
1363 ti_dma_ring_free(sc, &sc->ti_cdata.ti_gib_tag,
1364 (void *)&sc->ti_rdata.ti_info, sc->ti_cdata.ti_gib_map,
1365 &sc->ti_rdata.ti_info_paddr);
1367 /* Destroy the parent tag. */
1368 if (sc->ti_cdata.ti_parent_tag) {
1369 bus_dma_tag_destroy(sc->ti_cdata.ti_parent_tag);
1370 sc->ti_cdata.ti_parent_tag = NULL;
1375 * Intialize a standard receive ring descriptor.
1378 ti_newbuf_std(struct ti_softc *sc, int i)
1381 bus_dma_segment_t segs[1];
1383 struct ti_rx_desc *r;
1386 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1389 m->m_len = m->m_pkthdr.len = MCLBYTES;
1390 m_adj(m, ETHER_ALIGN);
1392 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_std_tag,
1393 sc->ti_cdata.ti_rx_std_sparemap, m, segs, &nsegs, 0);
1398 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1400 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1401 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag,
1402 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_POSTREAD);
1403 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag,
1404 sc->ti_cdata.ti_rx_std_maps[i]);
1407 map = sc->ti_cdata.ti_rx_std_maps[i];
1408 sc->ti_cdata.ti_rx_std_maps[i] = sc->ti_cdata.ti_rx_std_sparemap;
1409 sc->ti_cdata.ti_rx_std_sparemap = map;
1410 sc->ti_cdata.ti_rx_std_chain[i] = m;
1412 r = &sc->ti_rdata.ti_rx_std_ring[i];
1413 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1414 r->ti_len = segs[0].ds_len;
1415 r->ti_type = TI_BDTYPE_RECV_BD;
1418 r->ti_tcp_udp_cksum = 0;
1419 if (if_getcapenable(sc->ti_ifp) & IFCAP_RXCSUM)
1420 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1423 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag,
1424 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_PREREAD);
1429 * Intialize a mini receive ring descriptor. This only applies to
1433 ti_newbuf_mini(struct ti_softc *sc, int i)
1436 bus_dma_segment_t segs[1];
1438 struct ti_rx_desc *r;
1441 MGETHDR(m, M_NOWAIT, MT_DATA);
1444 m->m_len = m->m_pkthdr.len = MHLEN;
1445 m_adj(m, ETHER_ALIGN);
1447 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_mini_tag,
1448 sc->ti_cdata.ti_rx_mini_sparemap, m, segs, &nsegs, 0);
1453 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1455 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1456 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag,
1457 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_POSTREAD);
1458 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag,
1459 sc->ti_cdata.ti_rx_mini_maps[i]);
1462 map = sc->ti_cdata.ti_rx_mini_maps[i];
1463 sc->ti_cdata.ti_rx_mini_maps[i] = sc->ti_cdata.ti_rx_mini_sparemap;
1464 sc->ti_cdata.ti_rx_mini_sparemap = map;
1465 sc->ti_cdata.ti_rx_mini_chain[i] = m;
1467 r = &sc->ti_rdata.ti_rx_mini_ring[i];
1468 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1469 r->ti_len = segs[0].ds_len;
1470 r->ti_type = TI_BDTYPE_RECV_BD;
1471 r->ti_flags = TI_BDFLAG_MINI_RING;
1473 r->ti_tcp_udp_cksum = 0;
1474 if (if_getcapenable(sc->ti_ifp) & IFCAP_RXCSUM)
1475 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1478 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag,
1479 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_PREREAD);
1483 #ifndef TI_SF_BUF_JUMBO
1486 * Initialize a jumbo receive ring descriptor. This allocates
1487 * a jumbo buffer from the pool managed internally by the driver.
1490 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *dummy)
1493 bus_dma_segment_t segs[1];
1495 struct ti_rx_desc *r;
1500 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1503 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1504 m_adj(m, ETHER_ALIGN);
1506 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag,
1507 sc->ti_cdata.ti_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1512 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1514 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1515 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag,
1516 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_POSTREAD);
1517 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag,
1518 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1521 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1522 sc->ti_cdata.ti_rx_jumbo_maps[i] = sc->ti_cdata.ti_rx_jumbo_sparemap;
1523 sc->ti_cdata.ti_rx_jumbo_sparemap = map;
1524 sc->ti_cdata.ti_rx_jumbo_chain[i] = m;
1526 r = &sc->ti_rdata.ti_rx_jumbo_ring[i];
1527 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1528 r->ti_len = segs[0].ds_len;
1529 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1530 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1532 r->ti_tcp_udp_cksum = 0;
1533 if (if_getcapenable(sc->ti_ifp) & IFCAP_RXCSUM)
1534 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1537 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag,
1538 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_PREREAD);
1544 #if (PAGE_SIZE == 4096)
1550 #define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1551 #define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1552 #define NFS_HDR_LEN (UDP_HDR_LEN)
1553 static int HDR_LEN = TCP_HDR_LEN;
1556 * Initialize a jumbo receive ring descriptor. This allocates
1557 * a jumbo buffer from the pool managed internally by the driver.
1560 ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old)
1563 struct mbuf *cur, *m_new = NULL;
1564 struct mbuf *m[3] = {NULL, NULL, NULL};
1565 struct ti_rx_desc_ext *r;
1567 /* 1 extra buf to make nobufs easy*/
1568 struct sf_buf *sf[3] = {NULL, NULL, NULL};
1570 bus_dma_segment_t segs[4];
1573 if (m_old != NULL) {
1575 cur = m_old->m_next;
1576 for (i = 0; i <= NPAYLOAD; i++){
1581 /* Allocate the mbufs. */
1582 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1583 if (m_new == NULL) {
1584 device_printf(sc->ti_dev, "mbuf allocation failed "
1585 "-- packet dropped!\n");
1588 MGET(m[NPAYLOAD], M_NOWAIT, MT_DATA);
1589 if (m[NPAYLOAD] == NULL) {
1590 device_printf(sc->ti_dev, "cluster mbuf allocation "
1591 "failed -- packet dropped!\n");
1594 if (!(MCLGET(m[NPAYLOAD], M_NOWAIT))) {
1595 device_printf(sc->ti_dev, "mbuf allocation failed "
1596 "-- packet dropped!\n");
1599 m[NPAYLOAD]->m_len = MCLBYTES;
1601 for (i = 0; i < NPAYLOAD; i++){
1602 MGET(m[i], M_NOWAIT, MT_DATA);
1604 device_printf(sc->ti_dev, "mbuf allocation "
1605 "failed -- packet dropped!\n");
1608 frame = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT |
1610 if (frame == NULL) {
1611 device_printf(sc->ti_dev, "buffer allocation "
1612 "failed -- packet dropped!\n");
1613 printf(" index %d page %d\n", idx, i);
1616 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1617 if (sf[i] == NULL) {
1618 vm_page_unwire_noq(frame);
1619 vm_page_free(frame);
1620 device_printf(sc->ti_dev, "buffer allocation "
1621 "failed -- packet dropped!\n");
1622 printf(" index %d page %d\n", idx, i);
1626 for (i = 0; i < NPAYLOAD; i++){
1627 /* Attach the buffer to the mbuf. */
1628 m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1629 m[i]->m_len = PAGE_SIZE;
1630 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1631 sf_mext_free, (void*)sf_buf_kva(sf[i]), sf[i],
1633 m[i]->m_next = m[i+1];
1635 /* link the buffers to the header */
1636 m_new->m_next = m[0];
1637 m_new->m_data += ETHER_ALIGN;
1638 if (sc->ti_hdrsplit)
1639 m_new->m_len = MHLEN - ETHER_ALIGN;
1641 m_new->m_len = HDR_LEN;
1642 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1645 /* Set up the descriptor. */
1646 r = &sc->ti_rdata.ti_rx_jumbo_ring[idx];
1647 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1648 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1649 if (bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, map, m_new,
1652 if ((nsegs < 1) || (nsegs > 4))
1654 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr);
1655 r->ti_len0 = m_new->m_len;
1657 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr);
1658 r->ti_len1 = PAGE_SIZE;
1660 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr);
1661 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1663 if (PAGE_SIZE == 4096) {
1664 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr);
1665 r->ti_len3 = MCLBYTES;
1669 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1671 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1673 if (if_getcapenable(sc->ti_ifp) & IFCAP_RXCSUM)
1674 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1678 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, BUS_DMASYNC_PREREAD);
1685 * This can only be called before the mbufs are strung together.
1686 * If the mbufs are strung together, m_freem() will free the chain,
1687 * so that the later mbufs will be freed multiple times.
1692 for (i = 0; i < 3; i++) {
1696 sf_mext_free((void *)sf_buf_kva(sf[i]), sf[i]);
1703 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1704 * that's 1MB or memory, which is a lot. For now, we fill only the first
1705 * 256 ring entries and hope that our CPU is fast enough to keep up with
1709 ti_init_rx_ring_std(struct ti_softc *sc)
1712 struct ti_cmd_desc cmd;
1714 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1715 if (ti_newbuf_std(sc, i) != 0)
1719 sc->ti_std = TI_STD_RX_RING_CNT - 1;
1720 TI_UPDATE_STDPROD(sc, TI_STD_RX_RING_CNT - 1);
1726 ti_free_rx_ring_std(struct ti_softc *sc)
1731 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1732 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1733 map = sc->ti_cdata.ti_rx_std_maps[i];
1734 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, map,
1735 BUS_DMASYNC_POSTREAD);
1736 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, map);
1737 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1738 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1741 bzero(sc->ti_rdata.ti_rx_std_ring, TI_STD_RX_RING_SZ);
1742 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag,
1743 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1747 ti_init_rx_ring_jumbo(struct ti_softc *sc)
1749 struct ti_cmd_desc cmd;
1752 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1753 if (ti_newbuf_jumbo(sc, i, NULL) != 0)
1757 sc->ti_jumbo = TI_JUMBO_RX_RING_CNT - 1;
1758 TI_UPDATE_JUMBOPROD(sc, TI_JUMBO_RX_RING_CNT - 1);
1764 ti_free_rx_ring_jumbo(struct ti_softc *sc)
1769 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1770 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1771 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1772 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map,
1773 BUS_DMASYNC_POSTREAD);
1774 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map);
1775 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1776 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1779 bzero(sc->ti_rdata.ti_rx_jumbo_ring, TI_JUMBO_RX_RING_SZ);
1780 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag,
1781 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1785 ti_init_rx_ring_mini(struct ti_softc *sc)
1789 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1790 if (ti_newbuf_mini(sc, i) != 0)
1794 sc->ti_mini = TI_MINI_RX_RING_CNT - 1;
1795 TI_UPDATE_MINIPROD(sc, TI_MINI_RX_RING_CNT - 1);
1801 ti_free_rx_ring_mini(struct ti_softc *sc)
1806 if (sc->ti_rdata.ti_rx_mini_ring == NULL)
1809 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1810 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1811 map = sc->ti_cdata.ti_rx_mini_maps[i];
1812 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, map,
1813 BUS_DMASYNC_POSTREAD);
1814 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, map);
1815 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1816 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1819 bzero(sc->ti_rdata.ti_rx_mini_ring, TI_MINI_RX_RING_SZ);
1820 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag,
1821 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE);
1825 ti_free_tx_ring(struct ti_softc *sc)
1827 struct ti_txdesc *txd;
1830 if (sc->ti_rdata.ti_tx_ring == NULL)
1833 for (i = 0; i < TI_TX_RING_CNT; i++) {
1834 txd = &sc->ti_cdata.ti_txdesc[i];
1835 if (txd->tx_m != NULL) {
1836 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
1837 BUS_DMASYNC_POSTWRITE);
1838 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag,
1844 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ);
1845 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
1846 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE);
1850 ti_init_tx_ring(struct ti_softc *sc)
1852 struct ti_txdesc *txd;
1855 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq);
1856 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq);
1857 for (i = 0; i < TI_TX_RING_CNT; i++) {
1858 txd = &sc->ti_cdata.ti_txdesc[i];
1859 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
1862 sc->ti_tx_saved_considx = 0;
1863 sc->ti_tx_saved_prodidx = 0;
1864 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1869 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1870 * but we have to support the old way too so that Tigon 1 cards will
1874 ti_add_mcast(void *arg, struct sockaddr_dl *sdl, u_int count)
1876 struct ti_softc *sc = arg;
1877 struct ti_cmd_desc cmd;
1879 uint32_t ext[2] = {0, 0};
1881 m = (uint16_t *)LLADDR(sdl);
1883 switch (sc->ti_hwrev) {
1884 case TI_HWREV_TIGON:
1885 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1886 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1887 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1889 case TI_HWREV_TIGON_II:
1890 ext[0] = htons(m[0]);
1891 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1892 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1895 device_printf(sc->ti_dev, "unknown hwrev\n");
1902 ti_del_mcast(void *arg, struct sockaddr_dl *sdl, u_int count)
1904 struct ti_softc *sc = arg;
1905 struct ti_cmd_desc cmd;
1907 uint32_t ext[2] = {0, 0};
1909 m = (uint16_t *)LLADDR(sdl);
1911 switch (sc->ti_hwrev) {
1912 case TI_HWREV_TIGON:
1913 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1914 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1915 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1917 case TI_HWREV_TIGON_II:
1918 ext[0] = htons(m[0]);
1919 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1920 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1923 device_printf(sc->ti_dev, "unknown hwrev\n");
1931 * Configure the Tigon's multicast address filter.
1933 * The actual multicast table management is a bit of a pain, thanks to
1934 * slight brain damage on the part of both Alteon and us. With our
1935 * multicast code, we are only alerted when the multicast address table
1936 * changes and at that point we only have the current list of addresses:
1937 * we only know the current state, not the previous state, so we don't
1938 * actually know what addresses were removed or added. The firmware has
1939 * state, but we can't get our grubby mits on it, and there is no 'delete
1940 * all multicast addresses' command. Hence, we have to maintain our own
1941 * state so we know what addresses have been programmed into the NIC at
1945 ti_setmulti(struct ti_softc *sc)
1948 struct ti_cmd_desc cmd;
1955 if (if_getflags(ifp) & IFF_ALLMULTI) {
1956 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1959 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1962 /* Disable interrupts. */
1963 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1964 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1966 /* First, zot all the existing filters. */
1967 if_foreach_llmaddr(ifp, ti_del_mcast, sc);
1969 /* Now program new ones. */
1970 if_foreach_llmaddr(ifp, ti_add_mcast, sc);
1972 /* Re-enable interrupts. */
1973 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1977 * Check to see if the BIOS has configured us for a 64 bit slot when
1978 * we aren't actually in one. If we detect this condition, we can work
1979 * around it on the Tigon 2 by setting a bit in the PCI state register,
1980 * but for the Tigon 1 we must give up and abort the interface attach.
1983 ti_64bitslot_war(struct ti_softc *sc)
1986 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1987 CSR_WRITE_4(sc, 0x600, 0);
1988 CSR_WRITE_4(sc, 0x604, 0);
1989 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1990 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1991 if (sc->ti_hwrev == TI_HWREV_TIGON)
1994 TI_SETBIT(sc, TI_PCI_STATE,
1995 TI_PCISTATE_32BIT_BUS);
2005 * Do endian, PCI and DMA initialization. Also check the on-board ROM
2006 * self-test results.
2009 ti_chipinit(struct ti_softc *sc)
2012 uint32_t pci_writemax = 0;
2015 /* Initialize link to down state. */
2016 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
2018 /* Set endianness before we access any non-PCI registers. */
2019 #if 0 && BYTE_ORDER == BIG_ENDIAN
2020 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
2021 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
2023 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
2024 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
2027 /* Check the ROM failed bit to see if self-tests passed. */
2028 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
2029 device_printf(sc->ti_dev, "board self-diagnostics failed!\n");
2034 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
2036 /* Figure out the hardware revision. */
2037 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
2038 case TI_REV_TIGON_I:
2039 sc->ti_hwrev = TI_HWREV_TIGON;
2041 case TI_REV_TIGON_II:
2042 sc->ti_hwrev = TI_HWREV_TIGON_II;
2045 device_printf(sc->ti_dev, "unsupported chip revision\n");
2049 /* Do special setup for Tigon 2. */
2050 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
2051 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
2052 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
2053 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
2057 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
2058 * can't do header splitting.
2060 #ifdef TI_JUMBO_HDRSPLIT
2061 if (sc->ti_hwrev != TI_HWREV_TIGON)
2062 sc->ti_hdrsplit = 1;
2064 device_printf(sc->ti_dev,
2065 "can't do header splitting on a Tigon I board\n");
2066 #endif /* TI_JUMBO_HDRSPLIT */
2068 /* Set up the PCI state register. */
2069 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
2070 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
2071 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
2074 /* Clear the read/write max DMA parameters. */
2075 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
2076 TI_PCISTATE_READ_MAXDMA));
2078 /* Get cache line size. */
2079 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
2082 * If the system has set enabled the PCI memory write
2083 * and invalidate command in the command register, set
2084 * the write max parameter accordingly. This is necessary
2085 * to use MWI with the Tigon 2.
2087 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
2088 switch (cacheline) {
2097 /* Disable PCI memory write and invalidate. */
2099 device_printf(sc->ti_dev, "cache line size %d"
2100 " not supported; disabling PCI MWI\n",
2102 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
2103 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
2108 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
2110 /* This sets the min dma param all the way up (0xff). */
2111 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
2113 if (sc->ti_hdrsplit)
2114 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
2118 /* Configure DMA variables. */
2119 #if BYTE_ORDER == BIG_ENDIAN
2120 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
2121 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
2122 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
2123 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
2124 #else /* BYTE_ORDER */
2125 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
2126 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
2127 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
2128 #endif /* BYTE_ORDER */
2131 * Only allow 1 DMA channel to be active at a time.
2132 * I don't think this is a good idea, but without it
2133 * the firmware racks up lots of nicDmaReadRingFull
2134 * errors. This is not compatible with hardware checksums.
2136 if ((if_getcapenable(sc->ti_ifp) & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0)
2137 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
2139 /* Recommended settings from Tigon manual. */
2140 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
2141 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
2143 if (ti_64bitslot_war(sc)) {
2144 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, "
2153 * Initialize the general information block and firmware, and
2154 * start the CPU(s) running.
2157 ti_gibinit(struct ti_softc *sc)
2167 /* Disable interrupts for now. */
2168 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2170 /* Tell the chip where to find the general information block. */
2171 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI,
2172 (uint64_t)sc->ti_rdata.ti_info_paddr >> 32);
2173 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO,
2174 sc->ti_rdata.ti_info_paddr & 0xFFFFFFFF);
2176 /* Load the firmware into SRAM. */
2179 /* Set up the contents of the general info and ring control blocks. */
2181 /* Set up the event ring and producer pointer. */
2182 bzero(sc->ti_rdata.ti_event_ring, TI_EVENT_RING_SZ);
2183 rcb = &sc->ti_rdata.ti_info->ti_ev_rcb;
2184 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_event_ring_paddr);
2186 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_ev_prodidx_ptr,
2187 sc->ti_rdata.ti_status_paddr +
2188 offsetof(struct ti_status, ti_ev_prodidx_r));
2189 sc->ti_ev_prodidx.ti_idx = 0;
2190 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
2191 sc->ti_ev_saved_considx = 0;
2193 /* Set up the command ring and producer mailbox. */
2194 rcb = &sc->ti_rdata.ti_info->ti_cmd_rcb;
2195 ti_hostaddr64(&rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING));
2197 rcb->ti_max_len = 0;
2198 for (i = 0; i < TI_CMD_RING_CNT; i++) {
2199 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
2201 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
2202 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
2203 sc->ti_cmd_saved_prodidx = 0;
2206 * Assign the address of the stats refresh buffer.
2207 * We re-use the current stats buffer for this to
2210 bzero(&sc->ti_rdata.ti_info->ti_stats, sizeof(struct ti_stats));
2211 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_refresh_stats_ptr,
2212 sc->ti_rdata.ti_info_paddr + offsetof(struct ti_gib, ti_stats));
2214 /* Set up the standard receive ring. */
2215 rcb = &sc->ti_rdata.ti_info->ti_std_rx_rcb;
2216 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_std_ring_paddr);
2217 rcb->ti_max_len = TI_FRAMELEN;
2219 if (if_getcapenable(ifp) & IFCAP_RXCSUM)
2220 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2221 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2222 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
2223 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2225 /* Set up the jumbo receive ring. */
2226 rcb = &sc->ti_rdata.ti_info->ti_jumbo_rx_rcb;
2227 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_jumbo_ring_paddr);
2229 #ifndef TI_SF_BUF_JUMBO
2230 rcb->ti_max_len = MJUM9BYTES - ETHER_ALIGN;
2233 rcb->ti_max_len = PAGE_SIZE;
2234 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
2236 if (if_getcapenable(ifp) & IFCAP_RXCSUM)
2237 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2238 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2239 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
2240 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2243 * Set up the mini ring. Only activated on the
2244 * Tigon 2 but the slot in the config block is
2245 * still there on the Tigon 1.
2247 rcb = &sc->ti_rdata.ti_info->ti_mini_rx_rcb;
2248 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_mini_ring_paddr);
2249 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
2250 if (sc->ti_hwrev == TI_HWREV_TIGON)
2251 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
2254 if (if_getcapenable(ifp) & IFCAP_RXCSUM)
2255 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2256 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2257 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
2258 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2261 * Set up the receive return ring.
2263 rcb = &sc->ti_rdata.ti_info->ti_return_rcb;
2264 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_return_ring_paddr);
2266 rcb->ti_max_len = TI_RETURN_RING_CNT;
2267 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_return_prodidx_ptr,
2268 sc->ti_rdata.ti_status_paddr +
2269 offsetof(struct ti_status, ti_return_prodidx_r));
2272 * Set up the tx ring. Note: for the Tigon 2, we have the option
2273 * of putting the transmit ring in the host's address space and
2274 * letting the chip DMA it instead of leaving the ring in the NIC's
2275 * memory and accessing it through the shared memory region. We
2276 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
2277 * so we have to revert to the shared memory scheme if we detect
2280 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
2281 if (sc->ti_rdata.ti_tx_ring != NULL)
2282 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ);
2283 rcb = &sc->ti_rdata.ti_info->ti_tx_rcb;
2284 if (sc->ti_hwrev == TI_HWREV_TIGON)
2287 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
2288 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
2289 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2290 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2291 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2292 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2293 rcb->ti_max_len = TI_TX_RING_CNT;
2294 if (sc->ti_hwrev == TI_HWREV_TIGON)
2295 ti_hostaddr64(&rcb->ti_hostaddr, TI_TX_RING_BASE);
2297 ti_hostaddr64(&rcb->ti_hostaddr,
2298 sc->ti_rdata.ti_tx_ring_paddr);
2299 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_tx_considx_ptr,
2300 sc->ti_rdata.ti_status_paddr +
2301 offsetof(struct ti_status, ti_tx_considx_r));
2303 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map,
2304 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2305 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, sc->ti_cdata.ti_status_map,
2306 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2307 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag,
2308 sc->ti_cdata.ti_event_ring_map,
2309 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2310 if (sc->ti_rdata.ti_tx_ring != NULL)
2311 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
2312 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE);
2314 /* Set up tunables */
2316 if (if_getmtu(ifp) > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN)
2317 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
2318 (sc->ti_rx_coal_ticks / 10));
2321 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2322 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2323 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2324 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2325 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2326 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2328 /* Turn interrupts on. */
2329 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2330 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2333 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2339 * Probe for a Tigon chip. Check the PCI vendor and device IDs
2340 * against our list and return its name if we find a match.
2343 ti_probe(device_t dev)
2345 const struct ti_type *t;
2349 while (t->ti_name != NULL) {
2350 if ((pci_get_vendor(dev) == t->ti_vid) &&
2351 (pci_get_device(dev) == t->ti_did)) {
2352 device_set_desc(dev, t->ti_name);
2353 return (BUS_PROBE_DEFAULT);
2362 ti_attach(device_t dev)
2365 struct ti_softc *sc;
2369 sc = device_get_softc(dev);
2372 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2374 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0);
2375 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2376 ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
2378 device_printf(dev, "can not if_alloc()\n");
2382 if_sethwassist(ifp, TI_CSUM_FEATURES);
2383 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_RXCSUM);
2384 if_setcapenable(ifp, if_getcapabilities(sc->ti_ifp));
2387 * Map control/status registers.
2389 pci_enable_busmaster(dev);
2392 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2395 if (sc->ti_res == NULL) {
2396 device_printf(dev, "couldn't map memory\n");
2401 sc->ti_btag = rman_get_bustag(sc->ti_res);
2402 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2404 /* Allocate interrupt */
2407 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2408 RF_SHAREABLE | RF_ACTIVE);
2410 if (sc->ti_irq == NULL) {
2411 device_printf(dev, "couldn't map interrupt\n");
2416 if (ti_chipinit(sc)) {
2417 device_printf(dev, "chip initialization failed\n");
2422 /* Zero out the NIC's on-board SRAM. */
2423 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
2425 /* Init again -- zeroing memory may have clobbered some registers. */
2426 if (ti_chipinit(sc)) {
2427 device_printf(dev, "chip initialization failed\n");
2433 * Get station address from the EEPROM. Note: the manual states
2434 * that the MAC address is at offset 0x8c, however the data is
2435 * stored as two longwords (since that's how it's loaded into
2436 * the NIC). This means the MAC address is actually preceded
2437 * by two zero bytes. We need to skip over those.
2439 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2440 device_printf(dev, "failed to read station address\n");
2445 /* Allocate working area for memory dump. */
2446 sc->ti_membuf = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, M_NOWAIT);
2447 sc->ti_membuf2 = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF,
2449 if (sc->ti_membuf == NULL || sc->ti_membuf2 == NULL) {
2450 device_printf(dev, "cannot allocate memory buffer\n");
2454 if ((error = ti_dma_alloc(sc)) != 0)
2458 * We really need a better way to tell a 1000baseTX card
2459 * from a 1000baseSX one, since in theory there could be
2460 * OEMed 1000baseTX cards from lame vendors who aren't
2461 * clever enough to change the PCI ID. For the moment
2462 * though, the AceNIC is the only copper card available.
2464 if (pci_get_vendor(dev) == ALT_VENDORID &&
2465 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2467 /* Ok, it's not the only copper card available. */
2468 if (pci_get_vendor(dev) == NG_VENDORID &&
2469 pci_get_device(dev) == NG_DEVICEID_GA620T)
2472 /* Set default tunable values. */
2475 /* Set up ifnet structure */
2476 if_setsoftc(ifp, sc);
2477 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2478 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
2479 if_setioctlfn(ifp, ti_ioctl);
2480 if_setstartfn(ifp, ti_start);
2481 if_setinitfn(ifp, ti_init);
2482 if_setgetcounterfn(ifp, ti_get_counter);
2483 if_setbaudrate(ifp, IF_Gbps(1UL));
2484 if_setsendqlen(ifp, TI_TX_RING_CNT - 1);
2485 if_setsendqready(ifp);
2487 /* Set up ifmedia support. */
2488 if (sc->ti_copper) {
2490 * Copper cards allow manual 10/100 mode selection,
2491 * but not manual 1000baseTX mode selection. Why?
2492 * Because currently there's no way to specify the
2493 * master/slave setting through the firmware interface,
2494 * so Alteon decided to just bag it and handle it
2495 * via autonegotiation.
2497 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2498 ifmedia_add(&sc->ifmedia,
2499 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2500 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2501 ifmedia_add(&sc->ifmedia,
2502 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2503 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2504 ifmedia_add(&sc->ifmedia,
2505 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2507 /* Fiber cards don't support 10/100 modes. */
2508 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2509 ifmedia_add(&sc->ifmedia,
2510 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2512 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2513 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2516 * We're assuming here that card initialization is a sequential
2517 * thing. If it isn't, multiple cards probing at the same time
2518 * could stomp on the list of softcs here.
2521 /* Register the device */
2522 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT,
2523 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev));
2524 sc->dev->si_drv1 = sc;
2527 * Call MI attach routine.
2529 ether_ifattach(ifp, eaddr);
2531 /* VLAN capability setup. */
2532 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM |
2533 IFCAP_VLAN_HWTAGGING, 0);
2534 if_setcapenable(ifp, if_getcapabilities(ifp));
2535 /* Tell the upper layer we support VLAN over-sized frames. */
2536 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
2538 /* Driver supports link state tracking. */
2539 if_setcapabilitiesbit(ifp, IFCAP_LINKSTATE, 0);
2540 if_setcapenablebit(ifp, IFCAP_LINKSTATE, 0);
2542 /* Hook interrupt last to avoid having to lock softc */
2543 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE,
2544 NULL, ti_intr, sc, &sc->ti_intrhand);
2547 device_printf(dev, "couldn't set up irq\n");
2559 * Shutdown hardware and free up resources. This can be called any
2560 * time after the mutex has been initialized. It is called in both
2561 * the error case in attach and the normal detach case so it needs
2562 * to be careful about only freeing resources that have actually been
2566 ti_detach(device_t dev)
2568 struct ti_softc *sc;
2571 sc = device_get_softc(dev);
2573 destroy_dev(sc->dev);
2574 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2576 if (device_is_attached(dev)) {
2577 ether_ifdetach(ifp);
2583 /* These should only be active if attach succeeded */
2584 callout_drain(&sc->ti_watchdog);
2585 bus_generic_detach(dev);
2587 ifmedia_removeall(&sc->ifmedia);
2589 if (sc->ti_intrhand)
2590 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2592 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2594 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
2600 free(sc->ti_membuf, M_DEVBUF);
2602 free(sc->ti_membuf2, M_DEVBUF);
2604 mtx_destroy(&sc->ti_mtx);
2609 #ifdef TI_JUMBO_HDRSPLIT
2611 * If hdr_len is 0, that means that header splitting wasn't done on
2612 * this packet for some reason. The two most likely reasons are that
2613 * the protocol isn't a supported protocol for splitting, or this
2614 * packet had a fragment offset that wasn't 0.
2616 * The header length, if it is non-zero, will always be the length of
2617 * the headers on the packet, but that length could be longer than the
2618 * first mbuf. So we take the minimum of the two as the actual
2621 static __inline void
2622 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2625 int lengths[4] = {0, 0, 0, 0};
2626 struct mbuf *m, *mp;
2629 top->m_len = min(hdr_len, top->m_len);
2630 pkt_len -= top->m_len;
2631 lengths[i++] = top->m_len;
2634 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2635 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2636 pkt_len -= m->m_len;
2637 lengths[i++] = m->m_len;
2643 printf("got split packet: ");
2645 printf("got non-split packet: ");
2647 printf("%d,%d,%d,%d = %d\n", lengths[0],
2648 lengths[1], lengths[2], lengths[3],
2649 lengths[0] + lengths[1] + lengths[2] +
2654 panic("header splitting didn't");
2660 if (mp->m_next != NULL)
2661 panic("ti_hdr_split: last mbuf in chain should be null");
2663 #endif /* TI_JUMBO_HDRSPLIT */
2666 ti_discard_std(struct ti_softc *sc, int i)
2669 struct ti_rx_desc *r;
2671 r = &sc->ti_rdata.ti_rx_std_ring[i];
2672 r->ti_len = MCLBYTES - ETHER_ALIGN;
2673 r->ti_type = TI_BDTYPE_RECV_BD;
2676 r->ti_tcp_udp_cksum = 0;
2677 if (if_getcapenable(sc->ti_ifp) & IFCAP_RXCSUM)
2678 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2683 ti_discard_mini(struct ti_softc *sc, int i)
2686 struct ti_rx_desc *r;
2688 r = &sc->ti_rdata.ti_rx_mini_ring[i];
2689 r->ti_len = MHLEN - ETHER_ALIGN;
2690 r->ti_type = TI_BDTYPE_RECV_BD;
2691 r->ti_flags = TI_BDFLAG_MINI_RING;
2693 r->ti_tcp_udp_cksum = 0;
2694 if (if_getcapenable(sc->ti_ifp) & IFCAP_RXCSUM)
2695 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2699 #ifndef TI_SF_BUF_JUMBO
2701 ti_discard_jumbo(struct ti_softc *sc, int i)
2704 struct ti_rx_desc *r;
2706 r = &sc->ti_rdata.ti_rx_jumbo_ring[i];
2707 r->ti_len = MJUM9BYTES - ETHER_ALIGN;
2708 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
2709 r->ti_flags = TI_BDFLAG_JUMBO_RING;
2711 r->ti_tcp_udp_cksum = 0;
2712 if (if_getcapenable(sc->ti_ifp) & IFCAP_RXCSUM)
2713 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2719 * Frame reception handling. This is called if there's a frame
2720 * on the receive return list.
2722 * Note: we have to be able to handle three possibilities here:
2723 * 1) the frame is from the mini receive ring (can only happen)
2724 * on Tigon 2 boards)
2725 * 2) the frame is from the jumbo receive ring
2726 * 3) the frame is from the standard receive ring
2730 ti_rxeof(struct ti_softc *sc)
2733 #ifdef TI_SF_BUF_JUMBO
2736 struct ti_cmd_desc cmd;
2737 int jumbocnt, minicnt, stdcnt, ti_len;
2743 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag,
2744 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
2745 if (if_getmtu(ifp) > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN)
2746 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag,
2747 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
2748 if (sc->ti_rdata.ti_rx_mini_ring != NULL)
2749 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag,
2750 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_POSTWRITE);
2751 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag,
2752 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
2754 jumbocnt = minicnt = stdcnt = 0;
2755 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2756 struct ti_rx_desc *cur_rx;
2758 struct mbuf *m = NULL;
2759 uint16_t vlan_tag = 0;
2763 &sc->ti_rdata.ti_rx_return_ring[sc->ti_rx_saved_considx];
2764 rxidx = cur_rx->ti_idx;
2765 ti_len = cur_rx->ti_len;
2766 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2768 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2770 vlan_tag = cur_rx->ti_vlan_tag;
2773 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2775 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2776 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2777 #ifndef TI_SF_BUF_JUMBO
2778 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2779 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2780 ti_discard_jumbo(sc, rxidx);
2783 if (ti_newbuf_jumbo(sc, rxidx, NULL) != 0) {
2784 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2785 ti_discard_jumbo(sc, rxidx);
2789 #else /* !TI_SF_BUF_JUMBO */
2790 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2791 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx];
2792 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map,
2793 BUS_DMASYNC_POSTREAD);
2794 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map);
2795 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2796 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2797 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2800 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2801 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2802 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2805 #ifdef TI_JUMBO_HDRSPLIT
2806 if (sc->ti_hdrsplit)
2807 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2810 #endif /* TI_JUMBO_HDRSPLIT */
2811 m_adj(m, ti_len - m->m_pkthdr.len);
2812 #endif /* TI_SF_BUF_JUMBO */
2813 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2815 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2816 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2817 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2818 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2819 ti_discard_mini(sc, rxidx);
2822 if (ti_newbuf_mini(sc, rxidx) != 0) {
2823 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2824 ti_discard_mini(sc, rxidx);
2830 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2831 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2832 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2833 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2834 ti_discard_std(sc, rxidx);
2837 if (ti_newbuf_std(sc, rxidx) != 0) {
2838 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2839 ti_discard_std(sc, rxidx);
2845 m->m_pkthdr.len = ti_len;
2846 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2847 m->m_pkthdr.rcvif = ifp;
2849 if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
2850 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) {
2851 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2852 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2853 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2855 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) {
2856 m->m_pkthdr.csum_data =
2857 cur_rx->ti_tcp_udp_cksum;
2858 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2863 * If we received a packet with a vlan tag,
2864 * tag it before passing the packet upward.
2867 m->m_pkthdr.ether_vtag = vlan_tag;
2868 m->m_flags |= M_VLANTAG;
2875 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag,
2876 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_PREREAD);
2877 /* Only necessary on the Tigon 1. */
2878 if (sc->ti_hwrev == TI_HWREV_TIGON)
2879 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2880 sc->ti_rx_saved_considx);
2883 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag,
2884 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
2885 TI_UPDATE_STDPROD(sc, sc->ti_std);
2888 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag,
2889 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE);
2890 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2893 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag,
2894 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
2895 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2900 ti_txeof(struct ti_softc *sc)
2902 struct ti_txdesc *txd;
2903 struct ti_tx_desc txdesc;
2904 struct ti_tx_desc *cur_tx = NULL;
2910 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2914 if (sc->ti_rdata.ti_tx_ring != NULL)
2915 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
2916 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_POSTWRITE);
2918 * Go through our tx ring and free mbufs for those
2919 * frames that have been sent.
2921 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx;
2922 TI_INC(idx, TI_TX_RING_CNT)) {
2923 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2924 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc),
2925 sizeof(txdesc), &txdesc);
2928 cur_tx = &sc->ti_rdata.ti_tx_ring[idx];
2930 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2931 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0)
2933 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
2934 BUS_DMASYNC_POSTWRITE);
2935 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap);
2937 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2940 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q);
2941 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
2942 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2944 sc->ti_tx_saved_considx = idx;
2945 if (sc->ti_txcnt == 0)
2952 struct ti_softc *sc;
2959 /* Make sure this is really our interrupt. */
2960 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2965 /* Ack interrupt and stop others from occurring. */
2966 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2968 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
2969 bus_dmamap_sync(sc->ti_cdata.ti_status_tag,
2970 sc->ti_cdata.ti_status_map, BUS_DMASYNC_POSTREAD);
2971 /* Check RX return ring producer/consumer */
2974 /* Check TX ring producer/consumer */
2976 bus_dmamap_sync(sc->ti_cdata.ti_status_tag,
2977 sc->ti_cdata.ti_status_map, BUS_DMASYNC_PREREAD);
2980 ti_handle_events(sc);
2982 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
2983 /* Re-enable interrupts. */
2984 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2985 if (!if_sendq_empty(ifp))
2986 ti_start_locked(ifp);
2993 ti_get_counter(if_t ifp, ift_counter cnt)
2997 case IFCOUNTER_COLLISIONS:
2999 struct ti_softc *sc;
3003 sc = if_getsoftc(ifp);
3004 s = &sc->ti_rdata.ti_info->ti_stats;
3007 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag,
3008 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD);
3009 rv = s->dot3StatsSingleCollisionFrames +
3010 s->dot3StatsMultipleCollisionFrames +
3011 s->dot3StatsExcessiveCollisions +
3012 s->dot3StatsLateCollisions;
3013 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag,
3014 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_PREREAD);
3019 return (if_get_counter_default(ifp, cnt));
3024 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3025 * pointers to descriptors.
3028 ti_encap(struct ti_softc *sc, struct mbuf **m_head)
3030 struct ti_txdesc *txd;
3031 struct ti_tx_desc *f;
3032 struct ti_tx_desc txdesc;
3034 bus_dma_segment_t txsegs[TI_MAXTXSEGS];
3035 uint16_t csum_flags;
3036 int error, frag, i, nseg;
3038 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL)
3041 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
3042 *m_head, txsegs, &nseg, 0);
3043 if (error == EFBIG) {
3044 m = m_defrag(*m_head, M_NOWAIT);
3051 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag,
3052 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
3058 } else if (error != 0)
3066 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) {
3067 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap);
3070 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
3071 BUS_DMASYNC_PREWRITE);
3075 if (m->m_pkthdr.csum_flags & CSUM_IP)
3076 csum_flags |= TI_BDFLAG_IP_CKSUM;
3077 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3078 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
3080 frag = sc->ti_tx_saved_prodidx;
3081 for (i = 0; i < nseg; i++) {
3082 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3083 bzero(&txdesc, sizeof(txdesc));
3086 f = &sc->ti_rdata.ti_tx_ring[frag];
3087 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr);
3088 f->ti_len = txsegs[i].ds_len;
3089 f->ti_flags = csum_flags;
3090 if (m->m_flags & M_VLANTAG) {
3091 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
3092 f->ti_vlan_tag = m->m_pkthdr.ether_vtag;
3097 if (sc->ti_hwrev == TI_HWREV_TIGON)
3098 ti_mem_write(sc, TI_TX_RING_BASE + frag *
3099 sizeof(txdesc), sizeof(txdesc), &txdesc);
3100 TI_INC(frag, TI_TX_RING_CNT);
3103 sc->ti_tx_saved_prodidx = frag;
3104 /* set TI_BDFLAG_END on the last descriptor */
3105 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT;
3106 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3107 txdesc.ti_flags |= TI_BDFLAG_END;
3108 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc),
3109 sizeof(txdesc), &txdesc);
3111 sc->ti_rdata.ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END;
3113 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q);
3114 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q);
3116 sc->ti_txcnt += nseg;
3124 struct ti_softc *sc;
3126 sc = if_getsoftc(ifp);
3128 ti_start_locked(ifp);
3133 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3134 * to the mbuf data regions directly in the transmit descriptors.
3137 ti_start_locked(if_t ifp)
3139 struct ti_softc *sc;
3140 struct mbuf *m_head = NULL;
3143 sc = if_getsoftc(ifp);
3145 for (; !if_sendq_empty(ifp) &&
3146 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) {
3147 m_head = if_dequeue(ifp);
3152 * Pack the data into the transmit ring. If we
3153 * don't have room, set the OACTIVE flag and wait
3154 * for the NIC to drain the ring.
3156 if (ti_encap(sc, &m_head)) {
3159 if_sendq_prepend(ifp, m_head);
3160 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
3166 * If there's a BPF listener, bounce a copy of this frame
3169 ETHER_BPF_MTAP(ifp, m_head);
3173 if (sc->ti_rdata.ti_tx_ring != NULL)
3174 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
3175 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE);
3177 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx);
3180 * Set a timeout in case the chip goes out to lunch.
3189 struct ti_softc *sc;
3198 ti_init_locked(void *xsc)
3200 struct ti_softc *sc = xsc;
3202 if (if_getdrvflags(sc->ti_ifp) & IFF_DRV_RUNNING)
3205 /* Cancel pending I/O and flush buffers. */
3208 /* Init the gen info block, ring control blocks and firmware. */
3209 if (ti_gibinit(sc)) {
3210 device_printf(sc->ti_dev, "initialization failure\n");
3215 static void ti_init2(struct ti_softc *sc)
3217 struct ti_cmd_desc cmd;
3220 struct ifmedia *ifm;
3227 /* Specify MTU and interface index. */
3228 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev));
3229 CSR_WRITE_4(sc, TI_GCR_IFMTU, if_getmtu(ifp) +
3230 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
3231 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
3233 /* Load our MAC address. */
3234 ea = if_getlladdr(sc->ti_ifp);
3235 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]);
3236 CSR_WRITE_4(sc, TI_GCR_PAR1,
3237 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]);
3238 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
3240 /* Enable or disable promiscuous mode as needed. */
3241 if (if_getflags(ifp) & IFF_PROMISC) {
3242 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
3244 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
3247 /* Program multicast filter. */
3251 * If this is a Tigon 1, we should tell the
3252 * firmware to use software packet filtering.
3254 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3255 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
3259 if (ti_init_rx_ring_std(sc) != 0) {
3261 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n");
3265 /* Init jumbo RX ring. */
3266 if (if_getmtu(ifp) > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) {
3267 if (ti_init_rx_ring_jumbo(sc) != 0) {
3269 device_printf(sc->ti_dev,
3270 "no memory for jumbo Rx buffers.\n");
3276 * If this is a Tigon 2, we can also configure the
3279 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
3280 if (ti_init_rx_ring_mini(sc) != 0) {
3282 device_printf(sc->ti_dev,
3283 "no memory for mini Rx buffers.\n");
3288 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
3289 sc->ti_rx_saved_considx = 0;
3292 ti_init_tx_ring(sc);
3294 /* Tell firmware we're alive. */
3295 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
3297 /* Enable host interrupts. */
3298 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3300 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
3301 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
3302 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3305 * Make sure to set media properly. We have to do this
3306 * here since we have to issue commands in order to set
3307 * the link negotiation and we can't issue commands until
3308 * the firmware is running.
3311 tmp = ifm->ifm_media;
3312 ifm->ifm_media = ifm->ifm_cur->ifm_media;
3313 ti_ifmedia_upd_locked(sc);
3314 ifm->ifm_media = tmp;
3318 * Set media options.
3321 ti_ifmedia_upd(if_t ifp)
3323 struct ti_softc *sc;
3326 sc = if_getsoftc(ifp);
3328 error = ti_ifmedia_upd_locked(sc);
3335 ti_ifmedia_upd_locked(struct ti_softc *sc)
3337 struct ifmedia *ifm;
3338 struct ti_cmd_desc cmd;
3343 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3348 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3351 * Transmit flow control doesn't work on the Tigon 1.
3353 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3356 * Transmit flow control can also cause problems on the
3357 * Tigon 2, apparently with both the copper and fiber
3358 * boards. The symptom is that the interface will just
3359 * hang. This was reproduced with Alteon 180 switches.
3362 if (sc->ti_hwrev != TI_HWREV_TIGON)
3363 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3366 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3367 TI_GLNK_FULL_DUPLEX| flowctl |
3368 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
3370 flowctl = TI_LNK_RX_FLOWCTL_Y;
3372 if (sc->ti_hwrev != TI_HWREV_TIGON)
3373 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3376 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
3377 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
3378 TI_LNK_AUTONEGENB|TI_LNK_ENB);
3379 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3380 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
3384 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3386 if (sc->ti_hwrev != TI_HWREV_TIGON)
3387 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3390 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3391 flowctl |TI_GLNK_ENB);
3392 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
3393 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3394 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
3396 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3397 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3403 flowctl = TI_LNK_RX_FLOWCTL_Y;
3405 if (sc->ti_hwrev != TI_HWREV_TIGON)
3406 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3409 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3410 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3411 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3412 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3413 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3415 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3417 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3418 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3420 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3422 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3423 TI_CMD_CODE_NEGOTIATE_10_100, 0);
3431 * Report current media status.
3434 ti_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
3436 struct ti_softc *sc;
3439 sc = if_getsoftc(ifp);
3443 ifmr->ifm_status = IFM_AVALID;
3444 ifmr->ifm_active = IFM_ETHER;
3446 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
3451 ifmr->ifm_status |= IFM_ACTIVE;
3453 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3454 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3456 ifmr->ifm_active |= IFM_1000_T;
3458 ifmr->ifm_active |= IFM_1000_SX;
3459 if (media & TI_GLNK_FULL_DUPLEX)
3460 ifmr->ifm_active |= IFM_FDX;
3462 ifmr->ifm_active |= IFM_HDX;
3463 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3464 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3465 if (sc->ti_copper) {
3466 if (media & TI_LNK_100MB)
3467 ifmr->ifm_active |= IFM_100_TX;
3468 if (media & TI_LNK_10MB)
3469 ifmr->ifm_active |= IFM_10_T;
3471 if (media & TI_LNK_100MB)
3472 ifmr->ifm_active |= IFM_100_FX;
3473 if (media & TI_LNK_10MB)
3474 ifmr->ifm_active |= IFM_10_FL;
3476 if (media & TI_LNK_FULL_DUPLEX)
3477 ifmr->ifm_active |= IFM_FDX;
3478 if (media & TI_LNK_HALF_DUPLEX)
3479 ifmr->ifm_active |= IFM_HDX;
3485 ti_ioctl(if_t ifp, u_long command, caddr_t data)
3487 struct ti_softc *sc = if_getsoftc(ifp);
3488 struct ifreq *ifr = (struct ifreq *) data;
3489 struct ti_cmd_desc cmd;
3490 int mask, error = 0;
3495 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU)
3498 if_setmtu(ifp, ifr->ifr_mtu);
3499 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3500 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3508 if (if_getflags(ifp) & IFF_UP) {
3510 * If only the state of the PROMISC flag changed,
3511 * then just use the 'set promisc mode' command
3512 * instead of reinitializing the entire NIC. Doing
3513 * a full re-init means reloading the firmware and
3514 * waiting for it to start up, which may take a
3517 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
3518 if_getflags(ifp) & IFF_PROMISC &&
3519 !(sc->ti_if_flags & IFF_PROMISC)) {
3520 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3521 TI_CMD_CODE_PROMISC_ENB, 0);
3522 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
3523 !(if_getflags(ifp) & IFF_PROMISC) &&
3524 sc->ti_if_flags & IFF_PROMISC) {
3525 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3526 TI_CMD_CODE_PROMISC_DIS, 0);
3530 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3534 sc->ti_if_flags = if_getflags(ifp);
3540 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3546 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3550 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
3551 if ((mask & IFCAP_TXCSUM) != 0 &&
3552 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
3553 if_togglecapenable(ifp, IFCAP_TXCSUM);
3554 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
3555 if_sethwassistbits(ifp, TI_CSUM_FEATURES, 0);
3557 if_sethwassistbits(ifp, 0, TI_CSUM_FEATURES);
3559 if ((mask & IFCAP_RXCSUM) != 0 &&
3560 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
3561 if_togglecapenable(ifp, IFCAP_RXCSUM);
3562 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3563 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
3564 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
3565 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
3566 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
3567 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
3568 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM |
3569 IFCAP_VLAN_HWTAGGING)) != 0) {
3570 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3571 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3576 VLAN_CAPABILITIES(ifp);
3579 error = ether_ioctl(ifp, command, data);
3587 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3589 struct ti_softc *sc;
3596 sc->ti_flags |= TI_FLAG_DEBUGING;
3603 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3605 struct ti_softc *sc;
3612 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3619 * This ioctl routine goes along with the Tigon character device.
3622 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag,
3625 struct ti_softc *sc;
3637 struct ti_stats *outstats;
3639 outstats = (struct ti_stats *)addr;
3642 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag,
3643 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD);
3644 bcopy(&sc->ti_rdata.ti_info->ti_stats, outstats,
3645 sizeof(struct ti_stats));
3646 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag,
3647 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_PREREAD);
3651 case TIIOCGETPARAMS:
3653 struct ti_params *params;
3655 params = (struct ti_params *)addr;
3658 params->ti_stat_ticks = sc->ti_stat_ticks;
3659 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3660 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3661 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3662 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3663 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3664 params->param_mask = TI_PARAM_ALL;
3668 case TIIOCSETPARAMS:
3670 struct ti_params *params;
3672 params = (struct ti_params *)addr;
3675 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3676 sc->ti_stat_ticks = params->ti_stat_ticks;
3677 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3680 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3681 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3682 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3683 sc->ti_rx_coal_ticks);
3686 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3687 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3688 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3689 sc->ti_tx_coal_ticks);
3692 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3693 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3694 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3695 sc->ti_rx_max_coal_bds);
3698 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3699 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3700 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3701 sc->ti_tx_max_coal_bds);
3704 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3705 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3706 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3707 sc->ti_tx_buf_ratio);
3712 case TIIOCSETTRACE: {
3713 ti_trace_type trace_type;
3715 trace_type = *(ti_trace_type *)addr;
3718 * Set tracing to whatever the user asked for. Setting
3719 * this register to 0 should have the effect of disabling
3723 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3727 case TIIOCGETTRACE: {
3728 struct ti_trace_buf *trace_buf;
3729 uint32_t trace_start, cur_trace_ptr, trace_len;
3731 trace_buf = (struct ti_trace_buf *)addr;
3734 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3735 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3736 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3738 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, "
3739 "trace_len = %d\n", trace_start,
3740 cur_trace_ptr, trace_len);
3741 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n",
3742 trace_buf->buf_len);
3744 error = ti_copy_mem(sc, trace_start, min(trace_len,
3745 trace_buf->buf_len), (caddr_t)trace_buf->buf, 1, 1);
3747 trace_buf->fill_len = min(trace_len,
3748 trace_buf->buf_len);
3749 if (cur_trace_ptr < trace_start)
3750 trace_buf->cur_trace_ptr =
3751 trace_start - cur_trace_ptr;
3753 trace_buf->cur_trace_ptr =
3754 cur_trace_ptr - trace_start;
3756 trace_buf->fill_len = 0;
3762 * For debugging, five ioctls are needed:
3771 * From what I can tell, Alteon's Solaris Tigon driver
3772 * only has one character device, so you have to attach
3773 * to the Tigon board you're interested in. This seems
3774 * like a not-so-good way to do things, since unless you
3775 * subsequently specify the unit number of the device
3776 * you're interested in every ioctl, you'll only be
3777 * able to debug one board at a time.
3780 case ALT_READ_TG_MEM:
3781 case ALT_WRITE_TG_MEM:
3783 struct tg_mem *mem_param;
3784 uint32_t sram_end, scratch_end;
3786 mem_param = (struct tg_mem *)addr;
3788 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3789 sram_end = TI_END_SRAM_I;
3790 scratch_end = TI_END_SCRATCH_I;
3792 sram_end = TI_END_SRAM_II;
3793 scratch_end = TI_END_SCRATCH_II;
3797 * For now, we'll only handle accessing regular SRAM,
3801 if (mem_param->tgAddr >= TI_BEG_SRAM &&
3802 mem_param->tgAddr + mem_param->len <= sram_end) {
3804 * In this instance, we always copy to/from user
3805 * space, so the user space argument is set to 1.
3807 error = ti_copy_mem(sc, mem_param->tgAddr,
3808 mem_param->len, mem_param->userAddr, 1,
3809 cmd == ALT_READ_TG_MEM ? 1 : 0);
3810 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH &&
3811 mem_param->tgAddr <= scratch_end) {
3812 error = ti_copy_scratch(sc, mem_param->tgAddr,
3813 mem_param->len, mem_param->userAddr, 1,
3814 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_A);
3815 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG &&
3816 mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG) {
3817 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3818 if_printf(sc->ti_ifp,
3819 "invalid memory range for Tigon I\n");
3823 error = ti_copy_scratch(sc, mem_param->tgAddr -
3824 TI_SCRATCH_DEBUG_OFF, mem_param->len,
3825 mem_param->userAddr, 1,
3826 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_B);
3828 if_printf(sc->ti_ifp, "memory address %#x len %d is "
3829 "out of supported range\n",
3830 mem_param->tgAddr, mem_param->len);
3836 case ALT_READ_TG_REG:
3837 case ALT_WRITE_TG_REG:
3839 struct tg_reg *regs;
3842 regs = (struct tg_reg *)addr;
3845 * Make sure the address in question isn't out of range.
3847 if (regs->addr > TI_REG_MAX) {
3852 if (cmd == ALT_READ_TG_REG) {
3853 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3854 regs->addr, &tmpval, 1);
3855 regs->data = ntohl(tmpval);
3857 if ((regs->addr == TI_CPU_STATE)
3858 || (regs->addr == TI_CPU_CTL_B)) {
3859 if_printf(sc->ti_ifp, "register %#x = %#x\n",
3860 regs->addr, tmpval);
3864 tmpval = htonl(regs->data);
3865 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3866 regs->addr, &tmpval, 1);
3879 ti_watchdog(void *arg)
3881 struct ti_softc *sc;
3886 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3887 if (sc->ti_timer == 0 || --sc->ti_timer > 0)
3891 * When we're debugging, the chip is often stopped for long periods
3892 * of time, and that would normally cause the watchdog timer to fire.
3893 * Since that impedes debugging, we don't want to do that.
3895 if (sc->ti_flags & TI_FLAG_DEBUGING)
3899 if_printf(ifp, "watchdog timeout -- resetting\n");
3900 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3903 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3907 * Stop the adapter and free any mbufs allocated to the
3911 ti_stop(struct ti_softc *sc)
3914 struct ti_cmd_desc cmd;
3920 /* Disable host interrupts. */
3921 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3923 * Tell firmware we're shutting down.
3925 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3927 /* Halt and reinitialize. */
3928 if (ti_chipinit(sc) == 0) {
3929 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
3930 /* XXX ignore init errors. */
3934 /* Free the RX lists. */
3935 ti_free_rx_ring_std(sc);
3937 /* Free jumbo RX list. */
3938 ti_free_rx_ring_jumbo(sc);
3940 /* Free mini RX list. */
3941 ti_free_rx_ring_mini(sc);
3943 /* Free TX buffers. */
3944 ti_free_tx_ring(sc);
3946 sc->ti_ev_prodidx.ti_idx = 0;
3947 sc->ti_return_prodidx.ti_idx = 0;
3948 sc->ti_tx_considx.ti_idx = 0;
3949 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3951 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
3952 callout_stop(&sc->ti_watchdog);
3956 * Stop all chip I/O so that the kernel's probe routines don't
3957 * get confused by errant DMAs when rebooting.
3960 ti_shutdown(device_t dev)
3962 struct ti_softc *sc;
3964 sc = device_get_softc(dev);
3973 ti_sysctl_node(struct ti_softc *sc)
3975 struct sysctl_ctx_list *ctx;
3976 struct sysctl_oid_list *child;
3979 ctx = device_get_sysctl_ctx(sc->ti_dev);
3980 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ti_dev));
3984 snprintf(tname, sizeof(tname), "dev.ti.%d.dac",
3985 device_get_unit(sc->ti_dev));
3986 TUNABLE_INT_FETCH(tname, &sc->ti_dac);
3988 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_coal_ticks", CTLFLAG_RW,
3989 &sc->ti_rx_coal_ticks, 0, "Receive coalcesced ticks");
3990 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_max_coal_bds", CTLFLAG_RW,
3991 &sc->ti_rx_max_coal_bds, 0, "Receive max coalcesced BDs");
3993 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_coal_ticks", CTLFLAG_RW,
3994 &sc->ti_tx_coal_ticks, 0, "Send coalcesced ticks");
3995 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_max_coal_bds", CTLFLAG_RW,
3996 &sc->ti_tx_max_coal_bds, 0, "Send max coalcesced BDs");
3997 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_buf_ratio", CTLFLAG_RW,
3998 &sc->ti_tx_buf_ratio, 0,
3999 "Ratio of NIC memory devoted to TX buffer");
4001 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stat_ticks", CTLFLAG_RW,
4002 &sc->ti_stat_ticks, 0,
4003 "Number of clock ticks for statistics update interval");
4005 /* Pull in device tunables. */
4006 sc->ti_rx_coal_ticks = 170;
4007 resource_int_value(device_get_name(sc->ti_dev),
4008 device_get_unit(sc->ti_dev), "rx_coal_ticks",
4009 &sc->ti_rx_coal_ticks);
4010 sc->ti_rx_max_coal_bds = 64;
4011 resource_int_value(device_get_name(sc->ti_dev),
4012 device_get_unit(sc->ti_dev), "rx_max_coal_bds",
4013 &sc->ti_rx_max_coal_bds);
4015 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
4016 resource_int_value(device_get_name(sc->ti_dev),
4017 device_get_unit(sc->ti_dev), "tx_coal_ticks",
4018 &sc->ti_tx_coal_ticks);
4019 sc->ti_tx_max_coal_bds = 32;
4020 resource_int_value(device_get_name(sc->ti_dev),
4021 device_get_unit(sc->ti_dev), "tx_max_coal_bds",
4022 &sc->ti_tx_max_coal_bds);
4023 sc->ti_tx_buf_ratio = 21;
4024 resource_int_value(device_get_name(sc->ti_dev),
4025 device_get_unit(sc->ti_dev), "tx_buf_ratio",
4026 &sc->ti_tx_buf_ratio);
4028 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
4029 resource_int_value(device_get_name(sc->ti_dev),
4030 device_get_unit(sc->ti_dev), "stat_ticks",
4031 &sc->ti_stat_ticks);