2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
38 * Tigon register offsets. These are memory mapped registers
39 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
40 * Each register must be accessed using 32 bit operations.
42 * All reegisters are accessed through a 16K shared memory block.
43 * The first group of registers are actually copies of the PCI
44 * configuration space registers.
47 #define TI_PCI_ID 0x000 /* PCI device/vendor ID */
48 #define TI_PCI_CMDSTAT 0x004
49 #define TI_PCI_CLASSCODE 0x008
50 #define TI_PCI_BIST 0x00C
51 #define TI_PCI_LOMEM 0x010 /* Shared memory base address */
52 #define TI_PCI_SUBSYS 0x02C
53 #define TI_PCI_ROMBASE 0x030
54 #define TI_PCI_INT 0x03C
56 #ifndef PCIM_CMD_MWIEN
57 #define PCIM_CMD_MWIEN 0x0010
61 * Alteon AceNIC PCI vendor/device ID.
63 #define ALT_VENDORID 0x12AE
64 #define ALT_DEVICEID_ACENIC 0x0001
65 #define ALT_DEVICEID_ACENIC_COPPER 0x0002
68 * 3Com 3c985 PCI vendor/device ID.
70 #define TC_VENDORID 0x10B7
71 #define TC_DEVICEID_3C985 0x0001
74 * Netgear GA620 PCI vendor/device ID.
76 #define NG_VENDORID 0x1385
77 #define NG_DEVICEID_GA620 0x620A
78 #define NG_DEVICEID_GA620T 0x630A
81 * SGI device/vendor ID.
83 #define SGI_VENDORID 0x10A9
84 #define SGI_DEVICEID_TIGON 0x0009
87 * DEC vendor ID, Farallon device ID. Apparently, Farallon used
88 * the DEC vendor ID in their cards by mistake.
90 #define DEC_VENDORID 0x1011
91 #define DEC_DEVICEID_FARALLON_PN9000SX 0x001a
94 * Tigon configuration and control registers.
96 #define TI_MISC_HOST_CTL 0x040
97 #define TI_MISC_LOCAL_CTL 0x044
98 #define TI_SEM_AB 0x048 /* Tigon 2 only */
99 #define TI_MISC_CONF 0x050 /* Tigon 2 only */
100 #define TI_TIMER_BITS 0x054
101 #define TI_TIMERREF 0x058
102 #define TI_PCI_STATE 0x05C
103 #define TI_MAIN_EVENT_A 0x060
104 #define TI_MAILBOX_EVENT_A 0x064
105 #define TI_WINBASE 0x068
106 #define TI_WINDATA 0x06C
107 #define TI_MAIN_EVENT_B 0x070 /* Tigon 2 only */
108 #define TI_MAILBOX_EVENT_B 0x074 /* Tigon 2 only */
109 #define TI_TIMERREF_B 0x078 /* Tigon 2 only */
110 #define TI_SERIAL 0x07C
113 * Misc host control bits.
115 #define TI_MHC_INTSTATE 0x00000001
116 #define TI_MHC_CLEARINT 0x00000002
117 #define TI_MHC_RESET 0x00000008
118 #define TI_MHC_BYTE_SWAP_ENB 0x00000010
119 #define TI_MHC_WORD_SWAP_ENB 0x00000020
120 #define TI_MHC_MASK_INTS 0x00000040
121 #define TI_MHC_CHIP_REV_MASK 0xF0000000
123 #define TI_MHC_BIGENDIAN_INIT \
124 (TI_MHC_BYTE_SWAP_ENB|TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT)
126 #define TI_MHC_LITTLEENDIAN_INIT \
127 (TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT)
130 * Tigon chip rev values. Rev 4 is the Tigon 1. Rev 6 is the Tigon 2.
131 * Rev 5 is also the Tigon 2, but is a broken version which was never
132 * used in any actual hardware, so we ignore it.
134 #define TI_REV_TIGON_I 0x40000000
135 #define TI_REV_TIGON_II 0x60000000
138 * Firmware revision that we want.
140 #define TI_FIRMWARE_MAJOR 0xc
141 #define TI_FIRMWARE_MINOR 0x4
142 #define TI_FIRMWARE_FIX 0xb
145 * Miscellaneous Local Control register.
147 #define TI_MLC_EE_WRITE_ENB 0x00000010
148 #define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */
149 #define TI_MLC_LOCALADDR_21 0x00004000
150 #define TI_MLC_LOCALADDR_22 0x00008000
151 #define TI_MLC_SBUS_WRITEERR 0x00080000
152 #define TI_MLC_EE_CLK 0x00100000
153 #define TI_MLC_EE_TXEN 0x00200000
154 #define TI_MLC_EE_DOUT 0x00400000
155 #define TI_MLC_EE_DIN 0x00800000
157 /* Possible memory sizes. */
158 #define TI_MLC_SRAM_BANK_DISA 0x00000000
159 #define TI_MLC_SRAM_BANK_1024K 0x00000100
160 #define TI_MLC_SRAM_BANK_512K 0x00000200
161 #define TI_MLC_SRAM_BANK_256K 0x00000300
164 * Offset of MAC address inside EEPROM.
166 #define TI_EE_MAC_OFFSET 0x8c
168 #define TI_DMA_ASSIST 0x11C
169 #define TI_CPU_STATE 0x140
170 #define TI_CPU_PROGRAM_COUNTER 0x144
171 #define TI_SRAM_ADDR 0x154
172 #define TI_SRAM_DATA 0x158
173 #define TI_GEN_0 0x180
174 #define TI_GEN_X 0x1FC
175 #define TI_MAC_TX_STATE 0x200
176 #define TI_MAC_RX_STATE 0x220
177 #define TI_CPU_CTL_B 0x240 /* Tigon 2 only */
178 #define TI_CPU_PROGRAM_COUNTER_B 0x244 /* Tigon 2 only */
179 #define TI_SRAM_ADDR_B 0x254 /* Tigon 2 only */
180 #define TI_SRAM_DATA_B 0x258 /* Tigon 2 only */
181 #define TI_GEN_B_0 0x280 /* Tigon 2 only */
182 #define TI_GEN_B_X 0x2FC /* Tigon 2 only */
185 * Misc config register.
187 #define TI_MCR_SRAM_SYNCHRONOUS 0x00100000 /* Tigon 2 only */
190 * PCI state register.
192 #define TI_PCISTATE_FORCE_RESET 0x00000001
193 #define TI_PCISTATE_PROVIDE_LEN 0x00000002
194 #define TI_PCISTATE_READ_MAXDMA 0x0000001C
195 #define TI_PCISTATE_WRITE_MAXDMA 0x000000E0
196 #define TI_PCISTATE_MINDMA 0x0000FF00
197 #define TI_PCISTATE_FIFO_RETRY_ENB 0x00010000
198 #define TI_PCISTATE_USE_MEM_RD_MULT 0x00020000
199 #define TI_PCISTATE_NO_SWAP_READ_DMA 0x00040000
200 #define TI_PCISTATE_NO_SWAP_WRITE_DMA 0x00080000
201 #define TI_PCISTATE_66MHZ_BUS 0x00080000 /* Tigon 2 only */
202 #define TI_PCISTATE_32BIT_BUS 0x00100000 /* Tigon 2 only */
203 #define TI_PCISTATE_ENB_BYTE_ENABLES 0x00800000 /* Tigon 2 only */
204 #define TI_PCISTATE_READ_CMD 0x0F000000
205 #define TI_PCISTATE_WRITE_CMD 0xF0000000
207 #define TI_PCI_READMAX_4 0x04
208 #define TI_PCI_READMAX_16 0x08
209 #define TI_PCI_READMAX_32 0x0C
210 #define TI_PCI_READMAX_64 0x10
211 #define TI_PCI_READMAX_128 0x14
212 #define TI_PCI_READMAX_256 0x18
213 #define TI_PCI_READMAX_1024 0x1C
215 #define TI_PCI_WRITEMAX_4 0x20
216 #define TI_PCI_WRITEMAX_16 0x40
217 #define TI_PCI_WRITEMAX_32 0x60
218 #define TI_PCI_WRITEMAX_64 0x80
219 #define TI_PCI_WRITEMAX_128 0xA0
220 #define TI_PCI_WRITEMAX_256 0xC0
221 #define TI_PCI_WRITEMAX_1024 0xE0
223 #define TI_PCI_READ_CMD 0x06000000
224 #define TI_PCI_WRITE_CMD 0x70000000
227 * DMA state register.
229 #define TI_DMASTATE_ENABLE 0x00000001
230 #define TI_DMASTATE_PAUSE 0x00000002
233 * CPU state register.
235 #define TI_CPUSTATE_RESET 0x00000001
236 #define TI_CPUSTATE_STEP 0x00000002
237 #define TI_CPUSTATE_ROMFAIL 0x00000010
238 #define TI_CPUSTATE_HALT 0x00010000
240 * MAC TX state register
242 #define TI_TXSTATE_RESET 0x00000001
243 #define TI_TXSTATE_ENB 0x00000002
244 #define TI_TXSTATE_STOP 0x00000004
247 * MAC RX state register
249 #define TI_RXSTATE_RESET 0x00000001
250 #define TI_RXSTATE_ENB 0x00000002
251 #define TI_RXSTATE_STOP 0x00000004
254 * Tigon 2 mailbox registers. The mailbox area consists of 256 bytes
255 * split into 64 bit registers. Only the lower 32 bits of each mailbox
258 #define TI_MB_HOSTINTR_HI 0x500
259 #define TI_MB_HOSTINTR_LO 0x504
260 #define TI_MB_HOSTINTR TI_MB_HOSTINTR_LO
261 #define TI_MB_CMDPROD_IDX_HI 0x508
262 #define TI_MB_CMDPROD_IDX_LO 0x50C
263 #define TI_MB_CMDPROD_IDX TI_MB_CMDPROD_IDX_LO
264 #define TI_MB_SENDPROD_IDX_HI 0x510
265 #define TI_MB_SENDPROD_IDX_LO 0x514
266 #define TI_MB_SENDPROD_IDX TI_MB_SENDPROD_IDX_LO
267 #define TI_MB_STDRXPROD_IDX_HI 0x518 /* Tigon 2 only */
268 #define TI_MB_STDRXPROD_IDX_LO 0x51C /* Tigon 2 only */
269 #define TI_MB_STDRXPROD_IDX TI_MB_STDRXPROD_IDX_LO
270 #define TI_MB_JUMBORXPROD_IDX_HI 0x520 /* Tigon 2 only */
271 #define TI_MB_JUMBORXPROD_IDX_LO 0x524 /* Tigon 2 only */
272 #define TI_MB_JUMBORXPROD_IDX TI_MB_JUMBORXPROD_IDX_LO
273 #define TI_MB_MINIRXPROD_IDX_HI 0x528 /* Tigon 2 only */
274 #define TI_MB_MINIRXPROD_IDX_LO 0x52C /* Tigon 2 only */
275 #define TI_MB_MINIRXPROD_IDX TI_MB_MINIRXPROD_IDX_LO
276 #define TI_MB_RSVD 0x530
279 * Tigon 2 general communication registers. These are 64 and 32 bit
280 * registers which are only valid after the firmware has been
281 * loaded and started. They actually exist in NIC memory but are
282 * mapped into the host memory via the shared memory region.
284 * The NIC internally maps these registers starting at address 0,
285 * so to determine the NIC address of any of these registers, we
286 * subtract 0x600 (the address of the first register).
289 #define TI_GCR_BASE 0x600
290 #define TI_GCR_MACADDR 0x600
291 #define TI_GCR_PAR0 0x600
292 #define TI_GCR_PAR1 0x604
293 #define TI_GCR_GENINFO_HI 0x608
294 #define TI_GCR_GENINFO_LO 0x60C
295 #define TI_GCR_MCASTADDR 0x610 /* obsolete */
296 #define TI_GCR_MAR0 0x610 /* obsolete */
297 #define TI_GCR_MAR1 0x614 /* obsolete */
298 #define TI_GCR_OPMODE 0x618
299 #define TI_GCR_DMA_READCFG 0x61C
300 #define TI_GCR_DMA_WRITECFG 0x620
301 #define TI_GCR_TX_BUFFER_RATIO 0x624
302 #define TI_GCR_EVENTCONS_IDX 0x628
303 #define TI_GCR_CMDCONS_IDX 0x62C
304 #define TI_GCR_TUNEPARMS 0x630
305 #define TI_GCR_RX_COAL_TICKS 0x630
306 #define TI_GCR_TX_COAL_TICKS 0x634
307 #define TI_GCR_STAT_TICKS 0x638
308 #define TI_GCR_TX_MAX_COAL_BD 0x63C
309 #define TI_GCR_RX_MAX_COAL_BD 0x640
310 #define TI_GCR_NIC_TRACING 0x644
311 #define TI_GCR_GLINK 0x648
312 #define TI_GCR_LINK 0x64C
313 #define TI_GCR_NICTRACE_PTR 0x650
314 #define TI_GCR_NICTRACE_START 0x654
315 #define TI_GCR_NICTRACE_LEN 0x658
316 #define TI_GCR_IFINDEX 0x65C
317 #define TI_GCR_IFMTU 0x660
318 #define TI_GCR_MASK_INTRS 0x664
319 #define TI_GCR_GLINK_STAT 0x668
320 #define TI_GCR_LINK_STAT 0x66C
321 #define TI_GCR_RXRETURNCONS_IDX 0x680
322 #define TI_GCR_CMDRING 0x700
324 #define TI_GCR_NIC_ADDR(x) (x - TI_GCR_BASE)
327 * Local memory window. The local memory window is a 2K shared
328 * memory region which can be used to access the NIC's internal
329 * SRAM. The window can be mapped to a given 2K region using
330 * the TI_WINDOW_BASE register.
332 #define TI_WINDOW 0x800
333 #define TI_WINLEN 0x800
335 #define TI_TICKS_PER_SEC 1000000
338 * Operation mode register.
340 #define TI_OPMODE_BYTESWAP_BD 0x00000002
341 #define TI_OPMODE_WORDSWAP_BD 0x00000004
342 #define TI_OPMODE_WARN_ENB 0x00000008 /* not yet implemented */
343 #define TI_OPMODE_BYTESWAP_DATA 0x00000010
344 #define TI_OPMODE_1_DMA_ACTIVE 0x00000040
345 #define TI_OPMODE_SBUS 0x00000100
346 #define TI_OPMODE_DONT_FRAG_JUMBO 0x00000200
347 #define TI_OPMODE_INCLUDE_CRC 0x00000400
348 #define TI_OPMODE_RX_BADFRAMES 0x00000800
349 #define TI_OPMODE_NO_EVENT_INTRS 0x00001000
350 #define TI_OPMODE_NO_TX_INTRS 0x00002000
351 #define TI_OPMODE_NO_RX_INTRS 0x00004000
352 #define TI_OPMODE_FATAL_ENB 0x40000000 /* not yet implemented */
353 #define TI_OPMODE_JUMBO_HDRSPLIT 0x00008000
356 * DMA configuration thresholds.
358 #define TI_DMA_STATE_THRESH_16W 0x00000100
359 #define TI_DMA_STATE_THRESH_8W 0x00000080
360 #define TI_DMA_STATE_THRESH_4W 0x00000040
361 #define TI_DMA_STATE_THRESH_2W 0x00000020
362 #define TI_DMA_STATE_THRESH_1W 0x00000010
364 #define TI_DMA_STATE_FORCE_32_BIT 0x00000008
367 * Gigabit link status bits.
369 #define TI_GLNK_SENSE_NO_BEG 0x00002000
370 #define TI_GLNK_LOOPBACK 0x00004000
371 #define TI_GLNK_PREF 0x00008000
372 #define TI_GLNK_1000MB 0x00040000
373 #define TI_GLNK_FULL_DUPLEX 0x00080000
374 #define TI_GLNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */
375 #define TI_GLNK_RX_FLOWCTL_Y 0x00800000
376 #define TI_GLNK_AUTONEGENB 0x20000000
377 #define TI_GLNK_ENB 0x40000000
382 #define TI_LNK_LOOPBACK 0x00004000
383 #define TI_LNK_PREF 0x00008000
384 #define TI_LNK_10MB 0x00010000
385 #define TI_LNK_100MB 0x00020000
386 #define TI_LNK_1000MB 0x00040000
387 #define TI_LNK_FULL_DUPLEX 0x00080000
388 #define TI_LNK_HALF_DUPLEX 0x00100000
389 #define TI_LNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */
390 #define TI_LNK_RX_FLOWCTL_Y 0x00800000
391 #define TI_LNK_AUTONEGENB 0x20000000
392 #define TI_LNK_ENB 0x40000000
395 * Ring size constants.
397 #define TI_EVENT_RING_CNT 256
398 #define TI_CMD_RING_CNT 64
399 #define TI_STD_RX_RING_CNT 512
400 #define TI_JUMBO_RX_RING_CNT 256
401 #define TI_MINI_RX_RING_CNT 1024
402 #define TI_RETURN_RING_CNT 2048
404 #define TI_MAXTXSEGS 32
405 #define TI_RING_ALIGN 32
406 #define TI_JUMBO_RING_ALIGN 64
409 * Possible TX ring sizes.
411 #define TI_TX_RING_CNT_128 128
412 #define TI_TX_RING_BASE_128 0x3800
414 #define TI_TX_RING_CNT_256 256
415 #define TI_TX_RING_BASE_256 0x3000
417 #define TI_TX_RING_CNT_512 512
418 #define TI_TX_RING_BASE_512 0x2000
420 #define TI_TX_RING_CNT TI_TX_RING_CNT_512
421 #define TI_TX_RING_BASE TI_TX_RING_BASE_512
424 * The Tigon can have up to 8MB of external SRAM, however the Tigon 1
425 * is limited to 2MB total, and in general I think most adapters have
426 * around 1MB. We use this value for zeroing the NIC's SRAM, so to
427 * be safe we use the largest possible value (zeroing memory that
428 * isn't there doesn't hurt anything).
430 #define TI_MEM_MAX 0x7FFFFF
433 * Maximum register address on the Tigon.
435 #define TI_REG_MAX 0x3fff
438 * These values were taken from Alteon's tg.h.
440 #define TI_BEG_SRAM 0x0 /* host thinks it's here */
441 #define TI_BEG_SCRATCH 0xc00000 /* beg of scratch pad area */
442 #define TI_END_SRAM_II 0x800000 /* end of SRAM, for 2 MB stuffed */
443 #define TI_END_SCRATCH_II 0xc04000 /* end of scratch pad CPU A (16KB) */
444 #define TI_END_SCRATCH_B 0xc02000 /* end of scratch pad CPU B (8KB) */
445 #define TI_BEG_SCRATCH_B_DEBUG 0xd00000 /* beg of scratch pad for ioctl */
446 #define TI_END_SCRATCH_B_DEBUG 0xd02000 /* end of scratch pad for ioctl */
447 #define TI_SCRATCH_DEBUG_OFF 0x100000 /* offset for ioctl usage */
448 #define TI_END_SRAM_I 0x200000 /* end of SRAM, for 2 MB stuffed */
449 #define TI_END_SCRATCH_I 0xc00800 /* end of scratch pad area (2KB) */
450 #define TI_BEG_PROM 0x40000000 /* beg of PROM, special access */
451 #define TI_BEG_FLASH 0x80000000 /* beg of EEPROM, special access */
452 #define TI_END_FLASH 0x80100000 /* end of EEPROM for 1 MB stuff */
453 #define TI_BEG_SER_EEPROM 0xa0000000 /* beg of Serial EEPROM (fake out) */
454 #define TI_END_SER_EEPROM 0xa0002000 /* end of Serial EEPROM (fake out) */
455 #define TI_BEG_REGS 0xc0000000 /* beg of register area */
456 #define TI_END_REGS 0xc0000400 /* end of register area */
457 #define TI_END_WRITE_REGS 0xc0000180 /* can't write GPRs currently */
458 #define TI_BEG_REGS2 0xc0000200 /* beg of second writeable reg area */
459 /* the EEPROM is byte addressable in a pretty odd way */
460 #define EEPROM_BYTE_LOC 0xff000000
463 * From Alteon's tg.h.
465 #define TI_PROCESSOR_A 0
466 #define TI_PROCESSOR_B 1
467 #define TI_CPU_A TG_PROCESSOR_A
468 #define TI_CPU_B TG_PROCESSOR_B
471 * Following macro can be used to access to any of the CPU registers
472 * It will adjust the address appropriately.
474 * reg - The register to access, e.g TI_CPU_CONTROL
475 * cpu - cpu, i.e PROCESSOR_A or PROCESSOR_B (or TI_CPU_A or TI_CPU_B)
477 #define CPU_REG(reg, cpu) ((reg) + (cpu) * 0x100)
480 * Even on the alpha, pci addresses are 32-bit quantities
488 #define TI_HOSTADDR(x) x.ti_addr_lo
491 ti_hostaddr64(ti_hostaddr *x, bus_addr_t addr)
495 baddr = (uint64_t)addr;
496 x->ti_addr_lo = baddr & 0xffffffff;
497 x->ti_addr_hi = baddr >> 32;
501 * Ring control block structure. The rules for the max_len field
504 * For the send ring, max_len indicates the number of entries in the
505 * ring (128, 256 or 512).
507 * For the standard receive ring, max_len indicates the threshold
508 * used to decide when a frame should be put in the jumbo receive ring
509 * instead of the standard one.
511 * For the mini ring, max_len indicates the size of the buffers in the
512 * ring. This is the value used to decide when a frame is small enough
513 * to be placed in the mini ring.
515 * For the return receive ring, max_len indicates the number of entries
516 * in the ring. It can be one of 2048, 1024 or 0 (which is the same as
517 * 2048 for backwards compatibility). The value 1024 can only be used
518 * if the mini ring is disabled.
521 ti_hostaddr ti_hostaddr;
522 #if BYTE_ORDER == BIG_ENDIAN
532 #define TI_RCB_FLAG_TCP_UDP_CKSUM 0x00000001
533 #define TI_RCB_FLAG_IP_CKSUM 0x00000002
534 #define TI_RCB_FLAG_NO_PHDR_CKSUM 0x00000008
535 #define TI_RCB_FLAG_VLAN_ASSIST 0x00000010
536 #define TI_RCB_FLAG_COAL_UPD_ONLY 0x00000020
537 #define TI_RCB_FLAG_HOST_RING 0x00000040
538 #define TI_RCB_FLAG_IEEE_SNAP_CKSUM 0x00000080
539 #define TI_RCB_FLAG_USE_EXT_RX_BD 0x00000100
540 #define TI_RCB_FLAG_RING_DISABLED 0x00000200
548 * Tigon general information block. This resides in host memory
549 * and contains the status counters, ring control blocks and
554 struct ti_stats ti_stats;
555 struct ti_rcb ti_ev_rcb;
556 struct ti_rcb ti_cmd_rcb;
557 struct ti_rcb ti_tx_rcb;
558 struct ti_rcb ti_std_rx_rcb;
559 struct ti_rcb ti_jumbo_rx_rcb;
560 struct ti_rcb ti_mini_rx_rcb;
561 struct ti_rcb ti_return_rcb;
562 ti_hostaddr ti_ev_prodidx_ptr;
563 ti_hostaddr ti_return_prodidx_ptr;
564 ti_hostaddr ti_tx_considx_ptr;
565 ti_hostaddr ti_refresh_stats_ptr;
569 * Buffer descriptor structures. There are basically three types
570 * of structures: normal receive descriptors, extended receive
571 * descriptors and transmit descriptors. The extended receive
572 * descriptors are optionally used only for the jumbo receive ring.
577 #if BYTE_ORDER == BIG_ENDIAN
584 #if BYTE_ORDER == BIG_ENDIAN
591 #if BYTE_ORDER == BIG_ENDIAN
592 uint16_t ti_ip_cksum;
593 uint16_t ti_tcp_udp_cksum;
595 uint16_t ti_tcp_udp_cksum;
596 uint16_t ti_ip_cksum;
598 #if BYTE_ORDER == BIG_ENDIAN
599 uint16_t ti_error_flags;
600 uint16_t ti_vlan_tag;
602 uint16_t ti_vlan_tag;
603 uint16_t ti_error_flags;
609 #define TI_STD_RX_RING_SZ (sizeof(struct ti_rx_desc) * TI_STD_RX_RING_CNT)
610 #define TI_MINI_RX_RING_SZ (sizeof(struct ti_rx_desc) * TI_MINI_RX_RING_CNT)
611 #define TI_RX_RETURN_RING_SZ (sizeof(struct ti_rx_desc) * TI_RETURN_RING_CNT)
613 struct ti_rx_desc_ext {
614 ti_hostaddr ti_addr1;
615 ti_hostaddr ti_addr2;
616 ti_hostaddr ti_addr3;
617 #if BYTE_ORDER == BIG_ENDIAN
624 #if BYTE_ORDER == BIG_ENDIAN
631 ti_hostaddr ti_addr0;
632 #if BYTE_ORDER == BIG_ENDIAN
639 #if BYTE_ORDER == BIG_ENDIAN
646 #if BYTE_ORDER == BIG_ENDIAN
647 uint16_t ti_ip_cksum;
648 uint16_t ti_tcp_udp_cksum;
650 uint16_t ti_tcp_udp_cksum;
651 uint16_t ti_ip_cksum;
653 #if BYTE_ORDER == BIG_ENDIAN
654 uint16_t ti_error_flags;
655 uint16_t ti_vlan_tag;
657 uint16_t ti_vlan_tag;
658 uint16_t ti_error_flags;
664 #ifdef TI_SF_BUF_JUMBO
665 #define TI_JUMBO_RX_RING_SZ \
666 (sizeof(struct ti_rx_desc_ext) * TI_JUMBO_RX_RING_CNT)
668 #define TI_JUMBO_RX_RING_SZ \
669 (sizeof(struct ti_rx_desc) * TI_JUMBO_RX_RING_CNT)
673 * Transmit descriptors are, mercifully, very small.
677 #if BYTE_ORDER == BIG_ENDIAN
684 #if BYTE_ORDER == BIG_ENDIAN
686 uint16_t ti_vlan_tag;
688 uint16_t ti_vlan_tag;
693 #define TI_TX_RING_SZ (sizeof(struct ti_tx_desc) * TI_TX_RING_CNT)
696 * NOTE! On the Alpha, we have an alignment constraint.
697 * The first thing in the packet is a 14-byte Ethernet header.
698 * This means that the packet is misaligned. To compensate,
699 * we actually offset the data 2 bytes into the cluster. This
700 * aligns the packet after the Ethernet header at a 32-bit
704 #define TI_FRAMELEN 1518
705 #define TI_JUMBO_FRAMELEN 9018
706 #define TI_JUMBO_MTU (TI_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
707 #define TI_PAGE_SIZE PAGE_SIZE
708 #define TI_MIN_FRAMELEN 60
711 * Buffer descriptor error flags.
713 #define TI_BDERR_CRC 0x0001
714 #define TI_BDERR_COLLDETECT 0x0002
715 #define TI_BDERR_LINKLOST 0x0004
716 #define TI_BDERR_DECODE 0x0008
717 #define TI_BDERR_ODD_NIBBLES 0x0010
718 #define TI_BDERR_MAC_ABRT 0x0020
719 #define TI_BDERR_RUNT 0x0040
720 #define TI_BDERR_TRUNC 0x0080
721 #define TI_BDERR_GIANT 0x0100
724 * Buffer descriptor flags.
726 #define TI_BDFLAG_TCP_UDP_CKSUM 0x0001
727 #define TI_BDFLAG_IP_CKSUM 0x0002
728 #define TI_BDFLAG_END 0x0004
729 #define TI_BDFLAG_MORE 0x0008
730 #define TI_BDFLAG_JUMBO_RING 0x0010
731 #define TI_BDFLAG_UCAST_PKT 0x0020
732 #define TI_BDFLAG_MCAST_PKT 0x0040
733 #define TI_BDFLAG_BCAST_PKT 0x0060
734 #define TI_BDFLAG_IP_FRAG 0x0080
735 #define TI_BDFLAG_IP_FRAG_END 0x0100
736 #define TI_BDFLAG_VLAN_TAG 0x0200
737 #define TI_BDFLAG_ERROR 0x0400
738 #define TI_BDFLAG_COAL_NOW 0x0800
739 #define TI_BDFLAG_MINI_RING 0x1000
742 * Descriptor type flags. I think these only have meaning for
743 * the Tigon 1. I had to extract them from the sample driver source
744 * since they aren't in the manual.
746 #define TI_BDTYPE_TYPE_NULL 0x0000
747 #define TI_BDTYPE_SEND_BD 0x0001
748 #define TI_BDTYPE_RECV_BD 0x0002
749 #define TI_BDTYPE_RECV_JUMBO_BD 0x0003
750 #define TI_BDTYPE_RECV_BD_LAST 0x0004
751 #define TI_BDTYPE_SEND_DATA 0x0005
752 #define TI_BDTYPE_SEND_DATA_LAST 0x0006
753 #define TI_BDTYPE_RECV_DATA 0x0007
754 #define TI_BDTYPE_RECV_DATA_LAST 0x000b
755 #define TI_BDTYPE_EVENT_RUPT 0x000c
756 #define TI_BDTYPE_EVENT_NO_RUPT 0x000d
757 #define TI_BDTYPE_ODD_START 0x000e
758 #define TI_BDTYPE_UPDATE_STATS 0x000f
759 #define TI_BDTYPE_SEND_DUMMY_DMA 0x0010
760 #define TI_BDTYPE_EVENT_PROD 0x0011
761 #define TI_BDTYPE_TX_CONS 0x0012
762 #define TI_BDTYPE_RX_PROD 0x0013
763 #define TI_BDTYPE_REFRESH_STATS 0x0014
764 #define TI_BDTYPE_SEND_DATA_LAST_VLAN 0x0015
765 #define TI_BDTYPE_SEND_DATA_COAL 0x0016
766 #define TI_BDTYPE_SEND_DATA_LAST_COAL 0x0017
767 #define TI_BDTYPE_SEND_DATA_LAST_VLAN_COAL 0x0018
768 #define TI_BDTYPE_TX_CONS_NO_INTR 0x0019
771 * Tigon command structure.
777 #define TI_CMD_CMD(cmd) (((((cmd)->ti_cmdx)) >> 24) & 0xff)
778 #define TI_CMD_CODE(cmd) (((((cmd)->ti_cmdx)) >> 12) & 0xfff)
779 #define TI_CMD_IDX(cmd) ((((cmd)->ti_cmdx)) & 0xfff)
781 #define TI_CMD_HOST_STATE 0x01
782 #define TI_CMD_CODE_STACK_UP 0x01
783 #define TI_CMD_CODE_STACK_DOWN 0x02
786 * This command enables software address filtering. It's a workaround
787 * for a bug in the Tigon 1 and not implemented for the Tigon 2.
789 #define TI_CMD_FDR_FILTERING 0x02
790 #define TI_CMD_CODE_FILT_ENB 0x01
791 #define TI_CMD_CODE_FILT_DIS 0x02
793 #define TI_CMD_SET_RX_PROD_IDX 0x03 /* obsolete */
794 #define TI_CMD_UPDATE_GENCOM 0x04
795 #define TI_CMD_RESET_JUMBO_RING 0x05
796 #define TI_CMD_SET_PARTIAL_RX_CNT 0x06
797 #define TI_CMD_ADD_MCAST_ADDR 0x08 /* obsolete */
798 #define TI_CMD_DEL_MCAST_ADDR 0x09 /* obsolete */
800 #define TI_CMD_SET_PROMISC_MODE 0x0A
801 #define TI_CMD_CODE_PROMISC_ENB 0x01
802 #define TI_CMD_CODE_PROMISC_DIS 0x02
804 #define TI_CMD_LINK_NEGOTIATION 0x0B
805 #define TI_CMD_CODE_NEGOTIATE_BOTH 0x00
806 #define TI_CMD_CODE_NEGOTIATE_GIGABIT 0x01
807 #define TI_CMD_CODE_NEGOTIATE_10_100 0x02
809 #define TI_CMD_SET_MAC_ADDR 0x0C
810 #define TI_CMD_CLR_PROFILE 0x0D
812 #define TI_CMD_SET_ALLMULTI 0x0E
813 #define TI_CMD_CODE_ALLMULTI_ENB 0x01
814 #define TI_CMD_CODE_ALLMULTI_DIS 0x02
816 #define TI_CMD_CLR_STATS 0x0F
817 #define TI_CMD_SET_RX_JUMBO_PROD_IDX 0x10 /* obsolete */
818 #define TI_CMD_RFRSH_STATS 0x11
820 #define TI_CMD_EXT_ADD_MCAST 0x12
821 #define TI_CMD_EXT_DEL_MCAST 0x13
824 * Utility macros to make issuing commands a little simpler. Assumes
825 * that 'sc' and 'cmd' are in local scope.
827 #define TI_DO_CMD(x, y, z) do { \
828 cmd.ti_cmdx = (((x) << 24) | ((y) << 12) | ((z))); \
832 #define TI_DO_CMD_EXT(x, y, z, v, w) do { \
833 cmd.ti_cmdx = (((x) << 24) | ((y) << 12) | ((z))); \
834 ti_cmd_ext(sc, &cmd, (v), (w)); \
838 * Other utility macros.
840 #define TI_INC(x, y) (x) = ((x) + 1) % y
842 #define TI_UPDATE_JUMBOPROD(x, y) do { \
843 if ((x)->ti_hwrev == TI_HWREV_TIGON) \
844 TI_DO_CMD(TI_CMD_SET_RX_JUMBO_PROD_IDX, 0, (y)); \
846 CSR_WRITE_4((x), TI_MB_JUMBORXPROD_IDX, (y)); \
849 #define TI_UPDATE_MINIPROD(x, y) \
850 CSR_WRITE_4((x), TI_MB_MINIRXPROD_IDX, (y))
852 #define TI_UPDATE_STDPROD(x, y) do { \
853 if ((x)->ti_hwrev == TI_HWREV_TIGON) \
854 TI_DO_CMD(TI_CMD_SET_RX_PROD_IDX, 0, (y)); \
856 CSR_WRITE_4((x), TI_MB_STDRXPROD_IDX, (y)); \
860 * Tigon event structure.
862 struct ti_event_desc {
866 #define TI_EVENT_RING_SZ (sizeof(struct ti_event_desc) * TI_EVENT_RING_CNT)
868 #define TI_EVENT_EVENT(e) (((((e)->ti_eventx)) >> 24) & 0xff)
869 #define TI_EVENT_CODE(e) (((((e)->ti_eventx)) >> 12) & 0xfff)
870 #define TI_EVENT_IDX(e) (((((e)->ti_eventx))) & 0xfff)
875 #define TI_EV_FIRMWARE_UP 0x01
876 #define TI_EV_STATS_UPDATED 0x04
878 #define TI_EV_LINKSTAT_CHANGED 0x06
879 #define TI_EV_CODE_GIG_LINK_UP 0x01
880 #define TI_EV_CODE_LINK_DOWN 0x02
881 #define TI_EV_CODE_LINK_UP 0x03
883 #define TI_EV_ERROR 0x07
884 #define TI_EV_CODE_ERR_INVAL_CMD 0x01
885 #define TI_EV_CODE_ERR_UNIMP_CMD 0x02
886 #define TI_EV_CODE_ERR_BADCFG 0x03
888 #define TI_EV_MCAST_UPDATED 0x08
889 #define TI_EV_CODE_MCAST_ADD 0x01
890 #define TI_EV_CODE_MCAST_DEL 0x02
892 #define TI_EV_RESET_JUMBO_RING 0x09
894 * Register access macros. The Tigon always uses memory mapped register
895 * accesses and all registers must be accessed with 32 bit operations.
898 #define CSR_WRITE_4(sc, reg, val) \
899 bus_space_write_4((sc)->ti_btag, (sc)->ti_bhandle, (reg), (val))
901 #define CSR_READ_4(sc, reg) \
902 bus_space_read_4((sc)->ti_btag, (sc)->ti_bhandle, (reg))
904 #define TI_SETBIT(sc, reg, x) \
905 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) | (x)))
906 #define TI_CLRBIT(sc, reg, x) \
907 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & ~(x)))
911 bus_dmamap_t tx_dmamap;
912 STAILQ_ENTRY(ti_txdesc) tx_q;
915 STAILQ_HEAD(ti_txdq, ti_txdesc);
919 * Make sure producer structures are aligned on 32-byte cache
920 * line boundaries. We can create separate DMA area for each
921 * producer/consumer area but it wouldn't get much benefit
922 * since driver use a global driver lock.
924 struct ti_producer ti_ev_prodidx_r;
926 struct ti_producer ti_return_prodidx_r;
928 struct ti_producer ti_tx_considx_r;
933 * Ring structures. Most of these reside in host memory and we tell
934 * the NIC where they are via the ring control blocks. The exceptions
935 * are the tx and command rings, which live in NIC memory and which
936 * we access via the shared memory window.
938 struct ti_ring_data {
939 struct ti_gib *ti_info;
940 bus_addr_t ti_info_paddr;
941 struct ti_status *ti_status;
942 bus_addr_t ti_status_paddr;
943 struct ti_rx_desc *ti_rx_std_ring;
944 bus_addr_t ti_rx_std_ring_paddr;
945 #ifdef TI_SF_BUF_JUMBO
946 struct ti_rx_desc_ext *ti_rx_jumbo_ring;
948 struct ti_rx_desc *ti_rx_jumbo_ring;
950 bus_addr_t ti_rx_jumbo_ring_paddr;
951 struct ti_rx_desc *ti_rx_mini_ring;
952 bus_addr_t ti_rx_mini_ring_paddr;
953 struct ti_rx_desc *ti_rx_return_ring;
954 bus_addr_t ti_rx_return_ring_paddr;
955 struct ti_event_desc *ti_event_ring;
956 bus_addr_t ti_event_ring_paddr;
957 struct ti_tx_desc *ti_tx_ring;
958 bus_addr_t ti_tx_ring_paddr;
962 * Mbuf pointers. We need these to keep track of the virtual addresses
963 * of our mbuf chains since we can only convert from physical to virtual,
964 * not the other way around.
966 struct ti_chain_data {
967 bus_dma_tag_t ti_parent_tag;
968 bus_dma_tag_t ti_gib_tag;
969 bus_dmamap_t ti_gib_map;
970 bus_dma_tag_t ti_event_ring_tag;
971 bus_dmamap_t ti_event_ring_map;
972 bus_dma_tag_t ti_status_tag;
973 bus_dmamap_t ti_status_map;
974 bus_dma_tag_t ti_tx_ring_tag;
975 bus_dmamap_t ti_tx_ring_map;
976 bus_dma_tag_t ti_tx_tag;
977 struct ti_txdesc ti_txdesc[TI_TX_RING_CNT];
978 struct ti_txdq ti_txfreeq;
979 struct ti_txdq ti_txbusyq;
980 bus_dma_tag_t ti_rx_return_ring_tag;
981 bus_dmamap_t ti_rx_return_ring_map;
982 bus_dma_tag_t ti_rx_std_ring_tag;
983 bus_dmamap_t ti_rx_std_ring_map;
984 bus_dma_tag_t ti_rx_std_tag;
985 struct mbuf *ti_rx_std_chain[TI_STD_RX_RING_CNT];
986 bus_dmamap_t ti_rx_std_maps[TI_STD_RX_RING_CNT];
987 bus_dmamap_t ti_rx_std_sparemap;
988 bus_dma_tag_t ti_rx_jumbo_ring_tag;
989 bus_dmamap_t ti_rx_jumbo_ring_map;
990 bus_dma_tag_t ti_rx_jumbo_tag;
991 struct mbuf *ti_rx_jumbo_chain[TI_JUMBO_RX_RING_CNT];
992 bus_dmamap_t ti_rx_jumbo_maps[TI_JUMBO_RX_RING_CNT];
993 bus_dmamap_t ti_rx_jumbo_sparemap;
994 bus_dma_tag_t ti_rx_mini_ring_tag;
995 bus_dmamap_t ti_rx_mini_ring_map;
996 bus_dma_tag_t ti_rx_mini_tag;
997 struct mbuf *ti_rx_mini_chain[TI_MINI_RX_RING_CNT];
998 bus_dmamap_t ti_rx_mini_maps[TI_MINI_RX_RING_CNT];
999 bus_dmamap_t ti_rx_mini_sparemap;
1005 const char *ti_name;
1008 #define TI_HWREV_TIGON 0x01
1009 #define TI_HWREV_TIGON_II 0x02
1010 #define TI_TIMEOUT 1000
1011 #define TI_TXCONS_UNSET 0xFFFF /* impossible value */
1013 struct ti_mc_entry {
1014 struct ether_addr mc_addr;
1015 SLIST_ENTRY(ti_mc_entry) mc_entries;
1019 TI_FLAG_NONE = 0x00,
1020 TI_FLAG_DEBUGING = 0x01,
1021 TI_FLAG_WAIT_FOR_LINK = 0x02
1026 struct ifnet *ti_ifp;
1027 bus_space_handle_t ti_bhandle;
1028 bus_space_tag_t ti_btag;
1030 struct resource *ti_irq;
1031 struct resource *ti_res;
1032 struct ifmedia ifmedia; /* media info */
1033 uint8_t ti_hwrev; /* Tigon rev (1 or 2) */
1034 uint8_t ti_copper; /* 1000baseTX card */
1035 uint8_t ti_linkstat; /* Link state */
1036 int ti_hdrsplit; /* enable header splitting */
1038 struct ti_ring_data ti_rdata; /* rings */
1039 struct ti_chain_data ti_cdata; /* mbufs */
1040 #define ti_ev_prodidx ti_rdata.ti_status->ti_ev_prodidx_r
1041 #define ti_return_prodidx ti_rdata.ti_status->ti_return_prodidx_r
1042 #define ti_tx_considx ti_rdata.ti_status->ti_tx_considx_r
1043 int ti_tx_saved_prodidx;
1044 int ti_tx_saved_considx;
1045 int ti_rx_saved_considx;
1046 int ti_ev_saved_considx;
1047 int ti_cmd_saved_prodidx;
1048 int ti_std; /* current std ring head */
1049 int ti_mini; /* current mini ring head */
1050 int ti_jumbo; /* current jumo ring head */
1051 SLIST_HEAD(__ti_mchead, ti_mc_entry) ti_mc_listhead;
1052 uint32_t ti_stat_ticks;
1053 uint32_t ti_rx_coal_ticks;
1054 uint32_t ti_tx_coal_ticks;
1055 uint32_t ti_rx_max_coal_bds;
1056 uint32_t ti_tx_max_coal_bds;
1057 uint32_t ti_tx_buf_ratio;
1061 struct callout ti_watchdog;
1063 ti_flag_vals ti_flags;
1065 uint8_t *ti_membuf2;
1069 #define TI_LOCK(_sc) mtx_lock(&(_sc)->ti_mtx)
1070 #define TI_UNLOCK(_sc) mtx_unlock(&(_sc)->ti_mtx)
1071 #define TI_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ti_mtx, MA_OWNED)
1074 * Microchip Technology 24Cxx EEPROM control bytes
1076 #define EEPROM_CTL_READ 0xA1 /* 0101 0001 */
1077 #define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */
1080 * Note that EEPROM_START leaves transmission enabled.
1082 #define EEPROM_START do { \
1083 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock pin high */\
1084 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Set DATA bit to 1 */ \
1085 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit to write bit */\
1086 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA bit to 0 again */\
1087 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ \
1091 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so
1092 * that no further data can be written to the EEPROM I/O pin.
1094 #define EEPROM_STOP do { \
1095 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit */ \
1096 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA to 0 */ \
1097 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock high */ \
1098 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit */ \
1099 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Toggle DATA to 1 */ \
1100 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit. */ \
1101 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ \