2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
39 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
40 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
41 * the National Semiconductor DP83840A physical interface and the
42 * Microchip Technology 24Cxx series serial EEPROM.
44 * Written using the following four documents:
46 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
47 * National Semiconductor DP83840A data sheet (www.national.com)
48 * Microchip Technology 24C02C data sheet (www.microchip.com)
49 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
51 * Written by Bill Paul <wpaul@ctr.columbia.edu>
52 * Electrical Engineering Department
53 * Columbia University, New York City
56 * Some notes about the ThunderLAN:
58 * The ThunderLAN controller is a single chip containing PCI controller
59 * logic, approximately 3K of on-board SRAM, a LAN controller, and media
60 * independent interface (MII) bus. The MII allows the ThunderLAN chip to
61 * control up to 32 different physical interfaces (PHYs). The ThunderLAN
62 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
63 * to act as a complete ethernet interface.
65 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
66 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
67 * in full or half duplex. Some of the Compaq Deskpro machines use a
68 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
69 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
70 * concert with the ThunderLAN's internal PHY to provide full 10/100
71 * support. This is cheaper than using a standalone external PHY for both
72 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
73 * A serial EEPROM is also attached to the ThunderLAN chip to provide
74 * power-up default register settings and for storing the adapter's
75 * station address. Although not supported by this driver, the ThunderLAN
76 * chip can also be connected to token ring PHYs.
78 * The ThunderLAN has a set of registers which can be used to issue
79 * commands, acknowledge interrupts, and to manipulate other internal
80 * registers on its DIO bus. The primary registers can be accessed
81 * using either programmed I/O (inb/outb) or via PCI memory mapping,
82 * depending on how the card is configured during the PCI probing
83 * phase. It is even possible to have both PIO and memory mapped
84 * access turned on at the same time.
86 * Frame reception and transmission with the ThunderLAN chip is done
87 * using frame 'lists.' A list structure looks more or less like this:
90 * u_int32_t fragment_address;
91 * u_int32_t fragment_size;
94 * u_int32_t forward_pointer;
96 * u_int16_t frame_size;
97 * struct tl_frag fragments[10];
100 * The forward pointer in the list header can be either a 0 or the address
101 * of another list, which allows several lists to be linked together. Each
102 * list contains up to 10 fragment descriptors. This means the chip allows
103 * ethernet frames to be broken up into up to 10 chunks for transfer to
104 * and from the SRAM. Note that the forward pointer and fragment buffer
105 * addresses are physical memory addresses, not virtual. Note also that
106 * a single ethernet frame can not span lists: if the host wants to
107 * transmit a frame and the frame data is split up over more than 10
108 * buffers, the frame has to collapsed before it can be transmitted.
110 * To receive frames, the driver sets up a number of lists and populates
111 * the fragment descriptors, then it sends an RX GO command to the chip.
112 * When a frame is received, the chip will DMA it into the memory regions
113 * specified by the fragment descriptors and then trigger an RX 'end of
114 * frame interrupt' when done. The driver may choose to use only one
115 * fragment per list; this may result is slighltly less efficient use
116 * of memory in exchange for improving performance.
118 * To transmit frames, the driver again sets up lists and fragment
119 * descriptors, only this time the buffers contain frame data that
120 * is to be DMA'ed into the chip instead of out of it. Once the chip
121 * has transferred the data into its on-board SRAM, it will trigger a
122 * TX 'end of frame' interrupt. It will also generate an 'end of channel'
123 * interrupt when it reaches the end of the list.
126 * Some notes about this driver:
128 * The ThunderLAN chip provides a couple of different ways to organize
129 * reception, transmission and interrupt handling. The simplest approach
130 * is to use one list each for transmission and reception. In this mode,
131 * the ThunderLAN will generate two interrupts for every received frame
132 * (one RX EOF and one RX EOC) and two for each transmitted frame (one
133 * TX EOF and one TX EOC). This may make the driver simpler but it hurts
134 * performance to have to handle so many interrupts.
136 * Initially I wanted to create a circular list of receive buffers so
137 * that the ThunderLAN chip would think there was an infinitely long
138 * receive channel and never deliver an RXEOC interrupt. However this
139 * doesn't work correctly under heavy load: while the manual says the
140 * chip will trigger an RXEOF interrupt each time a frame is copied into
141 * memory, you can't count on the chip waiting around for you to acknowledge
142 * the interrupt before it starts trying to DMA the next frame. The result
143 * is that the chip might traverse the entire circular list and then wrap
144 * around before you have a chance to do anything about it. Consequently,
145 * the receive list is terminated (with a 0 in the forward pointer in the
146 * last element). Each time an RXEOF interrupt arrives, the used list
147 * is shifted to the end of the list. This gives the appearance of an
148 * infinitely large RX chain so long as the driver doesn't fall behind
149 * the chip and allow all of the lists to be filled up.
151 * If all the lists are filled, the adapter will deliver an RX 'end of
152 * channel' interrupt when it hits the 0 forward pointer at the end of
153 * the chain. The RXEOC handler then cleans out the RX chain and resets
154 * the list head pointer in the ch_parm register and restarts the receiver.
156 * For frame transmission, it is possible to program the ThunderLAN's
157 * transmit interrupt threshold so that the chip can acknowledge multiple
158 * lists with only a single TX EOF interrupt. This allows the driver to
159 * queue several frames in one shot, and only have to handle a total
160 * two interrupts (one TX EOF and one TX EOC) no matter how many frames
161 * are transmitted. Frame transmission is done directly out of the
162 * mbufs passed to the tl_start() routine via the interface send queue.
163 * The driver simply sets up the fragment descriptors in the transmit
164 * lists to point to the mbuf data regions and sends a TX GO command.
166 * Note that since the RX and TX lists themselves are always used
167 * only by the driver, the are malloc()ed once at driver initialization
168 * time and never free()ed.
170 * Also, in order to remain as platform independent as possible, this
171 * driver uses memory mapped register access to manipulate the card
172 * as opposed to programmed I/O. This avoids the use of the inb/outb
173 * (and related) instructions which are specific to the i386 platform.
175 * Using these techniques, this driver achieves very high performance
176 * by minimizing the amount of interrupts generated during large
177 * transfers and by completely avoiding buffer copies. Frame transfer
178 * to and from the ThunderLAN chip is performed entirely by the chip
179 * itself thereby reducing the load on the host CPU.
182 #include <sys/param.h>
183 #include <sys/systm.h>
184 #include <sys/sockio.h>
185 #include <sys/mbuf.h>
186 #include <sys/malloc.h>
187 #include <sys/kernel.h>
188 #include <sys/module.h>
189 #include <sys/socket.h>
192 #include <net/if_var.h>
193 #include <net/if_arp.h>
194 #include <net/ethernet.h>
195 #include <net/if_dl.h>
196 #include <net/if_media.h>
197 #include <net/if_types.h>
201 #include <vm/vm.h> /* for vtophys */
202 #include <vm/pmap.h> /* for vtophys */
203 #include <machine/bus.h>
204 #include <machine/resource.h>
206 #include <sys/rman.h>
208 #include <dev/mii/mii.h>
209 #include <dev/mii/mii_bitbang.h>
210 #include <dev/mii/miivar.h>
212 #include <dev/pci/pcireg.h>
213 #include <dev/pci/pcivar.h>
216 * Default to using PIO register access mode to pacify certain
217 * laptop docking stations with built-in ThunderLAN chips that
218 * don't seem to handle memory mapped mode properly.
220 #define TL_USEIOSPACE
222 #include <dev/tl/if_tlreg.h>
224 MODULE_DEPEND(tl, pci, 1, 1, 1);
225 MODULE_DEPEND(tl, ether, 1, 1, 1);
226 MODULE_DEPEND(tl, miibus, 1, 1, 1);
228 /* "device miibus" required. See GENERIC if you get errors here. */
229 #include "miibus_if.h"
232 * Various supported device vendors/types and their names.
235 static const struct tl_type tl_devs[] = {
236 { TI_VENDORID, TI_DEVICEID_THUNDERLAN,
237 "Texas Instruments ThunderLAN" },
238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
239 "Compaq Netelligent 10" },
240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
241 "Compaq Netelligent 10/100" },
242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
243 "Compaq Netelligent 10/100 Proliant" },
244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
245 "Compaq Netelligent 10/100 Dual Port" },
246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
247 "Compaq NetFlex-3/P Integrated" },
248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
249 "Compaq NetFlex-3/P" },
250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
251 "Compaq NetFlex 3/P w/ BNC" },
252 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
253 "Compaq Netelligent 10/100 TX Embedded UTP" },
254 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
255 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
256 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
257 "Compaq Netelligent 10/100 TX UTP" },
258 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
259 "Olicom OC-2183/2185" },
260 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
262 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
263 "Olicom OC-2326 10/100 TX UTP" },
267 static int tl_probe(device_t);
268 static int tl_attach(device_t);
269 static int tl_detach(device_t);
270 static int tl_intvec_rxeoc(void *, u_int32_t);
271 static int tl_intvec_txeoc(void *, u_int32_t);
272 static int tl_intvec_txeof(void *, u_int32_t);
273 static int tl_intvec_rxeof(void *, u_int32_t);
274 static int tl_intvec_adchk(void *, u_int32_t);
275 static int tl_intvec_netsts(void *, u_int32_t);
277 static int tl_newbuf(struct tl_softc *, struct tl_chain_onefrag *);
278 static void tl_stats_update(void *);
279 static int tl_encap(struct tl_softc *, struct tl_chain *, struct mbuf *);
281 static void tl_intr(void *);
282 static void tl_start(struct ifnet *);
283 static void tl_start_locked(struct ifnet *);
284 static int tl_ioctl(struct ifnet *, u_long, caddr_t);
285 static void tl_init(void *);
286 static void tl_init_locked(struct tl_softc *);
287 static void tl_stop(struct tl_softc *);
288 static void tl_watchdog(struct tl_softc *);
289 static int tl_shutdown(device_t);
290 static int tl_ifmedia_upd(struct ifnet *);
291 static void tl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
293 static u_int8_t tl_eeprom_putbyte(struct tl_softc *, int);
294 static u_int8_t tl_eeprom_getbyte(struct tl_softc *, int, u_int8_t *);
295 static int tl_read_eeprom(struct tl_softc *, caddr_t, int, int);
297 static int tl_miibus_readreg(device_t, int, int);
298 static int tl_miibus_writereg(device_t, int, int, int);
299 static void tl_miibus_statchg(device_t);
301 static void tl_setmode(struct tl_softc *, int);
302 static uint32_t tl_mchash(const uint8_t *);
303 static void tl_setmulti(struct tl_softc *);
304 static void tl_setfilt(struct tl_softc *, caddr_t, int);
305 static void tl_softreset(struct tl_softc *, int);
306 static void tl_hardreset(device_t);
307 static int tl_list_rx_init(struct tl_softc *);
308 static int tl_list_tx_init(struct tl_softc *);
310 static u_int8_t tl_dio_read8(struct tl_softc *, int);
311 static u_int16_t tl_dio_read16(struct tl_softc *, int);
312 static u_int32_t tl_dio_read32(struct tl_softc *, int);
313 static void tl_dio_write8(struct tl_softc *, int, int);
314 static void tl_dio_write16(struct tl_softc *, int, int);
315 static void tl_dio_write32(struct tl_softc *, int, int);
316 static void tl_dio_setbit(struct tl_softc *, int, int);
317 static void tl_dio_clrbit(struct tl_softc *, int, int);
318 static void tl_dio_setbit16(struct tl_softc *, int, int);
319 static void tl_dio_clrbit16(struct tl_softc *, int, int);
324 static uint32_t tl_mii_bitbang_read(device_t);
325 static void tl_mii_bitbang_write(device_t, uint32_t);
327 static const struct mii_bitbang_ops tl_mii_bitbang_ops = {
329 tl_mii_bitbang_write,
331 TL_SIO_MDATA, /* MII_BIT_MDO */
332 TL_SIO_MDATA, /* MII_BIT_MDI */
333 TL_SIO_MCLK, /* MII_BIT_MDC */
334 TL_SIO_MTXEN, /* MII_BIT_DIR_HOST_PHY */
335 0, /* MII_BIT_DIR_PHY_HOST */
340 #define TL_RES SYS_RES_IOPORT
341 #define TL_RID TL_PCI_LOIO
343 #define TL_RES SYS_RES_MEMORY
344 #define TL_RID TL_PCI_LOMEM
347 static device_method_t tl_methods[] = {
348 /* Device interface */
349 DEVMETHOD(device_probe, tl_probe),
350 DEVMETHOD(device_attach, tl_attach),
351 DEVMETHOD(device_detach, tl_detach),
352 DEVMETHOD(device_shutdown, tl_shutdown),
355 DEVMETHOD(miibus_readreg, tl_miibus_readreg),
356 DEVMETHOD(miibus_writereg, tl_miibus_writereg),
357 DEVMETHOD(miibus_statchg, tl_miibus_statchg),
362 static driver_t tl_driver = {
365 sizeof(struct tl_softc)
368 static devclass_t tl_devclass;
370 DRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0);
371 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0);
373 static u_int8_t tl_dio_read8(sc, reg)
378 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
379 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
380 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
381 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
382 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
383 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
386 static u_int16_t tl_dio_read16(sc, reg)
391 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
392 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
393 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
394 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
395 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
396 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
399 static u_int32_t tl_dio_read32(sc, reg)
404 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
405 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
406 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
407 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
408 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
409 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
412 static void tl_dio_write8(sc, reg, val)
418 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
419 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
420 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
421 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
422 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
423 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
426 static void tl_dio_write16(sc, reg, val)
432 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
433 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
434 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
435 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
436 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
437 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
440 static void tl_dio_write32(sc, reg, val)
446 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
447 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
448 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
449 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
450 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
451 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
455 tl_dio_setbit(sc, reg, bit)
462 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
463 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
464 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
465 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
466 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
467 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
469 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1,
470 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
471 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
475 tl_dio_clrbit(sc, reg, bit)
482 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
483 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
484 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
485 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
486 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
487 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
489 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1,
490 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
491 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
494 static void tl_dio_setbit16(sc, reg, bit)
501 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
502 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
503 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
504 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
505 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
506 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
508 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2,
509 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
510 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
513 static void tl_dio_clrbit16(sc, reg, bit)
520 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
521 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
522 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
523 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
524 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
525 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
527 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2,
528 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
529 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
533 * Send an instruction or address to the EEPROM, check for ACK.
535 static u_int8_t tl_eeprom_putbyte(sc, byte)
542 * Make sure we're in TX mode.
544 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
547 * Feed in each bit and stobe the clock.
549 for (i = 0x80; i; i >>= 1) {
551 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
553 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
556 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
558 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
564 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
569 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
570 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
571 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
577 * Read a byte of data stored in the EEPROM at address 'addr.'
579 static u_int8_t tl_eeprom_getbyte(sc, addr, dest)
586 device_t tl_dev = sc->tl_dev;
588 tl_dio_write8(sc, TL_NETSIO, 0);
593 * Send write control code to EEPROM.
595 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
596 device_printf(tl_dev, "failed to send write command, status: %x\n",
597 tl_dio_read8(sc, TL_NETSIO));
602 * Send address of byte we want to read.
604 if (tl_eeprom_putbyte(sc, addr)) {
605 device_printf(tl_dev, "failed to send address, status: %x\n",
606 tl_dio_read8(sc, TL_NETSIO));
613 * Send read control code to EEPROM.
615 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
616 device_printf(tl_dev, "failed to send write command, status: %x\n",
617 tl_dio_read8(sc, TL_NETSIO));
622 * Start reading bits from EEPROM.
624 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
625 for (i = 0x80; i; i >>= 1) {
626 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
628 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
630 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
637 * No ACK generated for read, so just return byte.
646 * Read a sequence of bytes from the EEPROM.
649 tl_read_eeprom(sc, dest, off, cnt)
658 for (i = 0; i < cnt; i++) {
659 err = tl_eeprom_getbyte(sc, off + i, &byte);
668 #define TL_SIO_MII (TL_SIO_MCLK | TL_SIO_MDATA | TL_SIO_MTXEN)
671 * Read the MII serial port for the MII bit-bang module.
674 tl_mii_bitbang_read(device_t dev)
679 sc = device_get_softc(dev);
681 val = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MII;
682 CSR_BARRIER(sc, TL_NETSIO, 1,
683 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
689 * Write the MII serial port for the MII bit-bang module.
692 tl_mii_bitbang_write(device_t dev, uint32_t val)
696 sc = device_get_softc(dev);
698 val = (tl_dio_read8(sc, TL_NETSIO) & ~TL_SIO_MII) | val;
699 CSR_BARRIER(sc, TL_NETSIO, 1,
700 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
701 tl_dio_write8(sc, TL_NETSIO, val);
702 CSR_BARRIER(sc, TL_NETSIO, 1,
703 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
707 tl_miibus_readreg(dev, phy, reg)
714 sc = device_get_softc(dev);
717 * Turn off MII interrupt by forcing MINTEN low.
719 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
721 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
724 val = mii_bitbang_readreg(dev, &tl_mii_bitbang_ops, phy, reg);
726 /* Reenable interrupts. */
728 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
735 tl_miibus_writereg(dev, phy, reg, data)
742 sc = device_get_softc(dev);
745 * Turn off MII interrupt by forcing MINTEN low.
747 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
749 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
752 mii_bitbang_writereg(dev, &tl_mii_bitbang_ops, phy, reg, data);
754 /* Reenable interrupts. */
756 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
763 tl_miibus_statchg(dev)
767 struct mii_data *mii;
769 sc = device_get_softc(dev);
770 mii = device_get_softc(sc->tl_miibus);
772 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
773 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
775 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
780 * Set modes for bitrate devices.
783 tl_setmode(sc, media)
787 if (IFM_SUBTYPE(media) == IFM_10_5)
788 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
789 if (IFM_SUBTYPE(media) == IFM_10_T) {
790 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
791 if ((media & IFM_GMASK) == IFM_FDX) {
792 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
793 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
795 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
796 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
802 * Calculate the hash of a MAC address for programming the multicast hash
803 * table. This hash is simply the address split into 6-bit chunks
805 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
806 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
807 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then
808 * the folded 24-bit value is split into 6-bit portions and XOR'd.
816 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
818 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
822 * The ThunderLAN has a perfect MAC address filter in addition to
823 * the multicast hash filter. The perfect filter can be programmed
824 * with up to four MAC addresses. The first one is always used to
825 * hold the station address, which leaves us free to use the other
826 * three for multicast addresses.
829 tl_setfilt(sc, addr, slot)
837 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
839 for (i = 0; i < ETHER_ADDR_LEN; i++)
840 tl_dio_write8(sc, regaddr + i, *(addr + i));
844 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
845 * linked list. This is fine, except addresses are added from the head
846 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
847 * group to always be in the perfect filter, but as more groups are added,
848 * the 224.0.0.1 entry (which is always added first) gets pushed down
849 * the list and ends up at the tail. So after 3 or 4 multicast groups
850 * are added, the all-hosts entry gets pushed out of the perfect filter
851 * and into the hash table.
853 * Because the multicast list is a doubly-linked list as opposed to a
854 * circular queue, we don't have the ability to just grab the tail of
855 * the list and traverse it backwards. Instead, we have to traverse
856 * the list once to find the tail, then traverse it again backwards to
857 * update the multicast filter.
864 u_int32_t hashes[2] = { 0, 0 };
866 struct ifmultiaddr *ifma;
867 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
870 /* First, zot all the existing filters. */
871 for (i = 1; i < 4; i++)
872 tl_setfilt(sc, (caddr_t)&dummy, i);
873 tl_dio_write32(sc, TL_HASH1, 0);
874 tl_dio_write32(sc, TL_HASH2, 0);
876 /* Now program new ones. */
877 if (ifp->if_flags & IFF_ALLMULTI) {
878 hashes[0] = 0xFFFFFFFF;
879 hashes[1] = 0xFFFFFFFF;
883 /* XXX want to maintain reverse semantics - pop list and re-add? */
884 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
885 if (ifma->ifma_addr->sa_family != AF_LINK)
888 * Program the first three multicast groups
889 * into the perfect filter. For all others,
890 * use the hash table.
894 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
900 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
902 hashes[0] |= (1 << h);
904 hashes[1] |= (1 << (h - 32));
906 if_maddr_runlock(ifp);
909 tl_dio_write32(sc, TL_HASH1, hashes[0]);
910 tl_dio_write32(sc, TL_HASH2, hashes[1]);
914 * This routine is recommended by the ThunderLAN manual to insure that
915 * the internal PHY is powered up correctly. It also recommends a one
916 * second pause at the end to 'wait for the clocks to start' but in my
917 * experience this isn't necessary.
926 mii_bitbang_sync(dev, &tl_mii_bitbang_ops);
928 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
930 for (i = 0; i < MII_NPHY; i++)
931 tl_miibus_writereg(dev, i, MII_BMCR, flags);
933 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
935 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
936 mii_bitbang_sync(dev, &tl_mii_bitbang_ops);
937 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
943 tl_softreset(sc, internal)
947 u_int32_t cmd, dummy, i;
949 /* Assert the adapter reset bit. */
950 CMD_SET(sc, TL_CMD_ADRST);
952 /* Turn off interrupts */
953 CMD_SET(sc, TL_CMD_INTSOFF);
955 /* First, clear the stats registers. */
956 for (i = 0; i < 5; i++)
957 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
959 /* Clear Areg and Hash registers */
960 for (i = 0; i < 8; i++)
961 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
964 * Set up Netconfig register. Enable one channel and
967 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
968 if (internal && !sc->tl_bitrate) {
969 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
971 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
974 /* Handle cards with bitrate devices. */
976 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
979 * Load adapter irq pacing timer and tx threshold.
980 * We make the transmit threshold 1 initially but we may
983 cmd = CSR_READ_4(sc, TL_HOSTCMD);
985 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
986 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
987 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
989 /* Unreset the MII */
990 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
992 /* Take the adapter out of reset */
993 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
995 /* Wait for things to settle down a little. */
1000 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
1001 * against our list and return its name if we find a match.
1007 const struct tl_type *t;
1011 while(t->tl_name != NULL) {
1012 if ((pci_get_vendor(dev) == t->tl_vid) &&
1013 (pci_get_device(dev) == t->tl_did)) {
1014 device_set_desc(dev, t->tl_name);
1015 return (BUS_PROBE_DEFAULT);
1028 const struct tl_type *t;
1030 struct tl_softc *sc;
1031 int error, flags, i, rid, unit;
1034 vid = pci_get_vendor(dev);
1035 did = pci_get_device(dev);
1036 sc = device_get_softc(dev);
1038 unit = device_get_unit(dev);
1041 while(t->tl_name != NULL) {
1042 if (vid == t->tl_vid && did == t->tl_did)
1047 if (t->tl_name == NULL) {
1048 device_printf(dev, "unknown device!?\n");
1052 mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1056 * Map control/status registers.
1058 pci_enable_busmaster(dev);
1060 #ifdef TL_USEIOSPACE
1063 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1067 * Some cards have the I/O and memory mapped address registers
1068 * reversed. Try both combinations before giving up.
1070 if (sc->tl_res == NULL) {
1072 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1077 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1079 if (sc->tl_res == NULL) {
1081 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1086 if (sc->tl_res == NULL) {
1087 device_printf(dev, "couldn't map ports/memory\n");
1094 * The ThunderLAN manual suggests jacking the PCI latency
1095 * timer all the way up to its maximum value. I'm not sure
1096 * if this is really necessary, but what the manual wants,
1099 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4);
1100 command |= 0x0000FF00;
1101 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4);
1104 /* Allocate interrupt */
1106 sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1107 RF_SHAREABLE | RF_ACTIVE);
1109 if (sc->tl_irq == NULL) {
1110 device_printf(dev, "couldn't map interrupt\n");
1116 * Now allocate memory for the TX and RX lists.
1118 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF,
1119 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1121 if (sc->tl_ldata == NULL) {
1122 device_printf(dev, "no memory for list buffers!\n");
1127 bzero(sc->tl_ldata, sizeof(struct tl_list_data));
1129 if (vid == COMPAQ_VENDORID || vid == TI_VENDORID)
1130 sc->tl_eeaddr = TL_EEPROM_EADDR;
1131 if (vid == OLICOM_VENDORID)
1132 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
1134 /* Reset the adapter. */
1135 tl_softreset(sc, 1);
1137 tl_softreset(sc, 1);
1140 * Get station address from the EEPROM.
1142 if (tl_read_eeprom(sc, eaddr, sc->tl_eeaddr, ETHER_ADDR_LEN)) {
1143 device_printf(dev, "failed to read station address\n");
1149 * XXX Olicom, in its desire to be different from the
1150 * rest of the world, has done strange things with the
1151 * encoding of the station address in the EEPROM. First
1152 * of all, they store the address at offset 0xF8 rather
1153 * than at 0x83 like the ThunderLAN manual suggests.
1154 * Second, they store the address in three 16-bit words in
1155 * network byte order, as opposed to storing it sequentially
1156 * like all the other ThunderLAN cards. In order to get
1157 * the station address in a form that matches what the Olicom
1158 * diagnostic utility specifies, we have to byte-swap each
1159 * word. To make things even more confusing, neither 00:00:28
1160 * nor 00:00:24 appear in the IEEE OUI database.
1162 if (vid == OLICOM_VENDORID) {
1163 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1165 p = (u_int16_t *)&eaddr[i];
1170 ifp = sc->tl_ifp = if_alloc(IFT_ETHER);
1172 device_printf(dev, "can not if_alloc()\n");
1177 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1178 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1179 ifp->if_ioctl = tl_ioctl;
1180 ifp->if_start = tl_start;
1181 ifp->if_init = tl_init;
1182 ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1;
1183 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1184 ifp->if_capenable |= IFCAP_VLAN_MTU;
1185 callout_init_mtx(&sc->tl_stat_callout, &sc->tl_mtx, 0);
1187 /* Reset the adapter again. */
1188 tl_softreset(sc, 1);
1190 tl_softreset(sc, 1);
1193 * Do MII setup. If no PHYs are found, then this is a
1194 * bitrate ThunderLAN chip that only supports 10baseT
1196 * XXX mii_attach() can fail for reason different than
1200 if (vid == COMPAQ_VENDORID) {
1201 if (did == COMPAQ_DEVICEID_NETEL_10_100_PROLIANT ||
1202 did == COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED ||
1203 did == COMPAQ_DEVICEID_NETFLEX_3P_BNC ||
1204 did == COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX)
1205 flags |= MIIF_MACPRIV0;
1206 if (did == COMPAQ_DEVICEID_NETEL_10 ||
1207 did == COMPAQ_DEVICEID_NETEL_10_100_DUAL ||
1208 did == COMPAQ_DEVICEID_NETFLEX_3P ||
1209 did == COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED)
1210 flags |= MIIF_MACPRIV1;
1211 } else if (vid == OLICOM_VENDORID && did == OLICOM_DEVICEID_OC2183)
1212 flags |= MIIF_MACPRIV0 | MIIF_MACPRIV1;
1213 if (mii_attach(dev, &sc->tl_miibus, ifp, tl_ifmedia_upd,
1214 tl_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0)) {
1215 struct ifmedia *ifm;
1217 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1218 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1219 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1220 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1221 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1222 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
1223 /* Reset again, this time setting bitrate mode. */
1224 tl_softreset(sc, 1);
1226 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1227 tl_ifmedia_upd(ifp);
1231 * Call MI attach routine.
1233 ether_ifattach(ifp, eaddr);
1235 /* Hook interrupt last to avoid having to lock softc */
1236 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1237 NULL, tl_intr, sc, &sc->tl_intrhand);
1240 device_printf(dev, "couldn't set up irq\n");
1241 ether_ifdetach(ifp);
1245 gone_by_fcp101_dev(dev);
1255 * Shutdown hardware and free up resources. This can be called any
1256 * time after the mutex has been initialized. It is called in both
1257 * the error case in attach and the normal detach case so it needs
1258 * to be careful about only freeing resources that have actually been
1265 struct tl_softc *sc;
1268 sc = device_get_softc(dev);
1269 KASSERT(mtx_initialized(&sc->tl_mtx), ("tl mutex not initialized"));
1272 /* These should only be active if attach succeeded */
1273 if (device_is_attached(dev)) {
1274 ether_ifdetach(ifp);
1278 callout_drain(&sc->tl_stat_callout);
1281 device_delete_child(dev, sc->tl_miibus);
1282 bus_generic_detach(dev);
1285 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF);
1287 ifmedia_removeall(&sc->ifmedia);
1289 if (sc->tl_intrhand)
1290 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1292 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1294 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1299 mtx_destroy(&sc->tl_mtx);
1305 * Initialize the transmit lists.
1309 struct tl_softc *sc;
1311 struct tl_chain_data *cd;
1312 struct tl_list_data *ld;
1317 for (i = 0; i < TL_TX_LIST_CNT; i++) {
1318 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
1319 if (i == (TL_TX_LIST_CNT - 1))
1320 cd->tl_tx_chain[i].tl_next = NULL;
1322 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
1325 cd->tl_tx_free = &cd->tl_tx_chain[0];
1326 cd->tl_tx_tail = cd->tl_tx_head = NULL;
1333 * Initialize the RX lists and allocate mbufs for them.
1337 struct tl_softc *sc;
1339 struct tl_chain_data *cd;
1340 struct tl_list_data *ld;
1346 for (i = 0; i < TL_RX_LIST_CNT; i++) {
1347 cd->tl_rx_chain[i].tl_ptr =
1348 (struct tl_list_onefrag *)&ld->tl_rx_list[i];
1349 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
1351 if (i == (TL_RX_LIST_CNT - 1)) {
1352 cd->tl_rx_chain[i].tl_next = NULL;
1353 ld->tl_rx_list[i].tlist_fptr = 0;
1355 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
1356 ld->tl_rx_list[i].tlist_fptr =
1357 vtophys(&ld->tl_rx_list[i + 1]);
1361 cd->tl_rx_head = &cd->tl_rx_chain[0];
1362 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1369 struct tl_softc *sc;
1370 struct tl_chain_onefrag *c;
1372 struct mbuf *m_new = NULL;
1374 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1380 c->tl_ptr->tlist_frsize = MCLBYTES;
1381 c->tl_ptr->tlist_fptr = 0;
1382 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
1383 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1384 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1389 * Interrupt handler for RX 'end of frame' condition (EOF). This
1390 * tells us that a full ethernet frame has been captured and we need
1393 * Reception is done using 'lists' which consist of a header and a
1394 * series of 10 data count/data address pairs that point to buffers.
1395 * Initially you're supposed to create a list, populate it with pointers
1396 * to buffers, then load the physical address of the list into the
1397 * ch_parm register. The adapter is then supposed to DMA the received
1398 * frame into the buffers for you.
1400 * To make things as fast as possible, we have the chip DMA directly
1401 * into mbufs. This saves us from having to do a buffer copy: we can
1402 * just hand the mbufs directly to ether_input(). Once the frame has
1403 * been sent on its way, the 'list' structure is assigned a new buffer
1404 * and moved to the end of the RX chain. As long we we stay ahead of
1405 * the chip, it will always think it has an endless receive channel.
1407 * If we happen to fall behind and the chip manages to fill up all of
1408 * the buffers, it will generate an end of channel interrupt and wait
1409 * for us to empty the chain and restart the receiver.
1412 tl_intvec_rxeof(xsc, type)
1416 struct tl_softc *sc;
1417 int r = 0, total_len = 0;
1418 struct ether_header *eh;
1421 struct tl_chain_onefrag *cur_rx;
1428 while(sc->tl_cdata.tl_rx_head != NULL) {
1429 cur_rx = sc->tl_cdata.tl_rx_head;
1430 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1433 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
1434 m = cur_rx->tl_mbuf;
1435 total_len = cur_rx->tl_ptr->tlist_frsize;
1437 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
1438 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1439 cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
1440 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1441 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1445 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
1446 vtophys(cur_rx->tl_ptr);
1447 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
1448 sc->tl_cdata.tl_rx_tail = cur_rx;
1451 * Note: when the ThunderLAN chip is in 'capture all
1452 * frames' mode, it will receive its own transmissions.
1453 * We drop don't need to process our own transmissions,
1454 * so we drop them here and continue.
1456 eh = mtod(m, struct ether_header *);
1457 /*if (ifp->if_flags & IFF_PROMISC && */
1458 if (!bcmp(eh->ether_shost, IF_LLADDR(sc->tl_ifp),
1464 m->m_pkthdr.rcvif = ifp;
1465 m->m_pkthdr.len = m->m_len = total_len;
1468 (*ifp->if_input)(ifp, m);
1476 * The RX-EOC condition hits when the ch_parm address hasn't been
1477 * initialized or the adapter reached a list with a forward pointer
1478 * of 0 (which indicates the end of the chain). In our case, this means
1479 * the card has hit the end of the receive buffer chain and we need to
1480 * empty out the buffers and shift the pointer back to the beginning again.
1483 tl_intvec_rxeoc(xsc, type)
1487 struct tl_softc *sc;
1489 struct tl_chain_data *cd;
1495 /* Flush out the receive queue and ack RXEOF interrupts. */
1496 r = tl_intvec_rxeof(xsc, type);
1497 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
1499 cd->tl_rx_head = &cd->tl_rx_chain[0];
1500 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1501 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
1502 r |= (TL_CMD_GO|TL_CMD_RT);
1507 tl_intvec_txeof(xsc, type)
1511 struct tl_softc *sc;
1513 struct tl_chain *cur_tx;
1518 * Go through our tx list and free mbufs for those
1519 * frames that have been sent.
1521 while (sc->tl_cdata.tl_tx_head != NULL) {
1522 cur_tx = sc->tl_cdata.tl_tx_head;
1523 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1525 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
1528 m_freem(cur_tx->tl_mbuf);
1529 cur_tx->tl_mbuf = NULL;
1531 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
1532 sc->tl_cdata.tl_tx_free = cur_tx;
1533 if (!cur_tx->tl_ptr->tlist_fptr)
1541 * The transmit end of channel interrupt. The adapter triggers this
1542 * interrupt to tell us it hit the end of the current transmit list.
1544 * A note about this: it's possible for a condition to arise where
1545 * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
1546 * You have to avoid this since the chip expects things to go in a
1547 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
1548 * When the TXEOF handler is called, it will free all of the transmitted
1549 * frames and reset the tx_head pointer to NULL. However, a TXEOC
1550 * interrupt should be received and acknowledged before any more frames
1551 * are queued for transmission. If tl_statrt() is called after TXEOF
1552 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
1553 * it could attempt to issue a transmit command prematurely.
1555 * To guard against this, tl_start() will only issue transmit commands
1556 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
1557 * can set this flag once tl_start() has cleared it.
1560 tl_intvec_txeoc(xsc, type)
1564 struct tl_softc *sc;
1571 /* Clear the timeout timer. */
1574 if (sc->tl_cdata.tl_tx_head == NULL) {
1575 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1576 sc->tl_cdata.tl_tx_tail = NULL;
1580 /* First we have to ack the EOC interrupt. */
1581 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
1582 /* Then load the address of the next TX list. */
1583 CSR_WRITE_4(sc, TL_CH_PARM,
1584 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
1585 /* Restart TX channel. */
1586 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1588 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1597 tl_intvec_adchk(xsc, type)
1601 struct tl_softc *sc;
1606 device_printf(sc->tl_dev, "adapter check: %x\n",
1607 (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
1609 tl_softreset(sc, 1);
1612 CMD_SET(sc, TL_CMD_INTSON);
1618 tl_intvec_netsts(xsc, type)
1622 struct tl_softc *sc;
1627 netsts = tl_dio_read16(sc, TL_NETSTS);
1628 tl_dio_write16(sc, TL_NETSTS, netsts);
1630 device_printf(sc->tl_dev, "network status: %x\n", netsts);
1639 struct tl_softc *sc;
1649 /* Disable interrupts */
1650 ints = CSR_READ_2(sc, TL_HOST_INT);
1651 CSR_WRITE_2(sc, TL_HOST_INT, ints);
1652 type = (ints << 16) & 0xFFFF0000;
1653 ivec = (ints & TL_VEC_MASK) >> 5;
1654 ints = (ints & TL_INT_MASK) >> 2;
1659 case (TL_INTR_INVALID):
1661 device_printf(sc->tl_dev, "got an invalid interrupt!\n");
1663 /* Re-enable interrupts but don't ack this one. */
1667 case (TL_INTR_TXEOF):
1668 r = tl_intvec_txeof((void *)sc, type);
1670 case (TL_INTR_TXEOC):
1671 r = tl_intvec_txeoc((void *)sc, type);
1673 case (TL_INTR_STATOFLOW):
1674 tl_stats_update(sc);
1677 case (TL_INTR_RXEOF):
1678 r = tl_intvec_rxeof((void *)sc, type);
1680 case (TL_INTR_DUMMY):
1681 device_printf(sc->tl_dev, "got a dummy interrupt\n");
1684 case (TL_INTR_ADCHK):
1686 r = tl_intvec_adchk((void *)sc, type);
1688 r = tl_intvec_netsts((void *)sc, type);
1690 case (TL_INTR_RXEOC):
1691 r = tl_intvec_rxeoc((void *)sc, type);
1694 device_printf(sc->tl_dev, "bogus interrupt type\n");
1698 /* Re-enable interrupts */
1700 CMD_PUT(sc, TL_CMD_ACK | r | type);
1703 if (ifp->if_snd.ifq_head != NULL)
1704 tl_start_locked(ifp);
1710 tl_stats_update(xsc)
1713 struct tl_softc *sc;
1715 struct tl_stats tl_stats;
1716 struct mii_data *mii;
1719 bzero((char *)&tl_stats, sizeof(struct tl_stats));
1725 p = (u_int32_t *)&tl_stats;
1727 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
1728 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1729 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1730 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1731 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1732 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1734 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tl_tx_goodframes(tl_stats));
1735 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1736 tl_stats.tl_tx_single_collision + tl_stats.tl_tx_multi_collision);
1737 if_inc_counter(ifp, IFCOUNTER_IPACKETS, tl_rx_goodframes(tl_stats));
1738 if_inc_counter(ifp, IFCOUNTER_IERRORS, tl_stats.tl_crc_errors +
1739 tl_stats.tl_code_errors + tl_rx_overrun(tl_stats));
1740 if_inc_counter(ifp, IFCOUNTER_OERRORS, tl_tx_underrun(tl_stats));
1742 if (tl_tx_underrun(tl_stats)) {
1744 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH;
1745 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) {
1748 device_printf(sc->tl_dev, "tx underrun -- increasing "
1749 "tx threshold to %d bytes\n",
1750 (64 * (tx_thresh * 4)));
1751 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1752 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4);
1756 if (sc->tl_timer > 0 && --sc->tl_timer == 0)
1759 callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc);
1761 if (!sc->tl_bitrate) {
1762 mii = device_get_softc(sc->tl_miibus);
1768 * Encapsulate an mbuf chain in a list by coupling the mbuf data
1769 * pointers to the fragment pointers.
1772 tl_encap(sc, c, m_head)
1773 struct tl_softc *sc;
1775 struct mbuf *m_head;
1778 struct tl_frag *f = NULL;
1781 struct ifnet *ifp = sc->tl_ifp;
1784 * Start packing the mbufs in this chain into
1785 * the fragment pointers. Stop when we run out
1786 * of fragments or hit the end of the mbuf chain.
1791 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1792 if (m->m_len != 0) {
1793 if (frag == TL_MAXFRAGS)
1795 total_len+= m->m_len;
1796 c->tl_ptr->tl_frag[frag].tlist_dadr =
1797 vtophys(mtod(m, vm_offset_t));
1798 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
1804 * Handle special cases.
1805 * Special case #1: we used up all 10 fragments, but
1806 * we have more mbufs left in the chain. Copy the
1807 * data into an mbuf cluster. Note that we don't
1808 * bother clearing the values in the other fragment
1809 * pointers/counters; it wouldn't gain us anything,
1810 * and would waste cycles.
1813 struct mbuf *m_new = NULL;
1815 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1816 if (m_new == NULL) {
1817 if_printf(ifp, "no memory for tx list\n");
1820 if (m_head->m_pkthdr.len > MHLEN) {
1821 if (!(MCLGET(m_new, M_NOWAIT))) {
1823 if_printf(ifp, "no memory for tx list\n");
1827 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1828 mtod(m_new, caddr_t));
1829 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1832 f = &c->tl_ptr->tl_frag[0];
1833 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
1834 f->tlist_dcnt = total_len = m_new->m_len;
1839 * Special case #2: the frame is smaller than the minimum
1840 * frame size. We have to pad it to make the chip happy.
1842 if (total_len < TL_MIN_FRAMELEN) {
1843 if (frag == TL_MAXFRAGS)
1845 "all frags filled but frame still to small!\n");
1846 f = &c->tl_ptr->tl_frag[frag];
1847 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
1848 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
1849 total_len += f->tlist_dcnt;
1853 c->tl_mbuf = m_head;
1854 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
1855 c->tl_ptr->tlist_frsize = total_len;
1856 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1857 c->tl_ptr->tlist_fptr = 0;
1863 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1864 * to the mbuf data regions directly in the transmit lists. We also save a
1865 * copy of the pointers since the transmit list fragment pointers are
1866 * physical addresses.
1872 struct tl_softc *sc;
1876 tl_start_locked(ifp);
1881 tl_start_locked(ifp)
1884 struct tl_softc *sc;
1885 struct mbuf *m_head = NULL;
1887 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
1893 * Check for an available queue slot. If there are none,
1896 if (sc->tl_cdata.tl_tx_free == NULL) {
1897 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1901 start_tx = sc->tl_cdata.tl_tx_free;
1903 while(sc->tl_cdata.tl_tx_free != NULL) {
1904 IF_DEQUEUE(&ifp->if_snd, m_head);
1908 /* Pick a chain member off the free list. */
1909 cur_tx = sc->tl_cdata.tl_tx_free;
1910 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
1912 cur_tx->tl_next = NULL;
1914 /* Pack the data into the list. */
1915 tl_encap(sc, cur_tx, m_head);
1917 /* Chain it together */
1919 prev->tl_next = cur_tx;
1920 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
1925 * If there's a BPF listener, bounce a copy of this frame
1928 BPF_MTAP(ifp, cur_tx->tl_mbuf);
1932 * If there are no packets queued, bail.
1938 * That's all we can stands, we can't stands no more.
1939 * If there are no other transfers pending, then issue the
1940 * TX GO command to the adapter to start things moving.
1941 * Otherwise, just leave the data in the queue and let
1942 * the EOF/EOC interrupt handler send.
1944 if (sc->tl_cdata.tl_tx_head == NULL) {
1945 sc->tl_cdata.tl_tx_head = start_tx;
1946 sc->tl_cdata.tl_tx_tail = cur_tx;
1950 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
1951 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1953 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1957 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
1958 sc->tl_cdata.tl_tx_tail = cur_tx;
1962 * Set a timeout in case the chip goes out to lunch.
1971 struct tl_softc *sc = xsc;
1980 struct tl_softc *sc;
1982 struct ifnet *ifp = sc->tl_ifp;
1983 struct mii_data *mii;
1990 * Cancel pending I/O.
1994 /* Initialize TX FIFO threshold */
1995 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1996 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG);
1998 /* Set PCI burst size */
1999 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG);
2002 * Set 'capture all frames' bit for promiscuous mode.
2004 if (ifp->if_flags & IFF_PROMISC)
2005 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2007 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2010 * Set capture broadcast bit to capture broadcast frames.
2012 if (ifp->if_flags & IFF_BROADCAST)
2013 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2015 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2017 tl_dio_write16(sc, TL_MAXRX, MCLBYTES);
2019 /* Init our MAC address */
2020 tl_setfilt(sc, IF_LLADDR(sc->tl_ifp), 0);
2022 /* Init multicast filter, if needed. */
2025 /* Init circular RX list. */
2026 if (tl_list_rx_init(sc) == ENOBUFS) {
2027 device_printf(sc->tl_dev,
2028 "initialization failed: no memory for rx buffers\n");
2033 /* Init TX pointers. */
2034 tl_list_tx_init(sc);
2036 /* Enable PCI interrupts. */
2037 CMD_SET(sc, TL_CMD_INTSON);
2039 /* Load the address of the rx list */
2040 CMD_SET(sc, TL_CMD_RT);
2041 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
2043 if (!sc->tl_bitrate) {
2044 if (sc->tl_miibus != NULL) {
2045 mii = device_get_softc(sc->tl_miibus);
2049 tl_ifmedia_upd(ifp);
2052 /* Send the RX go command */
2053 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
2055 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2056 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2058 /* Start the stats update counter */
2059 callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc);
2063 * Set media options.
2069 struct tl_softc *sc;
2070 struct mii_data *mii = NULL;
2076 tl_setmode(sc, sc->ifmedia.ifm_media);
2078 mii = device_get_softc(sc->tl_miibus);
2087 * Report current media status.
2090 tl_ifmedia_sts(ifp, ifmr)
2092 struct ifmediareq *ifmr;
2094 struct tl_softc *sc;
2095 struct mii_data *mii;
2100 ifmr->ifm_active = IFM_ETHER;
2102 if (sc->tl_bitrate) {
2103 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
2104 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2106 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2107 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
2108 ifmr->ifm_active |= IFM_HDX;
2110 ifmr->ifm_active |= IFM_FDX;
2113 mii = device_get_softc(sc->tl_miibus);
2115 ifmr->ifm_active = mii->mii_media_active;
2116 ifmr->ifm_status = mii->mii_media_status;
2122 tl_ioctl(ifp, command, data)
2127 struct tl_softc *sc = ifp->if_softc;
2128 struct ifreq *ifr = (struct ifreq *) data;
2134 if (ifp->if_flags & IFF_UP) {
2135 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2136 ifp->if_flags & IFF_PROMISC &&
2137 !(sc->tl_if_flags & IFF_PROMISC)) {
2138 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2140 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2141 !(ifp->if_flags & IFF_PROMISC) &&
2142 sc->tl_if_flags & IFF_PROMISC) {
2143 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2148 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2152 sc->tl_if_flags = ifp->if_flags;
2166 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2168 struct mii_data *mii;
2169 mii = device_get_softc(sc->tl_miibus);
2170 error = ifmedia_ioctl(ifp, ifr,
2171 &mii->mii_media, command);
2175 error = ether_ioctl(ifp, command, data);
2184 struct tl_softc *sc;
2191 if_printf(ifp, "device timeout\n");
2193 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2195 tl_softreset(sc, 1);
2200 * Stop the adapter and free any mbufs allocated to the
2205 struct tl_softc *sc;
2214 /* Stop the stats updater. */
2215 callout_stop(&sc->tl_stat_callout);
2217 /* Stop the transmitter */
2218 CMD_CLR(sc, TL_CMD_RT);
2219 CMD_SET(sc, TL_CMD_STOP);
2220 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2222 /* Stop the receiver */
2223 CMD_SET(sc, TL_CMD_RT);
2224 CMD_SET(sc, TL_CMD_STOP);
2225 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2228 * Disable host interrupts.
2230 CMD_SET(sc, TL_CMD_INTSOFF);
2233 * Clear list pointer.
2235 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2238 * Free the RX lists.
2240 for (i = 0; i < TL_RX_LIST_CNT; i++) {
2241 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
2242 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
2243 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
2246 bzero((char *)&sc->tl_ldata->tl_rx_list,
2247 sizeof(sc->tl_ldata->tl_rx_list));
2250 * Free the TX list buffers.
2252 for (i = 0; i < TL_TX_LIST_CNT; i++) {
2253 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
2254 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2255 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2258 bzero((char *)&sc->tl_ldata->tl_tx_list,
2259 sizeof(sc->tl_ldata->tl_tx_list));
2261 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2265 * Stop all chip I/O so that the kernel's probe routines don't
2266 * get confused by errant DMAs when rebooting.
2272 struct tl_softc *sc;
2274 sc = device_get_softc(dev);