2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
38 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
39 * the National Semiconductor DP83840A physical interface and the
40 * Microchip Technology 24Cxx series serial EEPROM.
42 * Written using the following four documents:
44 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
45 * National Semiconductor DP83840A data sheet (www.national.com)
46 * Microchip Technology 24C02C data sheet (www.microchip.com)
47 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
49 * Written by Bill Paul <wpaul@ctr.columbia.edu>
50 * Electrical Engineering Department
51 * Columbia University, New York City
54 * Some notes about the ThunderLAN:
56 * The ThunderLAN controller is a single chip containing PCI controller
57 * logic, approximately 3K of on-board SRAM, a LAN controller, and media
58 * independent interface (MII) bus. The MII allows the ThunderLAN chip to
59 * control up to 32 different physical interfaces (PHYs). The ThunderLAN
60 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
61 * to act as a complete ethernet interface.
63 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
64 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
65 * in full or half duplex. Some of the Compaq Deskpro machines use a
66 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
67 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
68 * concert with the ThunderLAN's internal PHY to provide full 10/100
69 * support. This is cheaper than using a standalone external PHY for both
70 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
71 * A serial EEPROM is also attached to the ThunderLAN chip to provide
72 * power-up default register settings and for storing the adapter's
73 * station address. Although not supported by this driver, the ThunderLAN
74 * chip can also be connected to token ring PHYs.
76 * The ThunderLAN has a set of registers which can be used to issue
77 * commands, acknowledge interrupts, and to manipulate other internal
78 * registers on its DIO bus. The primary registers can be accessed
79 * using either programmed I/O (inb/outb) or via PCI memory mapping,
80 * depending on how the card is configured during the PCI probing
81 * phase. It is even possible to have both PIO and memory mapped
82 * access turned on at the same time.
84 * Frame reception and transmission with the ThunderLAN chip is done
85 * using frame 'lists.' A list structure looks more or less like this:
88 * u_int32_t fragment_address;
89 * u_int32_t fragment_size;
92 * u_int32_t forward_pointer;
94 * u_int16_t frame_size;
95 * struct tl_frag fragments[10];
98 * The forward pointer in the list header can be either a 0 or the address
99 * of another list, which allows several lists to be linked together. Each
100 * list contains up to 10 fragment descriptors. This means the chip allows
101 * ethernet frames to be broken up into up to 10 chunks for transfer to
102 * and from the SRAM. Note that the forward pointer and fragment buffer
103 * addresses are physical memory addresses, not virtual. Note also that
104 * a single ethernet frame can not span lists: if the host wants to
105 * transmit a frame and the frame data is split up over more than 10
106 * buffers, the frame has to collapsed before it can be transmitted.
108 * To receive frames, the driver sets up a number of lists and populates
109 * the fragment descriptors, then it sends an RX GO command to the chip.
110 * When a frame is received, the chip will DMA it into the memory regions
111 * specified by the fragment descriptors and then trigger an RX 'end of
112 * frame interrupt' when done. The driver may choose to use only one
113 * fragment per list; this may result is slighltly less efficient use
114 * of memory in exchange for improving performance.
116 * To transmit frames, the driver again sets up lists and fragment
117 * descriptors, only this time the buffers contain frame data that
118 * is to be DMA'ed into the chip instead of out of it. Once the chip
119 * has transfered the data into its on-board SRAM, it will trigger a
120 * TX 'end of frame' interrupt. It will also generate an 'end of channel'
121 * interrupt when it reaches the end of the list.
124 * Some notes about this driver:
126 * The ThunderLAN chip provides a couple of different ways to organize
127 * reception, transmission and interrupt handling. The simplest approach
128 * is to use one list each for transmission and reception. In this mode,
129 * the ThunderLAN will generate two interrupts for every received frame
130 * (one RX EOF and one RX EOC) and two for each transmitted frame (one
131 * TX EOF and one TX EOC). This may make the driver simpler but it hurts
132 * performance to have to handle so many interrupts.
134 * Initially I wanted to create a circular list of receive buffers so
135 * that the ThunderLAN chip would think there was an infinitely long
136 * receive channel and never deliver an RXEOC interrupt. However this
137 * doesn't work correctly under heavy load: while the manual says the
138 * chip will trigger an RXEOF interrupt each time a frame is copied into
139 * memory, you can't count on the chip waiting around for you to acknowledge
140 * the interrupt before it starts trying to DMA the next frame. The result
141 * is that the chip might traverse the entire circular list and then wrap
142 * around before you have a chance to do anything about it. Consequently,
143 * the receive list is terminated (with a 0 in the forward pointer in the
144 * last element). Each time an RXEOF interrupt arrives, the used list
145 * is shifted to the end of the list. This gives the appearance of an
146 * infinitely large RX chain so long as the driver doesn't fall behind
147 * the chip and allow all of the lists to be filled up.
149 * If all the lists are filled, the adapter will deliver an RX 'end of
150 * channel' interrupt when it hits the 0 forward pointer at the end of
151 * the chain. The RXEOC handler then cleans out the RX chain and resets
152 * the list head pointer in the ch_parm register and restarts the receiver.
154 * For frame transmission, it is possible to program the ThunderLAN's
155 * transmit interrupt threshold so that the chip can acknowledge multiple
156 * lists with only a single TX EOF interrupt. This allows the driver to
157 * queue several frames in one shot, and only have to handle a total
158 * two interrupts (one TX EOF and one TX EOC) no matter how many frames
159 * are transmitted. Frame transmission is done directly out of the
160 * mbufs passed to the tl_start() routine via the interface send queue.
161 * The driver simply sets up the fragment descriptors in the transmit
162 * lists to point to the mbuf data regions and sends a TX GO command.
164 * Note that since the RX and TX lists themselves are always used
165 * only by the driver, the are malloc()ed once at driver initialization
166 * time and never free()ed.
168 * Also, in order to remain as platform independent as possible, this
169 * driver uses memory mapped register access to manipulate the card
170 * as opposed to programmed I/O. This avoids the use of the inb/outb
171 * (and related) instructions which are specific to the i386 platform.
173 * Using these techniques, this driver achieves very high performance
174 * by minimizing the amount of interrupts generated during large
175 * transfers and by completely avoiding buffer copies. Frame transfer
176 * to and from the ThunderLAN chip is performed entirely by the chip
177 * itself thereby reducing the load on the host CPU.
180 #include <sys/param.h>
181 #include <sys/systm.h>
182 #include <sys/sockio.h>
183 #include <sys/mbuf.h>
184 #include <sys/malloc.h>
185 #include <sys/kernel.h>
186 #include <sys/module.h>
187 #include <sys/socket.h>
190 #include <net/if_arp.h>
191 #include <net/ethernet.h>
192 #include <net/if_dl.h>
193 #include <net/if_media.h>
194 #include <net/if_types.h>
198 #include <vm/vm.h> /* for vtophys */
199 #include <vm/pmap.h> /* for vtophys */
200 #include <machine/bus.h>
201 #include <machine/resource.h>
203 #include <sys/rman.h>
205 #include <dev/mii/mii.h>
206 #include <dev/mii/mii_bitbang.h>
207 #include <dev/mii/miivar.h>
209 #include <dev/pci/pcireg.h>
210 #include <dev/pci/pcivar.h>
213 * Default to using PIO register access mode to pacify certain
214 * laptop docking stations with built-in ThunderLAN chips that
215 * don't seem to handle memory mapped mode properly.
217 #define TL_USEIOSPACE
219 #include <dev/tl/if_tlreg.h>
221 MODULE_DEPEND(tl, pci, 1, 1, 1);
222 MODULE_DEPEND(tl, ether, 1, 1, 1);
223 MODULE_DEPEND(tl, miibus, 1, 1, 1);
225 /* "device miibus" required. See GENERIC if you get errors here. */
226 #include "miibus_if.h"
229 * Various supported device vendors/types and their names.
232 static const struct tl_type tl_devs[] = {
233 { TI_VENDORID, TI_DEVICEID_THUNDERLAN,
234 "Texas Instruments ThunderLAN" },
235 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
236 "Compaq Netelligent 10" },
237 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
238 "Compaq Netelligent 10/100" },
239 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
240 "Compaq Netelligent 10/100 Proliant" },
241 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
242 "Compaq Netelligent 10/100 Dual Port" },
243 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
244 "Compaq NetFlex-3/P Integrated" },
245 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
246 "Compaq NetFlex-3/P" },
247 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
248 "Compaq NetFlex 3/P w/ BNC" },
249 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
250 "Compaq Netelligent 10/100 TX Embedded UTP" },
251 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
252 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
253 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
254 "Compaq Netelligent 10/100 TX UTP" },
255 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
256 "Olicom OC-2183/2185" },
257 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
259 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
260 "Olicom OC-2326 10/100 TX UTP" },
264 static int tl_probe(device_t);
265 static int tl_attach(device_t);
266 static int tl_detach(device_t);
267 static int tl_intvec_rxeoc(void *, u_int32_t);
268 static int tl_intvec_txeoc(void *, u_int32_t);
269 static int tl_intvec_txeof(void *, u_int32_t);
270 static int tl_intvec_rxeof(void *, u_int32_t);
271 static int tl_intvec_adchk(void *, u_int32_t);
272 static int tl_intvec_netsts(void *, u_int32_t);
274 static int tl_newbuf(struct tl_softc *, struct tl_chain_onefrag *);
275 static void tl_stats_update(void *);
276 static int tl_encap(struct tl_softc *, struct tl_chain *, struct mbuf *);
278 static void tl_intr(void *);
279 static void tl_start(struct ifnet *);
280 static void tl_start_locked(struct ifnet *);
281 static int tl_ioctl(struct ifnet *, u_long, caddr_t);
282 static void tl_init(void *);
283 static void tl_init_locked(struct tl_softc *);
284 static void tl_stop(struct tl_softc *);
285 static void tl_watchdog(struct tl_softc *);
286 static int tl_shutdown(device_t);
287 static int tl_ifmedia_upd(struct ifnet *);
288 static void tl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
290 static u_int8_t tl_eeprom_putbyte(struct tl_softc *, int);
291 static u_int8_t tl_eeprom_getbyte(struct tl_softc *, int, u_int8_t *);
292 static int tl_read_eeprom(struct tl_softc *, caddr_t, int, int);
294 static int tl_miibus_readreg(device_t, int, int);
295 static int tl_miibus_writereg(device_t, int, int, int);
296 static void tl_miibus_statchg(device_t);
298 static void tl_setmode(struct tl_softc *, int);
299 static uint32_t tl_mchash(const uint8_t *);
300 static void tl_setmulti(struct tl_softc *);
301 static void tl_setfilt(struct tl_softc *, caddr_t, int);
302 static void tl_softreset(struct tl_softc *, int);
303 static void tl_hardreset(device_t);
304 static int tl_list_rx_init(struct tl_softc *);
305 static int tl_list_tx_init(struct tl_softc *);
307 static u_int8_t tl_dio_read8(struct tl_softc *, int);
308 static u_int16_t tl_dio_read16(struct tl_softc *, int);
309 static u_int32_t tl_dio_read32(struct tl_softc *, int);
310 static void tl_dio_write8(struct tl_softc *, int, int);
311 static void tl_dio_write16(struct tl_softc *, int, int);
312 static void tl_dio_write32(struct tl_softc *, int, int);
313 static void tl_dio_setbit(struct tl_softc *, int, int);
314 static void tl_dio_clrbit(struct tl_softc *, int, int);
315 static void tl_dio_setbit16(struct tl_softc *, int, int);
316 static void tl_dio_clrbit16(struct tl_softc *, int, int);
321 static uint32_t tl_mii_bitbang_read(device_t);
322 static void tl_mii_bitbang_write(device_t, uint32_t);
324 static const struct mii_bitbang_ops tl_mii_bitbang_ops = {
326 tl_mii_bitbang_write,
328 TL_SIO_MDATA, /* MII_BIT_MDO */
329 TL_SIO_MDATA, /* MII_BIT_MDI */
330 TL_SIO_MCLK, /* MII_BIT_MDC */
331 TL_SIO_MTXEN, /* MII_BIT_DIR_HOST_PHY */
332 0, /* MII_BIT_DIR_PHY_HOST */
337 #define TL_RES SYS_RES_IOPORT
338 #define TL_RID TL_PCI_LOIO
340 #define TL_RES SYS_RES_MEMORY
341 #define TL_RID TL_PCI_LOMEM
344 static device_method_t tl_methods[] = {
345 /* Device interface */
346 DEVMETHOD(device_probe, tl_probe),
347 DEVMETHOD(device_attach, tl_attach),
348 DEVMETHOD(device_detach, tl_detach),
349 DEVMETHOD(device_shutdown, tl_shutdown),
352 DEVMETHOD(miibus_readreg, tl_miibus_readreg),
353 DEVMETHOD(miibus_writereg, tl_miibus_writereg),
354 DEVMETHOD(miibus_statchg, tl_miibus_statchg),
359 static driver_t tl_driver = {
362 sizeof(struct tl_softc)
365 static devclass_t tl_devclass;
367 DRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0);
368 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0);
370 static u_int8_t tl_dio_read8(sc, reg)
375 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
376 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
377 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
378 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
379 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
380 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
383 static u_int16_t tl_dio_read16(sc, reg)
388 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
389 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
390 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
391 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
392 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
393 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
396 static u_int32_t tl_dio_read32(sc, reg)
401 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
402 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
403 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
404 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
405 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
406 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
409 static void tl_dio_write8(sc, reg, val)
415 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
416 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
417 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
418 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
419 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
420 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
423 static void tl_dio_write16(sc, reg, val)
429 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
430 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
431 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
432 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
433 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
434 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
437 static void tl_dio_write32(sc, reg, val)
443 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
444 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
445 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
446 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
447 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
448 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
452 tl_dio_setbit(sc, reg, bit)
459 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
460 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
461 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
462 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
463 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
464 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
466 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1,
467 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
468 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
472 tl_dio_clrbit(sc, reg, bit)
479 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
480 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
481 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
482 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
483 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
484 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
486 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1,
487 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
488 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
491 static void tl_dio_setbit16(sc, reg, bit)
498 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
499 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
500 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
501 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
502 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
503 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
505 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2,
506 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
507 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
510 static void tl_dio_clrbit16(sc, reg, bit)
517 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
518 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
519 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
520 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
521 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
522 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
524 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2,
525 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
526 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
530 * Send an instruction or address to the EEPROM, check for ACK.
532 static u_int8_t tl_eeprom_putbyte(sc, byte)
536 register int i, ack = 0;
539 * Make sure we're in TX mode.
541 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
544 * Feed in each bit and stobe the clock.
546 for (i = 0x80; i; i >>= 1) {
548 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
550 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
553 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
555 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
561 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
566 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
567 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
568 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
574 * Read a byte of data stored in the EEPROM at address 'addr.'
576 static u_int8_t tl_eeprom_getbyte(sc, addr, dest)
583 device_t tl_dev = sc->tl_dev;
585 tl_dio_write8(sc, TL_NETSIO, 0);
590 * Send write control code to EEPROM.
592 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
593 device_printf(tl_dev, "failed to send write command, status: %x\n",
594 tl_dio_read8(sc, TL_NETSIO));
599 * Send address of byte we want to read.
601 if (tl_eeprom_putbyte(sc, addr)) {
602 device_printf(tl_dev, "failed to send address, status: %x\n",
603 tl_dio_read8(sc, TL_NETSIO));
610 * Send read control code to EEPROM.
612 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
613 device_printf(tl_dev, "failed to send write command, status: %x\n",
614 tl_dio_read8(sc, TL_NETSIO));
619 * Start reading bits from EEPROM.
621 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
622 for (i = 0x80; i; i >>= 1) {
623 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
625 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
627 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
634 * No ACK generated for read, so just return byte.
643 * Read a sequence of bytes from the EEPROM.
646 tl_read_eeprom(sc, dest, off, cnt)
655 for (i = 0; i < cnt; i++) {
656 err = tl_eeprom_getbyte(sc, off + i, &byte);
665 #define TL_SIO_MII (TL_SIO_MCLK | TL_SIO_MDATA | TL_SIO_MTXEN)
668 * Read the MII serial port for the MII bit-bang module.
671 tl_mii_bitbang_read(device_t dev)
676 sc = device_get_softc(dev);
678 val = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MII;
679 CSR_BARRIER(sc, TL_NETSIO, 1,
680 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
686 * Write the MII serial port for the MII bit-bang module.
689 tl_mii_bitbang_write(device_t dev, uint32_t val)
693 sc = device_get_softc(dev);
695 val = (tl_dio_read8(sc, TL_NETSIO) & ~TL_SIO_MII) | val;
696 CSR_BARRIER(sc, TL_NETSIO, 1,
697 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
698 tl_dio_write8(sc, TL_NETSIO, val);
699 CSR_BARRIER(sc, TL_NETSIO, 1,
700 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
704 tl_miibus_readreg(dev, phy, reg)
711 sc = device_get_softc(dev);
714 * Turn off MII interrupt by forcing MINTEN low.
716 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
718 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
721 val = mii_bitbang_readreg(dev, &tl_mii_bitbang_ops, phy, reg);
723 /* Reenable interrupts. */
725 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
732 tl_miibus_writereg(dev, phy, reg, data)
739 sc = device_get_softc(dev);
742 * Turn off MII interrupt by forcing MINTEN low.
744 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
746 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
749 mii_bitbang_writereg(dev, &tl_mii_bitbang_ops, phy, reg, data);
751 /* Reenable interrupts. */
753 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
760 tl_miibus_statchg(dev)
764 struct mii_data *mii;
766 sc = device_get_softc(dev);
767 mii = device_get_softc(sc->tl_miibus);
769 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
770 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
772 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
777 * Set modes for bitrate devices.
780 tl_setmode(sc, media)
784 if (IFM_SUBTYPE(media) == IFM_10_5)
785 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
786 if (IFM_SUBTYPE(media) == IFM_10_T) {
787 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
788 if ((media & IFM_GMASK) == IFM_FDX) {
789 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
790 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
792 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
793 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
799 * Calculate the hash of a MAC address for programming the multicast hash
800 * table. This hash is simply the address split into 6-bit chunks
802 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
803 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
804 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then
805 * the folded 24-bit value is split into 6-bit portions and XOR'd.
813 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
815 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
819 * The ThunderLAN has a perfect MAC address filter in addition to
820 * the multicast hash filter. The perfect filter can be programmed
821 * with up to four MAC addresses. The first one is always used to
822 * hold the station address, which leaves us free to use the other
823 * three for multicast addresses.
826 tl_setfilt(sc, addr, slot)
834 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
836 for (i = 0; i < ETHER_ADDR_LEN; i++)
837 tl_dio_write8(sc, regaddr + i, *(addr + i));
841 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
842 * linked list. This is fine, except addresses are added from the head
843 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
844 * group to always be in the perfect filter, but as more groups are added,
845 * the 224.0.0.1 entry (which is always added first) gets pushed down
846 * the list and ends up at the tail. So after 3 or 4 multicast groups
847 * are added, the all-hosts entry gets pushed out of the perfect filter
848 * and into the hash table.
850 * Because the multicast list is a doubly-linked list as opposed to a
851 * circular queue, we don't have the ability to just grab the tail of
852 * the list and traverse it backwards. Instead, we have to traverse
853 * the list once to find the tail, then traverse it again backwards to
854 * update the multicast filter.
861 u_int32_t hashes[2] = { 0, 0 };
863 struct ifmultiaddr *ifma;
864 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
867 /* First, zot all the existing filters. */
868 for (i = 1; i < 4; i++)
869 tl_setfilt(sc, (caddr_t)&dummy, i);
870 tl_dio_write32(sc, TL_HASH1, 0);
871 tl_dio_write32(sc, TL_HASH2, 0);
873 /* Now program new ones. */
874 if (ifp->if_flags & IFF_ALLMULTI) {
875 hashes[0] = 0xFFFFFFFF;
876 hashes[1] = 0xFFFFFFFF;
880 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
881 if (ifma->ifma_addr->sa_family != AF_LINK)
884 * Program the first three multicast groups
885 * into the perfect filter. For all others,
886 * use the hash table.
890 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
896 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
898 hashes[0] |= (1 << h);
900 hashes[1] |= (1 << (h - 32));
902 if_maddr_runlock(ifp);
905 tl_dio_write32(sc, TL_HASH1, hashes[0]);
906 tl_dio_write32(sc, TL_HASH2, hashes[1]);
910 * This routine is recommended by the ThunderLAN manual to insure that
911 * the internal PHY is powered up correctly. It also recommends a one
912 * second pause at the end to 'wait for the clocks to start' but in my
913 * experience this isn't necessary.
922 mii_bitbang_sync(dev, &tl_mii_bitbang_ops);
924 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
926 for (i = 0; i < MII_NPHY; i++)
927 tl_miibus_writereg(dev, i, MII_BMCR, flags);
929 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
931 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
932 mii_bitbang_sync(dev, &tl_mii_bitbang_ops);
933 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
939 tl_softreset(sc, internal)
943 u_int32_t cmd, dummy, i;
945 /* Assert the adapter reset bit. */
946 CMD_SET(sc, TL_CMD_ADRST);
948 /* Turn off interrupts */
949 CMD_SET(sc, TL_CMD_INTSOFF);
951 /* First, clear the stats registers. */
952 for (i = 0; i < 5; i++)
953 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
955 /* Clear Areg and Hash registers */
956 for (i = 0; i < 8; i++)
957 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
960 * Set up Netconfig register. Enable one channel and
963 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
964 if (internal && !sc->tl_bitrate) {
965 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
967 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
970 /* Handle cards with bitrate devices. */
972 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
975 * Load adapter irq pacing timer and tx threshold.
976 * We make the transmit threshold 1 initially but we may
979 cmd = CSR_READ_4(sc, TL_HOSTCMD);
981 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
982 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
983 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
985 /* Unreset the MII */
986 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
988 /* Take the adapter out of reset */
989 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
991 /* Wait for things to settle down a little. */
996 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
997 * against our list and return its name if we find a match.
1003 const struct tl_type *t;
1007 while(t->tl_name != NULL) {
1008 if ((pci_get_vendor(dev) == t->tl_vid) &&
1009 (pci_get_device(dev) == t->tl_did)) {
1010 device_set_desc(dev, t->tl_name);
1011 return (BUS_PROBE_DEFAULT);
1024 const struct tl_type *t;
1026 struct tl_softc *sc;
1027 int error, flags, i, rid, unit;
1030 vid = pci_get_vendor(dev);
1031 did = pci_get_device(dev);
1032 sc = device_get_softc(dev);
1034 unit = device_get_unit(dev);
1037 while(t->tl_name != NULL) {
1038 if (vid == t->tl_vid && did == t->tl_did)
1043 if (t->tl_name == NULL) {
1044 device_printf(dev, "unknown device!?\n");
1048 mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1052 * Map control/status registers.
1054 pci_enable_busmaster(dev);
1056 #ifdef TL_USEIOSPACE
1059 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1063 * Some cards have the I/O and memory mapped address registers
1064 * reversed. Try both combinations before giving up.
1066 if (sc->tl_res == NULL) {
1068 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1073 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1075 if (sc->tl_res == NULL) {
1077 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1082 if (sc->tl_res == NULL) {
1083 device_printf(dev, "couldn't map ports/memory\n");
1090 * The ThunderLAN manual suggests jacking the PCI latency
1091 * timer all the way up to its maximum value. I'm not sure
1092 * if this is really necessary, but what the manual wants,
1095 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4);
1096 command |= 0x0000FF00;
1097 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4);
1100 /* Allocate interrupt */
1102 sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1103 RF_SHAREABLE | RF_ACTIVE);
1105 if (sc->tl_irq == NULL) {
1106 device_printf(dev, "couldn't map interrupt\n");
1112 * Now allocate memory for the TX and RX lists.
1114 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF,
1115 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1117 if (sc->tl_ldata == NULL) {
1118 device_printf(dev, "no memory for list buffers!\n");
1123 bzero(sc->tl_ldata, sizeof(struct tl_list_data));
1125 if (vid == COMPAQ_VENDORID || vid == TI_VENDORID)
1126 sc->tl_eeaddr = TL_EEPROM_EADDR;
1127 if (vid == OLICOM_VENDORID)
1128 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
1130 /* Reset the adapter. */
1131 tl_softreset(sc, 1);
1133 tl_softreset(sc, 1);
1136 * Get station address from the EEPROM.
1138 if (tl_read_eeprom(sc, eaddr, sc->tl_eeaddr, ETHER_ADDR_LEN)) {
1139 device_printf(dev, "failed to read station address\n");
1145 * XXX Olicom, in its desire to be different from the
1146 * rest of the world, has done strange things with the
1147 * encoding of the station address in the EEPROM. First
1148 * of all, they store the address at offset 0xF8 rather
1149 * than at 0x83 like the ThunderLAN manual suggests.
1150 * Second, they store the address in three 16-bit words in
1151 * network byte order, as opposed to storing it sequentially
1152 * like all the other ThunderLAN cards. In order to get
1153 * the station address in a form that matches what the Olicom
1154 * diagnostic utility specifies, we have to byte-swap each
1155 * word. To make things even more confusing, neither 00:00:28
1156 * nor 00:00:24 appear in the IEEE OUI database.
1158 if (vid == OLICOM_VENDORID) {
1159 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1161 p = (u_int16_t *)&eaddr[i];
1166 ifp = sc->tl_ifp = if_alloc(IFT_ETHER);
1168 device_printf(dev, "can not if_alloc()\n");
1173 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1174 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1175 ifp->if_ioctl = tl_ioctl;
1176 ifp->if_start = tl_start;
1177 ifp->if_init = tl_init;
1178 ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1;
1179 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1180 ifp->if_capenable |= IFCAP_VLAN_MTU;
1181 callout_init_mtx(&sc->tl_stat_callout, &sc->tl_mtx, 0);
1183 /* Reset the adapter again. */
1184 tl_softreset(sc, 1);
1186 tl_softreset(sc, 1);
1189 * Do MII setup. If no PHYs are found, then this is a
1190 * bitrate ThunderLAN chip that only supports 10baseT
1192 * XXX mii_attach() can fail for reason different than
1196 if (vid == COMPAQ_VENDORID) {
1197 if (did == COMPAQ_DEVICEID_NETEL_10_100_PROLIANT ||
1198 did == COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED ||
1199 did == COMPAQ_DEVICEID_NETFLEX_3P_BNC ||
1200 did == COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX)
1201 flags |= MIIF_MACPRIV0;
1202 if (did == COMPAQ_DEVICEID_NETEL_10 ||
1203 did == COMPAQ_DEVICEID_NETEL_10_100_DUAL ||
1204 did == COMPAQ_DEVICEID_NETFLEX_3P ||
1205 did == COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED)
1206 flags |= MIIF_MACPRIV1;
1207 } else if (vid == OLICOM_VENDORID && did == OLICOM_DEVICEID_OC2183)
1208 flags |= MIIF_MACPRIV0 | MIIF_MACPRIV1;
1209 if (mii_attach(dev, &sc->tl_miibus, ifp, tl_ifmedia_upd,
1210 tl_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0)) {
1211 struct ifmedia *ifm;
1213 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1214 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1215 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1216 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1217 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1218 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
1219 /* Reset again, this time setting bitrate mode. */
1220 tl_softreset(sc, 1);
1222 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1223 tl_ifmedia_upd(ifp);
1227 * Call MI attach routine.
1229 ether_ifattach(ifp, eaddr);
1231 /* Hook interrupt last to avoid having to lock softc */
1232 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1233 NULL, tl_intr, sc, &sc->tl_intrhand);
1236 device_printf(dev, "couldn't set up irq\n");
1237 ether_ifdetach(ifp);
1249 * Shutdown hardware and free up resources. This can be called any
1250 * time after the mutex has been initialized. It is called in both
1251 * the error case in attach and the normal detach case so it needs
1252 * to be careful about only freeing resources that have actually been
1259 struct tl_softc *sc;
1262 sc = device_get_softc(dev);
1263 KASSERT(mtx_initialized(&sc->tl_mtx), ("tl mutex not initialized"));
1266 /* These should only be active if attach succeeded */
1267 if (device_is_attached(dev)) {
1268 ether_ifdetach(ifp);
1272 callout_drain(&sc->tl_stat_callout);
1275 device_delete_child(dev, sc->tl_miibus);
1276 bus_generic_detach(dev);
1279 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF);
1281 ifmedia_removeall(&sc->ifmedia);
1283 if (sc->tl_intrhand)
1284 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1286 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1288 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1293 mtx_destroy(&sc->tl_mtx);
1299 * Initialize the transmit lists.
1303 struct tl_softc *sc;
1305 struct tl_chain_data *cd;
1306 struct tl_list_data *ld;
1311 for (i = 0; i < TL_TX_LIST_CNT; i++) {
1312 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
1313 if (i == (TL_TX_LIST_CNT - 1))
1314 cd->tl_tx_chain[i].tl_next = NULL;
1316 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
1319 cd->tl_tx_free = &cd->tl_tx_chain[0];
1320 cd->tl_tx_tail = cd->tl_tx_head = NULL;
1327 * Initialize the RX lists and allocate mbufs for them.
1331 struct tl_softc *sc;
1333 struct tl_chain_data *cd;
1334 struct tl_list_data *ld;
1340 for (i = 0; i < TL_RX_LIST_CNT; i++) {
1341 cd->tl_rx_chain[i].tl_ptr =
1342 (struct tl_list_onefrag *)&ld->tl_rx_list[i];
1343 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
1345 if (i == (TL_RX_LIST_CNT - 1)) {
1346 cd->tl_rx_chain[i].tl_next = NULL;
1347 ld->tl_rx_list[i].tlist_fptr = 0;
1349 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
1350 ld->tl_rx_list[i].tlist_fptr =
1351 vtophys(&ld->tl_rx_list[i + 1]);
1355 cd->tl_rx_head = &cd->tl_rx_chain[0];
1356 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1363 struct tl_softc *sc;
1364 struct tl_chain_onefrag *c;
1366 struct mbuf *m_new = NULL;
1368 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1374 c->tl_ptr->tlist_frsize = MCLBYTES;
1375 c->tl_ptr->tlist_fptr = 0;
1376 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
1377 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1378 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1383 * Interrupt handler for RX 'end of frame' condition (EOF). This
1384 * tells us that a full ethernet frame has been captured and we need
1387 * Reception is done using 'lists' which consist of a header and a
1388 * series of 10 data count/data address pairs that point to buffers.
1389 * Initially you're supposed to create a list, populate it with pointers
1390 * to buffers, then load the physical address of the list into the
1391 * ch_parm register. The adapter is then supposed to DMA the received
1392 * frame into the buffers for you.
1394 * To make things as fast as possible, we have the chip DMA directly
1395 * into mbufs. This saves us from having to do a buffer copy: we can
1396 * just hand the mbufs directly to ether_input(). Once the frame has
1397 * been sent on its way, the 'list' structure is assigned a new buffer
1398 * and moved to the end of the RX chain. As long we we stay ahead of
1399 * the chip, it will always think it has an endless receive channel.
1401 * If we happen to fall behind and the chip manages to fill up all of
1402 * the buffers, it will generate an end of channel interrupt and wait
1403 * for us to empty the chain and restart the receiver.
1406 tl_intvec_rxeof(xsc, type)
1410 struct tl_softc *sc;
1411 int r = 0, total_len = 0;
1412 struct ether_header *eh;
1415 struct tl_chain_onefrag *cur_rx;
1422 while(sc->tl_cdata.tl_rx_head != NULL) {
1423 cur_rx = sc->tl_cdata.tl_rx_head;
1424 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1427 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
1428 m = cur_rx->tl_mbuf;
1429 total_len = cur_rx->tl_ptr->tlist_frsize;
1431 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
1433 cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
1434 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1435 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1439 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
1440 vtophys(cur_rx->tl_ptr);
1441 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
1442 sc->tl_cdata.tl_rx_tail = cur_rx;
1445 * Note: when the ThunderLAN chip is in 'capture all
1446 * frames' mode, it will receive its own transmissions.
1447 * We drop don't need to process our own transmissions,
1448 * so we drop them here and continue.
1450 eh = mtod(m, struct ether_header *);
1451 /*if (ifp->if_flags & IFF_PROMISC && */
1452 if (!bcmp(eh->ether_shost, IF_LLADDR(sc->tl_ifp),
1458 m->m_pkthdr.rcvif = ifp;
1459 m->m_pkthdr.len = m->m_len = total_len;
1462 (*ifp->if_input)(ifp, m);
1470 * The RX-EOC condition hits when the ch_parm address hasn't been
1471 * initialized or the adapter reached a list with a forward pointer
1472 * of 0 (which indicates the end of the chain). In our case, this means
1473 * the card has hit the end of the receive buffer chain and we need to
1474 * empty out the buffers and shift the pointer back to the beginning again.
1477 tl_intvec_rxeoc(xsc, type)
1481 struct tl_softc *sc;
1483 struct tl_chain_data *cd;
1489 /* Flush out the receive queue and ack RXEOF interrupts. */
1490 r = tl_intvec_rxeof(xsc, type);
1491 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
1493 cd->tl_rx_head = &cd->tl_rx_chain[0];
1494 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1495 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
1496 r |= (TL_CMD_GO|TL_CMD_RT);
1501 tl_intvec_txeof(xsc, type)
1505 struct tl_softc *sc;
1507 struct tl_chain *cur_tx;
1512 * Go through our tx list and free mbufs for those
1513 * frames that have been sent.
1515 while (sc->tl_cdata.tl_tx_head != NULL) {
1516 cur_tx = sc->tl_cdata.tl_tx_head;
1517 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1519 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
1522 m_freem(cur_tx->tl_mbuf);
1523 cur_tx->tl_mbuf = NULL;
1525 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
1526 sc->tl_cdata.tl_tx_free = cur_tx;
1527 if (!cur_tx->tl_ptr->tlist_fptr)
1535 * The transmit end of channel interrupt. The adapter triggers this
1536 * interrupt to tell us it hit the end of the current transmit list.
1538 * A note about this: it's possible for a condition to arise where
1539 * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
1540 * You have to avoid this since the chip expects things to go in a
1541 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
1542 * When the TXEOF handler is called, it will free all of the transmitted
1543 * frames and reset the tx_head pointer to NULL. However, a TXEOC
1544 * interrupt should be received and acknowledged before any more frames
1545 * are queued for transmission. If tl_statrt() is called after TXEOF
1546 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
1547 * it could attempt to issue a transmit command prematurely.
1549 * To guard against this, tl_start() will only issue transmit commands
1550 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
1551 * can set this flag once tl_start() has cleared it.
1554 tl_intvec_txeoc(xsc, type)
1558 struct tl_softc *sc;
1565 /* Clear the timeout timer. */
1568 if (sc->tl_cdata.tl_tx_head == NULL) {
1569 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1570 sc->tl_cdata.tl_tx_tail = NULL;
1574 /* First we have to ack the EOC interrupt. */
1575 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
1576 /* Then load the address of the next TX list. */
1577 CSR_WRITE_4(sc, TL_CH_PARM,
1578 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
1579 /* Restart TX channel. */
1580 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1582 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1591 tl_intvec_adchk(xsc, type)
1595 struct tl_softc *sc;
1600 device_printf(sc->tl_dev, "adapter check: %x\n",
1601 (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
1603 tl_softreset(sc, 1);
1606 CMD_SET(sc, TL_CMD_INTSON);
1612 tl_intvec_netsts(xsc, type)
1616 struct tl_softc *sc;
1621 netsts = tl_dio_read16(sc, TL_NETSTS);
1622 tl_dio_write16(sc, TL_NETSTS, netsts);
1624 device_printf(sc->tl_dev, "network status: %x\n", netsts);
1633 struct tl_softc *sc;
1643 /* Disable interrupts */
1644 ints = CSR_READ_2(sc, TL_HOST_INT);
1645 CSR_WRITE_2(sc, TL_HOST_INT, ints);
1646 type = (ints << 16) & 0xFFFF0000;
1647 ivec = (ints & TL_VEC_MASK) >> 5;
1648 ints = (ints & TL_INT_MASK) >> 2;
1653 case (TL_INTR_INVALID):
1655 device_printf(sc->tl_dev, "got an invalid interrupt!\n");
1657 /* Re-enable interrupts but don't ack this one. */
1661 case (TL_INTR_TXEOF):
1662 r = tl_intvec_txeof((void *)sc, type);
1664 case (TL_INTR_TXEOC):
1665 r = tl_intvec_txeoc((void *)sc, type);
1667 case (TL_INTR_STATOFLOW):
1668 tl_stats_update(sc);
1671 case (TL_INTR_RXEOF):
1672 r = tl_intvec_rxeof((void *)sc, type);
1674 case (TL_INTR_DUMMY):
1675 device_printf(sc->tl_dev, "got a dummy interrupt\n");
1678 case (TL_INTR_ADCHK):
1680 r = tl_intvec_adchk((void *)sc, type);
1682 r = tl_intvec_netsts((void *)sc, type);
1684 case (TL_INTR_RXEOC):
1685 r = tl_intvec_rxeoc((void *)sc, type);
1688 device_printf(sc->tl_dev, "bogus interrupt type\n");
1692 /* Re-enable interrupts */
1694 CMD_PUT(sc, TL_CMD_ACK | r | type);
1697 if (ifp->if_snd.ifq_head != NULL)
1698 tl_start_locked(ifp);
1704 tl_stats_update(xsc)
1707 struct tl_softc *sc;
1709 struct tl_stats tl_stats;
1710 struct mii_data *mii;
1713 bzero((char *)&tl_stats, sizeof(struct tl_stats));
1719 p = (u_int32_t *)&tl_stats;
1721 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
1722 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1723 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1724 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1725 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1726 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1728 ifp->if_opackets += tl_tx_goodframes(tl_stats);
1729 ifp->if_collisions += tl_stats.tl_tx_single_collision +
1730 tl_stats.tl_tx_multi_collision;
1731 ifp->if_ipackets += tl_rx_goodframes(tl_stats);
1732 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
1733 tl_rx_overrun(tl_stats);
1734 ifp->if_oerrors += tl_tx_underrun(tl_stats);
1736 if (tl_tx_underrun(tl_stats)) {
1738 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH;
1739 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) {
1742 device_printf(sc->tl_dev, "tx underrun -- increasing "
1743 "tx threshold to %d bytes\n",
1744 (64 * (tx_thresh * 4)));
1745 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1746 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4);
1750 if (sc->tl_timer > 0 && --sc->tl_timer == 0)
1753 callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc);
1755 if (!sc->tl_bitrate) {
1756 mii = device_get_softc(sc->tl_miibus);
1762 * Encapsulate an mbuf chain in a list by coupling the mbuf data
1763 * pointers to the fragment pointers.
1766 tl_encap(sc, c, m_head)
1767 struct tl_softc *sc;
1769 struct mbuf *m_head;
1772 struct tl_frag *f = NULL;
1775 struct ifnet *ifp = sc->tl_ifp;
1778 * Start packing the mbufs in this chain into
1779 * the fragment pointers. Stop when we run out
1780 * of fragments or hit the end of the mbuf chain.
1785 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1786 if (m->m_len != 0) {
1787 if (frag == TL_MAXFRAGS)
1789 total_len+= m->m_len;
1790 c->tl_ptr->tl_frag[frag].tlist_dadr =
1791 vtophys(mtod(m, vm_offset_t));
1792 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
1798 * Handle special cases.
1799 * Special case #1: we used up all 10 fragments, but
1800 * we have more mbufs left in the chain. Copy the
1801 * data into an mbuf cluster. Note that we don't
1802 * bother clearing the values in the other fragment
1803 * pointers/counters; it wouldn't gain us anything,
1804 * and would waste cycles.
1807 struct mbuf *m_new = NULL;
1809 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1810 if (m_new == NULL) {
1811 if_printf(ifp, "no memory for tx list\n");
1814 if (m_head->m_pkthdr.len > MHLEN) {
1815 MCLGET(m_new, M_NOWAIT);
1816 if (!(m_new->m_flags & M_EXT)) {
1818 if_printf(ifp, "no memory for tx list\n");
1822 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1823 mtod(m_new, caddr_t));
1824 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1827 f = &c->tl_ptr->tl_frag[0];
1828 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
1829 f->tlist_dcnt = total_len = m_new->m_len;
1834 * Special case #2: the frame is smaller than the minimum
1835 * frame size. We have to pad it to make the chip happy.
1837 if (total_len < TL_MIN_FRAMELEN) {
1838 if (frag == TL_MAXFRAGS)
1840 "all frags filled but frame still to small!\n");
1841 f = &c->tl_ptr->tl_frag[frag];
1842 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
1843 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
1844 total_len += f->tlist_dcnt;
1848 c->tl_mbuf = m_head;
1849 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
1850 c->tl_ptr->tlist_frsize = total_len;
1851 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1852 c->tl_ptr->tlist_fptr = 0;
1858 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1859 * to the mbuf data regions directly in the transmit lists. We also save a
1860 * copy of the pointers since the transmit list fragment pointers are
1861 * physical addresses.
1867 struct tl_softc *sc;
1871 tl_start_locked(ifp);
1876 tl_start_locked(ifp)
1879 struct tl_softc *sc;
1880 struct mbuf *m_head = NULL;
1882 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
1888 * Check for an available queue slot. If there are none,
1891 if (sc->tl_cdata.tl_tx_free == NULL) {
1892 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1896 start_tx = sc->tl_cdata.tl_tx_free;
1898 while(sc->tl_cdata.tl_tx_free != NULL) {
1899 IF_DEQUEUE(&ifp->if_snd, m_head);
1903 /* Pick a chain member off the free list. */
1904 cur_tx = sc->tl_cdata.tl_tx_free;
1905 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
1907 cur_tx->tl_next = NULL;
1909 /* Pack the data into the list. */
1910 tl_encap(sc, cur_tx, m_head);
1912 /* Chain it together */
1914 prev->tl_next = cur_tx;
1915 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
1920 * If there's a BPF listener, bounce a copy of this frame
1923 BPF_MTAP(ifp, cur_tx->tl_mbuf);
1927 * If there are no packets queued, bail.
1933 * That's all we can stands, we can't stands no more.
1934 * If there are no other transfers pending, then issue the
1935 * TX GO command to the adapter to start things moving.
1936 * Otherwise, just leave the data in the queue and let
1937 * the EOF/EOC interrupt handler send.
1939 if (sc->tl_cdata.tl_tx_head == NULL) {
1940 sc->tl_cdata.tl_tx_head = start_tx;
1941 sc->tl_cdata.tl_tx_tail = cur_tx;
1945 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
1946 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1948 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1952 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
1953 sc->tl_cdata.tl_tx_tail = cur_tx;
1957 * Set a timeout in case the chip goes out to lunch.
1966 struct tl_softc *sc = xsc;
1975 struct tl_softc *sc;
1977 struct ifnet *ifp = sc->tl_ifp;
1978 struct mii_data *mii;
1985 * Cancel pending I/O.
1989 /* Initialize TX FIFO threshold */
1990 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1991 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG);
1993 /* Set PCI burst size */
1994 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG);
1997 * Set 'capture all frames' bit for promiscuous mode.
1999 if (ifp->if_flags & IFF_PROMISC)
2000 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2002 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2005 * Set capture broadcast bit to capture broadcast frames.
2007 if (ifp->if_flags & IFF_BROADCAST)
2008 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2010 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2012 tl_dio_write16(sc, TL_MAXRX, MCLBYTES);
2014 /* Init our MAC address */
2015 tl_setfilt(sc, IF_LLADDR(sc->tl_ifp), 0);
2017 /* Init multicast filter, if needed. */
2020 /* Init circular RX list. */
2021 if (tl_list_rx_init(sc) == ENOBUFS) {
2022 device_printf(sc->tl_dev,
2023 "initialization failed: no memory for rx buffers\n");
2028 /* Init TX pointers. */
2029 tl_list_tx_init(sc);
2031 /* Enable PCI interrupts. */
2032 CMD_SET(sc, TL_CMD_INTSON);
2034 /* Load the address of the rx list */
2035 CMD_SET(sc, TL_CMD_RT);
2036 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
2038 if (!sc->tl_bitrate) {
2039 if (sc->tl_miibus != NULL) {
2040 mii = device_get_softc(sc->tl_miibus);
2044 tl_ifmedia_upd(ifp);
2047 /* Send the RX go command */
2048 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
2050 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2051 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2053 /* Start the stats update counter */
2054 callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc);
2058 * Set media options.
2064 struct tl_softc *sc;
2065 struct mii_data *mii = NULL;
2071 tl_setmode(sc, sc->ifmedia.ifm_media);
2073 mii = device_get_softc(sc->tl_miibus);
2082 * Report current media status.
2085 tl_ifmedia_sts(ifp, ifmr)
2087 struct ifmediareq *ifmr;
2089 struct tl_softc *sc;
2090 struct mii_data *mii;
2095 ifmr->ifm_active = IFM_ETHER;
2097 if (sc->tl_bitrate) {
2098 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
2099 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2101 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2102 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
2103 ifmr->ifm_active |= IFM_HDX;
2105 ifmr->ifm_active |= IFM_FDX;
2108 mii = device_get_softc(sc->tl_miibus);
2110 ifmr->ifm_active = mii->mii_media_active;
2111 ifmr->ifm_status = mii->mii_media_status;
2117 tl_ioctl(ifp, command, data)
2122 struct tl_softc *sc = ifp->if_softc;
2123 struct ifreq *ifr = (struct ifreq *) data;
2129 if (ifp->if_flags & IFF_UP) {
2130 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2131 ifp->if_flags & IFF_PROMISC &&
2132 !(sc->tl_if_flags & IFF_PROMISC)) {
2133 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2135 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2136 !(ifp->if_flags & IFF_PROMISC) &&
2137 sc->tl_if_flags & IFF_PROMISC) {
2138 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2143 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2147 sc->tl_if_flags = ifp->if_flags;
2161 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2163 struct mii_data *mii;
2164 mii = device_get_softc(sc->tl_miibus);
2165 error = ifmedia_ioctl(ifp, ifr,
2166 &mii->mii_media, command);
2170 error = ether_ioctl(ifp, command, data);
2179 struct tl_softc *sc;
2186 if_printf(ifp, "device timeout\n");
2190 tl_softreset(sc, 1);
2195 * Stop the adapter and free any mbufs allocated to the
2200 struct tl_softc *sc;
2209 /* Stop the stats updater. */
2210 callout_stop(&sc->tl_stat_callout);
2212 /* Stop the transmitter */
2213 CMD_CLR(sc, TL_CMD_RT);
2214 CMD_SET(sc, TL_CMD_STOP);
2215 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2217 /* Stop the receiver */
2218 CMD_SET(sc, TL_CMD_RT);
2219 CMD_SET(sc, TL_CMD_STOP);
2220 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2223 * Disable host interrupts.
2225 CMD_SET(sc, TL_CMD_INTSOFF);
2228 * Clear list pointer.
2230 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2233 * Free the RX lists.
2235 for (i = 0; i < TL_RX_LIST_CNT; i++) {
2236 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
2237 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
2238 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
2241 bzero((char *)&sc->tl_ldata->tl_rx_list,
2242 sizeof(sc->tl_ldata->tl_rx_list));
2245 * Free the TX list buffers.
2247 for (i = 0; i < TL_TX_LIST_CNT; i++) {
2248 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
2249 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2250 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2253 bzero((char *)&sc->tl_ldata->tl_tx_list,
2254 sizeof(sc->tl_ldata->tl_tx_list));
2256 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2260 * Stop all chip I/O so that the kernel's probe routines don't
2261 * get confused by errant DMAs when rebooting.
2267 struct tl_softc *sc;
2269 sc = device_get_softc(dev);