2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
38 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
39 * the National Semiconductor DP83840A physical interface and the
40 * Microchip Technology 24Cxx series serial EEPROM.
42 * Written using the following four documents:
44 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
45 * National Semiconductor DP83840A data sheet (www.national.com)
46 * Microchip Technology 24C02C data sheet (www.microchip.com)
47 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
49 * Written by Bill Paul <wpaul@ctr.columbia.edu>
50 * Electrical Engineering Department
51 * Columbia University, New York City
54 * Some notes about the ThunderLAN:
56 * The ThunderLAN controller is a single chip containing PCI controller
57 * logic, approximately 3K of on-board SRAM, a LAN controller, and media
58 * independent interface (MII) bus. The MII allows the ThunderLAN chip to
59 * control up to 32 different physical interfaces (PHYs). The ThunderLAN
60 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
61 * to act as a complete ethernet interface.
63 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
64 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
65 * in full or half duplex. Some of the Compaq Deskpro machines use a
66 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
67 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
68 * concert with the ThunderLAN's internal PHY to provide full 10/100
69 * support. This is cheaper than using a standalone external PHY for both
70 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
71 * A serial EEPROM is also attached to the ThunderLAN chip to provide
72 * power-up default register settings and for storing the adapter's
73 * station address. Although not supported by this driver, the ThunderLAN
74 * chip can also be connected to token ring PHYs.
76 * The ThunderLAN has a set of registers which can be used to issue
77 * commands, acknowledge interrupts, and to manipulate other internal
78 * registers on its DIO bus. The primary registers can be accessed
79 * using either programmed I/O (inb/outb) or via PCI memory mapping,
80 * depending on how the card is configured during the PCI probing
81 * phase. It is even possible to have both PIO and memory mapped
82 * access turned on at the same time.
84 * Frame reception and transmission with the ThunderLAN chip is done
85 * using frame 'lists.' A list structure looks more or less like this:
88 * u_int32_t fragment_address;
89 * u_int32_t fragment_size;
92 * u_int32_t forward_pointer;
94 * u_int16_t frame_size;
95 * struct tl_frag fragments[10];
98 * The forward pointer in the list header can be either a 0 or the address
99 * of another list, which allows several lists to be linked together. Each
100 * list contains up to 10 fragment descriptors. This means the chip allows
101 * ethernet frames to be broken up into up to 10 chunks for transfer to
102 * and from the SRAM. Note that the forward pointer and fragment buffer
103 * addresses are physical memory addresses, not virtual. Note also that
104 * a single ethernet frame can not span lists: if the host wants to
105 * transmit a frame and the frame data is split up over more than 10
106 * buffers, the frame has to collapsed before it can be transmitted.
108 * To receive frames, the driver sets up a number of lists and populates
109 * the fragment descriptors, then it sends an RX GO command to the chip.
110 * When a frame is received, the chip will DMA it into the memory regions
111 * specified by the fragment descriptors and then trigger an RX 'end of
112 * frame interrupt' when done. The driver may choose to use only one
113 * fragment per list; this may result is slighltly less efficient use
114 * of memory in exchange for improving performance.
116 * To transmit frames, the driver again sets up lists and fragment
117 * descriptors, only this time the buffers contain frame data that
118 * is to be DMA'ed into the chip instead of out of it. Once the chip
119 * has transfered the data into its on-board SRAM, it will trigger a
120 * TX 'end of frame' interrupt. It will also generate an 'end of channel'
121 * interrupt when it reaches the end of the list.
124 * Some notes about this driver:
126 * The ThunderLAN chip provides a couple of different ways to organize
127 * reception, transmission and interrupt handling. The simplest approach
128 * is to use one list each for transmission and reception. In this mode,
129 * the ThunderLAN will generate two interrupts for every received frame
130 * (one RX EOF and one RX EOC) and two for each transmitted frame (one
131 * TX EOF and one TX EOC). This may make the driver simpler but it hurts
132 * performance to have to handle so many interrupts.
134 * Initially I wanted to create a circular list of receive buffers so
135 * that the ThunderLAN chip would think there was an infinitely long
136 * receive channel and never deliver an RXEOC interrupt. However this
137 * doesn't work correctly under heavy load: while the manual says the
138 * chip will trigger an RXEOF interrupt each time a frame is copied into
139 * memory, you can't count on the chip waiting around for you to acknowledge
140 * the interrupt before it starts trying to DMA the next frame. The result
141 * is that the chip might traverse the entire circular list and then wrap
142 * around before you have a chance to do anything about it. Consequently,
143 * the receive list is terminated (with a 0 in the forward pointer in the
144 * last element). Each time an RXEOF interrupt arrives, the used list
145 * is shifted to the end of the list. This gives the appearance of an
146 * infinitely large RX chain so long as the driver doesn't fall behind
147 * the chip and allow all of the lists to be filled up.
149 * If all the lists are filled, the adapter will deliver an RX 'end of
150 * channel' interrupt when it hits the 0 forward pointer at the end of
151 * the chain. The RXEOC handler then cleans out the RX chain and resets
152 * the list head pointer in the ch_parm register and restarts the receiver.
154 * For frame transmission, it is possible to program the ThunderLAN's
155 * transmit interrupt threshold so that the chip can acknowledge multiple
156 * lists with only a single TX EOF interrupt. This allows the driver to
157 * queue several frames in one shot, and only have to handle a total
158 * two interrupts (one TX EOF and one TX EOC) no matter how many frames
159 * are transmitted. Frame transmission is done directly out of the
160 * mbufs passed to the tl_start() routine via the interface send queue.
161 * The driver simply sets up the fragment descriptors in the transmit
162 * lists to point to the mbuf data regions and sends a TX GO command.
164 * Note that since the RX and TX lists themselves are always used
165 * only by the driver, the are malloc()ed once at driver initialization
166 * time and never free()ed.
168 * Also, in order to remain as platform independent as possible, this
169 * driver uses memory mapped register access to manipulate the card
170 * as opposed to programmed I/O. This avoids the use of the inb/outb
171 * (and related) instructions which are specific to the i386 platform.
173 * Using these techniques, this driver achieves very high performance
174 * by minimizing the amount of interrupts generated during large
175 * transfers and by completely avoiding buffer copies. Frame transfer
176 * to and from the ThunderLAN chip is performed entirely by the chip
177 * itself thereby reducing the load on the host CPU.
180 #include <sys/param.h>
181 #include <sys/systm.h>
182 #include <sys/sockio.h>
183 #include <sys/mbuf.h>
184 #include <sys/malloc.h>
185 #include <sys/kernel.h>
186 #include <sys/module.h>
187 #include <sys/socket.h>
190 #include <net/if_arp.h>
191 #include <net/ethernet.h>
192 #include <net/if_dl.h>
193 #include <net/if_media.h>
194 #include <net/if_types.h>
198 #include <vm/vm.h> /* for vtophys */
199 #include <vm/pmap.h> /* for vtophys */
200 #include <machine/bus.h>
201 #include <machine/resource.h>
203 #include <sys/rman.h>
205 #include <dev/mii/mii.h>
206 #include <dev/mii/miivar.h>
208 #include <dev/pci/pcireg.h>
209 #include <dev/pci/pcivar.h>
212 * Default to using PIO register access mode to pacify certain
213 * laptop docking stations with built-in ThunderLAN chips that
214 * don't seem to handle memory mapped mode properly.
216 #define TL_USEIOSPACE
218 #include <dev/tl/if_tlreg.h>
220 MODULE_DEPEND(tl, pci, 1, 1, 1);
221 MODULE_DEPEND(tl, ether, 1, 1, 1);
222 MODULE_DEPEND(tl, miibus, 1, 1, 1);
224 /* "device miibus" required. See GENERIC if you get errors here. */
225 #include "miibus_if.h"
228 * Various supported device vendors/types and their names.
231 static struct tl_type tl_devs[] = {
232 { TI_VENDORID, TI_DEVICEID_THUNDERLAN,
233 "Texas Instruments ThunderLAN" },
234 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
235 "Compaq Netelligent 10" },
236 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
237 "Compaq Netelligent 10/100" },
238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
239 "Compaq Netelligent 10/100 Proliant" },
240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
241 "Compaq Netelligent 10/100 Dual Port" },
242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
243 "Compaq NetFlex-3/P Integrated" },
244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
245 "Compaq NetFlex-3/P" },
246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
247 "Compaq NetFlex 3/P w/ BNC" },
248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
249 "Compaq Netelligent 10/100 TX Embedded UTP" },
250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
251 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
252 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
253 "Compaq Netelligent 10/100 TX UTP" },
254 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
255 "Olicom OC-2183/2185" },
256 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
258 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
259 "Olicom OC-2326 10/100 TX UTP" },
263 static int tl_probe(device_t);
264 static int tl_attach(device_t);
265 static int tl_detach(device_t);
266 static int tl_intvec_rxeoc(void *, u_int32_t);
267 static int tl_intvec_txeoc(void *, u_int32_t);
268 static int tl_intvec_txeof(void *, u_int32_t);
269 static int tl_intvec_rxeof(void *, u_int32_t);
270 static int tl_intvec_adchk(void *, u_int32_t);
271 static int tl_intvec_netsts(void *, u_int32_t);
273 static int tl_newbuf(struct tl_softc *, struct tl_chain_onefrag *);
274 static void tl_stats_update(void *);
275 static int tl_encap(struct tl_softc *, struct tl_chain *, struct mbuf *);
277 static void tl_intr(void *);
278 static void tl_start(struct ifnet *);
279 static void tl_start_locked(struct ifnet *);
280 static int tl_ioctl(struct ifnet *, u_long, caddr_t);
281 static void tl_init(void *);
282 static void tl_init_locked(struct tl_softc *);
283 static void tl_stop(struct tl_softc *);
284 static void tl_watchdog(struct tl_softc *);
285 static int tl_shutdown(device_t);
286 static int tl_ifmedia_upd(struct ifnet *);
287 static void tl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
289 static u_int8_t tl_eeprom_putbyte(struct tl_softc *, int);
290 static u_int8_t tl_eeprom_getbyte(struct tl_softc *, int, u_int8_t *);
291 static int tl_read_eeprom(struct tl_softc *, caddr_t, int, int);
293 static void tl_mii_sync(struct tl_softc *);
294 static void tl_mii_send(struct tl_softc *, u_int32_t, int);
295 static int tl_mii_readreg(struct tl_softc *, struct tl_mii_frame *);
296 static int tl_mii_writereg(struct tl_softc *, struct tl_mii_frame *);
297 static int tl_miibus_readreg(device_t, int, int);
298 static int tl_miibus_writereg(device_t, int, int, int);
299 static void tl_miibus_statchg(device_t);
301 static void tl_setmode(struct tl_softc *, int);
302 static uint32_t tl_mchash(const uint8_t *);
303 static void tl_setmulti(struct tl_softc *);
304 static void tl_setfilt(struct tl_softc *, caddr_t, int);
305 static void tl_softreset(struct tl_softc *, int);
306 static void tl_hardreset(device_t);
307 static int tl_list_rx_init(struct tl_softc *);
308 static int tl_list_tx_init(struct tl_softc *);
310 static u_int8_t tl_dio_read8(struct tl_softc *, int);
311 static u_int16_t tl_dio_read16(struct tl_softc *, int);
312 static u_int32_t tl_dio_read32(struct tl_softc *, int);
313 static void tl_dio_write8(struct tl_softc *, int, int);
314 static void tl_dio_write16(struct tl_softc *, int, int);
315 static void tl_dio_write32(struct tl_softc *, int, int);
316 static void tl_dio_setbit(struct tl_softc *, int, int);
317 static void tl_dio_clrbit(struct tl_softc *, int, int);
318 static void tl_dio_setbit16(struct tl_softc *, int, int);
319 static void tl_dio_clrbit16(struct tl_softc *, int, int);
322 #define TL_RES SYS_RES_IOPORT
323 #define TL_RID TL_PCI_LOIO
325 #define TL_RES SYS_RES_MEMORY
326 #define TL_RID TL_PCI_LOMEM
329 static device_method_t tl_methods[] = {
330 /* Device interface */
331 DEVMETHOD(device_probe, tl_probe),
332 DEVMETHOD(device_attach, tl_attach),
333 DEVMETHOD(device_detach, tl_detach),
334 DEVMETHOD(device_shutdown, tl_shutdown),
337 DEVMETHOD(bus_print_child, bus_generic_print_child),
338 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
341 DEVMETHOD(miibus_readreg, tl_miibus_readreg),
342 DEVMETHOD(miibus_writereg, tl_miibus_writereg),
343 DEVMETHOD(miibus_statchg, tl_miibus_statchg),
348 static driver_t tl_driver = {
351 sizeof(struct tl_softc)
354 static devclass_t tl_devclass;
356 DRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0);
357 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0);
359 static u_int8_t tl_dio_read8(sc, reg)
363 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
364 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
367 static u_int16_t tl_dio_read16(sc, reg)
371 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
372 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
375 static u_int32_t tl_dio_read32(sc, reg)
379 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
380 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
383 static void tl_dio_write8(sc, reg, val)
388 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
389 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
393 static void tl_dio_write16(sc, reg, val)
398 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
399 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
403 static void tl_dio_write32(sc, reg, val)
408 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
409 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
414 tl_dio_setbit(sc, reg, bit)
421 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
422 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
424 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
430 tl_dio_clrbit(sc, reg, bit)
437 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
438 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
440 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
445 static void tl_dio_setbit16(sc, reg, bit)
452 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
453 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
455 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
460 static void tl_dio_clrbit16(sc, reg, bit)
467 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
468 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
470 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
476 * Send an instruction or address to the EEPROM, check for ACK.
478 static u_int8_t tl_eeprom_putbyte(sc, byte)
482 register int i, ack = 0;
485 * Make sure we're in TX mode.
487 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
490 * Feed in each bit and stobe the clock.
492 for (i = 0x80; i; i >>= 1) {
494 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
496 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
499 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
501 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
507 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
512 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
513 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
514 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
520 * Read a byte of data stored in the EEPROM at address 'addr.'
522 static u_int8_t tl_eeprom_getbyte(sc, addr, dest)
529 device_t tl_dev = sc->tl_dev;
531 tl_dio_write8(sc, TL_NETSIO, 0);
536 * Send write control code to EEPROM.
538 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
539 device_printf(tl_dev, "failed to send write command, status: %x\n",
540 tl_dio_read8(sc, TL_NETSIO));
545 * Send address of byte we want to read.
547 if (tl_eeprom_putbyte(sc, addr)) {
548 device_printf(tl_dev, "failed to send address, status: %x\n",
549 tl_dio_read8(sc, TL_NETSIO));
556 * Send read control code to EEPROM.
558 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
559 device_printf(tl_dev, "failed to send write command, status: %x\n",
560 tl_dio_read8(sc, TL_NETSIO));
565 * Start reading bits from EEPROM.
567 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
568 for (i = 0x80; i; i >>= 1) {
569 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
571 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
573 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
580 * No ACK generated for read, so just return byte.
589 * Read a sequence of bytes from the EEPROM.
592 tl_read_eeprom(sc, dest, off, cnt)
601 for (i = 0; i < cnt; i++) {
602 err = tl_eeprom_getbyte(sc, off + i, &byte);
617 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
619 for (i = 0; i < 32; i++) {
620 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
621 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
628 tl_mii_send(sc, bits, cnt)
635 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
636 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
638 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
640 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
642 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
647 tl_mii_readreg(sc, frame)
649 struct tl_mii_frame *frame;
658 * Set up frame for RX.
660 frame->mii_stdelim = TL_MII_STARTDELIM;
661 frame->mii_opcode = TL_MII_READOP;
662 frame->mii_turnaround = 0;
666 * Turn off MII interrupt by forcing MINTEN low.
668 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
670 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
676 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
679 * Send command/address info.
681 tl_mii_send(sc, frame->mii_stdelim, 2);
682 tl_mii_send(sc, frame->mii_opcode, 2);
683 tl_mii_send(sc, frame->mii_phyaddr, 5);
684 tl_mii_send(sc, frame->mii_regaddr, 5);
689 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
692 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
693 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
696 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
697 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
699 /* Complete the cycle */
700 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
703 * Now try reading data bits. If the ack failed, we still
704 * need to clock through 16 cycles to keep the PHYs in sync.
707 for(i = 0; i < 16; i++) {
708 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
709 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
714 for (i = 0x8000; i; i >>= 1) {
715 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
717 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
718 frame->mii_data |= i;
720 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
725 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
726 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
728 /* Reenable interrupts */
730 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
739 tl_mii_writereg(sc, frame)
741 struct tl_mii_frame *frame;
749 * Set up frame for TX.
752 frame->mii_stdelim = TL_MII_STARTDELIM;
753 frame->mii_opcode = TL_MII_WRITEOP;
754 frame->mii_turnaround = TL_MII_TURNAROUND;
757 * Turn off MII interrupt by forcing MINTEN low.
759 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
761 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
765 * Turn on data output.
767 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
769 tl_mii_send(sc, frame->mii_stdelim, 2);
770 tl_mii_send(sc, frame->mii_opcode, 2);
771 tl_mii_send(sc, frame->mii_phyaddr, 5);
772 tl_mii_send(sc, frame->mii_regaddr, 5);
773 tl_mii_send(sc, frame->mii_turnaround, 2);
774 tl_mii_send(sc, frame->mii_data, 16);
776 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
777 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
782 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
784 /* Reenable interrupts */
786 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
792 tl_miibus_readreg(dev, phy, reg)
797 struct tl_mii_frame frame;
799 sc = device_get_softc(dev);
800 bzero((char *)&frame, sizeof(frame));
802 frame.mii_phyaddr = phy;
803 frame.mii_regaddr = reg;
804 tl_mii_readreg(sc, &frame);
806 return(frame.mii_data);
810 tl_miibus_writereg(dev, phy, reg, data)
815 struct tl_mii_frame frame;
817 sc = device_get_softc(dev);
818 bzero((char *)&frame, sizeof(frame));
820 frame.mii_phyaddr = phy;
821 frame.mii_regaddr = reg;
822 frame.mii_data = data;
824 tl_mii_writereg(sc, &frame);
830 tl_miibus_statchg(dev)
834 struct mii_data *mii;
836 sc = device_get_softc(dev);
837 mii = device_get_softc(sc->tl_miibus);
839 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
840 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
842 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
849 * Set modes for bitrate devices.
852 tl_setmode(sc, media)
856 if (IFM_SUBTYPE(media) == IFM_10_5)
857 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
858 if (IFM_SUBTYPE(media) == IFM_10_T) {
859 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
860 if ((media & IFM_GMASK) == IFM_FDX) {
861 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
862 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
864 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
865 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
873 * Calculate the hash of a MAC address for programming the multicast hash
874 * table. This hash is simply the address split into 6-bit chunks
876 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
877 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
878 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then
879 * the folded 24-bit value is split into 6-bit portions and XOR'd.
887 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
889 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
893 * The ThunderLAN has a perfect MAC address filter in addition to
894 * the multicast hash filter. The perfect filter can be programmed
895 * with up to four MAC addresses. The first one is always used to
896 * hold the station address, which leaves us free to use the other
897 * three for multicast addresses.
900 tl_setfilt(sc, addr, slot)
908 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
910 for (i = 0; i < ETHER_ADDR_LEN; i++)
911 tl_dio_write8(sc, regaddr + i, *(addr + i));
917 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
918 * linked list. This is fine, except addresses are added from the head
919 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
920 * group to always be in the perfect filter, but as more groups are added,
921 * the 224.0.0.1 entry (which is always added first) gets pushed down
922 * the list and ends up at the tail. So after 3 or 4 multicast groups
923 * are added, the all-hosts entry gets pushed out of the perfect filter
924 * and into the hash table.
926 * Because the multicast list is a doubly-linked list as opposed to a
927 * circular queue, we don't have the ability to just grab the tail of
928 * the list and traverse it backwards. Instead, we have to traverse
929 * the list once to find the tail, then traverse it again backwards to
930 * update the multicast filter.
937 u_int32_t hashes[2] = { 0, 0 };
939 struct ifmultiaddr *ifma;
940 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
943 /* First, zot all the existing filters. */
944 for (i = 1; i < 4; i++)
945 tl_setfilt(sc, (caddr_t)&dummy, i);
946 tl_dio_write32(sc, TL_HASH1, 0);
947 tl_dio_write32(sc, TL_HASH2, 0);
949 /* Now program new ones. */
950 if (ifp->if_flags & IFF_ALLMULTI) {
951 hashes[0] = 0xFFFFFFFF;
952 hashes[1] = 0xFFFFFFFF;
956 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
957 if (ifma->ifma_addr->sa_family != AF_LINK)
960 * Program the first three multicast groups
961 * into the perfect filter. For all others,
962 * use the hash table.
966 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
972 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
974 hashes[0] |= (1 << h);
976 hashes[1] |= (1 << (h - 32));
978 if_maddr_runlock(ifp);
981 tl_dio_write32(sc, TL_HASH1, hashes[0]);
982 tl_dio_write32(sc, TL_HASH2, hashes[1]);
988 * This routine is recommended by the ThunderLAN manual to insure that
989 * the internal PHY is powered up correctly. It also recommends a one
990 * second pause at the end to 'wait for the clocks to start' but in my
991 * experience this isn't necessary.
1001 sc = device_get_softc(dev);
1005 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
1007 for (i = 0; i < MII_NPHY; i++)
1008 tl_miibus_writereg(dev, i, MII_BMCR, flags);
1010 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
1012 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
1014 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
1021 tl_softreset(sc, internal)
1022 struct tl_softc *sc;
1025 u_int32_t cmd, dummy, i;
1027 /* Assert the adapter reset bit. */
1028 CMD_SET(sc, TL_CMD_ADRST);
1030 /* Turn off interrupts */
1031 CMD_SET(sc, TL_CMD_INTSOFF);
1033 /* First, clear the stats registers. */
1034 for (i = 0; i < 5; i++)
1035 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
1037 /* Clear Areg and Hash registers */
1038 for (i = 0; i < 8; i++)
1039 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
1042 * Set up Netconfig register. Enable one channel and
1043 * one fragment mode.
1045 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
1046 if (internal && !sc->tl_bitrate) {
1047 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1049 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1052 /* Handle cards with bitrate devices. */
1054 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
1057 * Load adapter irq pacing timer and tx threshold.
1058 * We make the transmit threshold 1 initially but we may
1059 * change that later.
1061 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1063 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
1064 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
1065 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
1067 /* Unreset the MII */
1068 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
1070 /* Take the adapter out of reset */
1071 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
1073 /* Wait for things to settle down a little. */
1080 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
1081 * against our list and return its name if we find a match.
1091 while(t->tl_name != NULL) {
1092 if ((pci_get_vendor(dev) == t->tl_vid) &&
1093 (pci_get_device(dev) == t->tl_did)) {
1094 device_set_desc(dev, t->tl_name);
1095 return (BUS_PROBE_DEFAULT);
1110 struct tl_softc *sc;
1111 int error, flags, i, rid, unit;
1114 vid = pci_get_vendor(dev);
1115 did = pci_get_device(dev);
1116 sc = device_get_softc(dev);
1118 unit = device_get_unit(dev);
1121 while(t->tl_name != NULL) {
1122 if (vid == t->tl_vid && did == t->tl_did)
1127 if (t->tl_name == NULL) {
1128 device_printf(dev, "unknown device!?\n");
1132 mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1136 * Map control/status registers.
1138 pci_enable_busmaster(dev);
1140 #ifdef TL_USEIOSPACE
1143 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1147 * Some cards have the I/O and memory mapped address registers
1148 * reversed. Try both combinations before giving up.
1150 if (sc->tl_res == NULL) {
1152 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1157 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1159 if (sc->tl_res == NULL) {
1161 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1166 if (sc->tl_res == NULL) {
1167 device_printf(dev, "couldn't map ports/memory\n");
1174 * The ThunderLAN manual suggests jacking the PCI latency
1175 * timer all the way up to its maximum value. I'm not sure
1176 * if this is really necessary, but what the manual wants,
1179 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4);
1180 command |= 0x0000FF00;
1181 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4);
1184 /* Allocate interrupt */
1186 sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1187 RF_SHAREABLE | RF_ACTIVE);
1189 if (sc->tl_irq == NULL) {
1190 device_printf(dev, "couldn't map interrupt\n");
1196 * Now allocate memory for the TX and RX lists.
1198 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF,
1199 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1201 if (sc->tl_ldata == NULL) {
1202 device_printf(dev, "no memory for list buffers!\n");
1207 bzero(sc->tl_ldata, sizeof(struct tl_list_data));
1209 if (vid == COMPAQ_VENDORID || vid == TI_VENDORID)
1210 sc->tl_eeaddr = TL_EEPROM_EADDR;
1211 if (vid == OLICOM_VENDORID)
1212 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
1214 /* Reset the adapter. */
1215 tl_softreset(sc, 1);
1217 tl_softreset(sc, 1);
1220 * Get station address from the EEPROM.
1222 if (tl_read_eeprom(sc, eaddr, sc->tl_eeaddr, ETHER_ADDR_LEN)) {
1223 device_printf(dev, "failed to read station address\n");
1229 * XXX Olicom, in its desire to be different from the
1230 * rest of the world, has done strange things with the
1231 * encoding of the station address in the EEPROM. First
1232 * of all, they store the address at offset 0xF8 rather
1233 * than at 0x83 like the ThunderLAN manual suggests.
1234 * Second, they store the address in three 16-bit words in
1235 * network byte order, as opposed to storing it sequentially
1236 * like all the other ThunderLAN cards. In order to get
1237 * the station address in a form that matches what the Olicom
1238 * diagnostic utility specifies, we have to byte-swap each
1239 * word. To make things even more confusing, neither 00:00:28
1240 * nor 00:00:24 appear in the IEEE OUI database.
1242 if (vid == OLICOM_VENDORID) {
1243 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1245 p = (u_int16_t *)&eaddr[i];
1250 ifp = sc->tl_ifp = if_alloc(IFT_ETHER);
1252 device_printf(dev, "can not if_alloc()\n");
1257 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1258 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1259 ifp->if_ioctl = tl_ioctl;
1260 ifp->if_start = tl_start;
1261 ifp->if_init = tl_init;
1262 ifp->if_mtu = ETHERMTU;
1263 ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1;
1264 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1265 ifp->if_capenable |= IFCAP_VLAN_MTU;
1266 callout_init_mtx(&sc->tl_stat_callout, &sc->tl_mtx, 0);
1268 /* Reset the adapter again. */
1269 tl_softreset(sc, 1);
1271 tl_softreset(sc, 1);
1274 * Do MII setup. If no PHYs are found, then this is a
1275 * bitrate ThunderLAN chip that only supports 10baseT
1277 * XXX mii_attach() can fail for reason different than
1281 if (vid == COMPAQ_VENDORID) {
1282 if (did == COMPAQ_DEVICEID_NETEL_10_100_PROLIANT ||
1283 did == COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED ||
1284 did == COMPAQ_DEVICEID_NETFLEX_3P_BNC ||
1285 did == COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX)
1286 flags |= MIIF_MACPRIV0;
1287 if (did == COMPAQ_DEVICEID_NETEL_10 ||
1288 did == COMPAQ_DEVICEID_NETEL_10_100_DUAL ||
1289 did == COMPAQ_DEVICEID_NETFLEX_3P ||
1290 did == COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED)
1291 flags |= MIIF_MACPRIV1;
1292 } else if (vid == OLICOM_VENDORID && did == OLICOM_DEVICEID_OC2183)
1293 flags |= MIIF_MACPRIV0 | MIIF_MACPRIV1;
1294 if (mii_attach(dev, &sc->tl_miibus, ifp, tl_ifmedia_upd,
1295 tl_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0)) {
1296 struct ifmedia *ifm;
1298 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1299 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1300 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1301 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1302 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1303 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
1304 /* Reset again, this time setting bitrate mode. */
1305 tl_softreset(sc, 1);
1307 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1308 tl_ifmedia_upd(ifp);
1312 * Call MI attach routine.
1314 ether_ifattach(ifp, eaddr);
1316 /* Hook interrupt last to avoid having to lock softc */
1317 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1318 NULL, tl_intr, sc, &sc->tl_intrhand);
1321 device_printf(dev, "couldn't set up irq\n");
1322 ether_ifdetach(ifp);
1334 * Shutdown hardware and free up resources. This can be called any
1335 * time after the mutex has been initialized. It is called in both
1336 * the error case in attach and the normal detach case so it needs
1337 * to be careful about only freeing resources that have actually been
1344 struct tl_softc *sc;
1347 sc = device_get_softc(dev);
1348 KASSERT(mtx_initialized(&sc->tl_mtx), ("tl mutex not initialized"));
1351 /* These should only be active if attach succeeded */
1352 if (device_is_attached(dev)) {
1353 ether_ifdetach(ifp);
1357 callout_drain(&sc->tl_stat_callout);
1360 device_delete_child(dev, sc->tl_miibus);
1361 bus_generic_detach(dev);
1364 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF);
1366 ifmedia_removeall(&sc->ifmedia);
1368 if (sc->tl_intrhand)
1369 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1371 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1373 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1378 mtx_destroy(&sc->tl_mtx);
1384 * Initialize the transmit lists.
1388 struct tl_softc *sc;
1390 struct tl_chain_data *cd;
1391 struct tl_list_data *ld;
1396 for (i = 0; i < TL_TX_LIST_CNT; i++) {
1397 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
1398 if (i == (TL_TX_LIST_CNT - 1))
1399 cd->tl_tx_chain[i].tl_next = NULL;
1401 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
1404 cd->tl_tx_free = &cd->tl_tx_chain[0];
1405 cd->tl_tx_tail = cd->tl_tx_head = NULL;
1412 * Initialize the RX lists and allocate mbufs for them.
1416 struct tl_softc *sc;
1418 struct tl_chain_data *cd;
1419 struct tl_list_data *ld;
1425 for (i = 0; i < TL_RX_LIST_CNT; i++) {
1426 cd->tl_rx_chain[i].tl_ptr =
1427 (struct tl_list_onefrag *)&ld->tl_rx_list[i];
1428 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
1430 if (i == (TL_RX_LIST_CNT - 1)) {
1431 cd->tl_rx_chain[i].tl_next = NULL;
1432 ld->tl_rx_list[i].tlist_fptr = 0;
1434 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
1435 ld->tl_rx_list[i].tlist_fptr =
1436 vtophys(&ld->tl_rx_list[i + 1]);
1440 cd->tl_rx_head = &cd->tl_rx_chain[0];
1441 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1448 struct tl_softc *sc;
1449 struct tl_chain_onefrag *c;
1451 struct mbuf *m_new = NULL;
1453 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1459 c->tl_ptr->tlist_frsize = MCLBYTES;
1460 c->tl_ptr->tlist_fptr = 0;
1461 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
1462 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1463 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1468 * Interrupt handler for RX 'end of frame' condition (EOF). This
1469 * tells us that a full ethernet frame has been captured and we need
1472 * Reception is done using 'lists' which consist of a header and a
1473 * series of 10 data count/data address pairs that point to buffers.
1474 * Initially you're supposed to create a list, populate it with pointers
1475 * to buffers, then load the physical address of the list into the
1476 * ch_parm register. The adapter is then supposed to DMA the received
1477 * frame into the buffers for you.
1479 * To make things as fast as possible, we have the chip DMA directly
1480 * into mbufs. This saves us from having to do a buffer copy: we can
1481 * just hand the mbufs directly to ether_input(). Once the frame has
1482 * been sent on its way, the 'list' structure is assigned a new buffer
1483 * and moved to the end of the RX chain. As long we we stay ahead of
1484 * the chip, it will always think it has an endless receive channel.
1486 * If we happen to fall behind and the chip manages to fill up all of
1487 * the buffers, it will generate an end of channel interrupt and wait
1488 * for us to empty the chain and restart the receiver.
1491 tl_intvec_rxeof(xsc, type)
1495 struct tl_softc *sc;
1496 int r = 0, total_len = 0;
1497 struct ether_header *eh;
1500 struct tl_chain_onefrag *cur_rx;
1507 while(sc->tl_cdata.tl_rx_head != NULL) {
1508 cur_rx = sc->tl_cdata.tl_rx_head;
1509 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1512 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
1513 m = cur_rx->tl_mbuf;
1514 total_len = cur_rx->tl_ptr->tlist_frsize;
1516 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
1518 cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
1519 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1520 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1524 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
1525 vtophys(cur_rx->tl_ptr);
1526 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
1527 sc->tl_cdata.tl_rx_tail = cur_rx;
1530 * Note: when the ThunderLAN chip is in 'capture all
1531 * frames' mode, it will receive its own transmissions.
1532 * We drop don't need to process our own transmissions,
1533 * so we drop them here and continue.
1535 eh = mtod(m, struct ether_header *);
1536 /*if (ifp->if_flags & IFF_PROMISC && */
1537 if (!bcmp(eh->ether_shost, IF_LLADDR(sc->tl_ifp),
1543 m->m_pkthdr.rcvif = ifp;
1544 m->m_pkthdr.len = m->m_len = total_len;
1547 (*ifp->if_input)(ifp, m);
1555 * The RX-EOC condition hits when the ch_parm address hasn't been
1556 * initialized or the adapter reached a list with a forward pointer
1557 * of 0 (which indicates the end of the chain). In our case, this means
1558 * the card has hit the end of the receive buffer chain and we need to
1559 * empty out the buffers and shift the pointer back to the beginning again.
1562 tl_intvec_rxeoc(xsc, type)
1566 struct tl_softc *sc;
1568 struct tl_chain_data *cd;
1574 /* Flush out the receive queue and ack RXEOF interrupts. */
1575 r = tl_intvec_rxeof(xsc, type);
1576 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
1578 cd->tl_rx_head = &cd->tl_rx_chain[0];
1579 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1580 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
1581 r |= (TL_CMD_GO|TL_CMD_RT);
1586 tl_intvec_txeof(xsc, type)
1590 struct tl_softc *sc;
1592 struct tl_chain *cur_tx;
1597 * Go through our tx list and free mbufs for those
1598 * frames that have been sent.
1600 while (sc->tl_cdata.tl_tx_head != NULL) {
1601 cur_tx = sc->tl_cdata.tl_tx_head;
1602 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1604 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
1607 m_freem(cur_tx->tl_mbuf);
1608 cur_tx->tl_mbuf = NULL;
1610 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
1611 sc->tl_cdata.tl_tx_free = cur_tx;
1612 if (!cur_tx->tl_ptr->tlist_fptr)
1620 * The transmit end of channel interrupt. The adapter triggers this
1621 * interrupt to tell us it hit the end of the current transmit list.
1623 * A note about this: it's possible for a condition to arise where
1624 * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
1625 * You have to avoid this since the chip expects things to go in a
1626 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
1627 * When the TXEOF handler is called, it will free all of the transmitted
1628 * frames and reset the tx_head pointer to NULL. However, a TXEOC
1629 * interrupt should be received and acknowledged before any more frames
1630 * are queued for transmission. If tl_statrt() is called after TXEOF
1631 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
1632 * it could attempt to issue a transmit command prematurely.
1634 * To guard against this, tl_start() will only issue transmit commands
1635 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
1636 * can set this flag once tl_start() has cleared it.
1639 tl_intvec_txeoc(xsc, type)
1643 struct tl_softc *sc;
1650 /* Clear the timeout timer. */
1653 if (sc->tl_cdata.tl_tx_head == NULL) {
1654 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1655 sc->tl_cdata.tl_tx_tail = NULL;
1659 /* First we have to ack the EOC interrupt. */
1660 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
1661 /* Then load the address of the next TX list. */
1662 CSR_WRITE_4(sc, TL_CH_PARM,
1663 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
1664 /* Restart TX channel. */
1665 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1667 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1676 tl_intvec_adchk(xsc, type)
1680 struct tl_softc *sc;
1685 device_printf(sc->tl_dev, "adapter check: %x\n",
1686 (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
1688 tl_softreset(sc, 1);
1691 CMD_SET(sc, TL_CMD_INTSON);
1697 tl_intvec_netsts(xsc, type)
1701 struct tl_softc *sc;
1706 netsts = tl_dio_read16(sc, TL_NETSTS);
1707 tl_dio_write16(sc, TL_NETSTS, netsts);
1709 device_printf(sc->tl_dev, "network status: %x\n", netsts);
1718 struct tl_softc *sc;
1728 /* Disable interrupts */
1729 ints = CSR_READ_2(sc, TL_HOST_INT);
1730 CSR_WRITE_2(sc, TL_HOST_INT, ints);
1731 type = (ints << 16) & 0xFFFF0000;
1732 ivec = (ints & TL_VEC_MASK) >> 5;
1733 ints = (ints & TL_INT_MASK) >> 2;
1738 case (TL_INTR_INVALID):
1740 device_printf(sc->tl_dev, "got an invalid interrupt!\n");
1742 /* Re-enable interrupts but don't ack this one. */
1746 case (TL_INTR_TXEOF):
1747 r = tl_intvec_txeof((void *)sc, type);
1749 case (TL_INTR_TXEOC):
1750 r = tl_intvec_txeoc((void *)sc, type);
1752 case (TL_INTR_STATOFLOW):
1753 tl_stats_update(sc);
1756 case (TL_INTR_RXEOF):
1757 r = tl_intvec_rxeof((void *)sc, type);
1759 case (TL_INTR_DUMMY):
1760 device_printf(sc->tl_dev, "got a dummy interrupt\n");
1763 case (TL_INTR_ADCHK):
1765 r = tl_intvec_adchk((void *)sc, type);
1767 r = tl_intvec_netsts((void *)sc, type);
1769 case (TL_INTR_RXEOC):
1770 r = tl_intvec_rxeoc((void *)sc, type);
1773 device_printf(sc->tl_dev, "bogus interrupt type\n");
1777 /* Re-enable interrupts */
1779 CMD_PUT(sc, TL_CMD_ACK | r | type);
1782 if (ifp->if_snd.ifq_head != NULL)
1783 tl_start_locked(ifp);
1791 tl_stats_update(xsc)
1794 struct tl_softc *sc;
1796 struct tl_stats tl_stats;
1797 struct mii_data *mii;
1800 bzero((char *)&tl_stats, sizeof(struct tl_stats));
1806 p = (u_int32_t *)&tl_stats;
1808 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
1809 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1810 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1811 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1812 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1813 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1815 ifp->if_opackets += tl_tx_goodframes(tl_stats);
1816 ifp->if_collisions += tl_stats.tl_tx_single_collision +
1817 tl_stats.tl_tx_multi_collision;
1818 ifp->if_ipackets += tl_rx_goodframes(tl_stats);
1819 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
1820 tl_rx_overrun(tl_stats);
1821 ifp->if_oerrors += tl_tx_underrun(tl_stats);
1823 if (tl_tx_underrun(tl_stats)) {
1825 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH;
1826 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) {
1829 device_printf(sc->tl_dev, "tx underrun -- increasing "
1830 "tx threshold to %d bytes\n",
1831 (64 * (tx_thresh * 4)));
1832 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1833 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4);
1837 if (sc->tl_timer > 0 && --sc->tl_timer == 0)
1840 callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc);
1842 if (!sc->tl_bitrate) {
1843 mii = device_get_softc(sc->tl_miibus);
1851 * Encapsulate an mbuf chain in a list by coupling the mbuf data
1852 * pointers to the fragment pointers.
1855 tl_encap(sc, c, m_head)
1856 struct tl_softc *sc;
1858 struct mbuf *m_head;
1861 struct tl_frag *f = NULL;
1864 struct ifnet *ifp = sc->tl_ifp;
1867 * Start packing the mbufs in this chain into
1868 * the fragment pointers. Stop when we run out
1869 * of fragments or hit the end of the mbuf chain.
1874 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1875 if (m->m_len != 0) {
1876 if (frag == TL_MAXFRAGS)
1878 total_len+= m->m_len;
1879 c->tl_ptr->tl_frag[frag].tlist_dadr =
1880 vtophys(mtod(m, vm_offset_t));
1881 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
1887 * Handle special cases.
1888 * Special case #1: we used up all 10 fragments, but
1889 * we have more mbufs left in the chain. Copy the
1890 * data into an mbuf cluster. Note that we don't
1891 * bother clearing the values in the other fragment
1892 * pointers/counters; it wouldn't gain us anything,
1893 * and would waste cycles.
1896 struct mbuf *m_new = NULL;
1898 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1899 if (m_new == NULL) {
1900 if_printf(ifp, "no memory for tx list\n");
1903 if (m_head->m_pkthdr.len > MHLEN) {
1904 MCLGET(m_new, M_DONTWAIT);
1905 if (!(m_new->m_flags & M_EXT)) {
1907 if_printf(ifp, "no memory for tx list\n");
1911 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1912 mtod(m_new, caddr_t));
1913 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1916 f = &c->tl_ptr->tl_frag[0];
1917 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
1918 f->tlist_dcnt = total_len = m_new->m_len;
1923 * Special case #2: the frame is smaller than the minimum
1924 * frame size. We have to pad it to make the chip happy.
1926 if (total_len < TL_MIN_FRAMELEN) {
1927 if (frag == TL_MAXFRAGS)
1929 "all frags filled but frame still to small!\n");
1930 f = &c->tl_ptr->tl_frag[frag];
1931 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
1932 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
1933 total_len += f->tlist_dcnt;
1937 c->tl_mbuf = m_head;
1938 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
1939 c->tl_ptr->tlist_frsize = total_len;
1940 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1941 c->tl_ptr->tlist_fptr = 0;
1947 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1948 * to the mbuf data regions directly in the transmit lists. We also save a
1949 * copy of the pointers since the transmit list fragment pointers are
1950 * physical addresses.
1956 struct tl_softc *sc;
1960 tl_start_locked(ifp);
1965 tl_start_locked(ifp)
1968 struct tl_softc *sc;
1969 struct mbuf *m_head = NULL;
1971 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
1977 * Check for an available queue slot. If there are none,
1980 if (sc->tl_cdata.tl_tx_free == NULL) {
1981 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1985 start_tx = sc->tl_cdata.tl_tx_free;
1987 while(sc->tl_cdata.tl_tx_free != NULL) {
1988 IF_DEQUEUE(&ifp->if_snd, m_head);
1992 /* Pick a chain member off the free list. */
1993 cur_tx = sc->tl_cdata.tl_tx_free;
1994 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
1996 cur_tx->tl_next = NULL;
1998 /* Pack the data into the list. */
1999 tl_encap(sc, cur_tx, m_head);
2001 /* Chain it together */
2003 prev->tl_next = cur_tx;
2004 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
2009 * If there's a BPF listener, bounce a copy of this frame
2012 BPF_MTAP(ifp, cur_tx->tl_mbuf);
2016 * If there are no packets queued, bail.
2022 * That's all we can stands, we can't stands no more.
2023 * If there are no other transfers pending, then issue the
2024 * TX GO command to the adapter to start things moving.
2025 * Otherwise, just leave the data in the queue and let
2026 * the EOF/EOC interrupt handler send.
2028 if (sc->tl_cdata.tl_tx_head == NULL) {
2029 sc->tl_cdata.tl_tx_head = start_tx;
2030 sc->tl_cdata.tl_tx_tail = cur_tx;
2034 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
2035 cmd = CSR_READ_4(sc, TL_HOSTCMD);
2037 cmd |= TL_CMD_GO|TL_CMD_INTSON;
2041 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
2042 sc->tl_cdata.tl_tx_tail = cur_tx;
2046 * Set a timeout in case the chip goes out to lunch.
2057 struct tl_softc *sc = xsc;
2066 struct tl_softc *sc;
2068 struct ifnet *ifp = sc->tl_ifp;
2069 struct mii_data *mii;
2076 * Cancel pending I/O.
2080 /* Initialize TX FIFO threshold */
2081 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
2082 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG);
2084 /* Set PCI burst size */
2085 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG);
2088 * Set 'capture all frames' bit for promiscuous mode.
2090 if (ifp->if_flags & IFF_PROMISC)
2091 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2093 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2096 * Set capture broadcast bit to capture broadcast frames.
2098 if (ifp->if_flags & IFF_BROADCAST)
2099 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2101 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2103 tl_dio_write16(sc, TL_MAXRX, MCLBYTES);
2105 /* Init our MAC address */
2106 tl_setfilt(sc, IF_LLADDR(sc->tl_ifp), 0);
2108 /* Init multicast filter, if needed. */
2111 /* Init circular RX list. */
2112 if (tl_list_rx_init(sc) == ENOBUFS) {
2113 device_printf(sc->tl_dev,
2114 "initialization failed: no memory for rx buffers\n");
2119 /* Init TX pointers. */
2120 tl_list_tx_init(sc);
2122 /* Enable PCI interrupts. */
2123 CMD_SET(sc, TL_CMD_INTSON);
2125 /* Load the address of the rx list */
2126 CMD_SET(sc, TL_CMD_RT);
2127 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
2129 if (!sc->tl_bitrate) {
2130 if (sc->tl_miibus != NULL) {
2131 mii = device_get_softc(sc->tl_miibus);
2135 tl_ifmedia_upd(ifp);
2138 /* Send the RX go command */
2139 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
2141 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2142 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2144 /* Start the stats update counter */
2145 callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc);
2151 * Set media options.
2157 struct tl_softc *sc;
2158 struct mii_data *mii = NULL;
2164 tl_setmode(sc, sc->ifmedia.ifm_media);
2166 mii = device_get_softc(sc->tl_miibus);
2175 * Report current media status.
2178 tl_ifmedia_sts(ifp, ifmr)
2180 struct ifmediareq *ifmr;
2182 struct tl_softc *sc;
2183 struct mii_data *mii;
2188 ifmr->ifm_active = IFM_ETHER;
2190 if (sc->tl_bitrate) {
2191 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
2192 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2194 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2195 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
2196 ifmr->ifm_active |= IFM_HDX;
2198 ifmr->ifm_active |= IFM_FDX;
2201 mii = device_get_softc(sc->tl_miibus);
2203 ifmr->ifm_active = mii->mii_media_active;
2204 ifmr->ifm_status = mii->mii_media_status;
2212 tl_ioctl(ifp, command, data)
2217 struct tl_softc *sc = ifp->if_softc;
2218 struct ifreq *ifr = (struct ifreq *) data;
2224 if (ifp->if_flags & IFF_UP) {
2225 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2226 ifp->if_flags & IFF_PROMISC &&
2227 !(sc->tl_if_flags & IFF_PROMISC)) {
2228 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2230 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2231 !(ifp->if_flags & IFF_PROMISC) &&
2232 sc->tl_if_flags & IFF_PROMISC) {
2233 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2238 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2242 sc->tl_if_flags = ifp->if_flags;
2256 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2258 struct mii_data *mii;
2259 mii = device_get_softc(sc->tl_miibus);
2260 error = ifmedia_ioctl(ifp, ifr,
2261 &mii->mii_media, command);
2265 error = ether_ioctl(ifp, command, data);
2274 struct tl_softc *sc;
2281 if_printf(ifp, "device timeout\n");
2285 tl_softreset(sc, 1);
2292 * Stop the adapter and free any mbufs allocated to the
2297 struct tl_softc *sc;
2306 /* Stop the stats updater. */
2307 callout_stop(&sc->tl_stat_callout);
2309 /* Stop the transmitter */
2310 CMD_CLR(sc, TL_CMD_RT);
2311 CMD_SET(sc, TL_CMD_STOP);
2312 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2314 /* Stop the receiver */
2315 CMD_SET(sc, TL_CMD_RT);
2316 CMD_SET(sc, TL_CMD_STOP);
2317 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2320 * Disable host interrupts.
2322 CMD_SET(sc, TL_CMD_INTSOFF);
2325 * Clear list pointer.
2327 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2330 * Free the RX lists.
2332 for (i = 0; i < TL_RX_LIST_CNT; i++) {
2333 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
2334 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
2335 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
2338 bzero((char *)&sc->tl_ldata->tl_rx_list,
2339 sizeof(sc->tl_ldata->tl_rx_list));
2342 * Free the TX list buffers.
2344 for (i = 0; i < TL_TX_LIST_CNT; i++) {
2345 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
2346 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2347 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2350 bzero((char *)&sc->tl_ldata->tl_tx_list,
2351 sizeof(sc->tl_ldata->tl_tx_list));
2353 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2359 * Stop all chip I/O so that the kernel's probe routines don't
2360 * get confused by errant DMAs when rebooting.
2366 struct tl_softc *sc;
2368 sc = device_get_softc(dev);