2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
38 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
39 * the National Semiconductor DP83840A physical interface and the
40 * Microchip Technology 24Cxx series serial EEPROM.
42 * Written using the following four documents:
44 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
45 * National Semiconductor DP83840A data sheet (www.national.com)
46 * Microchip Technology 24C02C data sheet (www.microchip.com)
47 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
49 * Written by Bill Paul <wpaul@ctr.columbia.edu>
50 * Electrical Engineering Department
51 * Columbia University, New York City
54 * Some notes about the ThunderLAN:
56 * The ThunderLAN controller is a single chip containing PCI controller
57 * logic, approximately 3K of on-board SRAM, a LAN controller, and media
58 * independent interface (MII) bus. The MII allows the ThunderLAN chip to
59 * control up to 32 different physical interfaces (PHYs). The ThunderLAN
60 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
61 * to act as a complete ethernet interface.
63 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
64 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
65 * in full or half duplex. Some of the Compaq Deskpro machines use a
66 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
67 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
68 * concert with the ThunderLAN's internal PHY to provide full 10/100
69 * support. This is cheaper than using a standalone external PHY for both
70 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
71 * A serial EEPROM is also attached to the ThunderLAN chip to provide
72 * power-up default register settings and for storing the adapter's
73 * station address. Although not supported by this driver, the ThunderLAN
74 * chip can also be connected to token ring PHYs.
76 * The ThunderLAN has a set of registers which can be used to issue
77 * commands, acknowledge interrupts, and to manipulate other internal
78 * registers on its DIO bus. The primary registers can be accessed
79 * using either programmed I/O (inb/outb) or via PCI memory mapping,
80 * depending on how the card is configured during the PCI probing
81 * phase. It is even possible to have both PIO and memory mapped
82 * access turned on at the same time.
84 * Frame reception and transmission with the ThunderLAN chip is done
85 * using frame 'lists.' A list structure looks more or less like this:
88 * u_int32_t fragment_address;
89 * u_int32_t fragment_size;
92 * u_int32_t forward_pointer;
94 * u_int16_t frame_size;
95 * struct tl_frag fragments[10];
98 * The forward pointer in the list header can be either a 0 or the address
99 * of another list, which allows several lists to be linked together. Each
100 * list contains up to 10 fragment descriptors. This means the chip allows
101 * ethernet frames to be broken up into up to 10 chunks for transfer to
102 * and from the SRAM. Note that the forward pointer and fragment buffer
103 * addresses are physical memory addresses, not virtual. Note also that
104 * a single ethernet frame can not span lists: if the host wants to
105 * transmit a frame and the frame data is split up over more than 10
106 * buffers, the frame has to collapsed before it can be transmitted.
108 * To receive frames, the driver sets up a number of lists and populates
109 * the fragment descriptors, then it sends an RX GO command to the chip.
110 * When a frame is received, the chip will DMA it into the memory regions
111 * specified by the fragment descriptors and then trigger an RX 'end of
112 * frame interrupt' when done. The driver may choose to use only one
113 * fragment per list; this may result is slighltly less efficient use
114 * of memory in exchange for improving performance.
116 * To transmit frames, the driver again sets up lists and fragment
117 * descriptors, only this time the buffers contain frame data that
118 * is to be DMA'ed into the chip instead of out of it. Once the chip
119 * has transfered the data into its on-board SRAM, it will trigger a
120 * TX 'end of frame' interrupt. It will also generate an 'end of channel'
121 * interrupt when it reaches the end of the list.
124 * Some notes about this driver:
126 * The ThunderLAN chip provides a couple of different ways to organize
127 * reception, transmission and interrupt handling. The simplest approach
128 * is to use one list each for transmission and reception. In this mode,
129 * the ThunderLAN will generate two interrupts for every received frame
130 * (one RX EOF and one RX EOC) and two for each transmitted frame (one
131 * TX EOF and one TX EOC). This may make the driver simpler but it hurts
132 * performance to have to handle so many interrupts.
134 * Initially I wanted to create a circular list of receive buffers so
135 * that the ThunderLAN chip would think there was an infinitely long
136 * receive channel and never deliver an RXEOC interrupt. However this
137 * doesn't work correctly under heavy load: while the manual says the
138 * chip will trigger an RXEOF interrupt each time a frame is copied into
139 * memory, you can't count on the chip waiting around for you to acknowledge
140 * the interrupt before it starts trying to DMA the next frame. The result
141 * is that the chip might traverse the entire circular list and then wrap
142 * around before you have a chance to do anything about it. Consequently,
143 * the receive list is terminated (with a 0 in the forward pointer in the
144 * last element). Each time an RXEOF interrupt arrives, the used list
145 * is shifted to the end of the list. This gives the appearance of an
146 * infinitely large RX chain so long as the driver doesn't fall behind
147 * the chip and allow all of the lists to be filled up.
149 * If all the lists are filled, the adapter will deliver an RX 'end of
150 * channel' interrupt when it hits the 0 forward pointer at the end of
151 * the chain. The RXEOC handler then cleans out the RX chain and resets
152 * the list head pointer in the ch_parm register and restarts the receiver.
154 * For frame transmission, it is possible to program the ThunderLAN's
155 * transmit interrupt threshold so that the chip can acknowledge multiple
156 * lists with only a single TX EOF interrupt. This allows the driver to
157 * queue several frames in one shot, and only have to handle a total
158 * two interrupts (one TX EOF and one TX EOC) no matter how many frames
159 * are transmitted. Frame transmission is done directly out of the
160 * mbufs passed to the tl_start() routine via the interface send queue.
161 * The driver simply sets up the fragment descriptors in the transmit
162 * lists to point to the mbuf data regions and sends a TX GO command.
164 * Note that since the RX and TX lists themselves are always used
165 * only by the driver, the are malloc()ed once at driver initialization
166 * time and never free()ed.
168 * Also, in order to remain as platform independent as possible, this
169 * driver uses memory mapped register access to manipulate the card
170 * as opposed to programmed I/O. This avoids the use of the inb/outb
171 * (and related) instructions which are specific to the i386 platform.
173 * Using these techniques, this driver achieves very high performance
174 * by minimizing the amount of interrupts generated during large
175 * transfers and by completely avoiding buffer copies. Frame transfer
176 * to and from the ThunderLAN chip is performed entirely by the chip
177 * itself thereby reducing the load on the host CPU.
180 #include <sys/param.h>
181 #include <sys/systm.h>
182 #include <sys/sockio.h>
183 #include <sys/mbuf.h>
184 #include <sys/malloc.h>
185 #include <sys/kernel.h>
186 #include <sys/module.h>
187 #include <sys/socket.h>
190 #include <net/if_var.h>
191 #include <net/if_arp.h>
192 #include <net/ethernet.h>
193 #include <net/if_dl.h>
194 #include <net/if_media.h>
195 #include <net/if_types.h>
199 #include <vm/vm.h> /* for vtophys */
200 #include <vm/pmap.h> /* for vtophys */
201 #include <machine/bus.h>
202 #include <machine/resource.h>
204 #include <sys/rman.h>
206 #include <dev/mii/mii.h>
207 #include <dev/mii/mii_bitbang.h>
208 #include <dev/mii/miivar.h>
210 #include <dev/pci/pcireg.h>
211 #include <dev/pci/pcivar.h>
214 * Default to using PIO register access mode to pacify certain
215 * laptop docking stations with built-in ThunderLAN chips that
216 * don't seem to handle memory mapped mode properly.
218 #define TL_USEIOSPACE
220 #include <dev/tl/if_tlreg.h>
222 MODULE_DEPEND(tl, pci, 1, 1, 1);
223 MODULE_DEPEND(tl, ether, 1, 1, 1);
224 MODULE_DEPEND(tl, miibus, 1, 1, 1);
226 /* "device miibus" required. See GENERIC if you get errors here. */
227 #include "miibus_if.h"
230 * Various supported device vendors/types and their names.
233 static const struct tl_type tl_devs[] = {
234 { TI_VENDORID, TI_DEVICEID_THUNDERLAN,
235 "Texas Instruments ThunderLAN" },
236 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
237 "Compaq Netelligent 10" },
238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
239 "Compaq Netelligent 10/100" },
240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
241 "Compaq Netelligent 10/100 Proliant" },
242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
243 "Compaq Netelligent 10/100 Dual Port" },
244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
245 "Compaq NetFlex-3/P Integrated" },
246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
247 "Compaq NetFlex-3/P" },
248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
249 "Compaq NetFlex 3/P w/ BNC" },
250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
251 "Compaq Netelligent 10/100 TX Embedded UTP" },
252 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
253 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
254 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
255 "Compaq Netelligent 10/100 TX UTP" },
256 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
257 "Olicom OC-2183/2185" },
258 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
260 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
261 "Olicom OC-2326 10/100 TX UTP" },
265 static int tl_probe(device_t);
266 static int tl_attach(device_t);
267 static int tl_detach(device_t);
268 static int tl_intvec_rxeoc(void *, u_int32_t);
269 static int tl_intvec_txeoc(void *, u_int32_t);
270 static int tl_intvec_txeof(void *, u_int32_t);
271 static int tl_intvec_rxeof(void *, u_int32_t);
272 static int tl_intvec_adchk(void *, u_int32_t);
273 static int tl_intvec_netsts(void *, u_int32_t);
275 static int tl_newbuf(struct tl_softc *, struct tl_chain_onefrag *);
276 static void tl_stats_update(void *);
277 static int tl_encap(struct tl_softc *, struct tl_chain *, struct mbuf *);
279 static void tl_intr(void *);
280 static void tl_start(struct ifnet *);
281 static void tl_start_locked(struct ifnet *);
282 static int tl_ioctl(struct ifnet *, u_long, caddr_t);
283 static void tl_init(void *);
284 static void tl_init_locked(struct tl_softc *);
285 static void tl_stop(struct tl_softc *);
286 static void tl_watchdog(struct tl_softc *);
287 static int tl_shutdown(device_t);
288 static int tl_ifmedia_upd(struct ifnet *);
289 static void tl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
291 static u_int8_t tl_eeprom_putbyte(struct tl_softc *, int);
292 static u_int8_t tl_eeprom_getbyte(struct tl_softc *, int, u_int8_t *);
293 static int tl_read_eeprom(struct tl_softc *, caddr_t, int, int);
295 static int tl_miibus_readreg(device_t, int, int);
296 static int tl_miibus_writereg(device_t, int, int, int);
297 static void tl_miibus_statchg(device_t);
299 static void tl_setmode(struct tl_softc *, int);
300 static uint32_t tl_mchash(const uint8_t *);
301 static void tl_setmulti(struct tl_softc *);
302 static void tl_setfilt(struct tl_softc *, caddr_t, int);
303 static void tl_softreset(struct tl_softc *, int);
304 static void tl_hardreset(device_t);
305 static int tl_list_rx_init(struct tl_softc *);
306 static int tl_list_tx_init(struct tl_softc *);
308 static u_int8_t tl_dio_read8(struct tl_softc *, int);
309 static u_int16_t tl_dio_read16(struct tl_softc *, int);
310 static u_int32_t tl_dio_read32(struct tl_softc *, int);
311 static void tl_dio_write8(struct tl_softc *, int, int);
312 static void tl_dio_write16(struct tl_softc *, int, int);
313 static void tl_dio_write32(struct tl_softc *, int, int);
314 static void tl_dio_setbit(struct tl_softc *, int, int);
315 static void tl_dio_clrbit(struct tl_softc *, int, int);
316 static void tl_dio_setbit16(struct tl_softc *, int, int);
317 static void tl_dio_clrbit16(struct tl_softc *, int, int);
322 static uint32_t tl_mii_bitbang_read(device_t);
323 static void tl_mii_bitbang_write(device_t, uint32_t);
325 static const struct mii_bitbang_ops tl_mii_bitbang_ops = {
327 tl_mii_bitbang_write,
329 TL_SIO_MDATA, /* MII_BIT_MDO */
330 TL_SIO_MDATA, /* MII_BIT_MDI */
331 TL_SIO_MCLK, /* MII_BIT_MDC */
332 TL_SIO_MTXEN, /* MII_BIT_DIR_HOST_PHY */
333 0, /* MII_BIT_DIR_PHY_HOST */
338 #define TL_RES SYS_RES_IOPORT
339 #define TL_RID TL_PCI_LOIO
341 #define TL_RES SYS_RES_MEMORY
342 #define TL_RID TL_PCI_LOMEM
345 static device_method_t tl_methods[] = {
346 /* Device interface */
347 DEVMETHOD(device_probe, tl_probe),
348 DEVMETHOD(device_attach, tl_attach),
349 DEVMETHOD(device_detach, tl_detach),
350 DEVMETHOD(device_shutdown, tl_shutdown),
353 DEVMETHOD(miibus_readreg, tl_miibus_readreg),
354 DEVMETHOD(miibus_writereg, tl_miibus_writereg),
355 DEVMETHOD(miibus_statchg, tl_miibus_statchg),
360 static driver_t tl_driver = {
363 sizeof(struct tl_softc)
366 static devclass_t tl_devclass;
368 DRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0);
369 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0);
371 static u_int8_t tl_dio_read8(sc, reg)
376 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
377 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
378 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
379 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
380 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
381 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
384 static u_int16_t tl_dio_read16(sc, reg)
389 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
390 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
391 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
392 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
393 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
394 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
397 static u_int32_t tl_dio_read32(sc, reg)
402 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
403 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
404 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
405 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
406 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
407 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
410 static void tl_dio_write8(sc, reg, val)
416 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
417 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
418 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
419 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
420 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
421 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
424 static void tl_dio_write16(sc, reg, val)
430 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
431 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
432 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
433 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
434 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
435 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
438 static void tl_dio_write32(sc, reg, val)
444 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
445 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
446 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
447 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
448 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
449 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
453 tl_dio_setbit(sc, reg, bit)
460 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
461 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
462 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
463 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
464 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
465 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
467 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1,
468 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
469 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
473 tl_dio_clrbit(sc, reg, bit)
480 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
481 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
482 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
483 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
484 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
485 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
487 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1,
488 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
489 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
492 static void tl_dio_setbit16(sc, reg, bit)
499 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
500 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
501 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
502 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
503 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
504 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
506 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2,
507 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
508 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
511 static void tl_dio_clrbit16(sc, reg, bit)
518 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
519 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
520 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
521 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
522 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
523 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
525 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2,
526 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
527 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
531 * Send an instruction or address to the EEPROM, check for ACK.
533 static u_int8_t tl_eeprom_putbyte(sc, byte)
537 register int i, ack = 0;
540 * Make sure we're in TX mode.
542 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
545 * Feed in each bit and stobe the clock.
547 for (i = 0x80; i; i >>= 1) {
549 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
551 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
554 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
556 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
562 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
567 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
568 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
569 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
575 * Read a byte of data stored in the EEPROM at address 'addr.'
577 static u_int8_t tl_eeprom_getbyte(sc, addr, dest)
584 device_t tl_dev = sc->tl_dev;
586 tl_dio_write8(sc, TL_NETSIO, 0);
591 * Send write control code to EEPROM.
593 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
594 device_printf(tl_dev, "failed to send write command, status: %x\n",
595 tl_dio_read8(sc, TL_NETSIO));
600 * Send address of byte we want to read.
602 if (tl_eeprom_putbyte(sc, addr)) {
603 device_printf(tl_dev, "failed to send address, status: %x\n",
604 tl_dio_read8(sc, TL_NETSIO));
611 * Send read control code to EEPROM.
613 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
614 device_printf(tl_dev, "failed to send write command, status: %x\n",
615 tl_dio_read8(sc, TL_NETSIO));
620 * Start reading bits from EEPROM.
622 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
623 for (i = 0x80; i; i >>= 1) {
624 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
626 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
628 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
635 * No ACK generated for read, so just return byte.
644 * Read a sequence of bytes from the EEPROM.
647 tl_read_eeprom(sc, dest, off, cnt)
656 for (i = 0; i < cnt; i++) {
657 err = tl_eeprom_getbyte(sc, off + i, &byte);
666 #define TL_SIO_MII (TL_SIO_MCLK | TL_SIO_MDATA | TL_SIO_MTXEN)
669 * Read the MII serial port for the MII bit-bang module.
672 tl_mii_bitbang_read(device_t dev)
677 sc = device_get_softc(dev);
679 val = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MII;
680 CSR_BARRIER(sc, TL_NETSIO, 1,
681 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
687 * Write the MII serial port for the MII bit-bang module.
690 tl_mii_bitbang_write(device_t dev, uint32_t val)
694 sc = device_get_softc(dev);
696 val = (tl_dio_read8(sc, TL_NETSIO) & ~TL_SIO_MII) | val;
697 CSR_BARRIER(sc, TL_NETSIO, 1,
698 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
699 tl_dio_write8(sc, TL_NETSIO, val);
700 CSR_BARRIER(sc, TL_NETSIO, 1,
701 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
705 tl_miibus_readreg(dev, phy, reg)
712 sc = device_get_softc(dev);
715 * Turn off MII interrupt by forcing MINTEN low.
717 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
719 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
722 val = mii_bitbang_readreg(dev, &tl_mii_bitbang_ops, phy, reg);
724 /* Reenable interrupts. */
726 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
733 tl_miibus_writereg(dev, phy, reg, data)
740 sc = device_get_softc(dev);
743 * Turn off MII interrupt by forcing MINTEN low.
745 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
747 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
750 mii_bitbang_writereg(dev, &tl_mii_bitbang_ops, phy, reg, data);
752 /* Reenable interrupts. */
754 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
761 tl_miibus_statchg(dev)
765 struct mii_data *mii;
767 sc = device_get_softc(dev);
768 mii = device_get_softc(sc->tl_miibus);
770 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
771 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
773 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
778 * Set modes for bitrate devices.
781 tl_setmode(sc, media)
785 if (IFM_SUBTYPE(media) == IFM_10_5)
786 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
787 if (IFM_SUBTYPE(media) == IFM_10_T) {
788 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
789 if ((media & IFM_GMASK) == IFM_FDX) {
790 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
791 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
793 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
794 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
800 * Calculate the hash of a MAC address for programming the multicast hash
801 * table. This hash is simply the address split into 6-bit chunks
803 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
804 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
805 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then
806 * the folded 24-bit value is split into 6-bit portions and XOR'd.
814 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
816 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
820 * The ThunderLAN has a perfect MAC address filter in addition to
821 * the multicast hash filter. The perfect filter can be programmed
822 * with up to four MAC addresses. The first one is always used to
823 * hold the station address, which leaves us free to use the other
824 * three for multicast addresses.
827 tl_setfilt(sc, addr, slot)
835 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
837 for (i = 0; i < ETHER_ADDR_LEN; i++)
838 tl_dio_write8(sc, regaddr + i, *(addr + i));
842 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
843 * linked list. This is fine, except addresses are added from the head
844 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
845 * group to always be in the perfect filter, but as more groups are added,
846 * the 224.0.0.1 entry (which is always added first) gets pushed down
847 * the list and ends up at the tail. So after 3 or 4 multicast groups
848 * are added, the all-hosts entry gets pushed out of the perfect filter
849 * and into the hash table.
851 * Because the multicast list is a doubly-linked list as opposed to a
852 * circular queue, we don't have the ability to just grab the tail of
853 * the list and traverse it backwards. Instead, we have to traverse
854 * the list once to find the tail, then traverse it again backwards to
855 * update the multicast filter.
862 u_int32_t hashes[2] = { 0, 0 };
864 struct ifmultiaddr *ifma;
865 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
868 /* First, zot all the existing filters. */
869 for (i = 1; i < 4; i++)
870 tl_setfilt(sc, (caddr_t)&dummy, i);
871 tl_dio_write32(sc, TL_HASH1, 0);
872 tl_dio_write32(sc, TL_HASH2, 0);
874 /* Now program new ones. */
875 if (ifp->if_flags & IFF_ALLMULTI) {
876 hashes[0] = 0xFFFFFFFF;
877 hashes[1] = 0xFFFFFFFF;
881 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
882 if (ifma->ifma_addr->sa_family != AF_LINK)
885 * Program the first three multicast groups
886 * into the perfect filter. For all others,
887 * use the hash table.
891 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
897 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
899 hashes[0] |= (1 << h);
901 hashes[1] |= (1 << (h - 32));
903 if_maddr_runlock(ifp);
906 tl_dio_write32(sc, TL_HASH1, hashes[0]);
907 tl_dio_write32(sc, TL_HASH2, hashes[1]);
911 * This routine is recommended by the ThunderLAN manual to insure that
912 * the internal PHY is powered up correctly. It also recommends a one
913 * second pause at the end to 'wait for the clocks to start' but in my
914 * experience this isn't necessary.
923 mii_bitbang_sync(dev, &tl_mii_bitbang_ops);
925 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
927 for (i = 0; i < MII_NPHY; i++)
928 tl_miibus_writereg(dev, i, MII_BMCR, flags);
930 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
932 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
933 mii_bitbang_sync(dev, &tl_mii_bitbang_ops);
934 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
940 tl_softreset(sc, internal)
944 u_int32_t cmd, dummy, i;
946 /* Assert the adapter reset bit. */
947 CMD_SET(sc, TL_CMD_ADRST);
949 /* Turn off interrupts */
950 CMD_SET(sc, TL_CMD_INTSOFF);
952 /* First, clear the stats registers. */
953 for (i = 0; i < 5; i++)
954 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
956 /* Clear Areg and Hash registers */
957 for (i = 0; i < 8; i++)
958 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
961 * Set up Netconfig register. Enable one channel and
964 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
965 if (internal && !sc->tl_bitrate) {
966 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
968 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
971 /* Handle cards with bitrate devices. */
973 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
976 * Load adapter irq pacing timer and tx threshold.
977 * We make the transmit threshold 1 initially but we may
980 cmd = CSR_READ_4(sc, TL_HOSTCMD);
982 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
983 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
984 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
986 /* Unreset the MII */
987 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
989 /* Take the adapter out of reset */
990 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
992 /* Wait for things to settle down a little. */
997 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
998 * against our list and return its name if we find a match.
1004 const struct tl_type *t;
1008 while(t->tl_name != NULL) {
1009 if ((pci_get_vendor(dev) == t->tl_vid) &&
1010 (pci_get_device(dev) == t->tl_did)) {
1011 device_set_desc(dev, t->tl_name);
1012 return (BUS_PROBE_DEFAULT);
1025 const struct tl_type *t;
1027 struct tl_softc *sc;
1028 int error, flags, i, rid, unit;
1031 vid = pci_get_vendor(dev);
1032 did = pci_get_device(dev);
1033 sc = device_get_softc(dev);
1035 unit = device_get_unit(dev);
1038 while(t->tl_name != NULL) {
1039 if (vid == t->tl_vid && did == t->tl_did)
1044 if (t->tl_name == NULL) {
1045 device_printf(dev, "unknown device!?\n");
1049 mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1053 * Map control/status registers.
1055 pci_enable_busmaster(dev);
1057 #ifdef TL_USEIOSPACE
1060 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1064 * Some cards have the I/O and memory mapped address registers
1065 * reversed. Try both combinations before giving up.
1067 if (sc->tl_res == NULL) {
1069 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1074 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1076 if (sc->tl_res == NULL) {
1078 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1083 if (sc->tl_res == NULL) {
1084 device_printf(dev, "couldn't map ports/memory\n");
1091 * The ThunderLAN manual suggests jacking the PCI latency
1092 * timer all the way up to its maximum value. I'm not sure
1093 * if this is really necessary, but what the manual wants,
1096 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4);
1097 command |= 0x0000FF00;
1098 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4);
1101 /* Allocate interrupt */
1103 sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1104 RF_SHAREABLE | RF_ACTIVE);
1106 if (sc->tl_irq == NULL) {
1107 device_printf(dev, "couldn't map interrupt\n");
1113 * Now allocate memory for the TX and RX lists.
1115 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF,
1116 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1118 if (sc->tl_ldata == NULL) {
1119 device_printf(dev, "no memory for list buffers!\n");
1124 bzero(sc->tl_ldata, sizeof(struct tl_list_data));
1126 if (vid == COMPAQ_VENDORID || vid == TI_VENDORID)
1127 sc->tl_eeaddr = TL_EEPROM_EADDR;
1128 if (vid == OLICOM_VENDORID)
1129 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
1131 /* Reset the adapter. */
1132 tl_softreset(sc, 1);
1134 tl_softreset(sc, 1);
1137 * Get station address from the EEPROM.
1139 if (tl_read_eeprom(sc, eaddr, sc->tl_eeaddr, ETHER_ADDR_LEN)) {
1140 device_printf(dev, "failed to read station address\n");
1146 * XXX Olicom, in its desire to be different from the
1147 * rest of the world, has done strange things with the
1148 * encoding of the station address in the EEPROM. First
1149 * of all, they store the address at offset 0xF8 rather
1150 * than at 0x83 like the ThunderLAN manual suggests.
1151 * Second, they store the address in three 16-bit words in
1152 * network byte order, as opposed to storing it sequentially
1153 * like all the other ThunderLAN cards. In order to get
1154 * the station address in a form that matches what the Olicom
1155 * diagnostic utility specifies, we have to byte-swap each
1156 * word. To make things even more confusing, neither 00:00:28
1157 * nor 00:00:24 appear in the IEEE OUI database.
1159 if (vid == OLICOM_VENDORID) {
1160 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1162 p = (u_int16_t *)&eaddr[i];
1167 ifp = sc->tl_ifp = if_alloc(IFT_ETHER);
1169 device_printf(dev, "can not if_alloc()\n");
1174 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1175 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1176 ifp->if_ioctl = tl_ioctl;
1177 ifp->if_start = tl_start;
1178 ifp->if_init = tl_init;
1179 ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1;
1180 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1181 ifp->if_capenable |= IFCAP_VLAN_MTU;
1182 callout_init_mtx(&sc->tl_stat_callout, &sc->tl_mtx, 0);
1184 /* Reset the adapter again. */
1185 tl_softreset(sc, 1);
1187 tl_softreset(sc, 1);
1190 * Do MII setup. If no PHYs are found, then this is a
1191 * bitrate ThunderLAN chip that only supports 10baseT
1193 * XXX mii_attach() can fail for reason different than
1197 if (vid == COMPAQ_VENDORID) {
1198 if (did == COMPAQ_DEVICEID_NETEL_10_100_PROLIANT ||
1199 did == COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED ||
1200 did == COMPAQ_DEVICEID_NETFLEX_3P_BNC ||
1201 did == COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX)
1202 flags |= MIIF_MACPRIV0;
1203 if (did == COMPAQ_DEVICEID_NETEL_10 ||
1204 did == COMPAQ_DEVICEID_NETEL_10_100_DUAL ||
1205 did == COMPAQ_DEVICEID_NETFLEX_3P ||
1206 did == COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED)
1207 flags |= MIIF_MACPRIV1;
1208 } else if (vid == OLICOM_VENDORID && did == OLICOM_DEVICEID_OC2183)
1209 flags |= MIIF_MACPRIV0 | MIIF_MACPRIV1;
1210 if (mii_attach(dev, &sc->tl_miibus, ifp, tl_ifmedia_upd,
1211 tl_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0)) {
1212 struct ifmedia *ifm;
1214 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1215 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1216 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1217 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1218 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1219 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
1220 /* Reset again, this time setting bitrate mode. */
1221 tl_softreset(sc, 1);
1223 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1224 tl_ifmedia_upd(ifp);
1228 * Call MI attach routine.
1230 ether_ifattach(ifp, eaddr);
1232 /* Hook interrupt last to avoid having to lock softc */
1233 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1234 NULL, tl_intr, sc, &sc->tl_intrhand);
1237 device_printf(dev, "couldn't set up irq\n");
1238 ether_ifdetach(ifp);
1250 * Shutdown hardware and free up resources. This can be called any
1251 * time after the mutex has been initialized. It is called in both
1252 * the error case in attach and the normal detach case so it needs
1253 * to be careful about only freeing resources that have actually been
1260 struct tl_softc *sc;
1263 sc = device_get_softc(dev);
1264 KASSERT(mtx_initialized(&sc->tl_mtx), ("tl mutex not initialized"));
1267 /* These should only be active if attach succeeded */
1268 if (device_is_attached(dev)) {
1269 ether_ifdetach(ifp);
1273 callout_drain(&sc->tl_stat_callout);
1276 device_delete_child(dev, sc->tl_miibus);
1277 bus_generic_detach(dev);
1280 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF);
1282 ifmedia_removeall(&sc->ifmedia);
1284 if (sc->tl_intrhand)
1285 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1287 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1289 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1294 mtx_destroy(&sc->tl_mtx);
1300 * Initialize the transmit lists.
1304 struct tl_softc *sc;
1306 struct tl_chain_data *cd;
1307 struct tl_list_data *ld;
1312 for (i = 0; i < TL_TX_LIST_CNT; i++) {
1313 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
1314 if (i == (TL_TX_LIST_CNT - 1))
1315 cd->tl_tx_chain[i].tl_next = NULL;
1317 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
1320 cd->tl_tx_free = &cd->tl_tx_chain[0];
1321 cd->tl_tx_tail = cd->tl_tx_head = NULL;
1328 * Initialize the RX lists and allocate mbufs for them.
1332 struct tl_softc *sc;
1334 struct tl_chain_data *cd;
1335 struct tl_list_data *ld;
1341 for (i = 0; i < TL_RX_LIST_CNT; i++) {
1342 cd->tl_rx_chain[i].tl_ptr =
1343 (struct tl_list_onefrag *)&ld->tl_rx_list[i];
1344 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
1346 if (i == (TL_RX_LIST_CNT - 1)) {
1347 cd->tl_rx_chain[i].tl_next = NULL;
1348 ld->tl_rx_list[i].tlist_fptr = 0;
1350 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
1351 ld->tl_rx_list[i].tlist_fptr =
1352 vtophys(&ld->tl_rx_list[i + 1]);
1356 cd->tl_rx_head = &cd->tl_rx_chain[0];
1357 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1364 struct tl_softc *sc;
1365 struct tl_chain_onefrag *c;
1367 struct mbuf *m_new = NULL;
1369 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1375 c->tl_ptr->tlist_frsize = MCLBYTES;
1376 c->tl_ptr->tlist_fptr = 0;
1377 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
1378 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1379 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1384 * Interrupt handler for RX 'end of frame' condition (EOF). This
1385 * tells us that a full ethernet frame has been captured and we need
1388 * Reception is done using 'lists' which consist of a header and a
1389 * series of 10 data count/data address pairs that point to buffers.
1390 * Initially you're supposed to create a list, populate it with pointers
1391 * to buffers, then load the physical address of the list into the
1392 * ch_parm register. The adapter is then supposed to DMA the received
1393 * frame into the buffers for you.
1395 * To make things as fast as possible, we have the chip DMA directly
1396 * into mbufs. This saves us from having to do a buffer copy: we can
1397 * just hand the mbufs directly to ether_input(). Once the frame has
1398 * been sent on its way, the 'list' structure is assigned a new buffer
1399 * and moved to the end of the RX chain. As long we we stay ahead of
1400 * the chip, it will always think it has an endless receive channel.
1402 * If we happen to fall behind and the chip manages to fill up all of
1403 * the buffers, it will generate an end of channel interrupt and wait
1404 * for us to empty the chain and restart the receiver.
1407 tl_intvec_rxeof(xsc, type)
1411 struct tl_softc *sc;
1412 int r = 0, total_len = 0;
1413 struct ether_header *eh;
1416 struct tl_chain_onefrag *cur_rx;
1423 while(sc->tl_cdata.tl_rx_head != NULL) {
1424 cur_rx = sc->tl_cdata.tl_rx_head;
1425 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1428 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
1429 m = cur_rx->tl_mbuf;
1430 total_len = cur_rx->tl_ptr->tlist_frsize;
1432 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
1434 cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
1435 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1436 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1440 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
1441 vtophys(cur_rx->tl_ptr);
1442 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
1443 sc->tl_cdata.tl_rx_tail = cur_rx;
1446 * Note: when the ThunderLAN chip is in 'capture all
1447 * frames' mode, it will receive its own transmissions.
1448 * We drop don't need to process our own transmissions,
1449 * so we drop them here and continue.
1451 eh = mtod(m, struct ether_header *);
1452 /*if (ifp->if_flags & IFF_PROMISC && */
1453 if (!bcmp(eh->ether_shost, IF_LLADDR(sc->tl_ifp),
1459 m->m_pkthdr.rcvif = ifp;
1460 m->m_pkthdr.len = m->m_len = total_len;
1463 (*ifp->if_input)(ifp, m);
1471 * The RX-EOC condition hits when the ch_parm address hasn't been
1472 * initialized or the adapter reached a list with a forward pointer
1473 * of 0 (which indicates the end of the chain). In our case, this means
1474 * the card has hit the end of the receive buffer chain and we need to
1475 * empty out the buffers and shift the pointer back to the beginning again.
1478 tl_intvec_rxeoc(xsc, type)
1482 struct tl_softc *sc;
1484 struct tl_chain_data *cd;
1490 /* Flush out the receive queue and ack RXEOF interrupts. */
1491 r = tl_intvec_rxeof(xsc, type);
1492 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
1494 cd->tl_rx_head = &cd->tl_rx_chain[0];
1495 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1496 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
1497 r |= (TL_CMD_GO|TL_CMD_RT);
1502 tl_intvec_txeof(xsc, type)
1506 struct tl_softc *sc;
1508 struct tl_chain *cur_tx;
1513 * Go through our tx list and free mbufs for those
1514 * frames that have been sent.
1516 while (sc->tl_cdata.tl_tx_head != NULL) {
1517 cur_tx = sc->tl_cdata.tl_tx_head;
1518 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1520 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
1523 m_freem(cur_tx->tl_mbuf);
1524 cur_tx->tl_mbuf = NULL;
1526 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
1527 sc->tl_cdata.tl_tx_free = cur_tx;
1528 if (!cur_tx->tl_ptr->tlist_fptr)
1536 * The transmit end of channel interrupt. The adapter triggers this
1537 * interrupt to tell us it hit the end of the current transmit list.
1539 * A note about this: it's possible for a condition to arise where
1540 * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
1541 * You have to avoid this since the chip expects things to go in a
1542 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
1543 * When the TXEOF handler is called, it will free all of the transmitted
1544 * frames and reset the tx_head pointer to NULL. However, a TXEOC
1545 * interrupt should be received and acknowledged before any more frames
1546 * are queued for transmission. If tl_statrt() is called after TXEOF
1547 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
1548 * it could attempt to issue a transmit command prematurely.
1550 * To guard against this, tl_start() will only issue transmit commands
1551 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
1552 * can set this flag once tl_start() has cleared it.
1555 tl_intvec_txeoc(xsc, type)
1559 struct tl_softc *sc;
1566 /* Clear the timeout timer. */
1569 if (sc->tl_cdata.tl_tx_head == NULL) {
1570 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1571 sc->tl_cdata.tl_tx_tail = NULL;
1575 /* First we have to ack the EOC interrupt. */
1576 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
1577 /* Then load the address of the next TX list. */
1578 CSR_WRITE_4(sc, TL_CH_PARM,
1579 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
1580 /* Restart TX channel. */
1581 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1583 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1592 tl_intvec_adchk(xsc, type)
1596 struct tl_softc *sc;
1601 device_printf(sc->tl_dev, "adapter check: %x\n",
1602 (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
1604 tl_softreset(sc, 1);
1607 CMD_SET(sc, TL_CMD_INTSON);
1613 tl_intvec_netsts(xsc, type)
1617 struct tl_softc *sc;
1622 netsts = tl_dio_read16(sc, TL_NETSTS);
1623 tl_dio_write16(sc, TL_NETSTS, netsts);
1625 device_printf(sc->tl_dev, "network status: %x\n", netsts);
1634 struct tl_softc *sc;
1644 /* Disable interrupts */
1645 ints = CSR_READ_2(sc, TL_HOST_INT);
1646 CSR_WRITE_2(sc, TL_HOST_INT, ints);
1647 type = (ints << 16) & 0xFFFF0000;
1648 ivec = (ints & TL_VEC_MASK) >> 5;
1649 ints = (ints & TL_INT_MASK) >> 2;
1654 case (TL_INTR_INVALID):
1656 device_printf(sc->tl_dev, "got an invalid interrupt!\n");
1658 /* Re-enable interrupts but don't ack this one. */
1662 case (TL_INTR_TXEOF):
1663 r = tl_intvec_txeof((void *)sc, type);
1665 case (TL_INTR_TXEOC):
1666 r = tl_intvec_txeoc((void *)sc, type);
1668 case (TL_INTR_STATOFLOW):
1669 tl_stats_update(sc);
1672 case (TL_INTR_RXEOF):
1673 r = tl_intvec_rxeof((void *)sc, type);
1675 case (TL_INTR_DUMMY):
1676 device_printf(sc->tl_dev, "got a dummy interrupt\n");
1679 case (TL_INTR_ADCHK):
1681 r = tl_intvec_adchk((void *)sc, type);
1683 r = tl_intvec_netsts((void *)sc, type);
1685 case (TL_INTR_RXEOC):
1686 r = tl_intvec_rxeoc((void *)sc, type);
1689 device_printf(sc->tl_dev, "bogus interrupt type\n");
1693 /* Re-enable interrupts */
1695 CMD_PUT(sc, TL_CMD_ACK | r | type);
1698 if (ifp->if_snd.ifq_head != NULL)
1699 tl_start_locked(ifp);
1705 tl_stats_update(xsc)
1708 struct tl_softc *sc;
1710 struct tl_stats tl_stats;
1711 struct mii_data *mii;
1714 bzero((char *)&tl_stats, sizeof(struct tl_stats));
1720 p = (u_int32_t *)&tl_stats;
1722 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
1723 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1724 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1725 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1726 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1727 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1729 ifp->if_opackets += tl_tx_goodframes(tl_stats);
1730 ifp->if_collisions += tl_stats.tl_tx_single_collision +
1731 tl_stats.tl_tx_multi_collision;
1732 ifp->if_ipackets += tl_rx_goodframes(tl_stats);
1733 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
1734 tl_rx_overrun(tl_stats);
1735 ifp->if_oerrors += tl_tx_underrun(tl_stats);
1737 if (tl_tx_underrun(tl_stats)) {
1739 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH;
1740 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) {
1743 device_printf(sc->tl_dev, "tx underrun -- increasing "
1744 "tx threshold to %d bytes\n",
1745 (64 * (tx_thresh * 4)));
1746 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1747 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4);
1751 if (sc->tl_timer > 0 && --sc->tl_timer == 0)
1754 callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc);
1756 if (!sc->tl_bitrate) {
1757 mii = device_get_softc(sc->tl_miibus);
1763 * Encapsulate an mbuf chain in a list by coupling the mbuf data
1764 * pointers to the fragment pointers.
1767 tl_encap(sc, c, m_head)
1768 struct tl_softc *sc;
1770 struct mbuf *m_head;
1773 struct tl_frag *f = NULL;
1776 struct ifnet *ifp = sc->tl_ifp;
1779 * Start packing the mbufs in this chain into
1780 * the fragment pointers. Stop when we run out
1781 * of fragments or hit the end of the mbuf chain.
1786 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1787 if (m->m_len != 0) {
1788 if (frag == TL_MAXFRAGS)
1790 total_len+= m->m_len;
1791 c->tl_ptr->tl_frag[frag].tlist_dadr =
1792 vtophys(mtod(m, vm_offset_t));
1793 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
1799 * Handle special cases.
1800 * Special case #1: we used up all 10 fragments, but
1801 * we have more mbufs left in the chain. Copy the
1802 * data into an mbuf cluster. Note that we don't
1803 * bother clearing the values in the other fragment
1804 * pointers/counters; it wouldn't gain us anything,
1805 * and would waste cycles.
1808 struct mbuf *m_new = NULL;
1810 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1811 if (m_new == NULL) {
1812 if_printf(ifp, "no memory for tx list\n");
1815 if (m_head->m_pkthdr.len > MHLEN) {
1816 MCLGET(m_new, M_NOWAIT);
1817 if (!(m_new->m_flags & M_EXT)) {
1819 if_printf(ifp, "no memory for tx list\n");
1823 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1824 mtod(m_new, caddr_t));
1825 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1828 f = &c->tl_ptr->tl_frag[0];
1829 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
1830 f->tlist_dcnt = total_len = m_new->m_len;
1835 * Special case #2: the frame is smaller than the minimum
1836 * frame size. We have to pad it to make the chip happy.
1838 if (total_len < TL_MIN_FRAMELEN) {
1839 if (frag == TL_MAXFRAGS)
1841 "all frags filled but frame still to small!\n");
1842 f = &c->tl_ptr->tl_frag[frag];
1843 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
1844 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
1845 total_len += f->tlist_dcnt;
1849 c->tl_mbuf = m_head;
1850 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
1851 c->tl_ptr->tlist_frsize = total_len;
1852 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1853 c->tl_ptr->tlist_fptr = 0;
1859 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1860 * to the mbuf data regions directly in the transmit lists. We also save a
1861 * copy of the pointers since the transmit list fragment pointers are
1862 * physical addresses.
1868 struct tl_softc *sc;
1872 tl_start_locked(ifp);
1877 tl_start_locked(ifp)
1880 struct tl_softc *sc;
1881 struct mbuf *m_head = NULL;
1883 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
1889 * Check for an available queue slot. If there are none,
1892 if (sc->tl_cdata.tl_tx_free == NULL) {
1893 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1897 start_tx = sc->tl_cdata.tl_tx_free;
1899 while(sc->tl_cdata.tl_tx_free != NULL) {
1900 IF_DEQUEUE(&ifp->if_snd, m_head);
1904 /* Pick a chain member off the free list. */
1905 cur_tx = sc->tl_cdata.tl_tx_free;
1906 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
1908 cur_tx->tl_next = NULL;
1910 /* Pack the data into the list. */
1911 tl_encap(sc, cur_tx, m_head);
1913 /* Chain it together */
1915 prev->tl_next = cur_tx;
1916 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
1921 * If there's a BPF listener, bounce a copy of this frame
1924 BPF_MTAP(ifp, cur_tx->tl_mbuf);
1928 * If there are no packets queued, bail.
1934 * That's all we can stands, we can't stands no more.
1935 * If there are no other transfers pending, then issue the
1936 * TX GO command to the adapter to start things moving.
1937 * Otherwise, just leave the data in the queue and let
1938 * the EOF/EOC interrupt handler send.
1940 if (sc->tl_cdata.tl_tx_head == NULL) {
1941 sc->tl_cdata.tl_tx_head = start_tx;
1942 sc->tl_cdata.tl_tx_tail = cur_tx;
1946 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
1947 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1949 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1953 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
1954 sc->tl_cdata.tl_tx_tail = cur_tx;
1958 * Set a timeout in case the chip goes out to lunch.
1967 struct tl_softc *sc = xsc;
1976 struct tl_softc *sc;
1978 struct ifnet *ifp = sc->tl_ifp;
1979 struct mii_data *mii;
1986 * Cancel pending I/O.
1990 /* Initialize TX FIFO threshold */
1991 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1992 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG);
1994 /* Set PCI burst size */
1995 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG);
1998 * Set 'capture all frames' bit for promiscuous mode.
2000 if (ifp->if_flags & IFF_PROMISC)
2001 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2003 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2006 * Set capture broadcast bit to capture broadcast frames.
2008 if (ifp->if_flags & IFF_BROADCAST)
2009 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2011 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2013 tl_dio_write16(sc, TL_MAXRX, MCLBYTES);
2015 /* Init our MAC address */
2016 tl_setfilt(sc, IF_LLADDR(sc->tl_ifp), 0);
2018 /* Init multicast filter, if needed. */
2021 /* Init circular RX list. */
2022 if (tl_list_rx_init(sc) == ENOBUFS) {
2023 device_printf(sc->tl_dev,
2024 "initialization failed: no memory for rx buffers\n");
2029 /* Init TX pointers. */
2030 tl_list_tx_init(sc);
2032 /* Enable PCI interrupts. */
2033 CMD_SET(sc, TL_CMD_INTSON);
2035 /* Load the address of the rx list */
2036 CMD_SET(sc, TL_CMD_RT);
2037 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
2039 if (!sc->tl_bitrate) {
2040 if (sc->tl_miibus != NULL) {
2041 mii = device_get_softc(sc->tl_miibus);
2045 tl_ifmedia_upd(ifp);
2048 /* Send the RX go command */
2049 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
2051 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2052 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2054 /* Start the stats update counter */
2055 callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc);
2059 * Set media options.
2065 struct tl_softc *sc;
2066 struct mii_data *mii = NULL;
2072 tl_setmode(sc, sc->ifmedia.ifm_media);
2074 mii = device_get_softc(sc->tl_miibus);
2083 * Report current media status.
2086 tl_ifmedia_sts(ifp, ifmr)
2088 struct ifmediareq *ifmr;
2090 struct tl_softc *sc;
2091 struct mii_data *mii;
2096 ifmr->ifm_active = IFM_ETHER;
2098 if (sc->tl_bitrate) {
2099 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
2100 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2102 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2103 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
2104 ifmr->ifm_active |= IFM_HDX;
2106 ifmr->ifm_active |= IFM_FDX;
2109 mii = device_get_softc(sc->tl_miibus);
2111 ifmr->ifm_active = mii->mii_media_active;
2112 ifmr->ifm_status = mii->mii_media_status;
2118 tl_ioctl(ifp, command, data)
2123 struct tl_softc *sc = ifp->if_softc;
2124 struct ifreq *ifr = (struct ifreq *) data;
2130 if (ifp->if_flags & IFF_UP) {
2131 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2132 ifp->if_flags & IFF_PROMISC &&
2133 !(sc->tl_if_flags & IFF_PROMISC)) {
2134 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2136 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2137 !(ifp->if_flags & IFF_PROMISC) &&
2138 sc->tl_if_flags & IFF_PROMISC) {
2139 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2144 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2148 sc->tl_if_flags = ifp->if_flags;
2162 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2164 struct mii_data *mii;
2165 mii = device_get_softc(sc->tl_miibus);
2166 error = ifmedia_ioctl(ifp, ifr,
2167 &mii->mii_media, command);
2171 error = ether_ioctl(ifp, command, data);
2180 struct tl_softc *sc;
2187 if_printf(ifp, "device timeout\n");
2191 tl_softreset(sc, 1);
2196 * Stop the adapter and free any mbufs allocated to the
2201 struct tl_softc *sc;
2210 /* Stop the stats updater. */
2211 callout_stop(&sc->tl_stat_callout);
2213 /* Stop the transmitter */
2214 CMD_CLR(sc, TL_CMD_RT);
2215 CMD_SET(sc, TL_CMD_STOP);
2216 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2218 /* Stop the receiver */
2219 CMD_SET(sc, TL_CMD_RT);
2220 CMD_SET(sc, TL_CMD_STOP);
2221 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2224 * Disable host interrupts.
2226 CMD_SET(sc, TL_CMD_INTSOFF);
2229 * Clear list pointer.
2231 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2234 * Free the RX lists.
2236 for (i = 0; i < TL_RX_LIST_CNT; i++) {
2237 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
2238 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
2239 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
2242 bzero((char *)&sc->tl_ldata->tl_rx_list,
2243 sizeof(sc->tl_ldata->tl_rx_list));
2246 * Free the TX list buffers.
2248 for (i = 0; i < TL_TX_LIST_CNT; i++) {
2249 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
2250 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2251 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2254 bzero((char *)&sc->tl_ldata->tl_tx_list,
2255 sizeof(sc->tl_ldata->tl_tx_list));
2257 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2261 * Stop all chip I/O so that the kernel's probe routines don't
2262 * get confused by errant DMAs when rebooting.
2268 struct tl_softc *sc;
2270 sc = device_get_softc(dev);