sys/dev/tpm/tpm_crb.c

   1 /*-
   2  * Copyright (c) 2018 Stormshield.
   3  * Copyright (c) 2018 Semihalf.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  17  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  24  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  25  * POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include "tpm20.h"
  32
  33 /*
  34  * CRB register space as defined in
  35  * TCG_PC_Client_Platform_TPM_Profile_PTP_2.0_r1.03_v22
  36  */
  37 #define TPM_LOC_STATE                   0x0
  38 #define TPM_LOC_CTRL                    0x8
  39 #define TPM_LOC_STS                             0xC
  40 #define TPM_CRB_INTF_ID                 0x30
  41 #define TPM_CRB_CTRL_EXT                0x38
  42 #define TPM_CRB_CTRL_REQ                0x40
  43 #define TPM_CRB_CTRL_STS                0x44
  44 #define TPM_CRB_CTRL_CANCEL     0x48
  45 #define TPM_CRB_CTRL_START              0x4C
  46 #define TPM_CRB_INT_ENABLE              0x50
  47 #define TPM_CRB_INT_STS                 0x54
  48 #define TPM_CRB_CTRL_CMD_SIZE   0x58
  49 #define TPM_CRB_CTRL_CMD_LADDR  0x5C
  50 #define TPM_CRB_CTRL_CMD_HADDR  0x60
  51 #define TPM_CRB_CTRL_RSP_SIZE   0x64
  52 #define TPM_CRB_CTRL_RSP_ADDR   0x68
  53 #define TPM_CRB_CTRL_RSP_HADDR  0x6c
  54 #define TPM_CRB_DATA_BUFFER             0x80
  55
  56 #define TPM_LOC_STATE_ESTB                      BIT(0)
  57 #define TPM_LOC_STATE_ASSIGNED          BIT(1)
  58 #define TPM_LOC_STATE_ACTIVE_MASK       0x9C
  59 #define TPM_LOC_STATE_VALID                     BIT(7)
  60
  61 #define TPM_CRB_INTF_ID_TYPE_CRB        0x1
  62 #define TPM_CRB_INTF_ID_TYPE            0x7
  63
  64 #define TPM_LOC_CTRL_REQUEST            BIT(0)
  65 #define TPM_LOC_CTRL_RELINQUISH         BIT(1)
  66
  67 #define TPM_CRB_CTRL_REQ_GO_READY       BIT(0)
  68 #define TPM_CRB_CTRL_REQ_GO_IDLE        BIT(1)
  69
  70 #define TPM_CRB_CTRL_STS_ERR_BIT        BIT(0)
  71 #define TPM_CRB_CTRL_STS_IDLE_BIT       BIT(1)
  72
  73 #define TPM_CRB_CTRL_CANCEL_CMD         BIT(0)
  74
  75 #define TPM_CRB_CTRL_START_CMD          BIT(0)
  76
  77 #define TPM_CRB_INT_ENABLE_BIT          BIT(31)
  78
  79 struct tpmcrb_sc {
  80         struct tpm_sc   base;
  81         bus_size_t      cmd_off;
  82         bus_size_t      rsp_off;
  83         size_t          cmd_buf_size;
  84         size_t          rsp_buf_size;
  85 };
  86
  87
  88 int tpmcrb_transmit(struct tpm_sc *sc, size_t size);
  89
  90 static int tpmcrb_acpi_probe(device_t dev);
  91 static int tpmcrb_attach(device_t dev);
  92 static int tpmcrb_detach(device_t dev);
  93
  94 static ACPI_STATUS tpmcrb_fix_buff_offsets(ACPI_RESOURCE *res, void *arg);
  95
  96 static bool tpm_wait_for_u32(struct tpm_sc *sc, bus_size_t off,
  97     uint32_t mask, uint32_t val, int32_t timeout);
  98 static bool tpmcrb_request_locality(struct tpm_sc *sc, int locality);
  99 static void tpmcrb_relinquish_locality(struct tpm_sc *sc);
 100 static bool tpmcrb_cancel_cmd(struct tpm_sc *sc);
 101
 102 char *tpmcrb_ids[] = {"MSFT0101", NULL};
 103
 104 static int
 105 tpmcrb_acpi_probe(device_t dev)
 106 {
 107         int err;
 108         ACPI_TABLE_TPM23 *tbl;
 109         ACPI_STATUS status;
 110         err = ACPI_ID_PROBE(device_get_parent(dev), dev, tpmcrb_ids, NULL);
 111         if (err > 0)
 112                 return (err);
 113         /*Find TPM2 Header*/
 114         status = AcpiGetTable(ACPI_SIG_TPM2, 1, (ACPI_TABLE_HEADER **) &tbl);
 115         if(ACPI_FAILURE(status) ||
 116            tbl->StartMethod != TPM2_START_METHOD_CRB)
 117                 err = ENXIO;
 118
 119         device_set_desc(dev, "Trusted Platform Module 2.0, CRB mode");
 120         return (err);
 121 }
 122
 123 static ACPI_STATUS
 124 tpmcrb_fix_buff_offsets(ACPI_RESOURCE *res, void *arg)
 125 {
 126         struct tpmcrb_sc *crb_sc;
 127         size_t length;
 128         uint32_t base_addr;
 129
 130         crb_sc = (struct tpmcrb_sc *)arg;
 131
 132         if (res->Type != ACPI_RESOURCE_TYPE_FIXED_MEMORY32)
 133                 return (AE_OK);
 134
 135         base_addr = res->Data.FixedMemory32.Address;
 136         length = res->Data.FixedMemory32.AddressLength;
 137
 138         if (crb_sc->cmd_off > base_addr && crb_sc->cmd_off < base_addr + length)
 139                 crb_sc->cmd_off -= base_addr;
 140         if (crb_sc->rsp_off > base_addr && crb_sc->rsp_off < base_addr + length)
 141                 crb_sc->rsp_off -= base_addr;
 142
 143         return (AE_OK);
 144 }
 145
 146 static int
 147 tpmcrb_attach(device_t dev)
 148 {
 149         struct tpmcrb_sc *crb_sc;
 150         struct tpm_sc *sc;
 151         ACPI_HANDLE handle;
 152         ACPI_STATUS status;
 153         int result;
 154
 155         crb_sc = device_get_softc(dev);
 156         sc = &crb_sc->base;
 157         handle = acpi_get_handle(dev);
 158
 159         sc->dev = dev;
 160
 161         sc->mem_rid = 0;
 162         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 163                                              RF_ACTIVE);
 164         if (sc->mem_res == NULL)
 165                 return (ENXIO);
 166
 167         if(!tpmcrb_request_locality(sc, 0)) {
 168                 bus_release_resource(dev, SYS_RES_MEMORY,
 169                     sc->mem_rid, sc->mem_res);
 170                 return (ENXIO);
 171         }
 172
 173         /*
 174          * Disable all interrupts for now, since I don't have a device that
 175          * works in CRB mode and supports them.
 176          */
 177         AND4(sc, TPM_CRB_INT_ENABLE, ~TPM_CRB_INT_ENABLE_BIT);
 178         sc->interrupts = false;
 179
 180         /*
 181          * Read addresses of Tx/Rx buffers and their sizes. Note that they
 182          * can be implemented by a single buffer. Also for some reason CMD
 183          * addr is stored in two 4 byte neighboring registers, whereas RSP is
 184          * stored in a single 8 byte one.
 185          */
 186 #ifdef __amd64__
 187         crb_sc->rsp_off = RD8(sc, TPM_CRB_CTRL_RSP_ADDR);
 188 #else
 189         crb_sc->rsp_off = RD4(sc, TPM_CRB_CTRL_RSP_ADDR);
 190         crb_sc->rsp_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_RSP_HADDR) << 32);
 191 #endif
 192         crb_sc->cmd_off = RD4(sc, TPM_CRB_CTRL_CMD_LADDR);
 193         crb_sc->cmd_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_CMD_HADDR) << 32);
 194         crb_sc->cmd_buf_size = RD4(sc, TPM_CRB_CTRL_CMD_SIZE);
 195         crb_sc->rsp_buf_size = RD4(sc, TPM_CRB_CTRL_RSP_SIZE);
 196
 197         tpmcrb_relinquish_locality(sc);
 198
 199         /* Emulator returns address in acpi space instead of an offset */
 200         status = AcpiWalkResources(handle, "_CRS", tpmcrb_fix_buff_offsets,
 201                     (void *)crb_sc);
 202         if (ACPI_FAILURE(status)) {
 203                 tpmcrb_detach(dev);
 204                 return (ENXIO);
 205         }
 206
 207         if (crb_sc->rsp_off == crb_sc->cmd_off) {
 208                 /*
 209                  * If Tx/Rx buffers are implemented as one they have to be of
 210                  * same size
 211                  */
 212                 if (crb_sc->cmd_buf_size != crb_sc->rsp_buf_size) {
 213                         device_printf(sc->dev,
 214                             "Overlapping Tx/Rx buffers have different sizes\n");
 215                         tpmcrb_detach(dev);
 216                         return (ENXIO);
 217                 }
 218         }
 219
 220         sc->transmit = tpmcrb_transmit;
 221
 222         result = tpm20_init(sc);
 223         if (result != 0)
 224                 tpmcrb_detach(dev);
 225
 226         return (result);
 227 }
 228
 229 static int
 230 tpmcrb_detach(device_t dev)
 231 {
 232         struct tpm_sc *sc;
 233
 234         sc = device_get_softc(dev);
 235         tpm20_release(sc);
 236
 237         if (sc->mem_res != NULL)
 238                 bus_release_resource(dev, SYS_RES_MEMORY,
 239                     sc->mem_rid, sc->mem_res);
 240
 241         return (0);
 242 }
 243
 244 static bool
 245 tpm_wait_for_u32(struct tpm_sc *sc, bus_size_t off, uint32_t mask, uint32_t val,
 246     int32_t timeout)
 247 {
 248
 249         /* Check for condition */
 250         if ((RD4(sc, off) & mask) == val)
 251                 return (true);
 252
 253         while (timeout > 0) {
 254                 if ((RD4(sc, off) & mask) == val)
 255                         return (true);
 256
 257                 pause("TPM in polling mode", 1);
 258                 timeout -= tick;
 259         }
 260         return (false);
 261 }
 262
 263 static bool
 264 tpmcrb_request_locality(struct tpm_sc *sc, int locality)
 265 {
 266         uint32_t mask;
 267
 268         /* Currently we only support Locality 0 */
 269         if (locality != 0)
 270                 return (false);
 271
 272         mask = TPM_LOC_STATE_VALID | TPM_LOC_STATE_ASSIGNED;
 273
 274         OR4(sc, TPM_LOC_CTRL, TPM_LOC_CTRL_REQUEST);
 275         if (!tpm_wait_for_u32(sc, TPM_LOC_STATE, mask, mask, TPM_TIMEOUT_C))
 276                 return (false);
 277
 278         return (true);
 279 }
 280
 281 static void
 282 tpmcrb_relinquish_locality(struct tpm_sc *sc)
 283 {
 284
 285         OR4(sc, TPM_LOC_CTRL, TPM_LOC_CTRL_RELINQUISH);
 286 }
 287
 288 static bool
 289 tpmcrb_cancel_cmd(struct tpm_sc *sc)
 290 {
 291         uint32_t mask = ~0;
 292
 293         WR4(sc, TPM_CRB_CTRL_CANCEL, TPM_CRB_CTRL_CANCEL_CMD);
 294         if (!tpm_wait_for_u32(sc, TPM_CRB_CTRL_START,
 295                     mask, ~mask, TPM_TIMEOUT_B)) {
 296                 device_printf(sc->dev,
 297                     "Device failed to cancel command\n");
 298                 return (false);
 299         }
 300
 301         WR4(sc, TPM_CRB_CTRL_CANCEL, !TPM_CRB_CTRL_CANCEL_CMD);
 302         return (true);
 303 }
 304
 305 int
 306 tpmcrb_transmit(struct tpm_sc *sc, size_t length)
 307 {
 308         struct tpmcrb_sc *crb_sc;
 309         uint32_t mask, curr_cmd;
 310         int timeout, bytes_available;
 311
 312         crb_sc = (struct tpmcrb_sc *)sc;
 313
 314         sx_assert(&sc->dev_lock, SA_XLOCKED);
 315
 316         if (length > crb_sc->cmd_buf_size) {
 317                 device_printf(sc->dev,
 318                     "Requested transfer is bigger than buffer size\n");
 319                 return (E2BIG);
 320         }
 321
 322         if (RD4(sc, TPM_CRB_CTRL_STS) & TPM_CRB_CTRL_STS_ERR_BIT) {
 323                 device_printf(sc->dev,
 324                     "Device has Error bit set\n");
 325                 return (EIO);
 326         }
 327         if (!tpmcrb_request_locality(sc, 0)) {
 328                 device_printf(sc->dev,
 329                     "Failed to obtain locality\n");
 330                 return (EIO);
 331         }
 332         /* Clear cancellation bit */
 333         WR4(sc, TPM_CRB_CTRL_CANCEL, !TPM_CRB_CTRL_CANCEL_CMD);
 334
 335         /* Switch device to idle state if necessary */
 336         if (!(RD4(sc, TPM_CRB_CTRL_STS) & TPM_CRB_CTRL_STS_IDLE_BIT)) {
 337                 OR4(sc, TPM_CRB_CTRL_REQ, TPM_CRB_CTRL_REQ_GO_IDLE);
 338
 339                 mask = TPM_CRB_CTRL_STS_IDLE_BIT;
 340                 if (!tpm_wait_for_u32(sc, TPM_CRB_CTRL_STS,
 341                             mask, mask, TPM_TIMEOUT_C)) {
 342                         device_printf(sc->dev,
 343                             "Failed to transition to idle state\n");
 344                         return (EIO);
 345                 }
 346         }
 347         /* Switch to ready state */
 348         OR4(sc, TPM_CRB_CTRL_REQ, TPM_CRB_CTRL_REQ_GO_READY);
 349
 350         mask = TPM_CRB_CTRL_REQ_GO_READY;
 351         if (!tpm_wait_for_u32(sc, TPM_CRB_CTRL_STS,
 352                     mask, !mask, TPM_TIMEOUT_C)) {
 353                 device_printf(sc->dev,
 354                     "Failed to transition to ready state\n");
 355                 return (EIO);
 356         }
 357
 358         /*
 359          * Calculate timeout for current command.
 360          * Command code is passed in bytes 6-10.
 361          */
 362         curr_cmd = be32toh(*(uint32_t *) (&sc->buf[6]));
 363         timeout = tpm20_get_timeout(curr_cmd);
 364
 365         /* Send command and tell device to process it. */
 366         bus_write_region_stream_1(sc->mem_res, crb_sc->cmd_off,
 367             sc->buf, length);
 368         bus_barrier(sc->mem_res, crb_sc->cmd_off,
 369             length, BUS_SPACE_BARRIER_WRITE);
 370
 371         WR4(sc, TPM_CRB_CTRL_START, TPM_CRB_CTRL_START_CMD);
 372         bus_barrier(sc->mem_res, TPM_CRB_CTRL_START,
 373             4, BUS_SPACE_BARRIER_WRITE);
 374
 375         mask = ~0;
 376         if (!tpm_wait_for_u32(sc, TPM_CRB_CTRL_START, mask, ~mask, timeout)) {
 377                 device_printf(sc->dev,
 378                     "Timeout while waiting for device to process cmd\n");
 379                 if (!tpmcrb_cancel_cmd(sc))
 380                         return (EIO);
 381         }
 382
 383         /* Read response header. Length is passed in bytes 2 - 6. */
 384         bus_read_region_stream_1(sc->mem_res, crb_sc->rsp_off,
 385             sc->buf, TPM_HEADER_SIZE);
 386         bytes_available = be32toh(*(uint32_t *) (&sc->buf[2]));
 387
 388         if (bytes_available > TPM_BUFSIZE || bytes_available < TPM_HEADER_SIZE) {
 389                 device_printf(sc->dev,
 390                     "Incorrect response size: %d\n",
 391                     bytes_available);
 392                 return (EIO);
 393         }
 394
 395         bus_read_region_stream_1(sc->mem_res, crb_sc->rsp_off + TPM_HEADER_SIZE,
 396               &sc->buf[TPM_HEADER_SIZE], bytes_available - TPM_HEADER_SIZE);
 397
 398         OR4(sc, TPM_CRB_CTRL_REQ, TPM_CRB_CTRL_REQ_GO_IDLE);
 399
 400         tpmcrb_relinquish_locality(sc);
 401         sc->pending_data_length = bytes_available;
 402
 403         return (0);
 404 }
 405
 406 /* ACPI Driver */
 407 static device_method_t  tpmcrb_methods[] = {
 408         DEVMETHOD(device_probe,         tpmcrb_acpi_probe),
 409         DEVMETHOD(device_attach,        tpmcrb_attach),
 410         DEVMETHOD(device_detach,        tpmcrb_detach),
 411         DEVMETHOD(device_shutdown,      tpm20_shutdown),
 412         DEVMETHOD(device_suspend,       tpm20_suspend),
 413         {0, 0}
 414 };
 415 static driver_t tpmcrb_driver = {
 416         "tpmcrb", tpmcrb_methods, sizeof(struct tpmcrb_sc),
 417 };
 418
 419 devclass_t tpmcrb_devclass;
 420 DRIVER_MODULE(tpmcrb, acpi, tpmcrb_driver, tpmcrb_devclass, 0, 0);