sys/dev/trm/trm.c

   1 /*
   2  *      O.S   : FreeBSD CAM
   3  *      FILE NAME  : trm.c
   4  *           BY    : C.L. Huang         (ching@tekram.com.tw)
   5  *                   Erich Chen     (erich@tekram.com.tw)
   6  *      Description: Device Driver for Tekram SCSI adapters
   7  *                   DC395U/UW/F ,DC315/U(TRM-S1040)
   8  *                   DC395U2D/U2W(TRM-S2080)
   9  *                   PCI SCSI Bus Master Host Adapter
  10  *                   (SCSI chip set used Tekram ASIC TRM-S1040,TRM-S2080)
  11  */
  12
  13 #include <sys/cdefs.h>
  14 __FBSDID("$FreeBSD$");
  15
  16 /*
  17  *      HISTORY:
  18  *
  19  *      REV#    DATE    NAME            DESCRIPTION
  20  *  1.05   05/01/1999  ERICH CHEN  First released for 3.x.x (CAM)
  21  *  1.06   07/29/1999  ERICH CHEN  Modify for NEW PCI
  22  *  1.07   12/12/1999  ERICH CHEN  Modify for 3.3.x ,DCB no free
  23  *  1.08   06/12/2000  ERICH CHEN  Modify for 4.x.x
  24  *  1.09   11/03/2000  ERICH CHEN  Modify for 4.1.R ,new sim
  25  *  1.10   10/10/2001  Oscar Feng  Fixed CAM rescan hang up bug.
  26  *  1.11   10/13/2001  Oscar Feng  Fixed wrong Async speed display bug.
  27  */
  28
  29 /*-
  30  * (C)Copyright 1995-2001 Tekram Technology Co.,Ltd.
  31  *
  32  * Redistribution and use in source and binary forms, with or without
  33  * modification, are permitted provided that the following conditions
  34  * are met:
  35  * 1. Redistributions of source code must retain the above copyright
  36  *    notice, this list of conditions and the following disclaimer.
  37  * 2. Redistributions in binary form must reproduce the above copyright
  38  *    notice, this list of conditions and the following disclaimer in the
  39  *    documentation and/or other materials provided with the distribution.
  40  * 3. The name of the author may not be used to endorse or promote products
  41  *    derived from this software without specific prior written permission.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  44  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  45  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  46  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  47  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  48  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  49  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  50  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  51  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  52  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  53  *
  54  */
  55
  56 /*
  57  * Imported into FreeBSD source repository, and updated to compile under
  58  * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <se@FreeBSD.Org>, 1996-12-17
  59  */
  60
  61 /*
  62  * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard
  63  * <doginou@ci0.org>, 2002-03-04
  64  */
  65
  66 #include <sys/param.h>
  67
  68 #include <sys/systm.h>
  69 #include <sys/malloc.h>
  70 #include <sys/queue.h>
  71 #if __FreeBSD_version >= 500000
  72 #include <sys/bio.h>
  73 #endif
  74 #include <sys/buf.h>
  75 #include <sys/bus.h>
  76 #include <sys/kernel.h>
  77 #include <sys/module.h>
  78
  79 #include <vm/vm.h>
  80 #include <vm/pmap.h>
  81
  82 #include <dev/pci/pcivar.h>
  83 #include <dev/pci/pcireg.h>
  84 #include <machine/resource.h>
  85 #include <machine/bus.h>
  86 #include <sys/rman.h>
  87
  88 #include <cam/cam.h>
  89 #include <cam/cam_ccb.h>
  90 #include <cam/cam_sim.h>
  91 #include <cam/cam_xpt_sim.h>
  92 #include <cam/cam_debug.h>
  93
  94 #include <cam/scsi/scsi_all.h>
  95 #include <cam/scsi/scsi_message.h>
  96
  97 #include <dev/trm/trm.h>
  98
  99 #define trm_reg_read8(reg)      bus_space_read_1(pACB->tag, pACB->bsh, reg)
 100 #define trm_reg_read16(reg)     bus_space_read_2(pACB->tag, pACB->bsh, reg)
 101 #define trm_reg_read32(reg)     bus_space_read_4(pACB->tag, pACB->bsh, reg)
 102 #define trm_reg_write8(value,reg)       bus_space_write_1(pACB->tag, pACB->bsh,\
 103                 reg, value)
 104 #define trm_reg_write16(value,reg)      bus_space_write_2(pACB->tag, pACB->bsh,\
 105                 reg, value)
 106 #define trm_reg_write32(value,reg)      bus_space_write_4(pACB->tag, pACB->bsh,\
 107                 reg, value)
 108
 109 #define PCI_Vendor_ID_TEKRAM    0x1DE1
 110 #define PCI_Device_ID_TRM_S1040 0x0391
 111 #define PCI_DEVICEID_TRMS1040   0x03911DE1
 112 #define PCI_DEVICEID_TRMS2080   0x03921DE1
 113
 114 #ifdef trm_DEBUG1
 115 #define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg)
 116 #else
 117 #define TRM_DPRINTF(fmt, arg...) {}
 118 #endif /* TRM_DEBUG */
 119
 120 static void     trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB);
 121 static void     NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB);
 122 static u_int8_t NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr);
 123 static void     NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB);
 124 static void     NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData);
 125 static void     NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr);
 126 static void     NVRAM_trm_wait_30us(PACB pACB);
 127
 128 static void     trm_Interrupt(void *vpACB);
 129 static void     trm_DataOutPhase0(PACB pACB, PSRB pSRB,
 130                                          u_int16_t * pscsi_status);
 131 static void     trm_DataInPhase0(PACB pACB, PSRB pSRB,
 132                                         u_int16_t * pscsi_status);
 133 static void     trm_CommandPhase0(PACB pACB, PSRB pSRB,
 134                                          u_int16_t * pscsi_status);
 135 static void     trm_StatusPhase0(PACB pACB, PSRB pSRB,
 136                                         u_int16_t * pscsi_status);
 137 static void     trm_MsgOutPhase0(PACB pACB, PSRB pSRB,
 138                                         u_int16_t * pscsi_status);
 139 static void     trm_MsgInPhase0(PACB pACB, PSRB pSRB,
 140                                         u_int16_t * pscsi_status);
 141 static void     trm_DataOutPhase1(PACB pACB, PSRB pSRB,
 142                                          u_int16_t * pscsi_status);
 143 static void     trm_DataInPhase1(PACB pACB, PSRB pSRB,
 144                                         u_int16_t * pscsi_status);
 145 static void     trm_CommandPhase1(PACB pACB, PSRB pSRB,
 146                                          u_int16_t * pscsi_status);
 147 static void     trm_StatusPhase1(PACB pACB, PSRB pSRB,
 148                                         u_int16_t * pscsi_status);
 149 static void     trm_MsgOutPhase1(PACB pACB, PSRB pSRB,
 150                                         u_int16_t * pscsi_status);
 151 static void     trm_MsgInPhase1(PACB pACB, PSRB pSRB,
 152                                         u_int16_t * pscsi_status);
 153 static void     trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status);
 154 static void     trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status);
 155 static void     trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB);
 156 static void     trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir);
 157 static void     trm_Disconnect(PACB pACB);
 158 static void     trm_Reselect(PACB pACB);
 159 static void     trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB);
 160 static void     trm_DoingSRB_Done(PACB pACB);
 161 static void     trm_ScsiRstDetect(PACB pACB);
 162 static void     trm_ResetSCSIBus(PACB pACB);
 163 static void     trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB);
 164 static void     trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB);
 165 static void     trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB);
 166 static void     trm_SendSRB(PACB pACB, PSRB pSRB);
 167 static int      trm_probe(device_t tag);
 168 static int      trm_attach(device_t tag);
 169 static void     trm_reset(PACB pACB);
 170
 171 static u_int16_t        trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB);
 172
 173 static int      trm_initAdapter(PACB pACB, u_int16_t unit);
 174 static void     trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,
 175                                         u_int32_t i, u_int32_t j);
 176 static int      trm_initSRB(PACB pACB);
 177 static void     trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit);
 178 /* CAM SIM entry points */
 179 #define ccb_trmsrb_ptr spriv_ptr0
 180 #define ccb_trmacb_ptr spriv_ptr1
 181 static void     trm_action(struct cam_sim *psim, union ccb *pccb);
 182 static void     trm_poll(struct cam_sim *psim);
 183
 184
 185 static void * trm_SCSI_phase0[] = {
 186         trm_DataOutPhase0,    /* phase:0 */
 187         trm_DataInPhase0,     /* phase:1 */
 188         trm_CommandPhase0,    /* phase:2 */
 189         trm_StatusPhase0,     /* phase:3 */
 190         trm_Nop0,             /* phase:4 */
 191         trm_Nop1,             /* phase:5 */
 192         trm_MsgOutPhase0,     /* phase:6 */
 193         trm_MsgInPhase0,      /* phase:7 */
 194 };
 195
 196 /*
 197  *
 198  *          stateV = (void *) trm_SCSI_phase1[phase]
 199  *
 200  */
 201 static void * trm_SCSI_phase1[] = {
 202         trm_DataOutPhase1,    /* phase:0 */
 203         trm_DataInPhase1,     /* phase:1 */
 204         trm_CommandPhase1,    /* phase:2 */
 205         trm_StatusPhase1,     /* phase:3 */
 206         trm_Nop0,             /* phase:4 */
 207         trm_Nop1,             /* phase:5 */
 208         trm_MsgOutPhase1,     /* phase:6 */
 209         trm_MsgInPhase1,      /* phase:7 */
 210 };
 211
 212
 213 NVRAMTYPE trm_eepromBuf[TRM_MAX_ADAPTER_NUM];
 214 /*
 215  *Fast20:  000   50ns, 20.0 Mbytes/s
 216  *             001       75ns, 13.3 Mbytes/s
 217  *             010      100ns, 10.0 Mbytes/s
 218  *             011      125ns,  8.0 Mbytes/s
 219  *             100      150ns,  6.6 Mbytes/s
 220  *             101      175ns,  5.7 Mbytes/s
 221  *             110      200ns,  5.0 Mbytes/s
 222  *             111      250ns,  4.0 Mbytes/s
 223  *
 224  *Fast40:  000   25ns, 40.0 Mbytes/s
 225  *             001       50ns, 20.0 Mbytes/s
 226  *             010       75ns, 13.3 Mbytes/s
 227  *             011      100ns, 10.0 Mbytes/s
 228  *             100      125ns,  8.0 Mbytes/s
 229  *             101      150ns,  6.6 Mbytes/s
 230  *             110      175ns,  5.7 Mbytes/s
 231  *             111      200ns,  5.0 Mbytes/s
 232  */
 233                                              /* real period: */
 234 u_int8_t dc395x_clock_period[] = {
 235         12,/*  48  ns 20   MB/sec */
 236         18,/*  72  ns 13.3 MB/sec */
 237         25,/* 100  ns 10.0 MB/sec */
 238         31,/* 124  ns  8.0 MB/sec */
 239         37,/* 148  ns  6.6 MB/sec */
 240         43,/* 172  ns  5.7 MB/sec */
 241         50,/* 200  ns  5.0 MB/sec */
 242         62 /* 248  ns  4.0 MB/sec */
 243 };
 244
 245 u_int8_t dc395u2x_clock_period[]={
 246         10,/*  25  ns 40.0 MB/sec */
 247         12,/*  48  ns 20.0 MB/sec */
 248         18,/*  72  ns 13.3 MB/sec */
 249         25,/* 100  ns 10.0 MB/sec */
 250         31,/* 124  ns  8.0 MB/sec */
 251         37,/* 148  ns  6.6 MB/sec */
 252         43,/* 172  ns  5.7 MB/sec */
 253         50,/* 200  ns  5.0 MB/sec */
 254 };
 255
 256 #define  dc395x_tinfo_period           dc395x_clock_period
 257 #define  dc395u2x_tinfo_period         dc395u2x_clock_period
 258
 259 static PSRB
 260 trm_GetSRB(PACB pACB)
 261 {
 262         int     intflag;
 263         PSRB    pSRB;
 264
 265         intflag = splcam();
 266         pSRB = pACB->pFreeSRB;
 267         if (pSRB) {
 268                 pACB->pFreeSRB = pSRB->pNextSRB;
 269                 pSRB->pNextSRB = NULL;
 270         }
 271         splx(intflag);
 272         return (pSRB);
 273 }
 274
 275 static void
 276 trm_RewaitSRB0(PDCB pDCB, PSRB pSRB)
 277 {
 278         PSRB    psrb1;
 279         int     intflag;
 280
 281         intflag = splcam();
 282         if ((psrb1 = pDCB->pWaitingSRB)) {
 283                 pSRB->pNextSRB = psrb1;
 284                 pDCB->pWaitingSRB = pSRB;
 285         } else {
 286                 pSRB->pNextSRB = NULL;
 287                 pDCB->pWaitingSRB = pSRB;
 288                 pDCB->pWaitingLastSRB = pSRB;
 289         }
 290         splx(intflag);
 291 }
 292
 293 static void
 294 trm_RewaitSRB(PDCB pDCB, PSRB pSRB)
 295 {
 296         PSRB    psrb1;
 297         int     intflag;
 298
 299         intflag = splcam();
 300         pDCB->GoingSRBCnt--;
 301         psrb1 = pDCB->pGoingSRB;
 302         if (pSRB == psrb1)
 303                 /*
 304                  * if this SRB is GoingSRB
 305                  * remove this SRB from GoingSRB Q
 306                  */
 307                 pDCB->pGoingSRB = psrb1->pNextSRB;
 308         else {
 309                 /*
 310                  * if this SRB is not current GoingSRB
 311                  * remove this SRB from GoingSRB Q
 312                  */
 313                 while (pSRB != psrb1->pNextSRB)
 314                         psrb1 = psrb1->pNextSRB;
 315                 psrb1->pNextSRB = pSRB->pNextSRB;
 316                 if (pSRB == pDCB->pGoingLastSRB)
 317                         pDCB->pGoingLastSRB = psrb1;
 318         }
 319         if ((psrb1 = pDCB->pWaitingSRB)) {
 320                 /*
 321                  * if WaitingSRB Q is not NULL
 322                  * Q back this SRB into WaitingSRB
 323                  */
 324
 325                 pSRB->pNextSRB = psrb1;
 326                 pDCB->pWaitingSRB = pSRB;
 327         } else {
 328                 pSRB->pNextSRB = NULL;
 329                 pDCB->pWaitingSRB = pSRB;
 330                 pDCB->pWaitingLastSRB = pSRB;
 331         }
 332         splx(intflag);
 333 }
 334
 335 static void
 336 trm_DoWaitingSRB(PACB pACB)
 337 {
 338         int     intflag;
 339         PDCB    ptr, ptr1;
 340         PSRB    pSRB;
 341
 342         intflag = splcam();
 343         if (!(pACB->pActiveDCB) &&
 344             !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) {
 345                 ptr = pACB->pDCBRunRobin;
 346                 if (!ptr) {
 347                         ptr = pACB->pLinkDCB;
 348                         pACB->pDCBRunRobin = ptr;
 349                 }
 350                 ptr1 = ptr;
 351                 for (;ptr1 ;) {
 352                         pACB->pDCBRunRobin = ptr1->pNextDCB;
 353                         if (!(ptr1->MaxActiveCommandCnt > ptr1->GoingSRBCnt)
 354                             || !(pSRB = ptr1->pWaitingSRB)) {
 355                                 if (pACB->pDCBRunRobin == ptr)
 356                                         break;
 357                                 ptr1 = ptr1->pNextDCB;
 358                         } else {
 359                                 if (!trm_StartSCSI(pACB, ptr1, pSRB)) {
 360                                 /*
 361                                  * If trm_StartSCSI return 0 :
 362                                  * current interrupt status is interrupt enable
 363                                  * It's said that SCSI processor is unoccupied
 364                                  */
 365                                         ptr1->GoingSRBCnt++;
 366                                         if (ptr1->pWaitingLastSRB == pSRB) {
 367                                                 ptr1->pWaitingSRB = NULL;
 368                                                 ptr1->pWaitingLastSRB = NULL;
 369                                         } else
 370                                                 ptr1->pWaitingSRB = pSRB->pNextSRB;
 371                                         pSRB->pNextSRB = NULL;
 372                                         if (ptr1->pGoingSRB)
 373                                                 ptr1->pGoingLastSRB->pNextSRB = pSRB;
 374                                         else
 375                                                 ptr1->pGoingSRB = pSRB;
 376                                         ptr1->pGoingLastSRB = pSRB;
 377                                 }
 378                                 break;
 379                         }
 380                 }
 381         }
 382         splx(intflag);
 383         return;
 384 }
 385
 386 static void
 387 trm_SRBwaiting(PDCB pDCB, PSRB pSRB)
 388 {
 389
 390         if (pDCB->pWaitingSRB) {
 391                 pDCB->pWaitingLastSRB->pNextSRB = pSRB;
 392                 pDCB->pWaitingLastSRB = pSRB;
 393                 pSRB->pNextSRB = NULL;
 394         } else {
 395                 pDCB->pWaitingSRB = pSRB;
 396                 pDCB->pWaitingLastSRB = pSRB;
 397         }
 398 }
 399
 400 static u_int32_t
 401 trm_get_sense_bufaddr(PACB pACB, PSRB pSRB)
 402 {
 403         int offset;
 404
 405         offset = pSRB->TagNumber;
 406         return (pACB->sense_busaddr +
 407             (offset * sizeof(struct scsi_sense_data)));
 408 }
 409
 410 static struct scsi_sense_data *
 411 trm_get_sense_buf(PACB pACB, PSRB pSRB)
 412 {
 413         int offset;
 414
 415         offset = pSRB->TagNumber;
 416         return (&pACB->sense_buffers[offset]);
 417 }
 418 static void
 419 trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
 420 {
 421         int             flags;
 422         PACB            pACB;
 423         PSRB            pSRB;
 424         union ccb       *ccb;
 425         u_long          totalxferlen=0;
 426
 427         flags = splcam();
 428         pSRB = (PSRB)arg;
 429         ccb = pSRB->pccb;
 430         pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr;
 431         TRM_DPRINTF("trm_ExecuteSRB..........\n");
 432         if (nseg != 0) {
 433                 PSEG                    psg;
 434                 bus_dma_segment_t       *end_seg;
 435                 int                     op;
 436
 437                 /* Copy the segments into our SG list */
 438                 end_seg = dm_segs + nseg;
 439                 psg = pSRB->pSRBSGL;
 440                 while (dm_segs < end_seg) {
 441                         psg->address = dm_segs->ds_addr;
 442                         psg->length = (u_long)dm_segs->ds_len;
 443                         totalxferlen += dm_segs->ds_len;
 444                         psg++;
 445                         dm_segs++;
 446                 }
 447                 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
 448                         op = BUS_DMASYNC_PREREAD;
 449                 } else {
 450                         op = BUS_DMASYNC_PREWRITE;
 451                 }
 452                 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op);
 453         }
 454         pSRB->RetryCnt = 0;
 455         pSRB->SRBTotalXferLength = totalxferlen;
 456         pSRB->SRBSGCount = nseg;
 457         pSRB->SRBSGIndex = 0;
 458         pSRB->AdaptStatus = 0;
 459         pSRB->TargetStatus = 0;
 460         pSRB->MsgCnt = 0;
 461         pSRB->SRBStatus = 0;
 462         pSRB->SRBFlag = 0;
 463         pSRB->SRBState = 0;
 464         pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */
 465
 466         if (ccb->ccb_h.status != CAM_REQ_INPROG) {
 467                 if (nseg != 0)
 468                         bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap);
 469                 pSRB->pNextSRB = pACB->pFreeSRB;
 470                 pACB->pFreeSRB = pSRB;
 471                 xpt_done(ccb);
 472                 splx(flags);
 473                 return;
 474         }
 475         ccb->ccb_h.status |= CAM_SIM_QUEUED;
 476         trm_SendSRB(pACB, pSRB);
 477         splx(flags);
 478         return;
 479 }
 480
 481 static void
 482 trm_SendSRB(PACB pACB, PSRB pSRB)
 483 {
 484         PDCB    pDCB;
 485
 486         pDCB = pSRB->pSRBDCB;
 487         if (!(pDCB->MaxActiveCommandCnt > pDCB->GoingSRBCnt) || (pACB->pActiveDCB)
 488             || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) {
 489                 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxActiveCommandCnt);
 490                 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt);
 491                 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB);
 492                 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag);
 493                 trm_SRBwaiting(pDCB, pSRB);
 494                 goto SND_EXIT;
 495         }
 496
 497         if (pDCB->pWaitingSRB) {
 498                 trm_SRBwaiting(pDCB, pSRB);
 499                 pSRB = pDCB->pWaitingSRB;
 500                 pDCB->pWaitingSRB = pSRB->pNextSRB;
 501                 pSRB->pNextSRB = NULL;
 502         }
 503
 504         if (!trm_StartSCSI(pACB, pDCB, pSRB)) {
 505         /*
 506          * If trm_StartSCSI return 0 :
 507          * current interrupt status is interrupt enable
 508          * It's said that SCSI processor is unoccupied
 509          */
 510                 pDCB->GoingSRBCnt++; /* stack waiting SRB*/
 511                 if (pDCB->pGoingSRB) {
 512                         pDCB->pGoingLastSRB->pNextSRB = pSRB;
 513                         pDCB->pGoingLastSRB = pSRB;
 514                 } else {
 515                         pDCB->pGoingSRB = pSRB;
 516                         pDCB->pGoingLastSRB = pSRB;
 517                 }
 518         } else {
 519         /*
 520          * If trm_StartSCSI return 1 :
 521          * current interrupt status is interrupt disreenable
 522          * It's said that SCSI processor has more one SRB need to do
 523          */
 524                 trm_RewaitSRB0(pDCB, pSRB);
 525         }
 526 SND_EXIT:
 527         return;
 528 }
 529
 530
 531 static void
 532 trm_action(struct cam_sim *psim, union ccb *pccb)
 533 {
 534         PACB    pACB;
 535         int     actionflags;
 536         u_int   target_id,target_lun;
 537
 538         CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n"));
 539
 540         actionflags = splcam();
 541         pACB = (PACB) cam_sim_softc(psim);
 542         target_id  = pccb->ccb_h.target_id;
 543         target_lun = pccb->ccb_h.target_lun;
 544
 545         switch (pccb->ccb_h.func_code) {
 546                 /*
 547                  * Execute the requested I/O operation
 548                  */
 549                 case XPT_SCSI_IO: {
 550                         PDCB                    pDCB = NULL;
 551                         PSRB                    pSRB;
 552                         struct ccb_scsiio       *pcsio;
 553                         int                     error;
 554
 555                         pcsio = &pccb->csio;
 556                         TRM_DPRINTF(" XPT_SCSI_IO \n");
 557                         TRM_DPRINTF("trm: target_id= %d target_lun= %d \n"
 558                              ,target_id, target_lun);
 559                         TRM_DPRINTF(
 560                             "pACB->scan_devices[target_id][target_lun]= %d \n"
 561                             ,pACB->scan_devices[target_id][target_lun]);
 562                         if ((pccb->ccb_h.status & CAM_STATUS_MASK) !=
 563                             CAM_REQ_INPROG) {
 564                                 xpt_done(pccb);
 565                                 splx(actionflags);
 566                                 return;
 567                         }
 568                         pDCB = &pACB->DCBarray[target_id][target_lun];
 569                         if (!(pDCB->DCBstatus & DS_IN_QUEUE)) {
 570                                 pACB->scan_devices[target_id][target_lun] = 1;
 571                                 trm_initDCB(pACB, pDCB, pACB->AdapterUnit,
 572                                     target_id, target_lun);
 573                         }
 574                         /*
 575                          * Assign an SRB and connect it with this ccb.
 576                          */
 577                         pSRB = trm_GetSRB(pACB);
 578                         if (!pSRB) {
 579                                 /* Freeze SIMQ */
 580                                 pccb->ccb_h.status = CAM_RESRC_UNAVAIL;
 581                                 xpt_done(pccb);
 582                                 splx(actionflags);
 583                                 return;
 584                         }
 585                         pSRB->pSRBDCB = pDCB;
 586                         pccb->ccb_h.ccb_trmsrb_ptr = pSRB;
 587                         pccb->ccb_h.ccb_trmacb_ptr = pACB;
 588                         pSRB->pccb = pccb;
 589                         pSRB->ScsiCmdLen = pcsio->cdb_len;
 590                         /*
 591                          * move layer of CAM command block to layer of SCSI
 592                          * Request Block for SCSI processor command doing
 593                          */
 594                         if ((pccb->ccb_h.flags & CAM_CDB_POINTER) != 0) {
 595                                 if ((pccb->ccb_h.flags & CAM_CDB_PHYS) == 0) {
 596                                         bcopy(pcsio->cdb_io.cdb_ptr,pSRB->CmdBlock
 597                                             ,pcsio->cdb_len);
 598                                 } else {
 599                                         pccb->ccb_h.status = CAM_REQ_INVALID;
 600                                         pSRB->pNextSRB = pACB->pFreeSRB;
 601                                         pACB->pFreeSRB=  pSRB;
 602                                         xpt_done(pccb);
 603                                         splx(actionflags);
 604                                         return;
 605                                 }
 606                         } else
 607                                 bcopy(pcsio->cdb_io.cdb_bytes,
 608                                     pSRB->CmdBlock, pcsio->cdb_len);
 609                         error = bus_dmamap_load_ccb(pACB->buffer_dmat,
 610                                                     pSRB->dmamap,
 611                                                     pccb,
 612                                                     trm_ExecuteSRB,
 613                                                     pSRB,
 614                                                     0);
 615                         if (error == EINPROGRESS) {
 616                                 xpt_freeze_simq(pACB->psim, 1);
 617                                 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 618                         }
 619                         break;
 620                 }
 621                 /*
 622                  * Path routing inquiry
 623                  * Path Inquiry CCB
 624                  */
 625                 case XPT_PATH_INQ: {
 626                         struct ccb_pathinq *cpi = &pccb->cpi;
 627
 628                         TRM_DPRINTF(" XPT_PATH_INQ \n");
 629                         cpi->version_num = 1;
 630                         cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16;
 631                         cpi->target_sprt = 0;
 632                         cpi->hba_misc = 0;
 633                         cpi->hba_eng_cnt = 0;
 634                         cpi->max_target = 15 ;
 635                         cpi->max_lun = pACB->max_lun;        /* 7 or 0 */
 636                         cpi->initiator_id = pACB->AdaptSCSIID;
 637                         cpi->bus_id = cam_sim_bus(psim);
 638                         cpi->base_transfer_speed = 3300;
 639                         strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
 640                         strlcpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN);
 641                         strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
 642                         cpi->unit_number = cam_sim_unit(psim);
 643                         cpi->transport = XPORT_SPI;
 644                         cpi->transport_version = 2;
 645                         cpi->protocol = PROTO_SCSI;
 646                         cpi->protocol_version = SCSI_REV_2;
 647                         cpi->ccb_h.status = CAM_REQ_CMP;
 648                         xpt_done(pccb);
 649                         break;
 650                 }
 651                 /*
 652                  * XPT_ABORT = 0x10, Abort the specified CCB
 653                  * Abort XPT request CCB
 654                  */
 655                 case XPT_ABORT:
 656                         TRM_DPRINTF(" XPT_ABORT \n");
 657                         pccb->ccb_h.status = CAM_REQ_INVALID;
 658                         xpt_done(pccb);
 659                         break;
 660                 /*
 661                  * Reset the specified SCSI bus
 662                  * Reset SCSI Bus CCB
 663                  */
 664                 case XPT_RESET_BUS: {
 665                         int i;
 666
 667                         TRM_DPRINTF(" XPT_RESET_BUS \n");
 668                         trm_reset(pACB);
 669                         pACB->ACBFlag=0;
 670                         for (i=0; i<500; i++)
 671                                 DELAY(1000);
 672                         pccb->ccb_h.status = CAM_REQ_CMP;
 673                         xpt_done(pccb);
 674                         break;
 675                 }
 676                 /*
 677                  * Bus Device Reset the specified SCSI device
 678                  * Reset SCSI Device CCB
 679                  */
 680                 case XPT_RESET_DEV:
 681                 /*
 682                  * Don't (yet?) support vendor
 683                  * specific commands.
 684                  */
 685                         TRM_DPRINTF(" XPT_RESET_DEV \n");
 686                         pccb->ccb_h.status = CAM_REQ_INVALID;
 687                         xpt_done(pccb);
 688                         break;
 689                 /*
 690                  * Terminate the I/O process
 691                  * Terminate I/O Process Request CCB
 692                  */
 693                 case XPT_TERM_IO:
 694                         TRM_DPRINTF(" XPT_TERM_IO \n");
 695                         pccb->ccb_h.status = CAM_REQ_INVALID;
 696                         xpt_done(pccb);
 697                         break;
 698                 /*
 699                  * Get/Set transfer rate/width/disconnection/tag queueing
 700                  * settings
 701                  * (GET) default/user transfer settings for the target
 702                  */
 703                 case XPT_GET_TRAN_SETTINGS: {
 704                         struct  ccb_trans_settings *cts = &pccb->cts;
 705                         int     intflag;
 706                         struct  trm_transinfo *tinfo;
 707                         PDCB    pDCB;
 708                         struct ccb_trans_settings_scsi *scsi =
 709                             &cts->proto_specific.scsi;
 710                         struct ccb_trans_settings_spi *spi =
 711                             &cts->xport_specific.spi;
 712
 713                         cts->protocol = PROTO_SCSI;
 714                         cts->protocol_version = SCSI_REV_2;
 715                         cts->transport = XPORT_SPI;
 716                         cts->transport_version = 2;
 717
 718                         TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n");
 719                         pDCB = &pACB->DCBarray[target_id][target_lun];
 720                         intflag = splcam();
 721                         /*
 722                          * disable interrupt
 723                          */
 724                         if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
 725                                 /* current transfer settings */
 726                                 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB)
 727                                         spi->flags = CTS_SPI_FLAGS_DISC_ENB;
 728                                 else
 729                                         spi->flags = 0;/* no tag & disconnect */
 730                                 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB)
 731                                         scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
 732                                 tinfo = &pDCB->tinfo.current;
 733                                 TRM_DPRINTF("CURRENT:  cts->flags= %2x \n",
 734                                     cts->flags);
 735                         } else {
 736                           /* default(user) transfer settings */
 737                                 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB)
 738                                         spi->flags = CTS_SPI_FLAGS_DISC_ENB;
 739                                 else
 740                                         spi->flags = 0;
 741                                 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB)
 742                                         scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
 743                                 tinfo = &pDCB->tinfo.user;
 744                                 TRM_DPRINTF("USER: cts->flags= %2x \n",
 745                                         cts->flags);
 746                         }
 747                         spi->sync_period = tinfo->period;
 748                         spi->sync_offset = tinfo->offset;
 749                         spi->bus_width   = tinfo->width;
 750                         TRM_DPRINTF("pDCB->SyncPeriod: %d  \n",
 751                                 pDCB->SyncPeriod);
 752                         TRM_DPRINTF("period: %d  \n", tinfo->period);
 753                         TRM_DPRINTF("offset: %d  \n", tinfo->offset);
 754                         TRM_DPRINTF("width: %d  \n", tinfo->width);
 755
 756                         splx(intflag);
 757                         spi->valid = CTS_SPI_VALID_SYNC_RATE |
 758                             CTS_SPI_VALID_SYNC_OFFSET |
 759                             CTS_SPI_VALID_BUS_WIDTH |
 760                             CTS_SPI_VALID_DISC;
 761                         scsi->valid = CTS_SCSI_VALID_TQ;
 762                         pccb->ccb_h.status = CAM_REQ_CMP;
 763                         xpt_done(pccb);
 764                                             }
 765                         break;
 766                 /*
 767                  * Get/Set transfer rate/width/disconnection/tag queueing
 768                  * settings
 769                  * (Set) transfer rate/width negotiation settings
 770                  */
 771                 case XPT_SET_TRAN_SETTINGS: {
 772                         struct  ccb_trans_settings *cts =  &pccb->cts;
 773                         u_int   update_type;
 774                         int     intflag;
 775                         PDCB    pDCB;
 776                         struct ccb_trans_settings_scsi *scsi =
 777                             &cts->proto_specific.scsi;
 778                         struct ccb_trans_settings_spi *spi =
 779                             &cts->xport_specific.spi;
 780
 781                         TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n");
 782                         update_type = 0;
 783                         if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
 784                                 update_type |= TRM_TRANS_GOAL;
 785                         if (cts->type == CTS_TYPE_USER_SETTINGS)
 786                                 update_type |= TRM_TRANS_USER;
 787                         intflag = splcam();
 788                         pDCB = &pACB->DCBarray[target_id][target_lun];
 789
 790                         if ((spi->valid & CTS_SPI_VALID_DISC) != 0) {
 791                           /*ccb disc enables */
 792                                 if (update_type & TRM_TRANS_GOAL) {
 793                                         if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB)
 794                                             != 0)
 795                                                 pDCB->tinfo.disc_tag
 796                                                     |= TRM_CUR_DISCENB;
 797                                         else
 798                                                 pDCB->tinfo.disc_tag &=
 799                                                     ~TRM_CUR_DISCENB;
 800                                 }
 801                                 if (update_type & TRM_TRANS_USER) {
 802                                         if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB)
 803                                             != 0)
 804                                                 pDCB->tinfo.disc_tag
 805                                                     |= TRM_USR_DISCENB;
 806                                         else
 807                                                 pDCB->tinfo.disc_tag &=
 808                                                     ~TRM_USR_DISCENB;
 809                                 }
 810                         }
 811                         if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) {
 812                           /* if ccb tag q active */
 813                                 if (update_type & TRM_TRANS_GOAL) {
 814                                         if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB)
 815                                             != 0)
 816                                                 pDCB->tinfo.disc_tag |=
 817                                                     TRM_CUR_TAGENB;
 818                                         else
 819                                                 pDCB->tinfo.disc_tag &=
 820                                                     ~TRM_CUR_TAGENB;
 821                                 }
 822                                 if (update_type & TRM_TRANS_USER) {
 823                                         if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB)
 824                                             != 0)
 825                                                 pDCB->tinfo.disc_tag |=
 826                                                     TRM_USR_TAGENB;
 827                                         else
 828                                                 pDCB->tinfo.disc_tag &=
 829                                                     ~TRM_USR_TAGENB;
 830                                 }
 831                         }
 832                         /* Minimum sync period factor   */
 833
 834                         if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) {
 835                                 /* if ccb sync active */
 836                                 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */
 837                                 if ((spi->sync_period != 0) &&
 838                                     (spi->sync_period < 125))
 839                                         spi->sync_period = 125;
 840                                 /* 1/(125*4) minsync 2 MByte/sec */
 841                                 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET)
 842                                     != 0) {
 843                                         if (spi->sync_offset == 0)
 844                                                 spi->sync_period = 0;
 845                                         /* TRM-S1040 MaxSyncOffset = 15 bytes*/
 846                                         if (spi->sync_offset > 15)
 847                                                 spi->sync_offset = 15;
 848                                 }
 849                         }
 850                         if ((update_type & TRM_TRANS_USER) != 0) {
 851                                 pDCB->tinfo.user.period = spi->sync_period;
 852                                 pDCB->tinfo.user.offset = spi->sync_offset;
 853                                 pDCB->tinfo.user.width  = spi->bus_width;
 854                         }
 855                         if ((update_type & TRM_TRANS_GOAL) != 0) {
 856                                 pDCB->tinfo.goal.period = spi->sync_period;
 857                                 pDCB->tinfo.goal.offset = spi->sync_offset;
 858                                 pDCB->tinfo.goal.width  = spi->bus_width;
 859                         }
 860                         splx(intflag);
 861                         pccb->ccb_h.status = CAM_REQ_CMP;
 862                         xpt_done(pccb);
 863                         break;
 864                                             }
 865                 /*
 866                  * Calculate the geometry parameters for a device give
 867                  * the sector size and volume size.
 868                  */
 869                 case XPT_CALC_GEOMETRY:
 870                         TRM_DPRINTF(" XPT_CALC_GEOMETRY \n");
 871                         cam_calc_geometry(&pccb->ccg, /*extended*/1);
 872                         xpt_done(pccb);
 873                         break;
 874                 default:
 875                         pccb->ccb_h.status = CAM_REQ_INVALID;
 876                         xpt_done(pccb);
 877                         break;
 878         }
 879         splx(actionflags);
 880 }
 881
 882 static void
 883 trm_poll(struct cam_sim *psim)
 884 {
 885         trm_Interrupt(cam_sim_softc(psim));
 886 }
 887
 888 static void
 889 trm_ResetDevParam(PACB pACB)
 890 {
 891         PDCB            pDCB, pdcb;
 892         PNVRAMTYPE      pEEpromBuf;
 893         u_int8_t        PeriodIndex;
 894
 895         pDCB = pACB->pLinkDCB;
 896         if (pDCB == NULL)
 897                 return;
 898         pdcb = pDCB;
 899         do {
 900                 pDCB->SyncMode  &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE);
 901                 pDCB->SyncPeriod = 0;
 902                 pDCB->SyncOffset = 0;
 903                 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit];
 904                 pDCB->DevMode =
 905                   pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0;
 906                 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg;
 907                 PeriodIndex =
 908                    pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07;
 909                 if (pACB->AdaptType == 1) /* is U2? */
 910                         pDCB->MaxNegoPeriod = dc395u2x_clock_period[PeriodIndex];
 911                 else
 912                         pDCB->MaxNegoPeriod = dc395x_clock_period[PeriodIndex];
 913                 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) &&
 914                     (pACB->Config & HCC_WIDE_CARD))
 915                         pDCB->SyncMode |= WIDE_NEGO_ENABLE;
 916                 pDCB = pDCB->pNextDCB;
 917         }
 918         while (pdcb != pDCB);
 919 }
 920
 921 static void
 922 trm_RecoverSRB(PACB pACB)
 923 {
 924         PDCB            pDCB, pdcb;
 925         PSRB            psrb, psrb2;
 926         u_int16_t       cnt, i;
 927
 928         pDCB = pACB->pLinkDCB;
 929         if (pDCB == NULL)
 930                 return;
 931         pdcb = pDCB;
 932         do {
 933                 cnt = pdcb->GoingSRBCnt;
 934                 psrb = pdcb->pGoingSRB;
 935                 for (i = 0; i < cnt; i++) {
 936                         psrb2 = psrb;
 937                         psrb = psrb->pNextSRB;
 938                         if (pdcb->pWaitingSRB) {
 939                                 psrb2->pNextSRB = pdcb->pWaitingSRB;
 940                                 pdcb->pWaitingSRB = psrb2;
 941                         } else {
 942                                 pdcb->pWaitingSRB = psrb2;
 943                                 pdcb->pWaitingLastSRB = psrb2;
 944                                 psrb2->pNextSRB = NULL;
 945                         }
 946                 }
 947                 pdcb->GoingSRBCnt = 0;
 948                 pdcb->pGoingSRB = NULL;
 949                 pdcb = pdcb->pNextDCB;
 950         }
 951         while (pdcb != pDCB);
 952 }
 953
 954 static void
 955 trm_reset(PACB pACB)
 956 {
 957         int             intflag;
 958         u_int16_t       i;
 959
 960         TRM_DPRINTF("trm: RESET");
 961         intflag = splcam();
 962         trm_reg_write8(0x00, TRMREG_DMA_INTEN);
 963         trm_reg_write8(0x00, TRMREG_SCSI_INTEN);
 964
 965         trm_ResetSCSIBus(pACB);
 966         for (i = 0; i < 500; i++)
 967                 DELAY(1000);
 968         trm_reg_write8(0x7F, TRMREG_SCSI_INTEN);
 969         /* Enable DMA interrupt */
 970         trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN);
 971         /* Clear DMA FIFO */
 972         trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL);
 973         /* Clear SCSI FIFO */
 974         trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL);
 975         trm_ResetDevParam(pACB);
 976         trm_DoingSRB_Done(pACB);
 977         pACB->pActiveDCB = NULL;
 978         pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */
 979         trm_DoWaitingSRB(pACB);
 980         /* Tell the XPT layer that a bus reset occurred    */
 981         if (pACB->ppath != NULL)
 982                 xpt_async(AC_BUS_RESET, pACB->ppath, NULL);
 983         splx(intflag);
 984         return;
 985 }
 986
 987 static u_int16_t
 988 trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB)
 989 {
 990         u_int16_t       return_code;
 991         u_int8_t        scsicommand, i,command,identify_message;
 992         u_int8_t *      ptr;
 993         union  ccb      *pccb;
 994         struct ccb_scsiio *pcsio;
 995
 996         pccb  = pSRB->pccb;
 997         pcsio = &pccb->csio;
 998
 999         trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID);
1000         trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID);
1001         trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC);
1002         trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET);
1003         pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */
1004         /* Flush FIFO */
1005         trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL);
1006
1007         identify_message = pDCB->IdentifyMsg;
1008
1009         if ((pSRB->CmdBlock[0] == INQUIRY) ||
1010             (pSRB->CmdBlock[0] == REQUEST_SENSE) ||
1011             (pSRB->SRBFlag & AUTO_REQSENSE)) {
1012                 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) &&
1013                       !(pDCB->SyncMode & WIDE_NEGO_DONE))
1014                 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) &&
1015                   !(pDCB->SyncMode & SYNC_NEGO_DONE))) {
1016                         if (!(pDCB->IdentifyMsg & 7) ||
1017                             (pSRB->CmdBlock[0] != INQUIRY)) {
1018                                 scsicommand = SCMD_SEL_ATNSTOP;
1019                                 pSRB->SRBState = SRB_MSGOUT;
1020                                 goto polling;
1021                         }
1022                 }
1023         /*
1024         * Send identify message
1025         */
1026                 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO);
1027                 scsicommand = SCMD_SEL_ATN;
1028                 pSRB->SRBState = SRB_START_;
1029         } else {
1030                 /* not inquiry,request sense,auto request sense */
1031                 /*
1032                  * Send identify message
1033                  */
1034                 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO);
1035                 scsicommand = SCMD_SEL_ATN;
1036                 pSRB->SRBState = SRB_START_;
1037                 if (pDCB->SyncMode & EN_TAG_QUEUING) {
1038                   /* Send Tag message */
1039                         trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO);
1040                         trm_reg_write8(pSRB->TagNumber, TRMREG_SCSI_FIFO);
1041                         scsicommand = SCMD_SEL_ATN3;
1042                 }
1043         }
1044 polling:
1045         /*
1046          *       Send CDB ..command block .........
1047          */
1048         if (pSRB->SRBFlag & AUTO_REQSENSE) {
1049                 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO);
1050                 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO);
1051                 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1052                 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1053                 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO);
1054                 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1055         } else {
1056                 ptr = (u_int8_t *) pSRB->CmdBlock;
1057                 for (i = 0; i < pSRB->ScsiCmdLen ; i++) {
1058                         command = *ptr++;
1059                         trm_reg_write8(command,TRMREG_SCSI_FIFO);
1060                 }
1061         }
1062         if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) {
1063             /*
1064              * If trm_StartSCSI return 1 :
1065              * current interrupt status is interrupt disreenable
1066              * It's said that SCSI processor has more one SRB need to do,
1067              * SCSI processor has been occupied by one SRB.
1068              */
1069                 pSRB->SRBState = SRB_READY;
1070                 return_code = 1;
1071         } else {
1072           /*
1073            * If trm_StartSCSI return 0 :
1074            * current interrupt status is interrupt enable
1075            * It's said that SCSI processor is unoccupied
1076            */
1077                 pSRB->ScsiPhase  = SCSI_NOP1; /* SCSI bus free Phase */
1078                 pACB->pActiveDCB = pDCB;
1079                 pDCB->pActiveSRB = pSRB;
1080                 return_code = 0;
1081                 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT,
1082                     TRMREG_SCSI_CONTROL);/* it's important for atn stop*/
1083                 /*
1084                  * SCSI cammand
1085                  */
1086                 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND);
1087         }
1088         return (return_code);
1089 }
1090
1091 static void
1092 trm_Interrupt(vpACB)
1093 void *vpACB;
1094 {
1095         PACB            pACB;
1096         PDCB            pDCB;
1097         PSRB            pSRB;
1098         u_int16_t       phase;
1099         void            (*stateV)(PACB, PSRB, u_int16_t *);
1100         u_int16_t       scsi_status=0;
1101         u_int8_t        scsi_intstatus;
1102
1103         pACB = vpACB;
1104
1105         scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS);
1106         if (!(scsi_status & SCSIINTERRUPT)) {
1107                 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......");
1108                 return;
1109         }
1110         TRM_DPRINTF("scsi_status=%2x,",scsi_status);
1111
1112         scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS);
1113
1114         TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus);
1115
1116         if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) {
1117                 trm_Disconnect(pACB);
1118                 return;
1119         }
1120
1121         if (scsi_intstatus & INT_RESELECTED) {
1122                 trm_Reselect(pACB);
1123                 return;
1124         }
1125         if (scsi_intstatus & INT_SCSIRESET) {
1126                 trm_ScsiRstDetect(pACB);
1127                 return;
1128         }
1129
1130         if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) {
1131                 pDCB = pACB->pActiveDCB;
1132                 KASSERT(pDCB != NULL, ("no active DCB"));
1133                 pSRB = pDCB->pActiveSRB;
1134                 if (pDCB->DCBFlag & ABORT_DEV_)
1135                                 trm_EnableMsgOutAbort1(pACB, pSRB);
1136                 phase = (u_int16_t) pSRB->ScsiPhase;  /* phase: */
1137                 stateV = (void *) trm_SCSI_phase0[phase];
1138                 stateV(pACB, pSRB, &scsi_status);
1139                 pSRB->ScsiPhase = scsi_status & PHASEMASK;
1140                 /* phase:0,1,2,3,4,5,6,7 */
1141                 phase = (u_int16_t) scsi_status & PHASEMASK;
1142                 stateV = (void *) trm_SCSI_phase1[phase];
1143                 stateV(pACB, pSRB, &scsi_status);
1144         }
1145 }
1146
1147 static void
1148 trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1149 {
1150
1151         if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT))
1152                 *pscsi_status = PH_BUS_FREE;
1153         /*.. initial phase*/
1154 }
1155
1156 static void
1157 trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1158 {
1159         u_int8_t        bval;
1160         u_int16_t       i, cnt;
1161         u_int8_t *      ptr;
1162         PDCB            pDCB;
1163
1164         trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL);
1165         pDCB = pACB->pActiveDCB;
1166         if (!(pSRB->SRBState & SRB_MSGOUT)) {
1167                 cnt = pSRB->MsgCnt;
1168                 if (cnt) {
1169                         ptr = (u_int8_t *) pSRB->MsgOutBuf;
1170                         for (i = 0; i < cnt; i++) {
1171                                 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO);
1172                                 ptr++;
1173                         }
1174                         pSRB->MsgCnt = 0;
1175                         if ((pDCB->DCBFlag & ABORT_DEV_) &&
1176                             (pSRB->MsgOutBuf[0] == MSG_ABORT)) {
1177                                 pSRB->SRBState = SRB_ABORT_SENT;
1178                         }
1179                 } else {
1180                         bval = MSG_ABORT;
1181                         if ((pSRB->CmdBlock[0] == INQUIRY) ||
1182                                         (pSRB->CmdBlock[0] == REQUEST_SENSE) ||
1183                                         (pSRB->SRBFlag & AUTO_REQSENSE)) {
1184                                 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) {
1185                                         goto  mop1;
1186                                 }
1187                         }
1188                         trm_reg_write8(bval, TRMREG_SCSI_FIFO);
1189                 }
1190         } else {
1191 mop1:   /* message out phase */
1192                 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO)
1193                     && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) {
1194                   /*
1195                    * WIDE DATA TRANSFER REQUEST code (03h)
1196                    */
1197                         pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP);
1198                         trm_reg_write8((pDCB->IdentifyMsg & 0xBF),
1199                             TRMREG_SCSI_FIFO);
1200                         trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO);
1201                         /* (01h) */
1202                         trm_reg_write8(2,TRMREG_SCSI_FIFO);
1203                         /* Message length (02h) */
1204                         trm_reg_write8(3,TRMREG_SCSI_FIFO);
1205                         /* wide data xfer (03h) */
1206                         trm_reg_write8(1,TRMREG_SCSI_FIFO);
1207                         /* width:0(8bit),1(16bit),2(32bit) */
1208                         pSRB->SRBState |= SRB_DO_WIDE_NEGO;
1209                 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO)
1210                     && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) {
1211                   /*
1212                    * SYNCHRONOUS DATA TRANSFER REQUEST code (01h)
1213                    */
1214                         if (!(pDCB->SyncMode & WIDE_NEGO_DONE))
1215                                 trm_reg_write8((pDCB->IdentifyMsg & 0xBF),
1216                                                 TRMREG_SCSI_FIFO);
1217                         trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO);
1218                   /* (01h) */
1219                         trm_reg_write8(3,TRMREG_SCSI_FIFO);
1220                   /* Message length (03h) */
1221                         trm_reg_write8(1,TRMREG_SCSI_FIFO);
1222                   /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */
1223                         trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO);
1224                   /* Transfer peeriod factor */
1225                         trm_reg_write8((pACB->AdaptType == 1) ? 31 : 15,
1226                             TRMREG_SCSI_FIFO);
1227                   /* REQ/ACK offset */
1228                         pSRB->SRBState |= SRB_DO_SYNC_NEGO;
1229                 }
1230         }
1231         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1232         /* it's important for atn stop */
1233         /*
1234          * SCSI cammand
1235          */
1236         trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND);
1237 }
1238
1239 static void
1240 trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1241 {
1242
1243 }
1244
1245 static void
1246 trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1247 {
1248         PDCB                    pDCB;
1249         u_int8_t *              ptr;
1250         u_int16_t               i, cnt;
1251         union  ccb              *pccb;
1252         struct ccb_scsiio       *pcsio;
1253
1254         pccb  = pSRB->pccb;
1255         pcsio = &pccb->csio;
1256
1257         trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL);
1258         if (!(pSRB->SRBFlag & AUTO_REQSENSE)) {
1259                 cnt = (u_int16_t) pSRB->ScsiCmdLen;
1260                 ptr = (u_int8_t *) pSRB->CmdBlock;
1261                 for (i = 0; i < cnt; i++) {
1262                         trm_reg_write8(*ptr, TRMREG_SCSI_FIFO);
1263                         ptr++;
1264                 }
1265         } else {
1266                 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO);
1267                 pDCB = pACB->pActiveDCB;
1268                 /* target id */
1269                 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO);
1270                 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1271                 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1272                 /* sizeof(struct scsi_sense_data) */
1273                 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO);
1274                 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1275         }
1276         pSRB->SRBState = SRB_COMMAND;
1277         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1278         /* it's important for atn stop*/
1279         /*
1280          * SCSI cammand
1281          */
1282         trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND);
1283 }
1284
1285 static void
1286 trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1287 {
1288         PDCB            pDCB;
1289         u_int8_t        TempDMAstatus,SGIndexTemp;
1290         u_int16_t       scsi_status;
1291         PSEG            pseg;
1292         u_long          TempSRBXferredLength,dLeftCounter=0;
1293
1294         pDCB = pSRB->pSRBDCB;
1295         scsi_status = *pscsi_status;
1296
1297         if (!(pSRB->SRBState & SRB_XFERPAD)) {
1298                 if (scsi_status & PARITYERROR)
1299                         pSRB->SRBStatus |= PARITY_ERROR;
1300                 if (!(scsi_status & SCSIXFERDONE)) {
1301                   /*
1302                    * when data transfer from DMA FIFO to SCSI FIFO
1303                    * if there was some data left in SCSI FIFO
1304                    */
1305                         dLeftCounter = (u_long)
1306                           (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x3F);
1307                         if (pDCB->SyncPeriod & WIDE_SYNC) {
1308                           /*
1309                            * if WIDE scsi SCSI FIFOCNT unit is word
1310                            * so need to * 2
1311                            */
1312                                 dLeftCounter <<= 1;
1313                         }
1314                 }
1315                 /*
1316                  * caculate all the residue data that not yet tranfered
1317                  * SCSI transfer counter + left in SCSI FIFO data
1318                  *
1319                  * .....TRM_SCSI_COUNTER (24bits)
1320                  * The counter always decrement by one for every SCSI byte
1321                  *transfer.
1322                  * .....TRM_SCSI_FIFOCNT (5bits)
1323                  * The counter is SCSI FIFO offset counter
1324                  */
1325                 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER);
1326                 if (dLeftCounter == 1) {
1327                         dLeftCounter = 0;
1328                         trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL);
1329                 }
1330                 if ((dLeftCounter == 0) ||
1331                     (scsi_status & SCSIXFERCNT_2_ZERO)) {
1332                         TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS);
1333                         while (!(TempDMAstatus & DMAXFERCOMP)) {
1334                                 TempDMAstatus =
1335                                   trm_reg_read8(TRMREG_DMA_STATUS);
1336                         }
1337                         pSRB->SRBTotalXferLength = 0;
1338                 } else {
1339                   /* Update SG list             */
1340                   /*
1341                    * if transfer not yet complete
1342                    * there were some data residue in SCSI FIFO or
1343                    * SCSI transfer counter not empty
1344                    */
1345                         if (pSRB->SRBTotalXferLength != dLeftCounter) {
1346                           /*
1347                            * data that had transferred length
1348                            */
1349                                 TempSRBXferredLength =
1350                                   pSRB->SRBTotalXferLength - dLeftCounter;
1351                                 /*
1352                                  * next time to be transferred length
1353                                  */
1354                                 pSRB->SRBTotalXferLength = dLeftCounter;
1355                                 /*
1356                                  * parsing from last time disconnect SRBSGIndex
1357                                  */
1358                                 pseg =
1359                                   pSRB->pSRBSGL + pSRB->SRBSGIndex;
1360                                 for (SGIndexTemp = pSRB->SRBSGIndex;
1361                                     SGIndexTemp < pSRB->SRBSGCount;
1362                                     SGIndexTemp++) {
1363                                         /*
1364                                          * find last time which SG transfer be
1365                                          * disconnect
1366                                          */
1367                                         if (TempSRBXferredLength >=
1368                                             pseg->length)
1369                                                 TempSRBXferredLength -=
1370                                                   pseg->length;
1371                                         else {
1372                                           /*
1373                                            * update last time disconnected SG
1374                                            * list
1375                                            */
1376                                                 pseg->length -=
1377                                                   TempSRBXferredLength;
1378                                                 /* residue data length  */
1379                                                 pseg->address +=
1380                                                   TempSRBXferredLength;
1381                                                 /* residue data pointer */
1382                                                 pSRB->SRBSGIndex = SGIndexTemp;
1383                                                 break;
1384                                         }
1385                                         pseg++;
1386                                 }
1387                         }
1388                 }
1389         }
1390         trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL);
1391 }
1392
1393
1394 static void
1395 trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1396 {
1397         u_int16_t       ioDir;
1398         /*
1399          * do prepare befor transfer when data out phase
1400          */
1401
1402         ioDir = XFERDATAOUT;
1403         trm_DataIO_transfer(pACB, pSRB, ioDir);
1404 }
1405
1406 static void
1407 trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1408 {
1409         u_int8_t        TempDMAstatus, SGIndexTemp;
1410         u_int16_t       scsi_status;
1411         PSEG            pseg;
1412         u_long          TempSRBXferredLength,dLeftCounter = 0;
1413
1414         scsi_status = *pscsi_status;
1415         if (!(pSRB->SRBState & SRB_XFERPAD)) {
1416                 if (scsi_status & PARITYERROR)
1417                         pSRB->SRBStatus |= PARITY_ERROR;
1418                 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER);
1419                 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) {
1420                         TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS);
1421                         while (!(TempDMAstatus & DMAXFERCOMP))
1422                                 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS);
1423                         pSRB->SRBTotalXferLength = 0;
1424                 } else {
1425                   /*
1426                    * parsing the case:
1427                    * when a transfer not yet complete
1428                    * but be disconnected by uper layer
1429                    * if transfer not yet complete
1430                    * there were some data residue in SCSI FIFO or
1431                    * SCSI transfer counter not empty
1432                    */
1433                   if (pSRB->SRBTotalXferLength != dLeftCounter) {
1434                                 /*
1435                                  * data that had transferred length
1436                                  */
1437                         TempSRBXferredLength =
1438                           pSRB->SRBTotalXferLength - dLeftCounter;
1439                                 /*
1440                                  * next time to be transferred length
1441                                  */
1442                         pSRB->SRBTotalXferLength = dLeftCounter;
1443                                 /*
1444                                  * parsing from last time disconnect SRBSGIndex
1445                                  */
1446                         pseg = pSRB->pSRBSGL + pSRB->SRBSGIndex;
1447                         for (SGIndexTemp = pSRB->SRBSGIndex;
1448                             SGIndexTemp < pSRB->SRBSGCount;
1449                             SGIndexTemp++) {
1450                           /*
1451                            * find last time which SG transfer be disconnect
1452                            */
1453                                 if (TempSRBXferredLength >= pseg->length)
1454                                         TempSRBXferredLength -= pseg->length;
1455                                 else {
1456                                   /*
1457                                    * update last time disconnected SG list
1458                                    */
1459                                         pseg->length -= TempSRBXferredLength;
1460                                         /* residue data length  */
1461                                         pseg->address += TempSRBXferredLength;
1462                                         /* residue data pointer */
1463                                         pSRB->SRBSGIndex = SGIndexTemp;
1464                                         break;
1465                                 }
1466                                 pseg++;
1467                         }
1468                   }
1469                 }
1470         }
1471 }
1472
1473 static void
1474 trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1475 {
1476         u_int16_t       ioDir;
1477         /*
1478          * do prepare befor transfer when data in phase
1479          */
1480
1481         ioDir = XFERDATAIN;
1482         trm_DataIO_transfer(pACB, pSRB, ioDir);
1483 }
1484
1485 static void
1486 trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir)
1487 {
1488         u_int8_t        bval;
1489         PDCB            pDCB;
1490
1491         pDCB = pSRB->pSRBDCB;
1492         if (pSRB->SRBSGIndex < pSRB->SRBSGCount) {
1493                 if (pSRB->SRBTotalXferLength != 0) {
1494                         /*
1495                          * load what physical address of Scatter/Gather list
1496                          table want to be transfer
1497                          */
1498                         TRM_DPRINTF(" SG->address=%8x \n",pSRB->pSRBSGL->address);
1499                         TRM_DPRINTF(" SG->length=%8x \n",pSRB->pSRBSGL->length);
1500                         TRM_DPRINTF(" pDCB->SyncPeriod=%x \n",pDCB->SyncPeriod);
1501                         TRM_DPRINTF(" pSRB->pSRBSGL=%8x \n",(unsigned int)pSRB->pSRBSGL);
1502                         TRM_DPRINTF(" pSRB->SRBSGPhyAddr=%8x \n",pSRB->SRBSGPhyAddr);
1503                         TRM_DPRINTF(" pSRB->SRBSGIndex=%d \n",pSRB->SRBSGIndex);
1504                         TRM_DPRINTF(" pSRB->SRBSGCount=%d \n",pSRB->SRBSGCount);
1505                         TRM_DPRINTF(" pSRB->SRBTotalXferLength=%d \n",pSRB->SRBTotalXferLength);
1506
1507                         pSRB->SRBState = SRB_DATA_XFER;
1508                         trm_reg_write32(0, TRMREG_DMA_XHIGHADDR);
1509                         trm_reg_write32(
1510                             (pSRB->SRBSGPhyAddr +
1511                              ((u_long)pSRB->SRBSGIndex << 3)),
1512                             TRMREG_DMA_XLOWADDR);
1513                         /*
1514                          * load how many bytes in the Scatter/Gather
1515                          * list table
1516                          */
1517                         trm_reg_write32(
1518                             ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3),
1519                             TRMREG_DMA_XCNT);
1520                         /*
1521                          * load total transfer length (24bits) max value
1522                          * 16Mbyte
1523                          */
1524                         trm_reg_write32(pSRB->SRBTotalXferLength,
1525                             TRMREG_SCSI_COUNTER);
1526                         /* Start DMA transfer */
1527                         trm_reg_write16(ioDir, TRMREG_DMA_COMMAND);
1528                         /* Start SCSI transfer */
1529                         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1530                         /* it's important for atn stop */
1531                         /*
1532                          * SCSI cammand
1533                          */
1534                         bval = (ioDir == XFERDATAOUT) ?
1535                           SCMD_DMA_OUT : SCMD_DMA_IN;
1536                         trm_reg_write8(bval, TRMREG_SCSI_COMMAND);
1537                 } else {
1538                   /* xfer pad */
1539                         if (pSRB->SRBSGCount) {
1540                                 pSRB->AdaptStatus = H_OVER_UNDER_RUN;
1541                                 pSRB->SRBStatus |= OVER_RUN;
1542                         }
1543                         if (pDCB->SyncPeriod & WIDE_SYNC)
1544                                 trm_reg_write32(2,TRMREG_SCSI_COUNTER);
1545                         else
1546                                 trm_reg_write32(1,TRMREG_SCSI_COUNTER);
1547                         if (ioDir == XFERDATAOUT)
1548                                 trm_reg_write16(0, TRMREG_SCSI_FIFO);
1549                         else
1550                                 trm_reg_read16(TRMREG_SCSI_FIFO);
1551                         pSRB->SRBState |= SRB_XFERPAD;
1552                         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1553                         /* it's important for atn stop */
1554                         /*
1555                          * SCSI cammand
1556                          */
1557                         bval = (ioDir == XFERDATAOUT) ?
1558                           SCMD_FIFO_OUT : SCMD_FIFO_IN;
1559                         trm_reg_write8(bval, TRMREG_SCSI_COMMAND);
1560                 }
1561         }
1562 }
1563
1564 static void
1565 trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1566 {
1567
1568         pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO);
1569         pSRB->SRBState = SRB_COMPLETED;
1570         *pscsi_status = PH_BUS_FREE;
1571         /*.. initial phase*/
1572         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1573         /* it's important for atn stop */
1574         /*
1575          * SCSI cammand
1576          */
1577         trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1578 }
1579
1580
1581
1582 static void
1583 trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1584 {
1585
1586         if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) {
1587                 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40))
1588                         trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL);
1589                 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000))
1590                         trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL);
1591         } else {
1592                 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000))
1593                         trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL);
1594                 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40))
1595                         trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL);
1596         }
1597         pSRB->SRBState = SRB_STATUS;
1598         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1599         /* it's important for atn stop */
1600         /*
1601          * SCSI cammand
1602          */
1603         trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND);
1604 }
1605
1606 /*
1607  *scsiiom
1608  *       trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors
1609  *            stateV = (void *) trm_SCSI_phase0[phase]
1610  *                         if phase =7
1611  * extended message codes:
1612  *
1613  *   code        description
1614  *
1615  *    02h        Reserved
1616  *    00h        MODIFY DATA  POINTER
1617  *    01h        SYNCHRONOUS DATA TRANSFER REQUEST
1618  *    03h        WIDE DATA TRANSFER REQUEST
1619  * 04h - 7Fh     Reserved
1620  * 80h - FFh     Vendor specific
1621  *
1622  */
1623
1624 static void
1625 trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1626 {
1627         u_int8_t        message_in_code,bIndex,message_in_tag_id;
1628         PDCB            pDCB;
1629         PSRB            pSRBTemp;
1630
1631         pDCB = pACB->pActiveDCB;
1632
1633         message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO);
1634         if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) {
1635                 if (message_in_code == MSG_DISCONNECT) {
1636                         pSRB->SRBState = SRB_DISCONNECT;
1637                         *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1638                         /* it's important for atn stop */
1639                         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1640                         /*
1641                          * SCSI command
1642                          */
1643                         trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1644                         return;
1645                 } else if (message_in_code == MSG_SAVE_PTR) {
1646                         *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1647                         /* it's important for atn stop */
1648                         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1649                         /*
1650                          * SCSI command
1651                          */
1652                         trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1653                         return;
1654                 } else if ((message_in_code == MSG_EXTENDED) ||
1655                     ((message_in_code >= MSG_SIMPLE_QTAG) &&
1656                      (message_in_code <= MSG_ORDER_QTAG))) {
1657                         pSRB->SRBState |= SRB_EXTEND_MSGIN;
1658                         pSRB->MsgInBuf[0] = message_in_code;
1659                         /* extended message      (01h) */
1660                         pSRB->MsgCnt = 1;
1661                         pSRB->pMsgPtr = &pSRB->MsgInBuf[1];
1662                         /* extended message length (n) */
1663                         *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1664                         /* it's important for atn stop */
1665                         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1666                         /*
1667                          * SCSI command
1668                          */
1669                         trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1670                         return;
1671                 } else if (message_in_code == MSG_REJECT_) {
1672                         /* Reject message */
1673                         if (pDCB->SyncMode & WIDE_NEGO_ENABLE) {
1674                           /* do wide nego reject */
1675                                 pDCB = pSRB->pSRBDCB;
1676                                 pDCB->SyncMode |= WIDE_NEGO_DONE;
1677                                 pDCB->SyncMode &= ~(SYNC_NEGO_DONE |
1678                                     EN_ATN_STOP | WIDE_NEGO_ENABLE);
1679                                 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN);
1680                                 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE)
1681                                     && !(pDCB->SyncMode & SYNC_NEGO_DONE)) {
1682                                   /* Set ATN, in case ATN was clear */
1683                                         pSRB->SRBState |= SRB_MSGOUT;
1684                                         trm_reg_write16(
1685                                             DO_SETATN,
1686                                             TRMREG_SCSI_CONTROL);
1687                                 } else {
1688                                   /* Clear ATN */
1689                                         trm_reg_write16(
1690                                             DO_CLRATN,
1691                                             TRMREG_SCSI_CONTROL);
1692                                 }
1693                         } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) {
1694                           /* do sync nego reject */
1695                                 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL);
1696                                 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) {
1697                                         pDCB = pSRB->pSRBDCB;
1698                                         pDCB->SyncMode &=
1699                                           ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE);
1700                                         pDCB->SyncPeriod = 0;
1701                                         pDCB->SyncOffset = 0;
1702                                         /*
1703                                          *
1704                                          *   program SCSI control register
1705                                          *
1706                                          */
1707                                         trm_reg_write8(pDCB->SyncPeriod,
1708                                             TRMREG_SCSI_SYNC);
1709                                         trm_reg_write8(pDCB->SyncOffset,
1710                                             TRMREG_SCSI_OFFSET);
1711                                         trm_SetXferRate(pACB,pSRB,pDCB);
1712                                 }
1713                         }
1714                         *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1715                         /* it's important for atn stop */
1716                         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1717                         /*
1718                          * SCSI command
1719                          */
1720                         trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1721                         return;
1722                 } else if (message_in_code == MSG_IGNOREWIDE) {
1723                         trm_reg_write32(1, TRMREG_SCSI_COUNTER);
1724                         trm_reg_read8(TRMREG_SCSI_FIFO);
1725                         *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1726                         /* it's important for atn stop */
1727                         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1728                         /*
1729                          * SCSI command
1730                          */
1731                         trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1732                         return;
1733                 } else {
1734                   /* Restore data pointer message */
1735                   /* Save data pointer message    */
1736                   /* Completion message           */
1737                   /* NOP message                  */
1738                         *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1739                         /* it's important for atn stop */
1740                         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1741                         /*
1742                          * SCSI command
1743                          */
1744                         trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1745                         return;
1746                 }
1747         } else {
1748           /*
1749            * Parsing incoming extented messages
1750            */
1751                 *pSRB->pMsgPtr = message_in_code;
1752                 pSRB->MsgCnt++;
1753                 pSRB->pMsgPtr++;
1754                 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]);
1755                 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]);
1756                 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]);
1757                 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]);
1758                 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]);
1759                 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG)
1760                     && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) {
1761                   /*
1762                    * is QUEUE tag message :
1763                    *
1764                    * byte 0:
1765                    * HEAD    QUEUE TAG (20h)
1766                    * ORDERED QUEUE TAG (21h)
1767                    * SIMPLE  QUEUE TAG (22h)
1768                    * byte 1:
1769                    * Queue tag (00h - FFh)
1770                    */
1771                         if (pSRB->MsgCnt == 2) {
1772                                 pSRB->SRBState = 0;
1773                                 message_in_tag_id = pSRB->MsgInBuf[1];
1774                                 pSRB = pDCB->pGoingSRB;
1775                                 pSRBTemp = pDCB->pGoingLastSRB;
1776                                 if (pSRB) {
1777                                         for (;;) {
1778                                                 if (pSRB->TagNumber !=
1779                                                     message_in_tag_id) {
1780                                                         if (pSRB == pSRBTemp) {
1781                                                                 goto  mingx0;
1782                                                         }
1783                                                         pSRB = pSRB->pNextSRB;
1784                                                 } else
1785                                                         break;
1786                                         }
1787                                         if (pDCB->DCBFlag & ABORT_DEV_) {
1788                                                 pSRB->SRBState = SRB_ABORT_SENT;
1789                                                 trm_EnableMsgOutAbort1(
1790                                                     pACB, pSRB);
1791                                         }
1792                                         if (!(pSRB->SRBState & SRB_DISCONNECT)) {
1793                                                 TRM_DPRINTF("SRB not yet disconnect........ \n ");
1794                                                 goto  mingx0;
1795                                         }
1796                                         pDCB->pActiveSRB = pSRB;
1797                                         pSRB->SRBState = SRB_DATA_XFER;
1798                                 } else {
1799 mingx0:
1800                                         pSRB = &pACB->TmpSRB;
1801                                         pSRB->SRBState = SRB_UNEXPECT_RESEL;
1802                                         pDCB->pActiveSRB = pSRB;
1803                                         pSRB->MsgOutBuf[0] = MSG_ABORT_TAG;
1804                                         trm_EnableMsgOutAbort2(
1805                                             pACB,
1806                                             pSRB);
1807                                 }
1808                         }
1809                         *pscsi_status = PH_BUS_FREE;
1810                         /* .. initial phase */
1811                         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1812                         /* it's important for atn stop */
1813                         /*
1814                          * SCSI command
1815                          */
1816                         trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1817                         return;
1818                 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) &&
1819                     (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) {
1820                   /*
1821                    * is Wide data xfer Extended message :
1822                    * ======================================
1823                    * WIDE DATA TRANSFER REQUEST
1824                    * ======================================
1825                    * byte 0 :  Extended message (01h)
1826                    * byte 1 :  Extended message length (02h)
1827                    * byte 2 :  WIDE DATA TRANSFER code (03h)
1828                    * byte 3 :  Transfer width exponent
1829                    */
1830                         pDCB = pSRB->pSRBDCB;
1831                         pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO);
1832                         if ((pSRB->MsgInBuf[1] != 2)) {
1833                           /* Length is wrong, reject it  */
1834                                 pDCB->SyncMode &=
1835                                   ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE);
1836                                 pSRB->MsgCnt = 1;
1837                                 pSRB->MsgInBuf[0] = MSG_REJECT_;
1838                                 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL);
1839                                 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1840                                 /* it's important for atn stop */
1841                                 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1842                                 /*
1843                                  * SCSI command
1844                                  */
1845                                 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1846                                 return;
1847                         }
1848                         if (pDCB->SyncMode & WIDE_NEGO_ENABLE) {
1849                           /* Do wide negoniation */
1850                                 if (pSRB->MsgInBuf[3] > 2) {
1851                                   /* > 32 bit   */
1852                                   /* reject_msg: */
1853                                         pDCB->SyncMode &=
1854                                           ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE);
1855                                         pSRB->MsgCnt = 1;
1856                                         pSRB->MsgInBuf[0] = MSG_REJECT_;
1857                                         trm_reg_write16(DO_SETATN,
1858                                             TRMREG_SCSI_CONTROL);
1859                                         *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1860                                         /* it's important for atn stop */
1861                                         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1862                                         /*
1863                                          * SCSI command
1864                                          */
1865                                         trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1866                                         return;
1867                                 }
1868                                 if (pSRB->MsgInBuf[3] == 2) {
1869                                         pSRB->MsgInBuf[3] = 1;
1870                                         /* do 16 bits   */
1871                                 } else {
1872                                         if (!(pDCB->SyncMode
1873                                               & WIDE_NEGO_DONE)) {
1874                                                 pSRB->SRBState &=
1875                                                   ~(SRB_DO_WIDE_NEGO+SRB_MSGIN);
1876                                                 pDCB->SyncMode |=
1877                                                   WIDE_NEGO_DONE;
1878                                                 pDCB->SyncMode &=
1879                                                   ~(SYNC_NEGO_DONE |
1880                                                       EN_ATN_STOP |
1881                                                       WIDE_NEGO_ENABLE);
1882                                                 if (pSRB->MsgInBuf[3] != 0) {
1883                                                   /* is Wide data xfer */
1884                                                         pDCB->SyncPeriod |=
1885                                                           WIDE_SYNC;
1886                                                         pDCB->tinfo.current.width
1887                                                           = MSG_EXT_WDTR_BUS_16_BIT;
1888                                                         pDCB->tinfo.goal.width
1889                                                           = MSG_EXT_WDTR_BUS_16_BIT;
1890                                                 }
1891                                         }
1892                                 }
1893                         } else
1894                                 pSRB->MsgInBuf[3] = 0;
1895                         pSRB->SRBState |= SRB_MSGOUT;
1896                         trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL);
1897                         *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1898                         /* it's important for atn stop */
1899                         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1900                         /*
1901                          * SCSI command
1902                          */
1903                         trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1904                         return;
1905                 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) &&
1906                     (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) {
1907                         /*
1908                          * is 8bit transfer Extended message :
1909                          * =================================
1910                          * SYNCHRONOUS DATA TRANSFER REQUEST
1911                          * =================================
1912                          * byte 0 :  Extended message (01h)
1913                          * byte 1 :  Extended message length (03)
1914                          * byte 2 :  SYNCHRONOUS DATA TRANSFER code (01h)
1915                          * byte 3 :  Transfer period factor
1916                          * byte 4 :  REQ/ACK offset
1917                          */
1918                         pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO);
1919                         if ((pSRB->MsgInBuf[1] != 3) ||
1920                             (pSRB->MsgInBuf[2] != 1)) {
1921                           /* reject_msg: */
1922                                 pSRB->MsgCnt = 1;
1923                                 pSRB->MsgInBuf[0] = MSG_REJECT_;
1924                                 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL);
1925                                 *pscsi_status = PH_BUS_FREE;
1926                                 /* .. initial phase */
1927                                 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1928                                 /* it's important for atn stop */
1929                                 /*
1930                                  * SCSI cammand
1931                                  */
1932                                 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1933                                 return;
1934                         } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) {
1935                                 /* set async */
1936                                 pDCB = pSRB->pSRBDCB;
1937                                 /* disable sync & sync nego */
1938                                 pDCB->SyncMode &=
1939                                   ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE);
1940                                 pDCB->SyncPeriod = 0;
1941                                 pDCB->SyncOffset = 0;
1942                                 pDCB->tinfo.goal.period = 0;
1943                                 pDCB->tinfo.goal.offset = 0;
1944                                 pDCB->tinfo.current.period = 0;
1945                                 pDCB->tinfo.current.offset = 0;
1946                                 pDCB->tinfo.current.width =
1947                                   MSG_EXT_WDTR_BUS_8_BIT;
1948                                 /*
1949                                  *
1950                                  *   program SCSI control register
1951                                  *
1952                                  */
1953                                 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC);
1954                                 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET);
1955                                 trm_SetXferRate(pACB,pSRB,pDCB);
1956                                 *pscsi_status = PH_BUS_FREE;
1957                                 /* .. initial phase */
1958                                 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1959                                 /* it's important for atn stop */
1960                                 /*
1961                                  * SCSI cammand
1962                                  */
1963                                 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1964                                 return;
1965                         } else {
1966                                 /* set sync */
1967                                 pDCB = pSRB->pSRBDCB;
1968                                 pDCB->SyncMode |=
1969                                   SYNC_NEGO_ENABLE+SYNC_NEGO_DONE;
1970                                 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3];
1971                                 /* Transfer period factor */
1972                                 pDCB->SyncOffset = pSRB->MsgInBuf[4];
1973                                 /* REQ/ACK offset */
1974                                 if (pACB->AdaptType == 1) {
1975                                         for(bIndex = 0; bIndex < 7; bIndex++) {
1976                                                 if (pSRB->MsgInBuf[3] <=
1977                                            dc395u2x_clock_period[bIndex]) {
1978                                             pDCB->tinfo.goal.period =
1979                                                 dc395u2x_tinfo_period[bIndex];
1980                                             pDCB->tinfo.current.period =
1981                                                 dc395u2x_tinfo_period[bIndex];
1982                                         pDCB->tinfo.goal.offset =
1983                                             pDCB->SyncOffset;
1984                                         pDCB->tinfo.current.offset =
1985                                             pDCB->SyncOffset;
1986                                         pDCB->SyncPeriod |= (bIndex|LVDS_SYNC);
1987                                         break;
1988                                                 }
1989                                         }
1990                                 } else {
1991                                         for(bIndex = 0; bIndex < 7; bIndex++) {
1992                                                 if (pSRB->MsgInBuf[3] <=
1993                                                  dc395x_clock_period[bIndex]) {
1994                                                    pDCB->tinfo.goal.period =
1995                                                 dc395x_tinfo_period[bIndex];
1996                                                    pDCB->tinfo.current.period =
1997                                                 dc395x_tinfo_period[bIndex];
1998                                                    pDCB->tinfo.goal.offset =
1999                                                 pDCB->SyncOffset;
2000                                                    pDCB->tinfo.current.offset =
2001                                                        pDCB->SyncOffset;
2002                                                    pDCB->SyncPeriod |=
2003                                                        (bIndex|ALT_SYNC);
2004                                                    break;
2005                                                 }
2006                                         }
2007                                 }
2008                                 /*
2009                                  *
2010                                  *   program SCSI control register
2011                                  *
2012                                  */
2013                                 trm_reg_write8(pDCB->SyncPeriod,
2014                                     TRMREG_SCSI_SYNC);
2015                                 trm_reg_write8(pDCB->SyncOffset,
2016                                     TRMREG_SCSI_OFFSET);
2017                                 trm_SetXferRate(pACB,pSRB,pDCB);
2018                                 *pscsi_status=PH_BUS_FREE;/*.. initial phase*/
2019                                 trm_reg_write16(DO_DATALATCH,TRMREG_SCSI_CONTROL);/* it's important for atn stop*/
2020                     /*
2021                     ** SCSI command
2022                     */
2023                                 trm_reg_write8(SCMD_MSGACCEPT,TRMREG_SCSI_COMMAND);
2024                                 return;
2025                         }
2026                 }
2027         *pscsi_status = PH_BUS_FREE;
2028         /* .. initial phase */
2029         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2030         /* it's important for atn stop */
2031         /*
2032          * SCSI cammand
2033          */
2034         trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2035         }
2036 }
2037
2038 static void
2039 trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
2040 {
2041
2042         trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL);
2043         trm_reg_write32(1,TRMREG_SCSI_COUNTER);
2044         if (!(pSRB->SRBState & SRB_MSGIN)) {
2045                 pSRB->SRBState &= SRB_DISCONNECT;
2046                 pSRB->SRBState |= SRB_MSGIN;
2047         }
2048         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2049         /* it's important for atn stop*/
2050         /*
2051          * SCSI cammand
2052          */
2053         trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND);
2054 }
2055
2056 static void
2057 trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
2058 {
2059
2060 }
2061
2062 static void
2063 trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
2064 {
2065
2066 }
2067
2068 static void
2069 trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB)
2070 {
2071         union ccb       *pccb;
2072         struct ccb_trans_settings neg;
2073         u_int16_t       cnt, i;
2074         u_int8_t        bval;
2075         PDCB            pDCBTemp;
2076
2077         /*
2078          * set all lun device's  period , offset
2079          */
2080         TRM_DPRINTF("trm_SetXferRate\n");
2081         pccb = pSRB->pccb;
2082         memset(&neg, 0, sizeof (neg));
2083         neg.xport_specific.spi.sync_period = pDCB->tinfo.goal.period;
2084         neg.xport_specific.spi.sync_offset = pDCB->tinfo.goal.offset;
2085         neg.xport_specific.spi.valid =
2086             CTS_SPI_VALID_SYNC_RATE | CTS_SPI_VALID_SYNC_OFFSET;
2087         xpt_setup_ccb(&neg.ccb_h, pccb->ccb_h.path, /* priority */1);
2088         xpt_async(AC_TRANSFER_NEG, pccb->ccb_h.path, &neg);
2089         if (!(pDCB->IdentifyMsg & 0x07)) {
2090                 pDCBTemp = pACB->pLinkDCB;
2091                 cnt = pACB->DeviceCnt;
2092                 bval = pDCB->TargetID;
2093                 for (i = 0; i < cnt; i++) {
2094                         if (pDCBTemp->TargetID == bval) {
2095                                 pDCBTemp->SyncPeriod = pDCB->SyncPeriod;
2096                                 pDCBTemp->SyncOffset = pDCB->SyncOffset;
2097                                 pDCBTemp->SyncMode = pDCB->SyncMode;
2098                         }
2099                         pDCBTemp = pDCBTemp->pNextDCB;
2100                 }
2101         }
2102         return;
2103 }
2104
2105 /*
2106  * scsiiom
2107  *            trm_Interrupt
2108  *
2109  *
2110  *    ---SCSI bus phase
2111  *
2112  *      PH_DATA_OUT             0x00     Data out phase
2113  *      PH_DATA_IN              0x01     Data in phase
2114  *      PH_COMMAND              0x02     Command phase
2115  *      PH_STATUS               0x03     Status phase
2116  *      PH_BUS_FREE             0x04     Invalid phase used as bus free
2117  *      PH_BUS_FREE             0x05     Invalid phase used as bus free
2118  *      PH_MSG_OUT              0x06     Message out phase
2119  *      PH_MSG_IN               0x07     Message in phase
2120  *
2121  */
2122 static void
2123 trm_Disconnect(PACB pACB)
2124 {
2125         PDCB            pDCB;
2126         PSRB            pSRB, psrb;
2127         u_int16_t       i,j, cnt;
2128         u_int           target_id,target_lun;
2129
2130         TRM_DPRINTF("trm_Disconnect...............\n ");
2131
2132         pDCB = pACB->pActiveDCB;
2133         if (!pDCB) {
2134                 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n ");
2135                 j = 400;
2136                 while (--j)
2137                         DELAY(1);
2138                 /* 1 msec */
2139                 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT),
2140                     TRMREG_SCSI_CONTROL);
2141                 return;
2142         }
2143         pSRB = pDCB->pActiveSRB;
2144         /* bug pSRB=0 */
2145         target_id  = pSRB->pccb->ccb_h.target_id;
2146         target_lun = pSRB->pccb->ccb_h.target_lun;
2147         TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB);
2148         pACB->pActiveDCB = 0;
2149         pSRB->ScsiPhase = PH_BUS_FREE;
2150         /* SCSI bus free Phase */
2151         trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL);
2152         if (pSRB->SRBState & SRB_UNEXPECT_RESEL) {
2153                 pSRB->SRBState = 0;
2154                 trm_DoWaitingSRB(pACB);
2155         } else if (pSRB->SRBState & SRB_ABORT_SENT) {
2156                 pDCB->DCBFlag = 0;
2157                 cnt = pDCB->GoingSRBCnt;
2158                 pDCB->GoingSRBCnt = 0;
2159                 pSRB = pDCB->pGoingSRB;
2160                 for (i = 0; i < cnt; i++) {
2161                         psrb = pSRB->pNextSRB;
2162                         pSRB->pNextSRB = pACB->pFreeSRB;
2163                         pACB->pFreeSRB = pSRB;
2164                         pSRB = psrb;
2165                 }
2166                 pDCB->pGoingSRB = 0;
2167                 trm_DoWaitingSRB(pACB);
2168         } else {
2169                 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) ||
2170                     !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) {
2171                   /* Selection time out */
2172                         if (!(pACB->scan_devices[target_id][target_lun]) &&
2173                             pSRB->CmdBlock[0] != 0x00 && /* TEST UNIT READY */
2174                             pSRB->CmdBlock[0] != INQUIRY) {
2175                                 pSRB->SRBState = SRB_READY;
2176                                 trm_RewaitSRB(pDCB, pSRB);
2177                         } else {
2178                                 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT;
2179                                 goto  disc1;
2180                         }
2181                 } else if (pSRB->SRBState & SRB_DISCONNECT) {
2182                         /*
2183                          * SRB_DISCONNECT
2184                          */
2185                         trm_DoWaitingSRB(pACB);
2186                 } else if (pSRB->SRBState & SRB_COMPLETED) {
2187 disc1:
2188                   /*
2189                    * SRB_COMPLETED
2190                    */
2191                         pDCB->pActiveSRB = 0;
2192                         pSRB->SRBState = SRB_FREE;
2193                         trm_SRBdone(pACB, pDCB, pSRB);
2194                 }
2195         }
2196         return;
2197 }
2198
2199 static void
2200 trm_Reselect(PACB pACB)
2201 {
2202         PDCB            pDCB;
2203         PSRB            pSRB;
2204         u_int16_t       RselTarLunId;
2205
2206         TRM_DPRINTF("trm_Reselect................. \n");
2207         pDCB = pACB->pActiveDCB;
2208         if (pDCB) {
2209           /* Arbitration lost but Reselection win */
2210                 pSRB = pDCB->pActiveSRB;
2211                 pSRB->SRBState = SRB_READY;
2212                 trm_RewaitSRB(pDCB, pSRB);
2213         }
2214         /* Read Reselected Target Id and LUN */
2215         RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF;
2216         pDCB = pACB->pLinkDCB;
2217         while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) {
2218           /* get pDCB of the reselect id */
2219                 pDCB = pDCB->pNextDCB;
2220         }
2221
2222         pACB->pActiveDCB = pDCB;
2223         if (pDCB->SyncMode & EN_TAG_QUEUING) {
2224                 pSRB = &pACB->TmpSRB;
2225                 pDCB->pActiveSRB = pSRB;
2226         } else {
2227                 pSRB = pDCB->pActiveSRB;
2228                 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) {
2229                   /*
2230                    * abort command
2231                    */
2232                         pSRB = &pACB->TmpSRB;
2233                         pSRB->SRBState = SRB_UNEXPECT_RESEL;
2234                         pDCB->pActiveSRB = pSRB;
2235                         trm_EnableMsgOutAbort1(pACB, pSRB);
2236                 } else {
2237                         if (pDCB->DCBFlag & ABORT_DEV_) {
2238                                 pSRB->SRBState = SRB_ABORT_SENT;
2239                                 trm_EnableMsgOutAbort1(pACB, pSRB);
2240                         } else
2241                                 pSRB->SRBState = SRB_DATA_XFER;
2242                 }
2243         }
2244         pSRB->ScsiPhase = PH_BUS_FREE;
2245         /* SCSI bus free Phase */
2246         /*
2247          * Program HA ID, target ID, period and offset
2248          */
2249         trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID);
2250         /* target ID */
2251         trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID);
2252         /* host   ID */
2253         trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC);
2254         /* period    */
2255         trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET);
2256         /* offset    */
2257         trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2258         /* it's important for atn stop*/
2259         /*
2260          * SCSI cammand
2261          */
2262         trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2263         /* to rls the /ACK signal */
2264 }
2265
2266 static void
2267 trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB)
2268 {
2269         PSRB                    psrb;
2270         u_int8_t                bval, bval1,status;
2271         union ccb               *pccb;
2272         struct ccb_scsiio       *pcsio;
2273         PSCSI_INQDATA           ptr;
2274         int                     intflag;
2275         u_int                   target_id,target_lun;
2276         PDCB                    pTempDCB;
2277
2278         pccb  = pSRB->pccb;
2279         if (pccb == NULL)
2280                 return;
2281         pcsio = &pccb->csio;
2282         target_id  = pSRB->pccb->ccb_h.target_id;
2283         target_lun = pSRB->pccb->ccb_h.target_lun;
2284         if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
2285                 bus_dmasync_op_t op;
2286                 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
2287                         op = BUS_DMASYNC_POSTREAD;
2288                 else
2289                         op = BUS_DMASYNC_POSTWRITE;
2290                 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op);
2291                 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap);
2292         }
2293         /*
2294          *
2295          * target status
2296          *
2297          */
2298         status = pSRB->TargetStatus;
2299         pcsio->scsi_status=SCSI_STAT_GOOD;
2300         pccb->ccb_h.status = CAM_REQ_CMP;
2301         if (pSRB->SRBFlag & AUTO_REQSENSE) {
2302           /*
2303            * status of auto request sense
2304            */
2305                 pSRB->SRBFlag &= ~AUTO_REQSENSE;
2306                 pSRB->AdaptStatus = 0;
2307                 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND;
2308
2309                 if (status == SCSI_STATUS_CHECK_COND) {
2310                         pccb->ccb_h.status = CAM_SEL_TIMEOUT;
2311                         goto ckc_e;
2312                 }
2313                 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0];
2314                 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1];
2315                 pSRB->SRBTotalXferLength = pSRB->Segment1[1];
2316                 pSRB->pSRBSGL->address = pSRB->SgSenseTemp.address;
2317                 pSRB->pSRBSGL->length = pSRB->SgSenseTemp.length;
2318                 pcsio->scsi_status = SCSI_STATUS_CHECK_COND;
2319                 bcopy(trm_get_sense_buf(pACB, pSRB), &pcsio->sense_data,
2320                     pcsio->sense_len);
2321                 pcsio->ccb_h.status = CAM_SCSI_STATUS_ERROR
2322                     | CAM_AUTOSNS_VALID;
2323                 goto ckc_e;
2324         }
2325         /*
2326          * target status
2327          */
2328         if (status) {
2329                 if (status == SCSI_STATUS_CHECK_COND) {
2330                         if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) {
2331                           TRM_DPRINTF("trm_RequestSense..................\n");
2332                           trm_RequestSense(pACB, pDCB, pSRB);
2333                           return;
2334                         }
2335                         pcsio->scsi_status = SCSI_STATUS_CHECK_COND;
2336                         pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
2337                         goto ckc_e;
2338                 } else if (status == SCSI_STAT_QUEUEFULL) {
2339                         bval = (u_int8_t) pDCB->GoingSRBCnt;
2340                         bval--;
2341                         pDCB->MaxActiveCommandCnt = bval;
2342                         trm_RewaitSRB(pDCB, pSRB);
2343                         pSRB->AdaptStatus = 0;
2344                         pSRB->TargetStatus = 0;
2345                         return;
2346                 } else if (status == SCSI_STAT_SEL_TIMEOUT) {
2347                         pSRB->AdaptStatus  = H_SEL_TIMEOUT;
2348                         pSRB->TargetStatus = 0;
2349                         pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT;
2350                         pccb->ccb_h.status = CAM_SEL_TIMEOUT;
2351                 } else if (status == SCSI_STAT_BUSY) {
2352                         TRM_DPRINTF("trm: target busy at %s %d\n",
2353                                 __FILE__, __LINE__);
2354                         pcsio->scsi_status = SCSI_STAT_BUSY;
2355                         pccb->ccb_h.status = CAM_SCSI_BUSY;
2356                         return;
2357                   /* The device busy, try again later?    */
2358                 } else if (status == SCSI_STAT_RESCONFLICT) {
2359                         TRM_DPRINTF("trm: target reserved at %s %d\n",
2360                                 __FILE__, __LINE__);
2361                         pcsio->scsi_status = SCSI_STAT_RESCONFLICT;
2362                         pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;     /*XXX*/
2363                         return;
2364                 } else {
2365                         pSRB->AdaptStatus = 0;
2366                         if (pSRB->RetryCnt) {
2367                                 pSRB->RetryCnt--;
2368                                 pSRB->TargetStatus = 0;
2369                                 pSRB->SRBSGIndex = 0;
2370                                 if (trm_StartSCSI(pACB, pDCB, pSRB)) {
2371                                   /*
2372                                    * If trm_StartSCSI return 1 :
2373                                    * current interrupt status is interrupt
2374                                    * disreenable
2375                                    * It's said that SCSI processor has more
2376                                    * one SRB need to do
2377                                    */
2378                                         trm_RewaitSRB(pDCB, pSRB);
2379                                 }
2380                                 return;
2381                         } else {
2382                                 TRM_DPRINTF("trm: driver stuffup at %s %d\n",
2383                                         __FILE__, __LINE__);
2384                                 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
2385                         }
2386                 }
2387         } else {
2388         /*
2389          * process initiator status..........................
2390          * Adapter (initiator) status
2391          */
2392                 status = pSRB->AdaptStatus;
2393                 if (status & H_OVER_UNDER_RUN) {
2394                         pSRB->TargetStatus = 0;
2395                         pccb->ccb_h.status = CAM_DATA_RUN_ERR;
2396                         /* Illegal length (over/under run) */
2397                 } else if (pSRB->SRBStatus & PARITY_ERROR) {
2398                         TRM_DPRINTF("trm: driver stuffup %s %d\n",
2399                                 __FILE__, __LINE__);
2400                         pDCB->tinfo.goal.period = 0;
2401                         pDCB->tinfo.goal.offset = 0;
2402                         /* Driver failed to perform operation */
2403                         pccb->ccb_h.status = CAM_UNCOR_PARITY;
2404                 } else {
2405                   /* no error */
2406                         pSRB->AdaptStatus = 0;
2407                         pSRB->TargetStatus = 0;
2408                         pccb->ccb_h.status = CAM_REQ_CMP;
2409                         /* there is no error, (sense is invalid) */
2410                 }
2411         }
2412 ckc_e:
2413         if (pACB->scan_devices[target_id][target_lun]) {
2414           /*
2415            *   if SCSI command in "scan devices" duty
2416            */
2417                 if (pSRB->CmdBlock[0] == TEST_UNIT_READY)
2418                         pACB->scan_devices[target_id][target_lun] = 0;
2419                 /* SCSI command phase :test unit ready */
2420                 else if (pSRB->CmdBlock[0] == INQUIRY) {
2421                   /*
2422                    * SCSI command phase :inquiry scsi device data
2423                    * (type,capacity,manufacture....
2424                    */
2425                         if (pccb->ccb_h.status == CAM_SEL_TIMEOUT)
2426                                 goto NO_DEV;
2427                         ptr = (PSCSI_INQDATA) pcsio->data_ptr;
2428                         /* page fault */
2429                         TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n",
2430                             ptr->DevType);
2431                         bval1 = ptr->DevType & SCSI_DEVTYPE;
2432                         if (bval1 == SCSI_NODEV) {
2433 NO_DEV:
2434                                 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n",
2435                                     target_id,
2436                                     target_lun);
2437                                 intflag = splcam();
2438                                 pACB->scan_devices[target_id][target_lun] = 0;
2439                                 /* no device set scan device flag =0*/
2440                                 /* pDCB Q link */
2441                                 /* move the head of DCB to tempDCB*/
2442                                 pTempDCB=pACB->pLinkDCB;
2443                                 /* search current DCB for pass link */
2444                                 while (pTempDCB->pNextDCB != pDCB) {
2445                                         pTempDCB = pTempDCB->pNextDCB;
2446                                 }
2447                                 /*
2448                                  * when the current DCB found than connect
2449                                  * current DCB tail
2450                                  */
2451                                 /* to the DCB tail that before current DCB */
2452                                 pTempDCB->pNextDCB = pDCB->pNextDCB;
2453                                 /*
2454                                  * if there was only one DCB ,connect his tail
2455                                  * to his head
2456                                  */
2457                                 if (pACB->pLinkDCB == pDCB)
2458                                         pACB->pLinkDCB = pTempDCB->pNextDCB;
2459                                 if (pACB->pDCBRunRobin == pDCB)
2460                                         pACB->pDCBRunRobin = pTempDCB->pNextDCB;
2461                                 pDCB->DCBstatus &= ~DS_IN_QUEUE;
2462                                 pACB->DeviceCnt--;
2463                                 if (pACB->DeviceCnt == 0) {
2464                                         pACB->pLinkDCB = NULL;
2465                                         pACB->pDCBRunRobin = NULL;
2466                                 }
2467                                 splx(intflag);
2468                         } else {
2469 #ifdef trm_DEBUG1
2470                                 int j;
2471                                 for (j = 0; j < 28; j++) {
2472                                         TRM_DPRINTF("ptr=%2x ",
2473                                                 ((u_int8_t *)ptr)[j]);
2474                                 }
2475 #endif
2476                                 pDCB->DevType = bval1;
2477                                 if (bval1 == SCSI_DASD ||
2478                                     bval1 == SCSI_OPTICAL) {
2479                                         if ((((ptr->Vers & 0x07) >= 2) ||
2480                                               ((ptr->RDF & 0x0F) == 2)) &&
2481                                             (ptr->Flags & SCSI_INQ_CMDQUEUE) &&
2482                                             (pDCB->DevMode & TAG_QUEUING_) &&
2483                                             (pDCB->DevMode & EN_DISCONNECT_)) {
2484                                                 if (pDCB->DevMode &
2485                                                     TAG_QUEUING_) {
2486                                                         pDCB->
2487                                                             MaxActiveCommandCnt =
2488                                                           pACB->TagMaxNum;
2489                                                         pDCB->SyncMode |=
2490                                                           EN_TAG_QUEUING;
2491                                                         pDCB->tinfo.disc_tag |=
2492                                                           TRM_CUR_TAGENB;
2493                                                 } else {
2494                                                         pDCB->SyncMode |=
2495                                                           EN_ATN_STOP;
2496                                                         pDCB->tinfo.disc_tag &=
2497                                                           ~TRM_CUR_TAGENB;
2498                                                 }
2499                                         }
2500                                 }
2501                         }
2502                         /* pSRB->CmdBlock[0] == INQUIRY */
2503                 }
2504                 /* pACB->scan_devices[target_id][target_lun] */
2505         }
2506         intflag = splcam();
2507         /*  ReleaseSRB(pDCB, pSRB); */
2508         if (pSRB == pDCB->pGoingSRB)
2509                 pDCB->pGoingSRB = pSRB->pNextSRB;
2510         else {
2511                 psrb = pDCB->pGoingSRB;
2512                 while (psrb->pNextSRB != pSRB) {
2513                         psrb = psrb->pNextSRB;
2514                 }
2515                 psrb->pNextSRB = pSRB->pNextSRB;
2516                 if (pSRB == pDCB->pGoingLastSRB) {
2517                         pDCB->pGoingLastSRB = psrb;
2518                 }
2519         }
2520         pSRB->pNextSRB = pACB->pFreeSRB;
2521         pACB->pFreeSRB = pSRB;
2522         pDCB->GoingSRBCnt--;
2523         trm_DoWaitingSRB(pACB);
2524
2525         splx(intflag);
2526         /*  Notify cmd done */
2527         xpt_done (pccb);
2528 }
2529
2530 static void
2531 trm_DoingSRB_Done(PACB pACB)
2532 {
2533         PDCB            pDCB, pdcb;
2534         PSRB            psrb, psrb2;
2535         u_int16_t       cnt, i;
2536         union ccb       *pccb;
2537
2538         pDCB = pACB->pLinkDCB;
2539         if (pDCB == NULL)
2540                 return;
2541         pdcb = pDCB;
2542         do {
2543                 cnt = pdcb->GoingSRBCnt;
2544                 psrb = pdcb->pGoingSRB;
2545                 for (i = 0; i < cnt; i++) {
2546                         psrb2 = psrb->pNextSRB;
2547                         pccb = psrb->pccb;
2548                         pccb->ccb_h.status = CAM_SEL_TIMEOUT;
2549                         /*  ReleaseSRB(pDCB, pSRB); */
2550                         psrb->pNextSRB = pACB->pFreeSRB;
2551                         pACB->pFreeSRB = psrb;
2552                         xpt_done(pccb);
2553                         psrb  = psrb2;
2554                 }
2555                 pdcb->GoingSRBCnt = 0;
2556                 pdcb->pGoingSRB = NULL;
2557                 pdcb = pdcb->pNextDCB;
2558         }
2559         while (pdcb != pDCB);
2560 }
2561
2562 static void
2563 trm_ResetSCSIBus(PACB pACB)
2564 {
2565         int     intflag;
2566
2567         intflag = splcam();
2568         pACB->ACBFlag |= RESET_DEV;
2569
2570         trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL);
2571         while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET));
2572         splx(intflag);
2573         return;
2574 }
2575
2576 static void
2577 trm_ScsiRstDetect(PACB pACB)
2578 {
2579         int     intflag;
2580         u_long  wlval;
2581
2582         TRM_DPRINTF("trm_ScsiRstDetect \n");
2583         wlval = 1000;
2584         while (--wlval)
2585                 DELAY(1000);
2586         intflag = splcam();
2587         trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL);
2588
2589         trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL);
2590
2591         if (pACB->ACBFlag & RESET_DEV)
2592                 pACB->ACBFlag |= RESET_DONE;
2593         else {
2594                 pACB->ACBFlag |= RESET_DETECT;
2595                 trm_ResetDevParam(pACB);
2596                 /*      trm_DoingSRB_Done(pACB); ???? */
2597                 trm_RecoverSRB(pACB);
2598                 pACB->pActiveDCB = NULL;
2599                 pACB->ACBFlag = 0;
2600                 trm_DoWaitingSRB(pACB);
2601         }
2602         splx(intflag);
2603         return;
2604 }
2605
2606 static void
2607 trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB)
2608 {
2609         union ccb               *pccb;
2610         struct ccb_scsiio       *pcsio;
2611
2612         pccb  = pSRB->pccb;
2613         pcsio = &pccb->csio;
2614
2615         pSRB->SRBFlag |= AUTO_REQSENSE;
2616         pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0]));
2617         pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4]));
2618         pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) +
2619             pSRB->SRBSGCount);
2620         pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */
2621
2622         /* $$$$$$ Status of initiator/target $$$$$$$$ */
2623         pSRB->AdaptStatus = 0;
2624         pSRB->TargetStatus = 0;
2625         /* $$$$$$ Status of initiator/target $$$$$$$$ */
2626
2627         pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data);
2628         pSRB->SgSenseTemp.address = pSRB->pSRBSGL->address;
2629         pSRB->SgSenseTemp.length  = pSRB->pSRBSGL->length;
2630         pSRB->pSRBSGL->address = trm_get_sense_bufaddr(pACB, pSRB);
2631         pSRB->pSRBSGL->length = (u_long) sizeof(struct scsi_sense_data);
2632         pSRB->SRBSGCount = 1;
2633         pSRB->SRBSGIndex = 0;
2634
2635         *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003;
2636         pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5;
2637         *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len;
2638         pSRB->ScsiCmdLen = 6;
2639
2640         if (trm_StartSCSI(pACB, pDCB, pSRB))
2641            /*
2642             * If trm_StartSCSI return 1 :
2643             * current interrupt status is interrupt disreenable
2644             * It's said that SCSI processor has more one SRB need to do
2645             */
2646                 trm_RewaitSRB(pDCB, pSRB);
2647 }
2648
2649 static void
2650 trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB)
2651 {
2652
2653         pSRB->MsgCnt = 1;
2654         trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL);
2655 }
2656
2657 static void
2658 trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB)
2659 {
2660
2661         pSRB->MsgOutBuf[0] = MSG_ABORT;
2662         trm_EnableMsgOutAbort2(pACB, pSRB);
2663 }
2664
2665 static void
2666 trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j)
2667 {
2668         PNVRAMTYPE      pEEpromBuf;
2669         u_int8_t        bval,PeriodIndex;
2670         u_int           target_id,target_lun;
2671         PDCB            pTempDCB;
2672         int             intflag;
2673
2674         target_id  = i;
2675         target_lun = j;
2676
2677         /*
2678          *  Using the lun 0 device to init other DCB first, if the device
2679          *  has been initialized.
2680          *  I don't want init sync arguments one by one, it is the same.
2681          */
2682         if (target_lun != 0 &&
2683             (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE))
2684                 bcopy(&pACB->DCBarray[target_id][0], pDCB,
2685                     sizeof(TRM_DCB));
2686         intflag = splcam();
2687         if (pACB->pLinkDCB == 0) {
2688                 pACB->pLinkDCB = pDCB;
2689                 /*
2690                  * RunRobin impersonate the role
2691                  * that let each device had good proportion
2692                  * about SCSI command proceeding
2693                  */
2694                 pACB->pDCBRunRobin = pDCB;
2695                 pDCB->pNextDCB = pDCB;
2696         } else {
2697                 pTempDCB=pACB->pLinkDCB;
2698                 /* search the last nod of DCB link */
2699                 while (pTempDCB->pNextDCB != pACB->pLinkDCB)
2700                         pTempDCB = pTempDCB->pNextDCB;
2701                 /* connect current DCB with last DCB tail */
2702                 pTempDCB->pNextDCB = pDCB;
2703                 /* connect current DCB tail to this DCB Q head */
2704                 pDCB->pNextDCB=pACB->pLinkDCB;
2705         }
2706         splx(intflag);
2707
2708         pACB->DeviceCnt++;
2709         pDCB->TargetID = target_id;
2710         pDCB->TargetLUN =  target_lun;
2711         pDCB->pWaitingSRB = NULL;
2712         pDCB->pGoingSRB = NULL;
2713         pDCB->GoingSRBCnt = 0;
2714         pDCB->pActiveSRB = NULL;
2715         pDCB->MaxActiveCommandCnt = 1;
2716         pDCB->DCBFlag = 0;
2717         pDCB->DCBstatus |= DS_IN_QUEUE;
2718         /* $$$$$$$ */
2719         pEEpromBuf = &trm_eepromBuf[unit];
2720         pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0;
2721         pDCB->AdpMode = pEEpromBuf->NvramChannelCfg;
2722         /* $$$$$$$ */
2723         /*
2724          * disconnect enable ?
2725          */
2726         if (pDCB->DevMode & NTC_DO_DISCONNECT) {
2727                 bval = 0xC0;
2728                 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ;
2729         } else {
2730                 bval = 0x80;
2731                 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB);
2732         }
2733         bval |= target_lun;
2734         pDCB->IdentifyMsg = bval;
2735         if (target_lun != 0 &&
2736             (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE))
2737                 return;
2738         /* $$$$$$$ */
2739         /*
2740          * tag Qing enable ?
2741          */
2742         if (pDCB->DevMode & TAG_QUEUING_) {
2743                 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ;
2744         } else
2745                 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB);
2746         /* $$$$$$$ */
2747         /*
2748          * wide nego ,sync nego enable ?
2749          */
2750         pDCB->SyncPeriod = 0;
2751         pDCB->SyncOffset = 0;
2752         PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07;
2753         if (pACB->AdaptType==1) {/* is U2? */
2754             pDCB->MaxNegoPeriod=dc395u2x_clock_period[ PeriodIndex ];
2755             pDCB->tinfo.user.period=pDCB->MaxNegoPeriod;
2756             pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 31 : 0;
2757         } else {
2758         pDCB->MaxNegoPeriod=dc395x_clock_period[ PeriodIndex ];
2759             pDCB->tinfo.user.period=pDCB->MaxNegoPeriod;
2760             pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0;
2761         }
2762         pDCB->SyncMode = 0;
2763         if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) &&
2764             (pACB->Config & HCC_WIDE_CARD))
2765                 pDCB->SyncMode |= WIDE_NEGO_ENABLE;
2766         /* enable wide nego */
2767         if (pDCB->DevMode & NTC_DO_SYNC_NEGO)
2768                 pDCB->SyncMode |= SYNC_NEGO_ENABLE;
2769         /* enable sync nego */
2770         /* $$$$$$$ */
2771         /*
2772          *      Fill in tinfo structure.
2773          */
2774         pDCB->tinfo.user.width  = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ?
2775           MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT;
2776
2777         pDCB->tinfo.current.period = 0;
2778         pDCB->tinfo.current.offset = 0;
2779         pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT;
2780 }
2781
2782 static void
2783 trm_srbmapSG(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2784 {
2785         PSRB pSRB;
2786
2787         pSRB=(PSRB) arg;
2788         pSRB->SRBSGPhyAddr=segs->ds_addr;
2789         return;
2790 }
2791
2792 static void
2793 trm_destroySRB(PACB pACB)
2794 {
2795         PSRB pSRB;
2796
2797         pSRB = pACB->pFreeSRB;
2798         while (pSRB) {
2799                 if (pSRB->SRBSGPhyAddr)
2800                         bus_dmamap_unload(pACB->sg_dmat, pSRB->sg_dmamap);
2801                 if (pSRB->pSRBSGL)
2802                         bus_dmamem_free(pACB->sg_dmat, pSRB->pSRBSGL,
2803                             pSRB->sg_dmamap);
2804                 if (pSRB->dmamap)
2805                         bus_dmamap_destroy(pACB->buffer_dmat, pSRB->dmamap);
2806                 pSRB = pSRB->pNextSRB;
2807         }
2808 }
2809
2810 static int
2811 trm_initSRB(PACB pACB)
2812 {
2813         u_int16_t    i;
2814         PSRB    pSRB;
2815         int error;
2816
2817         for (i = 0; i < TRM_MAX_SRB_CNT; i++) {
2818                 pSRB = (PSRB)&pACB->pFreeSRB[i];
2819
2820                 if (bus_dmamem_alloc(pACB->sg_dmat, (void **)&pSRB->pSRBSGL,
2821                     BUS_DMA_NOWAIT, &pSRB->sg_dmamap) !=0 ) {
2822                         return ENXIO;
2823                 }
2824                 bus_dmamap_load(pACB->sg_dmat, pSRB->sg_dmamap, pSRB->pSRBSGL,
2825                     TRM_MAX_SG_LISTENTRY * sizeof(SGentry),
2826                     trm_srbmapSG, pSRB, /*flags*/0);
2827                 if (i != TRM_MAX_SRB_CNT - 1) {
2828                         /*
2829                          * link all SRB
2830                          */
2831                         pSRB->pNextSRB = &pACB->pFreeSRB[i+1];
2832                 } else {
2833                         /*
2834                          * load NULL to NextSRB of the last SRB
2835                          */
2836                         pSRB->pNextSRB = NULL;
2837                 }
2838                 pSRB->TagNumber = i;
2839
2840                 /*
2841                  * Create the dmamap.  This is no longer optional!
2842                  */
2843                 if ((error = bus_dmamap_create(pACB->buffer_dmat, 0,
2844                                                &pSRB->dmamap)) != 0)
2845                         return (error);
2846
2847         }
2848         return (0);
2849 }
2850
2851
2852
2853
2854 static void
2855 trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit)
2856 {
2857         PNVRAMTYPE      pEEpromBuf;
2858
2859         pEEpromBuf = &trm_eepromBuf[unit];
2860         pACB->max_id = 15;
2861
2862         if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN)
2863                 pACB->max_lun = 7;
2864         else
2865                 pACB->max_lun = 0;
2866
2867         TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n",
2868             pACB->max_id, pACB->max_lun);
2869         pACB->pLinkDCB = NULL;
2870         pACB->pDCBRunRobin = NULL;
2871         pACB->pActiveDCB = NULL;
2872         pACB->AdapterUnit = (u_int8_t)unit;
2873         pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId;
2874         pACB->AdaptSCSILUN = 0;
2875         pACB->DeviceCnt = 0;
2876         pACB->AdaptType = adaptType;
2877         pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag;
2878         pACB->ACBFlag = 0;
2879         return;
2880 }
2881
2882 static void
2883 NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB)
2884 {
2885         u_int8_t        *bpEeprom = (u_int8_t *) pEEpromBuf;
2886         u_int8_t        bAddr;
2887
2888         /* Enable SEEPROM */
2889         trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM),
2890             TRMREG_GEN_CONTROL);
2891         /*
2892          * Write enable
2893          */
2894         NVRAM_trm_write_cmd(pACB, 0x04, 0xFF);
2895         trm_reg_write8(0, TRMREG_GEN_NVRAM);
2896         NVRAM_trm_wait_30us(pACB);
2897         for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) {
2898                 NVRAM_trm_set_data(pACB, bAddr, *bpEeprom);
2899         }
2900         /*
2901          * Write disable
2902          */
2903         NVRAM_trm_write_cmd(pACB, 0x04, 0x00);
2904         trm_reg_write8(0 , TRMREG_GEN_NVRAM);
2905         NVRAM_trm_wait_30us(pACB);
2906         /* Disable SEEPROM */
2907         trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM),
2908             TRMREG_GEN_CONTROL);
2909         return;
2910 }
2911
2912 static void
2913 NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData)
2914 {
2915         int             i;
2916         u_int8_t        bSendData;
2917         /*
2918          * Send write command & address
2919          */
2920
2921         NVRAM_trm_write_cmd(pACB, 0x05, bAddr);
2922         /*
2923          * Write data
2924          */
2925         for (i = 0; i < 8; i++, bData <<= 1) {
2926                 bSendData = NVR_SELECT;
2927                 if (bData & 0x80)
2928                   /* Start from bit 7   */
2929                         bSendData |= NVR_BITOUT;
2930                 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM);
2931                 NVRAM_trm_wait_30us(pACB);
2932                 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM);
2933                 NVRAM_trm_wait_30us(pACB);
2934         }
2935         trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM);
2936         NVRAM_trm_wait_30us(pACB);
2937         /*
2938          * Disable chip select
2939          */
2940         trm_reg_write8(0 , TRMREG_GEN_NVRAM);
2941         NVRAM_trm_wait_30us(pACB);
2942         trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM);
2943         NVRAM_trm_wait_30us(pACB);
2944         /*
2945          * Wait for write ready
2946          */
2947         while (1) {
2948                 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM);
2949                 NVRAM_trm_wait_30us(pACB);
2950                 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM);
2951                 NVRAM_trm_wait_30us(pACB);
2952                 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) {
2953                         break;
2954                 }
2955         }
2956         /*
2957          * Disable chip select
2958          */
2959         trm_reg_write8(0, TRMREG_GEN_NVRAM);
2960         return;
2961 }
2962
2963 static void
2964 NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB)
2965 {
2966         u_int8_t        *bpEeprom = (u_int8_t*) pEEpromBuf;
2967         u_int8_t        bAddr;
2968
2969         /*
2970          * Enable SEEPROM
2971          */
2972         trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM),
2973             TRMREG_GEN_CONTROL);
2974         for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++)
2975                 *bpEeprom = NVRAM_trm_get_data(pACB, bAddr);
2976         /*
2977          * Disable SEEPROM
2978          */
2979         trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM),
2980             TRMREG_GEN_CONTROL);
2981         return;
2982 }
2983
2984 static u_int8_t
2985 NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr)
2986 {
2987         int             i;
2988         u_int8_t        bReadData, bData = 0;
2989         /*
2990         * Send read command & address
2991         */
2992
2993         NVRAM_trm_write_cmd(pACB, 0x06, bAddr);
2994
2995         for (i = 0; i < 8; i++) {
2996           /*
2997            * Read data
2998            */
2999                 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM);
3000                 NVRAM_trm_wait_30us(pACB);
3001                 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM);
3002                 /*
3003                  * Get data bit while falling edge
3004                  */
3005                 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM);
3006                 bData <<= 1;
3007                 if (bReadData & NVR_BITIN) {
3008                         bData |= 1;
3009                 }
3010                 NVRAM_trm_wait_30us(pACB);
3011         }
3012         /*
3013          * Disable chip select
3014          */
3015         trm_reg_write8(0, TRMREG_GEN_NVRAM);
3016         return (bData);
3017 }
3018
3019 static void
3020 NVRAM_trm_wait_30us(PACB pACB)
3021 {
3022
3023         /*    ScsiPortStallExecution(30);        wait 30 us     */
3024         trm_reg_write8(5, TRMREG_GEN_TIMER);
3025         while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT));
3026         return;
3027 }
3028
3029 static void
3030 NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr)
3031 {
3032         int             i;
3033         u_int8_t        bSendData;
3034
3035         for (i = 0; i < 3; i++, bCmd <<= 1) {
3036           /*
3037            * Program SB+OP code
3038            */
3039                 bSendData = NVR_SELECT;
3040                 if (bCmd & 0x04)
3041                         bSendData |= NVR_BITOUT;
3042                 /* start from bit 2 */
3043                 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM);
3044                 NVRAM_trm_wait_30us(pACB);
3045                 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM);
3046                 NVRAM_trm_wait_30us(pACB);
3047         }
3048         for (i = 0; i < 7; i++, bAddr <<= 1) {
3049           /*
3050            * Program address
3051            */
3052                 bSendData = NVR_SELECT;
3053                 if (bAddr & 0x40)
3054                   /* Start from bit 6   */
3055                         bSendData |= NVR_BITOUT;
3056                 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM);
3057                 NVRAM_trm_wait_30us(pACB);
3058                 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM);
3059                 NVRAM_trm_wait_30us(pACB);
3060         }
3061         trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM);
3062         NVRAM_trm_wait_30us(pACB);
3063 }
3064
3065 static void
3066 trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB)
3067 {
3068         u_int16_t       *wpEeprom = (u_int16_t *) pEEpromBuf;
3069         u_int16_t       wAddr, wCheckSum;
3070         u_long  dAddr, *dpEeprom;
3071
3072         NVRAM_trm_read_all(pEEpromBuf,pACB);
3073         wCheckSum = 0;
3074         for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf;
3075             wAddr < 64; wAddr++, wpEeprom++) {
3076                 wCheckSum += *wpEeprom;
3077         }
3078         if (wCheckSum != 0x1234) {
3079           /*
3080            * Checksum error, load default
3081            */
3082                 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM;
3083                 pEEpromBuf->NvramSubVendorID[1] =
3084                   (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8);
3085                 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040;
3086                 pEEpromBuf->NvramSubSysID[1] =
3087                   (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8);
3088                 pEEpromBuf->NvramSubClass = 0x00;
3089                 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM;
3090                 pEEpromBuf->NvramVendorID[1] =
3091                   (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8);
3092                 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040;
3093                 pEEpromBuf->NvramDeviceID[1] =
3094                   (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8);
3095                 pEEpromBuf->NvramReserved = 0x00;
3096
3097                 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget;
3098                     dAddr < 16; dAddr++, dpEeprom++) {
3099                         *dpEeprom = 0x00000077;
3100                         /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */
3101                 }
3102
3103                 *dpEeprom++ = 0x04000F07;
3104                 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */
3105                 *dpEeprom++ = 0x00000015;
3106                 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */
3107                 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++)
3108                         *dpEeprom = 0x00;
3109                 pEEpromBuf->NvramCheckSum = 0x00;
3110                 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf;
3111                     wAddr < 63; wAddr++, wpEeprom++)
3112                         wCheckSum += *wpEeprom;
3113                 *wpEeprom = 0x1234 - wCheckSum;
3114                 NVRAM_trm_write_all(pEEpromBuf,pACB);
3115         }
3116         return;
3117 }
3118 static int
3119 trm_initAdapter(PACB pACB, u_int16_t unit)
3120 {
3121         PNVRAMTYPE      pEEpromBuf;
3122         u_int16_t       wval;
3123         u_int8_t        bval;
3124
3125         pEEpromBuf = &trm_eepromBuf[unit];
3126
3127         /* 250ms selection timeout */
3128         trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT);
3129         /* Mask all the interrupt */
3130         trm_reg_write8(0x00, TRMREG_DMA_INTEN);
3131         trm_reg_write8(0x00, TRMREG_SCSI_INTEN);
3132         /* Reset SCSI module */
3133         trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL);
3134         /* program configuration 0 */
3135         pACB->Config = HCC_AUTOTERM | HCC_PARITY;
3136         if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI)
3137                 pACB->Config |= HCC_WIDE_CARD;
3138         if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET)
3139                 pACB->Config |= HCC_SCSI_RESET;
3140         if (pACB->Config & HCC_PARITY)
3141                 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK;
3142         else
3143                 bval = PHASELATCH | INITIATOR | BLOCKRST ;
3144         trm_reg_write8(bval,TRMREG_SCSI_CONFIG0);
3145         /* program configuration 1 */
3146         trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1);
3147         /* program Host ID */
3148         bval = pEEpromBuf->NvramScsiId;
3149         trm_reg_write8(bval, TRMREG_SCSI_HOSTID);
3150         /* set ansynchronous transfer */
3151         trm_reg_write8(0x00, TRMREG_SCSI_OFFSET);
3152         /* Trun LED control off*/
3153         wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F;
3154         trm_reg_write16(wval, TRMREG_GEN_CONTROL);
3155         /* DMA config */
3156         wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE;
3157         trm_reg_write16(wval, TRMREG_DMA_CONFIG);
3158         /* Clear pending interrupt status */
3159         trm_reg_read8(TRMREG_SCSI_INTSTATUS);
3160         /* Enable SCSI interrupt */
3161         trm_reg_write8(0x7F, TRMREG_SCSI_INTEN);
3162         trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN);
3163         return (0);
3164 }
3165
3166 static void
3167 trm_mapSRB(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3168 {
3169         PACB pACB;
3170
3171         pACB = (PACB)arg;
3172         pACB->srb_physbase = segs->ds_addr;
3173 }
3174
3175 static void
3176 trm_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3177 {
3178         bus_addr_t *baddr;
3179
3180         baddr = (bus_addr_t *)arg;
3181         *baddr = segs->ds_addr;
3182 }
3183
3184 static PACB
3185 trm_init(u_int16_t unit, device_t dev)
3186 {
3187         PACB            pACB;
3188         int             rid = PCIR_BAR(0), i = 0, j = 0;
3189         u_int16_t       adaptType = 0;
3190
3191         pACB = (PACB) device_get_softc(dev);
3192         if (!pACB) {
3193                 printf("trm%d: cannot allocate ACB !\n", unit);
3194                 return (NULL);
3195         }
3196         pACB->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
3197             &rid, RF_ACTIVE);
3198         if (pACB->iores == NULL) {
3199                 printf("trm_init: bus_alloc_resource failed!\n");
3200                 return (NULL);
3201         }
3202         switch (pci_get_devid(dev)) {
3203         case PCI_DEVICEID_TRMS1040:
3204                 adaptType = 0;
3205                 break;
3206         case PCI_DEVICEID_TRMS2080:
3207                 adaptType = 1;
3208                 break;
3209         default:
3210                 printf("trm_init %d: unknown adapter type!\n", unit);
3211                 goto bad;
3212         }
3213         pACB->dev = dev;
3214         pACB->tag = rman_get_bustag(pACB->iores);
3215         pACB->bsh = rman_get_bushandle(pACB->iores);
3216         if (bus_dma_tag_create(
3217         /*parent_dmat*/ bus_get_dma_tag(dev),
3218         /*alignment*/   1,
3219         /*boundary*/    0,
3220         /*lowaddr*/     BUS_SPACE_MAXADDR,
3221         /*highaddr*/    BUS_SPACE_MAXADDR,
3222         /*filter*/      NULL,
3223         /*filterarg*/   NULL,
3224         /*maxsize*/     BUS_SPACE_MAXSIZE_32BIT,
3225         /*nsegments*/   BUS_SPACE_UNRESTRICTED,
3226         /*maxsegsz*/    BUS_SPACE_MAXSIZE_32BIT,
3227         /*flags*/       0,
3228         /*lockfunc*/    NULL,
3229         /*lockarg*/     NULL,
3230         /* dmat */      &pACB->parent_dmat) != 0)
3231                 goto bad;
3232         if (bus_dma_tag_create(
3233         /*parent_dmat*/ pACB->parent_dmat,
3234         /*alignment*/   1,
3235         /*boundary*/    0,
3236         /*lowaddr*/     BUS_SPACE_MAXADDR,
3237         /*highaddr*/    BUS_SPACE_MAXADDR,
3238         /*filter*/      NULL,
3239         /*filterarg*/   NULL,
3240         /*maxsize*/     TRM_MAXPHYS,
3241         /*nsegments*/   TRM_NSEG,
3242         /*maxsegsz*/    TRM_MAXTRANSFER_SIZE,
3243         /*flags*/       BUS_DMA_ALLOCNOW,
3244         /*lockfunc*/    busdma_lock_mutex,
3245         /*lockarg*/     &Giant,
3246         /* dmat */      &pACB->buffer_dmat) != 0)
3247                 goto bad;
3248         /* DMA tag for our ccb structures */
3249         if (bus_dma_tag_create(
3250         /*parent_dmat*/pACB->parent_dmat,
3251         /*alignment*/  1,
3252         /*boundary*/   0,
3253         /*lowaddr*/    BUS_SPACE_MAXADDR,
3254         /*highaddr*/   BUS_SPACE_MAXADDR,
3255         /*filter*/     NULL,
3256         /*filterarg*/  NULL,
3257         /*maxsize*/    TRM_MAX_SRB_CNT * sizeof(TRM_SRB),
3258         /*nsegments*/  1,
3259         /*maxsegsz*/   TRM_MAXTRANSFER_SIZE,
3260         /*flags*/      0,
3261         /*lockfunc*/   busdma_lock_mutex,
3262         /*lockarg*/    &Giant,
3263         /*dmat*/       &pACB->srb_dmat) != 0) {
3264                 printf("trm_init %d: bus_dma_tag_create SRB failure\n", unit);
3265                 goto bad;
3266         }
3267         if (bus_dmamem_alloc(pACB->srb_dmat, (void **)&pACB->pFreeSRB,
3268             BUS_DMA_NOWAIT, &pACB->srb_dmamap) != 0) {
3269                 printf("trm_init %d: bus_dmamem_alloc SRB failure\n", unit);
3270                 goto bad;
3271         }
3272         bus_dmamap_load(pACB->srb_dmat, pACB->srb_dmamap, pACB->pFreeSRB,
3273             TRM_MAX_SRB_CNT * sizeof(TRM_SRB), trm_mapSRB, pACB,
3274             /* flags */0);
3275         /* Create, allocate, and map DMA buffers for autosense data */
3276         if (bus_dma_tag_create(
3277             /*parent_dmat*/pACB->parent_dmat,
3278             /*alignment*/1,
3279             /*boundary*/0,
3280             /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
3281             /*highaddr*/BUS_SPACE_MAXADDR,
3282             /*filter*/NULL, /*filterarg*/NULL,
3283             sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT,
3284             /*nsegments*/1,
3285             /*maxsegsz*/TRM_MAXTRANSFER_SIZE,
3286             /*flags*/0, /*lockfunc*/busdma_lock_mutex,
3287             /*lockarg*/&Giant, &pACB->sense_dmat) != 0) {
3288           if (bootverbose)
3289             device_printf(dev, "cannot create sense buffer dmat\n");
3290           goto bad;
3291         }
3292
3293         if (bus_dmamem_alloc(pACB->sense_dmat, (void **)&pACB->sense_buffers,
3294                              BUS_DMA_NOWAIT, &pACB->sense_dmamap) != 0)
3295                 goto bad;
3296
3297         bus_dmamap_load(pACB->sense_dmat, pACB->sense_dmamap,
3298                        pACB->sense_buffers,
3299                        sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT,
3300                        trm_dmamap_cb, &pACB->sense_busaddr, /*flags*/0);
3301
3302         trm_check_eeprom(&trm_eepromBuf[unit],pACB);
3303         trm_initACB(pACB, adaptType, unit);
3304         for (i = 0; i < (pACB->max_id + 1); i++) {
3305                 if (pACB->AdaptSCSIID == i)
3306                         continue;
3307                 for(j = 0; j < (pACB->max_lun + 1); j++) {
3308                         pACB->scan_devices[i][j] = 1;
3309                         /* we assume we need to scan all devices */
3310                         trm_initDCB(pACB, &pACB->DCBarray[i][j], unit, i, j);
3311                 }
3312         }
3313         bzero(pACB->pFreeSRB, TRM_MAX_SRB_CNT * sizeof(TRM_SRB));
3314         if (bus_dma_tag_create(
3315                     /*parent_dmat*/pACB->parent_dmat,
3316                     /*alignment*/  1,
3317                     /*boundary*/   0,
3318                     /*lowaddr*/    BUS_SPACE_MAXADDR,
3319                     /*highaddr*/   BUS_SPACE_MAXADDR,
3320                     /*filter*/     NULL,
3321                     /*filterarg*/  NULL,
3322                     /*maxsize*/    TRM_MAX_SG_LISTENTRY * sizeof(SGentry),
3323                     /*nsegments*/  1,
3324                     /*maxsegsz*/   TRM_MAXTRANSFER_SIZE,
3325                     /*flags*/      0,
3326                     /*lockfunc*/   busdma_lock_mutex,
3327                     /*lockarg*/    &Giant,
3328                     /*dmat*/       &pACB->sg_dmat) != 0)
3329                 goto bad;
3330
3331         if (trm_initSRB(pACB)) {
3332                 printf("trm_initSRB: error\n");
3333                 goto bad;
3334         }
3335         if (trm_initAdapter(pACB, unit)) {
3336                 printf("trm_initAdapter: initial ERROR\n");
3337                 goto bad;
3338         }
3339         return (pACB);
3340 bad:
3341         if (pACB->iores)
3342                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0),
3343                     pACB->iores);
3344         if (pACB->sense_dmamap) {
3345                 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap);
3346                 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers,
3347                     pACB->sense_dmamap);
3348         }
3349         if (pACB->sense_dmat)
3350                 bus_dma_tag_destroy(pACB->sense_dmat);
3351         if (pACB->sg_dmat) {
3352                 trm_destroySRB(pACB);
3353                 bus_dma_tag_destroy(pACB->sg_dmat);
3354         }
3355         if (pACB->pFreeSRB) {
3356                 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap);
3357                 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB,
3358                     pACB->srb_dmamap);
3359         }
3360         if (pACB->srb_dmat)
3361                 bus_dma_tag_destroy(pACB->srb_dmat);
3362         if (pACB->buffer_dmat)
3363                 bus_dma_tag_destroy(pACB->buffer_dmat);
3364         if (pACB->parent_dmat)
3365                 bus_dma_tag_destroy(pACB->parent_dmat);
3366         return (NULL);
3367 }
3368
3369 static int
3370 trm_attach(device_t dev)
3371 {
3372         struct  cam_devq *device_Q;
3373         u_long  device_id;
3374         PACB    pACB = 0;
3375         int     rid = 0;
3376         int unit = device_get_unit(dev);
3377
3378         device_id = pci_get_devid(dev);
3379         /*
3380          * These cards do not allow memory mapped accesses
3381          */
3382         if ((pACB = trm_init((u_int16_t) unit,
3383             dev)) == NULL) {
3384                 printf("trm%d: trm_init error!\n",unit);
3385                 return (ENXIO);
3386         }
3387         /* After setting up the adapter, map our interrupt */
3388         /*
3389          * Now let the CAM generic SCSI layer find the SCSI devices on the bus
3390          * start queue to reset to the idle loop.
3391          * Create device queue of SIM(s)
3392          * (MAX_START_JOB - 1) : max_sim_transactions
3393          */
3394         pACB->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3395             RF_SHAREABLE | RF_ACTIVE);
3396         if (pACB->irq == NULL ||
3397             bus_setup_intr(dev, pACB->irq,
3398             INTR_TYPE_CAM, NULL, trm_Interrupt, pACB, &pACB->ih)) {
3399                 printf("trm%d: register Interrupt handler error!\n", unit);
3400                 goto bad;
3401         }
3402         device_Q = cam_simq_alloc(TRM_MAX_START_JOB);
3403         if (device_Q == NULL){
3404                 printf("trm%d: device_Q == NULL !\n",unit);
3405                 goto bad;
3406         }
3407         /*
3408          * Now tell the generic SCSI layer
3409          * about our bus.
3410          * If this is the xpt layer creating a sim, then it's OK
3411          * to wait for an allocation.
3412          * XXX Should we pass in a flag to indicate that wait is OK?
3413          *
3414          *                    SIM allocation
3415          *
3416          *                 SCSI Interface Modules
3417          * The sim driver creates a sim for each controller.  The sim device
3418          * queue is separately created in order to allow resource sharing betwee
3419          * sims.  For instance, a driver may create one sim for each channel of
3420          * a multi-channel controller and use the same queue for each channel.
3421          * In this way, the queue resources are shared across all the channels
3422          * of the multi-channel controller.
3423          * trm_action     : sim_action_func
3424          * trm_poll       : sim_poll_func
3425          * "trm"        : sim_name ,if sim_name =  "xpt" ..M_DEVBUF,M_WAITOK
3426          * pACB         : *softc    if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT
3427          * pACB->unit   : unit
3428          * 1            : max_dev_transactions
3429          * MAX_TAGS     : max_tagged_dev_transactions
3430          *
3431          *  *******Construct our first channel SIM entry
3432          */
3433         pACB->psim = cam_sim_alloc(trm_action,
3434             trm_poll,
3435             "trm",
3436             pACB,
3437             unit,
3438             &Giant,
3439             1,
3440             TRM_MAX_TAGS_CMD_QUEUE,
3441             device_Q);
3442         if (pACB->psim == NULL) {
3443                 printf("trm%d: SIM allocate fault !\n",unit);
3444                 cam_simq_free(device_Q);  /* SIM allocate fault*/
3445                 goto bad;
3446         }
3447         if (xpt_bus_register(pACB->psim, dev, 0) != CAM_SUCCESS)  {
3448                 printf("trm%d: xpt_bus_register fault !\n",unit);
3449                 goto bad;
3450         }
3451         if (xpt_create_path(&pACB->ppath,
3452               NULL,
3453               cam_sim_path(pACB->psim),
3454               CAM_TARGET_WILDCARD,
3455               CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
3456                 printf("trm%d: xpt_create_path fault !\n",unit);
3457                 xpt_bus_deregister(cam_sim_path(pACB->psim));
3458                 goto bad;
3459         }
3460         return (0);
3461 bad:
3462         if (pACB->iores)
3463                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0),
3464                     pACB->iores);
3465         if (pACB->sg_dmat) {
3466                 trm_destroySRB(pACB);
3467                 bus_dma_tag_destroy(pACB->sg_dmat);
3468         }
3469
3470         if (pACB->pFreeSRB) {
3471                 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap);
3472                 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB,
3473                     pACB->srb_dmamap);
3474         }
3475         if (pACB->srb_dmat)
3476                 bus_dma_tag_destroy(pACB->srb_dmat);
3477         if (pACB->sense_buffers) {
3478                   bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap);
3479                   bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers,
3480                       pACB->sense_dmamap);
3481         }
3482         if (pACB->sense_dmat)
3483                 bus_dma_tag_destroy(pACB->sense_dmat);
3484         if (pACB->buffer_dmat)
3485                 bus_dma_tag_destroy(pACB->buffer_dmat);
3486         if (pACB->ih)
3487                 bus_teardown_intr(dev, pACB->irq, pACB->ih);
3488         if (pACB->irq)
3489                 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq);
3490         if (pACB->psim)
3491                 cam_sim_free(pACB->psim, TRUE);
3492
3493         return (ENXIO);
3494
3495 }
3496
3497 /*
3498 *                  pci_device
3499 *         trm_probe (device_t tag, pcidi_t type)
3500 *
3501 */
3502 static int
3503 trm_probe(device_t dev)
3504 {
3505         switch (pci_get_devid(dev)) {
3506         case PCI_DEVICEID_TRMS1040:
3507                 device_set_desc(dev,
3508                     "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter");
3509                 return (BUS_PROBE_DEFAULT);
3510         case PCI_DEVICEID_TRMS2080:
3511                 device_set_desc(dev,
3512                     "Tekram DC395U2D/U2W Fast40 Wide SCSI Adapter");
3513                 return (BUS_PROBE_DEFAULT);
3514         default:
3515                 return (ENXIO);
3516         }
3517 }
3518
3519 static int
3520 trm_detach(device_t dev)
3521 {
3522         PACB pACB = device_get_softc(dev);
3523
3524         bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), pACB->iores);
3525         trm_destroySRB(pACB);
3526         bus_dma_tag_destroy(pACB->sg_dmat);
3527         bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap);
3528         bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB,
3529             pACB->srb_dmamap);
3530         bus_dma_tag_destroy(pACB->srb_dmat);
3531         bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap);
3532         bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers,
3533             pACB->sense_dmamap);
3534         bus_dma_tag_destroy(pACB->sense_dmat);
3535         bus_dma_tag_destroy(pACB->buffer_dmat);
3536         bus_teardown_intr(dev, pACB->irq, pACB->ih);
3537         bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq);
3538         xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL);
3539         xpt_free_path(pACB->ppath);
3540         xpt_bus_deregister(cam_sim_path(pACB->psim));
3541         cam_sim_free(pACB->psim, TRUE);
3542         return (0);
3543 }
3544 static device_method_t trm_methods[] = {
3545         /* Device interface */
3546         DEVMETHOD(device_probe,         trm_probe),
3547         DEVMETHOD(device_attach,        trm_attach),
3548         DEVMETHOD(device_detach,        trm_detach),
3549         { 0, 0 }
3550 };
3551
3552 static driver_t trm_driver = {
3553         "trm", trm_methods, sizeof(struct _ACB)
3554 };
3555
3556 static devclass_t trm_devclass;
3557 DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0);
3558 MODULE_DEPEND(trm, pci, 1, 1, 1);
3559 MODULE_DEPEND(trm, cam, 1, 1, 1);