4 * BY : C.L. Huang (ching@tekram.com.tw)
5 * Erich Chen (erich@tekram.com.tw)
6 * Description: Device Driver for Tekram SCSI adapters
7 * DC395U/UW/F ,DC315/U(TRM-S1040)
8 * DC395U2D/U2W(TRM-S2080)
9 * PCI SCSI Bus Master Host Adapter
10 * (SCSI chip set used Tekram ASIC TRM-S1040,TRM-S2080)
13 #include <sys/cdefs.h>
14 __FBSDID("$FreeBSD$");
19 * REV# DATE NAME DESCRIPTION
20 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM)
21 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI
22 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free
23 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x
24 * 1.09 11/03/2000 ERICH CHEN Modify for 4.1.R ,new sim
25 * 1.10 10/10/2001 Oscar Feng Fixed CAM rescan hang up bug.
26 * 1.11 10/13/2001 Oscar Feng Fixed wrong Async speed display bug.
30 * (C)Copyright 1995-2001 Tekram Technology Co.,Ltd.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
40 * 3. The name of the author may not be used to endorse or promote products
41 * derived from this software without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
44 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
46 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
48 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
50 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
52 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 * Imported into FreeBSD source repository, and updated to compile under
58 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <se@FreeBSD.Org>, 1996-12-17
62 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard
63 * <doginou@ci0.org>, 2002-03-04
66 #include <sys/param.h>
68 #include <sys/systm.h>
69 #include <sys/malloc.h>
70 #include <sys/queue.h>
71 #if __FreeBSD_version >= 500000
76 #include <sys/kernel.h>
77 #include <sys/module.h>
82 #include <dev/pci/pcivar.h>
83 #include <dev/pci/pcireg.h>
84 #include <machine/resource.h>
85 #include <machine/bus.h>
89 #include <cam/cam_ccb.h>
90 #include <cam/cam_sim.h>
91 #include <cam/cam_xpt_sim.h>
92 #include <cam/cam_debug.h>
94 #include <cam/scsi/scsi_all.h>
95 #include <cam/scsi/scsi_message.h>
97 #include <dev/trm/trm.h>
99 #define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg)
100 #define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg)
101 #define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg)
102 #define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\
104 #define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\
106 #define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\
109 #define PCI_Vendor_ID_TEKRAM 0x1DE1
110 #define PCI_Device_ID_TRM_S1040 0x0391
111 #define PCI_DEVICEID_TRMS1040 0x03911DE1
112 #define PCI_DEVICEID_TRMS2080 0x03921DE1
115 #define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg)
117 #define TRM_DPRINTF(fmt, arg...) {}
118 #endif /* TRM_DEBUG */
120 static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB);
121 static void NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB);
122 static u_int8_t NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr);
123 static void NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB);
124 static void NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData);
125 static void NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr);
126 static void NVRAM_trm_wait_30us(PACB pACB);
128 static void trm_Interrupt(void *vpACB);
129 static void trm_DataOutPhase0(PACB pACB, PSRB pSRB,
130 u_int16_t * pscsi_status);
131 static void trm_DataInPhase0(PACB pACB, PSRB pSRB,
132 u_int16_t * pscsi_status);
133 static void trm_CommandPhase0(PACB pACB, PSRB pSRB,
134 u_int16_t * pscsi_status);
135 static void trm_StatusPhase0(PACB pACB, PSRB pSRB,
136 u_int16_t * pscsi_status);
137 static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB,
138 u_int16_t * pscsi_status);
139 static void trm_MsgInPhase0(PACB pACB, PSRB pSRB,
140 u_int16_t * pscsi_status);
141 static void trm_DataOutPhase1(PACB pACB, PSRB pSRB,
142 u_int16_t * pscsi_status);
143 static void trm_DataInPhase1(PACB pACB, PSRB pSRB,
144 u_int16_t * pscsi_status);
145 static void trm_CommandPhase1(PACB pACB, PSRB pSRB,
146 u_int16_t * pscsi_status);
147 static void trm_StatusPhase1(PACB pACB, PSRB pSRB,
148 u_int16_t * pscsi_status);
149 static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB,
150 u_int16_t * pscsi_status);
151 static void trm_MsgInPhase1(PACB pACB, PSRB pSRB,
152 u_int16_t * pscsi_status);
153 static void trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status);
154 static void trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status);
155 static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB);
156 static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir);
157 static void trm_Disconnect(PACB pACB);
158 static void trm_Reselect(PACB pACB);
159 static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB);
160 static void trm_DoingSRB_Done(PACB pACB);
161 static void trm_ScsiRstDetect(PACB pACB);
162 static void trm_ResetSCSIBus(PACB pACB);
163 static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB);
164 static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB);
165 static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB);
166 static void trm_SendSRB(PACB pACB, PSRB pSRB);
167 static int trm_probe(device_t tag);
168 static int trm_attach(device_t tag);
169 static void trm_reset(PACB pACB);
171 static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB);
173 static int trm_initAdapter(PACB pACB, u_int16_t unit);
174 static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,
175 u_int32_t i, u_int32_t j);
176 static int trm_initSRB(PACB pACB);
177 static void trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit);
178 /* CAM SIM entry points */
179 #define ccb_trmsrb_ptr spriv_ptr0
180 #define ccb_trmacb_ptr spriv_ptr1
181 static void trm_action(struct cam_sim *psim, union ccb *pccb);
182 static void trm_poll(struct cam_sim *psim);
185 static void * trm_SCSI_phase0[] = {
186 trm_DataOutPhase0, /* phase:0 */
187 trm_DataInPhase0, /* phase:1 */
188 trm_CommandPhase0, /* phase:2 */
189 trm_StatusPhase0, /* phase:3 */
190 trm_Nop0, /* phase:4 */
191 trm_Nop1, /* phase:5 */
192 trm_MsgOutPhase0, /* phase:6 */
193 trm_MsgInPhase0, /* phase:7 */
198 * stateV = (void *) trm_SCSI_phase1[phase]
201 static void * trm_SCSI_phase1[] = {
202 trm_DataOutPhase1, /* phase:0 */
203 trm_DataInPhase1, /* phase:1 */
204 trm_CommandPhase1, /* phase:2 */
205 trm_StatusPhase1, /* phase:3 */
206 trm_Nop0, /* phase:4 */
207 trm_Nop1, /* phase:5 */
208 trm_MsgOutPhase1, /* phase:6 */
209 trm_MsgInPhase1, /* phase:7 */
213 NVRAMTYPE trm_eepromBuf[TRM_MAX_ADAPTER_NUM];
215 *Fast20: 000 50ns, 20.0 Mbytes/s
216 * 001 75ns, 13.3 Mbytes/s
217 * 010 100ns, 10.0 Mbytes/s
218 * 011 125ns, 8.0 Mbytes/s
219 * 100 150ns, 6.6 Mbytes/s
220 * 101 175ns, 5.7 Mbytes/s
221 * 110 200ns, 5.0 Mbytes/s
222 * 111 250ns, 4.0 Mbytes/s
224 *Fast40: 000 25ns, 40.0 Mbytes/s
225 * 001 50ns, 20.0 Mbytes/s
226 * 010 75ns, 13.3 Mbytes/s
227 * 011 100ns, 10.0 Mbytes/s
228 * 100 125ns, 8.0 Mbytes/s
229 * 101 150ns, 6.6 Mbytes/s
230 * 110 175ns, 5.7 Mbytes/s
231 * 111 200ns, 5.0 Mbytes/s
234 u_int8_t dc395x_clock_period[] = {
235 12,/* 48 ns 20 MB/sec */
236 18,/* 72 ns 13.3 MB/sec */
237 25,/* 100 ns 10.0 MB/sec */
238 31,/* 124 ns 8.0 MB/sec */
239 37,/* 148 ns 6.6 MB/sec */
240 43,/* 172 ns 5.7 MB/sec */
241 50,/* 200 ns 5.0 MB/sec */
242 62 /* 248 ns 4.0 MB/sec */
245 u_int8_t dc395u2x_clock_period[]={
246 10,/* 25 ns 40.0 MB/sec */
247 12,/* 48 ns 20.0 MB/sec */
248 18,/* 72 ns 13.3 MB/sec */
249 25,/* 100 ns 10.0 MB/sec */
250 31,/* 124 ns 8.0 MB/sec */
251 37,/* 148 ns 6.6 MB/sec */
252 43,/* 172 ns 5.7 MB/sec */
253 50,/* 200 ns 5.0 MB/sec */
256 #define dc395x_tinfo_period dc395x_clock_period
257 #define dc395u2x_tinfo_period dc395u2x_clock_period
260 trm_GetSRB(PACB pACB)
266 pSRB = pACB->pFreeSRB;
268 pACB->pFreeSRB = pSRB->pNextSRB;
269 pSRB->pNextSRB = NULL;
276 trm_RewaitSRB0(PDCB pDCB, PSRB pSRB)
282 if ((psrb1 = pDCB->pWaitingSRB)) {
283 pSRB->pNextSRB = psrb1;
284 pDCB->pWaitingSRB = pSRB;
286 pSRB->pNextSRB = NULL;
287 pDCB->pWaitingSRB = pSRB;
288 pDCB->pWaitingLastSRB = pSRB;
294 trm_RewaitSRB(PDCB pDCB, PSRB pSRB)
301 psrb1 = pDCB->pGoingSRB;
304 * if this SRB is GoingSRB
305 * remove this SRB from GoingSRB Q
307 pDCB->pGoingSRB = psrb1->pNextSRB;
310 * if this SRB is not current GoingSRB
311 * remove this SRB from GoingSRB Q
313 while (pSRB != psrb1->pNextSRB)
314 psrb1 = psrb1->pNextSRB;
315 psrb1->pNextSRB = pSRB->pNextSRB;
316 if (pSRB == pDCB->pGoingLastSRB)
317 pDCB->pGoingLastSRB = psrb1;
319 if ((psrb1 = pDCB->pWaitingSRB)) {
321 * if WaitingSRB Q is not NULL
322 * Q back this SRB into WaitingSRB
325 pSRB->pNextSRB = psrb1;
326 pDCB->pWaitingSRB = pSRB;
328 pSRB->pNextSRB = NULL;
329 pDCB->pWaitingSRB = pSRB;
330 pDCB->pWaitingLastSRB = pSRB;
336 trm_DoWaitingSRB(PACB pACB)
343 if (!(pACB->pActiveDCB) &&
344 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) {
345 ptr = pACB->pDCBRunRobin;
347 ptr = pACB->pLinkDCB;
348 pACB->pDCBRunRobin = ptr;
352 pACB->pDCBRunRobin = ptr1->pNextDCB;
353 if (!(ptr1->MaxActiveCommandCnt > ptr1->GoingSRBCnt)
354 || !(pSRB = ptr1->pWaitingSRB)) {
355 if (pACB->pDCBRunRobin == ptr)
357 ptr1 = ptr1->pNextDCB;
359 if (!trm_StartSCSI(pACB, ptr1, pSRB)) {
361 * If trm_StartSCSI return 0 :
362 * current interrupt status is interrupt enable
363 * It's said that SCSI processor is unoccupied
366 if (ptr1->pWaitingLastSRB == pSRB) {
367 ptr1->pWaitingSRB = NULL;
368 ptr1->pWaitingLastSRB = NULL;
370 ptr1->pWaitingSRB = pSRB->pNextSRB;
371 pSRB->pNextSRB = NULL;
373 ptr1->pGoingLastSRB->pNextSRB = pSRB;
375 ptr1->pGoingSRB = pSRB;
376 ptr1->pGoingLastSRB = pSRB;
387 trm_SRBwaiting(PDCB pDCB, PSRB pSRB)
390 if (pDCB->pWaitingSRB) {
391 pDCB->pWaitingLastSRB->pNextSRB = pSRB;
392 pDCB->pWaitingLastSRB = pSRB;
393 pSRB->pNextSRB = NULL;
395 pDCB->pWaitingSRB = pSRB;
396 pDCB->pWaitingLastSRB = pSRB;
401 trm_get_sense_bufaddr(PACB pACB, PSRB pSRB)
405 offset = pSRB->TagNumber;
406 return (pACB->sense_busaddr +
407 (offset * sizeof(struct scsi_sense_data)));
410 static struct scsi_sense_data *
411 trm_get_sense_buf(PACB pACB, PSRB pSRB)
415 offset = pSRB->TagNumber;
416 return (&pACB->sense_buffers[offset]);
419 trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
425 u_long totalxferlen=0;
430 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr;
431 TRM_DPRINTF("trm_ExecuteSRB..........\n");
434 bus_dma_segment_t *end_seg;
437 /* Copy the segments into our SG list */
438 end_seg = dm_segs + nseg;
440 while (dm_segs < end_seg) {
441 psg->address = dm_segs->ds_addr;
442 psg->length = (u_long)dm_segs->ds_len;
443 totalxferlen += dm_segs->ds_len;
447 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
448 op = BUS_DMASYNC_PREREAD;
450 op = BUS_DMASYNC_PREWRITE;
452 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op);
455 pSRB->SRBTotalXferLength = totalxferlen;
456 pSRB->SRBSGCount = nseg;
457 pSRB->SRBSGIndex = 0;
458 pSRB->AdaptStatus = 0;
459 pSRB->TargetStatus = 0;
464 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */
466 if (ccb->ccb_h.status != CAM_REQ_INPROG) {
468 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap);
469 pSRB->pNextSRB = pACB->pFreeSRB;
470 pACB->pFreeSRB = pSRB;
475 ccb->ccb_h.status |= CAM_SIM_QUEUED;
477 /* XXX Need a timeout handler */
478 ccb->ccb_h.timeout_ch = timeout(trmtimeout, (caddr_t)srb, (ccb->ccb_h.timeout * hz) / 1000);
480 trm_SendSRB(pACB, pSRB);
486 trm_SendSRB(PACB pACB, PSRB pSRB)
490 pDCB = pSRB->pSRBDCB;
491 if (!(pDCB->MaxActiveCommandCnt > pDCB->GoingSRBCnt) || (pACB->pActiveDCB)
492 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) {
493 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxActiveCommandCnt);
494 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt);
495 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB);
496 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag);
497 trm_SRBwaiting(pDCB, pSRB);
501 if (pDCB->pWaitingSRB) {
502 trm_SRBwaiting(pDCB, pSRB);
503 pSRB = pDCB->pWaitingSRB;
504 pDCB->pWaitingSRB = pSRB->pNextSRB;
505 pSRB->pNextSRB = NULL;
508 if (!trm_StartSCSI(pACB, pDCB, pSRB)) {
510 * If trm_StartSCSI return 0 :
511 * current interrupt status is interrupt enable
512 * It's said that SCSI processor is unoccupied
514 pDCB->GoingSRBCnt++; /* stack waiting SRB*/
515 if (pDCB->pGoingSRB) {
516 pDCB->pGoingLastSRB->pNextSRB = pSRB;
517 pDCB->pGoingLastSRB = pSRB;
519 pDCB->pGoingSRB = pSRB;
520 pDCB->pGoingLastSRB = pSRB;
524 * If trm_StartSCSI return 1 :
525 * current interrupt status is interrupt disreenable
526 * It's said that SCSI processor has more one SRB need to do
528 trm_RewaitSRB0(pDCB, pSRB);
536 trm_action(struct cam_sim *psim, union ccb *pccb)
540 u_int target_id,target_lun;
542 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n"));
544 actionflags = splcam();
545 pACB = (PACB) cam_sim_softc(psim);
546 target_id = pccb->ccb_h.target_id;
547 target_lun = pccb->ccb_h.target_lun;
549 switch (pccb->ccb_h.func_code) {
551 TRM_DPRINTF(" XPT_NOOP \n");
552 pccb->ccb_h.status = CAM_REQ_INVALID;
556 * Execute the requested I/O operation
561 struct ccb_scsiio *pcsio;
565 TRM_DPRINTF(" XPT_SCSI_IO \n");
566 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n"
567 ,target_id, target_lun);
569 "pACB->scan_devices[target_id][target_lun]= %d \n"
570 ,pACB->scan_devices[target_id][target_lun]);
571 if ((pccb->ccb_h.status & CAM_STATUS_MASK) !=
577 pDCB = &pACB->DCBarray[target_id][target_lun];
578 if (!(pDCB->DCBstatus & DS_IN_QUEUE)) {
579 pACB->scan_devices[target_id][target_lun] = 1;
580 trm_initDCB(pACB, pDCB, pACB->AdapterUnit,
581 target_id, target_lun);
584 * Assign an SRB and connect it with this ccb.
586 pSRB = trm_GetSRB(pACB);
589 pccb->ccb_h.status = CAM_RESRC_UNAVAIL;
594 pSRB->pSRBDCB = pDCB;
595 pccb->ccb_h.ccb_trmsrb_ptr = pSRB;
596 pccb->ccb_h.ccb_trmacb_ptr = pACB;
598 pSRB->ScsiCmdLen = pcsio->cdb_len;
600 * move layer of CAM command block to layer of SCSI
601 * Request Block for SCSI processor command doing
603 if ((pccb->ccb_h.flags & CAM_CDB_POINTER) != 0) {
604 if ((pccb->ccb_h.flags & CAM_CDB_PHYS) == 0) {
605 bcopy(pcsio->cdb_io.cdb_ptr,pSRB->CmdBlock
608 pccb->ccb_h.status = CAM_REQ_INVALID;
609 pSRB->pNextSRB = pACB->pFreeSRB;
610 pACB->pFreeSRB= pSRB;
616 bcopy(pcsio->cdb_io.cdb_bytes,
617 pSRB->CmdBlock, pcsio->cdb_len);
618 error = bus_dmamap_load_ccb(pACB->buffer_dmat,
624 if (error == EINPROGRESS) {
625 xpt_freeze_simq(pACB->psim, 1);
626 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
631 TRM_DPRINTF(" XPT_GDEV_TYPE \n");
632 pccb->ccb_h.status = CAM_REQ_INVALID;
636 TRM_DPRINTF(" XPT_GDEVLIST \n");
637 pccb->ccb_h.status = CAM_REQ_INVALID;
641 * Path routing inquiry
645 struct ccb_pathinq *cpi = &pccb->cpi;
647 TRM_DPRINTF(" XPT_PATH_INQ \n");
648 cpi->version_num = 1;
649 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16;
650 cpi->target_sprt = 0;
652 cpi->hba_eng_cnt = 0;
653 cpi->max_target = 15 ;
654 cpi->max_lun = pACB->max_lun; /* 7 or 0 */
655 cpi->initiator_id = pACB->AdaptSCSIID;
656 cpi->bus_id = cam_sim_bus(psim);
657 cpi->base_transfer_speed = 3300;
658 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
659 strncpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN);
660 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
661 cpi->unit_number = cam_sim_unit(psim);
662 cpi->transport = XPORT_SPI;
663 cpi->transport_version = 2;
664 cpi->protocol = PROTO_SCSI;
665 cpi->protocol_version = SCSI_REV_2;
666 cpi->ccb_h.status = CAM_REQ_CMP;
671 * Release a frozen SIM queue
675 TRM_DPRINTF(" XPT_REL_SIMQ \n");
676 pccb->ccb_h.status = CAM_REQ_INVALID;
680 * Set Asynchronous Callback Parameters
681 * Set Asynchronous Callback CCB
684 TRM_DPRINTF(" XPT_SASYNC_CB \n");
685 pccb->ccb_h.status = CAM_REQ_INVALID;
689 * Set device type information
690 * Set Device Type CCB
693 TRM_DPRINTF(" XPT_SDEV_TYPE \n");
694 pccb->ccb_h.status = CAM_REQ_INVALID;
698 * Get EDT entries matching the given pattern
701 TRM_DPRINTF(" XPT_DEV_MATCH \n");
702 pccb->ccb_h.status = CAM_REQ_INVALID;
706 * Turn on debugging for a bus, target or lun
709 TRM_DPRINTF(" XPT_DEBUG \n");
710 pccb->ccb_h.status = CAM_REQ_INVALID;
714 * XPT_ABORT = 0x10, Abort the specified CCB
715 * Abort XPT request CCB
718 TRM_DPRINTF(" XPT_ABORT \n");
719 pccb->ccb_h.status = CAM_REQ_INVALID;
723 * Reset the specified SCSI bus
726 case XPT_RESET_BUS: {
729 TRM_DPRINTF(" XPT_RESET_BUS \n");
732 for (i=0; i<500; i++)
734 pccb->ccb_h.status = CAM_REQ_CMP;
739 * Bus Device Reset the specified SCSI device
740 * Reset SCSI Device CCB
744 * Don't (yet?) support vendor
747 TRM_DPRINTF(" XPT_RESET_DEV \n");
748 pccb->ccb_h.status = CAM_REQ_INVALID;
752 * Terminate the I/O process
753 * Terminate I/O Process Request CCB
756 TRM_DPRINTF(" XPT_TERM_IO \n");
757 pccb->ccb_h.status = CAM_REQ_INVALID;
761 * Get/Set transfer rate/width/disconnection/tag queueing
763 * (GET) default/user transfer settings for the target
765 case XPT_GET_TRAN_SETTINGS: {
766 struct ccb_trans_settings *cts = &pccb->cts;
768 struct trm_transinfo *tinfo;
770 struct ccb_trans_settings_scsi *scsi =
771 &cts->proto_specific.scsi;
772 struct ccb_trans_settings_spi *spi =
773 &cts->xport_specific.spi;
775 cts->protocol = PROTO_SCSI;
776 cts->protocol_version = SCSI_REV_2;
777 cts->transport = XPORT_SPI;
778 cts->transport_version = 2;
780 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n");
781 pDCB = &pACB->DCBarray[target_id][target_lun];
786 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
787 /* current transfer settings */
788 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB)
789 spi->flags = CTS_SPI_FLAGS_DISC_ENB;
791 spi->flags = 0;/* no tag & disconnect */
792 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB)
793 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
794 tinfo = &pDCB->tinfo.current;
795 TRM_DPRINTF("CURRENT: cts->flags= %2x \n",
798 /* default(user) transfer settings */
799 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB)
800 spi->flags = CTS_SPI_FLAGS_DISC_ENB;
803 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB)
804 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
805 tinfo = &pDCB->tinfo.user;
806 TRM_DPRINTF("USER: cts->flags= %2x \n",
809 spi->sync_period = tinfo->period;
810 spi->sync_offset = tinfo->offset;
811 spi->bus_width = tinfo->width;
812 TRM_DPRINTF("pDCB->SyncPeriod: %d \n",
814 TRM_DPRINTF("period: %d \n", tinfo->period);
815 TRM_DPRINTF("offset: %d \n", tinfo->offset);
816 TRM_DPRINTF("width: %d \n", tinfo->width);
819 spi->valid = CTS_SPI_VALID_SYNC_RATE |
820 CTS_SPI_VALID_SYNC_OFFSET |
821 CTS_SPI_VALID_BUS_WIDTH |
823 scsi->valid = CTS_SCSI_VALID_TQ;
824 pccb->ccb_h.status = CAM_REQ_CMP;
829 * Get/Set transfer rate/width/disconnection/tag queueing
831 * (Set) transfer rate/width negotiation settings
833 case XPT_SET_TRAN_SETTINGS: {
834 struct ccb_trans_settings *cts = &pccb->cts;
838 struct ccb_trans_settings_scsi *scsi =
839 &cts->proto_specific.scsi;
840 struct ccb_trans_settings_spi *spi =
841 &cts->xport_specific.spi;
843 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n");
845 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
846 update_type |= TRM_TRANS_GOAL;
847 if (cts->type == CTS_TYPE_USER_SETTINGS)
848 update_type |= TRM_TRANS_USER;
850 pDCB = &pACB->DCBarray[target_id][target_lun];
852 if ((spi->valid & CTS_SPI_VALID_DISC) != 0) {
853 /*ccb disc enables */
854 if (update_type & TRM_TRANS_GOAL) {
855 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB)
860 pDCB->tinfo.disc_tag &=
863 if (update_type & TRM_TRANS_USER) {
864 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB)
869 pDCB->tinfo.disc_tag &=
873 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) {
874 /* if ccb tag q active */
875 if (update_type & TRM_TRANS_GOAL) {
876 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB)
878 pDCB->tinfo.disc_tag |=
881 pDCB->tinfo.disc_tag &=
884 if (update_type & TRM_TRANS_USER) {
885 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB)
887 pDCB->tinfo.disc_tag |=
890 pDCB->tinfo.disc_tag &=
894 /* Minimum sync period factor */
896 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) {
897 /* if ccb sync active */
898 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */
899 if ((spi->sync_period != 0) &&
900 (spi->sync_period < 125))
901 spi->sync_period = 125;
902 /* 1/(125*4) minsync 2 MByte/sec */
903 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET)
905 if (spi->sync_offset == 0)
906 spi->sync_period = 0;
907 /* TRM-S1040 MaxSyncOffset = 15 bytes*/
908 if (spi->sync_offset > 15)
909 spi->sync_offset = 15;
912 if ((update_type & TRM_TRANS_USER) != 0) {
913 pDCB->tinfo.user.period = spi->sync_period;
914 pDCB->tinfo.user.offset = spi->sync_offset;
915 pDCB->tinfo.user.width = spi->bus_width;
917 if ((update_type & TRM_TRANS_GOAL) != 0) {
918 pDCB->tinfo.goal.period = spi->sync_period;
919 pDCB->tinfo.goal.offset = spi->sync_offset;
920 pDCB->tinfo.goal.width = spi->bus_width;
923 pccb->ccb_h.status = CAM_REQ_CMP;
928 * Calculate the geometry parameters for a device give
929 * the sector size and volume size.
931 case XPT_CALC_GEOMETRY:
932 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n");
933 cam_calc_geometry(&pccb->ccg, /*extended*/1);
937 TRM_DPRINTF(" XPT_ENG_INQ \n");
938 pccb->ccb_h.status = CAM_REQ_INVALID;
942 * HBA execute engine request
943 * This structure must match SCSIIO size
946 TRM_DPRINTF(" XPT_ENG_EXEC \n");
947 pccb->ccb_h.status = CAM_REQ_INVALID;
951 * XPT_EN_LUN = 0x30, Enable LUN as a target
952 * Target mode structures.
956 * Don't (yet?) support vendor
959 TRM_DPRINTF(" XPT_EN_LUN \n");
960 pccb->ccb_h.status = CAM_REQ_INVALID;
964 * Execute target I/O request
968 * Don't (yet?) support vendor
971 TRM_DPRINTF(" XPT_TARGET_IO \n");
972 pccb->ccb_h.status = CAM_REQ_INVALID;
976 * Accept Host Target Mode CDB
978 case XPT_ACCEPT_TARGET_IO:
980 * Don't (yet?) support vendor
983 TRM_DPRINTF(" XPT_ACCEPT_TARGET_IO \n");
984 pccb->ccb_h.status = CAM_REQ_INVALID;
988 * Continue Host Target I/O Connection
990 case XPT_CONT_TARGET_IO:
992 * Don't (yet?) support vendor
995 TRM_DPRINTF(" XPT_CONT_TARGET_IO \n");
996 pccb->ccb_h.status = CAM_REQ_INVALID;
1000 * Notify Host Target driver of event
1002 case XPT_IMMED_NOTIFY:
1003 TRM_DPRINTF(" XPT_IMMED_NOTIFY \n");
1004 pccb->ccb_h.status = CAM_REQ_INVALID;
1008 * Acknowledgement of event
1010 case XPT_NOTIFY_ACK:
1011 TRM_DPRINTF(" XPT_NOTIFY_ACK \n");
1012 pccb->ccb_h.status = CAM_REQ_INVALID;
1016 * XPT_VUNIQUE = 0x80
1019 pccb->ccb_h.status = CAM_REQ_INVALID;
1023 pccb->ccb_h.status = CAM_REQ_INVALID;
1031 trm_poll(struct cam_sim *psim)
1033 trm_Interrupt(cam_sim_softc(psim));
1037 trm_ResetDevParam(PACB pACB)
1040 PNVRAMTYPE pEEpromBuf;
1041 u_int8_t PeriodIndex;
1043 pDCB = pACB->pLinkDCB;
1048 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE);
1049 pDCB->SyncPeriod = 0;
1050 pDCB->SyncOffset = 0;
1051 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit];
1053 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0;
1054 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg;
1056 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07;
1057 if (pACB->AdaptType == 1) /* is U2? */
1058 pDCB->MaxNegoPeriod = dc395u2x_clock_period[PeriodIndex];
1060 pDCB->MaxNegoPeriod = dc395x_clock_period[PeriodIndex];
1061 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) &&
1062 (pACB->Config & HCC_WIDE_CARD))
1063 pDCB->SyncMode |= WIDE_NEGO_ENABLE;
1064 pDCB = pDCB->pNextDCB;
1066 while (pdcb != pDCB);
1070 trm_RecoverSRB(PACB pACB)
1076 pDCB = pACB->pLinkDCB;
1081 cnt = pdcb->GoingSRBCnt;
1082 psrb = pdcb->pGoingSRB;
1083 for (i = 0; i < cnt; i++) {
1085 psrb = psrb->pNextSRB;
1086 if (pdcb->pWaitingSRB) {
1087 psrb2->pNextSRB = pdcb->pWaitingSRB;
1088 pdcb->pWaitingSRB = psrb2;
1090 pdcb->pWaitingSRB = psrb2;
1091 pdcb->pWaitingLastSRB = psrb2;
1092 psrb2->pNextSRB = NULL;
1095 pdcb->GoingSRBCnt = 0;
1096 pdcb->pGoingSRB = NULL;
1097 pdcb = pdcb->pNextDCB;
1099 while (pdcb != pDCB);
1103 trm_reset(PACB pACB)
1108 TRM_DPRINTF("trm: RESET");
1110 trm_reg_write8(0x00, TRMREG_DMA_INTEN);
1111 trm_reg_write8(0x00, TRMREG_SCSI_INTEN);
1113 trm_ResetSCSIBus(pACB);
1114 for (i = 0; i < 500; i++)
1116 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN);
1117 /* Enable DMA interrupt */
1118 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN);
1119 /* Clear DMA FIFO */
1120 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL);
1121 /* Clear SCSI FIFO */
1122 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL);
1123 trm_ResetDevParam(pACB);
1124 trm_DoingSRB_Done(pACB);
1125 pACB->pActiveDCB = NULL;
1126 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */
1127 trm_DoWaitingSRB(pACB);
1128 /* Tell the XPT layer that a bus reset occured */
1129 if (pACB->ppath != NULL)
1130 xpt_async(AC_BUS_RESET, pACB->ppath, NULL);
1136 trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB)
1138 u_int16_t return_code;
1139 u_int8_t scsicommand, i,command,identify_message;
1142 struct ccb_scsiio *pcsio;
1145 pcsio = &pccb->csio;
1147 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID);
1148 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID);
1149 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC);
1150 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET);
1151 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */
1153 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL);
1155 identify_message = pDCB->IdentifyMsg;
1157 if ((pSRB->CmdBlock[0] == INQUIRY) ||
1158 (pSRB->CmdBlock[0] == REQUEST_SENSE) ||
1159 (pSRB->SRBFlag & AUTO_REQSENSE)) {
1160 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) &&
1161 !(pDCB->SyncMode & WIDE_NEGO_DONE))
1162 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) &&
1163 !(pDCB->SyncMode & SYNC_NEGO_DONE))) {
1164 if (!(pDCB->IdentifyMsg & 7) ||
1165 (pSRB->CmdBlock[0] != INQUIRY)) {
1166 scsicommand = SCMD_SEL_ATNSTOP;
1167 pSRB->SRBState = SRB_MSGOUT;
1172 * Send identify message
1174 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO);
1175 scsicommand = SCMD_SEL_ATN;
1176 pSRB->SRBState = SRB_START_;
1178 /* not inquiry,request sense,auto request sense */
1180 * Send identify message
1182 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO);
1183 scsicommand = SCMD_SEL_ATN;
1184 pSRB->SRBState = SRB_START_;
1185 if (pDCB->SyncMode & EN_TAG_QUEUING) {
1186 /* Send Tag message */
1187 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO);
1188 trm_reg_write8(pSRB->TagNumber, TRMREG_SCSI_FIFO);
1189 scsicommand = SCMD_SEL_ATN3;
1194 * Send CDB ..command block .........
1196 if (pSRB->SRBFlag & AUTO_REQSENSE) {
1197 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO);
1198 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO);
1199 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1200 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1201 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO);
1202 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1204 ptr = (u_int8_t *) pSRB->CmdBlock;
1205 for (i = 0; i < pSRB->ScsiCmdLen ; i++) {
1207 trm_reg_write8(command,TRMREG_SCSI_FIFO);
1210 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) {
1212 * If trm_StartSCSI return 1 :
1213 * current interrupt status is interrupt disreenable
1214 * It's said that SCSI processor has more one SRB need to do,
1215 * SCSI processor has been occupied by one SRB.
1217 pSRB->SRBState = SRB_READY;
1221 * If trm_StartSCSI return 0 :
1222 * current interrupt status is interrupt enable
1223 * It's said that SCSI processor is unoccupied
1225 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */
1226 pACB->pActiveDCB = pDCB;
1227 pDCB->pActiveSRB = pSRB;
1229 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT,
1230 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/
1234 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND);
1236 return (return_code);
1240 trm_Interrupt(vpACB)
1247 void (*stateV)(PACB, PSRB, u_int16_t *);
1248 u_int16_t scsi_status=0;
1249 u_int8_t scsi_intstatus;
1253 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS);
1254 if (!(scsi_status & SCSIINTERRUPT)) {
1255 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......");
1258 TRM_DPRINTF("scsi_status=%2x,",scsi_status);
1260 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS);
1262 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus);
1264 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) {
1265 trm_Disconnect(pACB);
1269 if (scsi_intstatus & INT_RESELECTED) {
1273 if (scsi_intstatus & INT_SCSIRESET) {
1274 trm_ScsiRstDetect(pACB);
1278 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) {
1279 pDCB = pACB->pActiveDCB;
1280 KASSERT(pDCB != NULL, ("no active DCB"));
1281 pSRB = pDCB->pActiveSRB;
1282 if (pDCB->DCBFlag & ABORT_DEV_)
1283 trm_EnableMsgOutAbort1(pACB, pSRB);
1284 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */
1285 stateV = (void *) trm_SCSI_phase0[phase];
1286 stateV(pACB, pSRB, &scsi_status);
1287 pSRB->ScsiPhase = scsi_status & PHASEMASK;
1288 /* phase:0,1,2,3,4,5,6,7 */
1289 phase = (u_int16_t) scsi_status & PHASEMASK;
1290 stateV = (void *) trm_SCSI_phase1[phase];
1291 stateV(pACB, pSRB, &scsi_status);
1296 trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1299 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT))
1300 *pscsi_status = PH_BUS_FREE;
1301 /*.. initial phase*/
1305 trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1312 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL);
1313 pDCB = pACB->pActiveDCB;
1314 if (!(pSRB->SRBState & SRB_MSGOUT)) {
1317 ptr = (u_int8_t *) pSRB->MsgOutBuf;
1318 for (i = 0; i < cnt; i++) {
1319 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO);
1323 if ((pDCB->DCBFlag & ABORT_DEV_) &&
1324 (pSRB->MsgOutBuf[0] == MSG_ABORT)) {
1325 pSRB->SRBState = SRB_ABORT_SENT;
1329 if ((pSRB->CmdBlock[0] == INQUIRY) ||
1330 (pSRB->CmdBlock[0] == REQUEST_SENSE) ||
1331 (pSRB->SRBFlag & AUTO_REQSENSE)) {
1332 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) {
1336 trm_reg_write8(bval, TRMREG_SCSI_FIFO);
1339 mop1: /* message out phase */
1340 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO)
1341 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) {
1343 * WIDE DATA TRANSFER REQUEST code (03h)
1345 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP);
1346 trm_reg_write8((pDCB->IdentifyMsg & 0xBF),
1348 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO);
1350 trm_reg_write8(2,TRMREG_SCSI_FIFO);
1351 /* Message length (02h) */
1352 trm_reg_write8(3,TRMREG_SCSI_FIFO);
1353 /* wide data xfer (03h) */
1354 trm_reg_write8(1,TRMREG_SCSI_FIFO);
1355 /* width:0(8bit),1(16bit),2(32bit) */
1356 pSRB->SRBState |= SRB_DO_WIDE_NEGO;
1357 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO)
1358 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) {
1360 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h)
1362 if (!(pDCB->SyncMode & WIDE_NEGO_DONE))
1363 trm_reg_write8((pDCB->IdentifyMsg & 0xBF),
1365 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO);
1367 trm_reg_write8(3,TRMREG_SCSI_FIFO);
1368 /* Message length (03h) */
1369 trm_reg_write8(1,TRMREG_SCSI_FIFO);
1370 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */
1371 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO);
1372 /* Transfer peeriod factor */
1373 trm_reg_write8((pACB->AdaptType == 1) ? 31 : 15,
1375 /* REQ/ACK offset */
1376 pSRB->SRBState |= SRB_DO_SYNC_NEGO;
1379 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1380 /* it's important for atn stop */
1384 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND);
1388 trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1394 trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1400 struct ccb_scsiio *pcsio;
1403 pcsio = &pccb->csio;
1405 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL);
1406 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) {
1407 cnt = (u_int16_t) pSRB->ScsiCmdLen;
1408 ptr = (u_int8_t *) pSRB->CmdBlock;
1409 for (i = 0; i < cnt; i++) {
1410 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO);
1414 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO);
1415 pDCB = pACB->pActiveDCB;
1417 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO);
1418 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1419 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1420 /* sizeof(struct scsi_sense_data) */
1421 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO);
1422 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1424 pSRB->SRBState = SRB_COMMAND;
1425 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1426 /* it's important for atn stop*/
1430 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND);
1434 trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1437 u_int8_t TempDMAstatus,SGIndexTemp;
1438 u_int16_t scsi_status;
1440 u_long TempSRBXferredLength,dLeftCounter=0;
1442 pDCB = pSRB->pSRBDCB;
1443 scsi_status = *pscsi_status;
1445 if (!(pSRB->SRBState & SRB_XFERPAD)) {
1446 if (scsi_status & PARITYERROR)
1447 pSRB->SRBStatus |= PARITY_ERROR;
1448 if (!(scsi_status & SCSIXFERDONE)) {
1450 * when data transfer from DMA FIFO to SCSI FIFO
1451 * if there was some data left in SCSI FIFO
1453 dLeftCounter = (u_long)
1454 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x3F);
1455 if (pDCB->SyncPeriod & WIDE_SYNC) {
1457 * if WIDE scsi SCSI FIFOCNT unit is word
1464 * caculate all the residue data that not yet tranfered
1465 * SCSI transfer counter + left in SCSI FIFO data
1467 * .....TRM_SCSI_COUNTER (24bits)
1468 * The counter always decrement by one for every SCSI byte
1470 * .....TRM_SCSI_FIFOCNT (5bits)
1471 * The counter is SCSI FIFO offset counter
1473 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER);
1474 if (dLeftCounter == 1) {
1476 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL);
1478 if ((dLeftCounter == 0) ||
1479 (scsi_status & SCSIXFERCNT_2_ZERO)) {
1480 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS);
1481 while (!(TempDMAstatus & DMAXFERCOMP)) {
1483 trm_reg_read8(TRMREG_DMA_STATUS);
1485 pSRB->SRBTotalXferLength = 0;
1487 /* Update SG list */
1489 * if transfer not yet complete
1490 * there were some data residue in SCSI FIFO or
1491 * SCSI transfer counter not empty
1493 if (pSRB->SRBTotalXferLength != dLeftCounter) {
1495 * data that had transferred length
1497 TempSRBXferredLength =
1498 pSRB->SRBTotalXferLength - dLeftCounter;
1500 * next time to be transferred length
1502 pSRB->SRBTotalXferLength = dLeftCounter;
1504 * parsing from last time disconnect SRBSGIndex
1507 pSRB->pSRBSGL + pSRB->SRBSGIndex;
1508 for (SGIndexTemp = pSRB->SRBSGIndex;
1509 SGIndexTemp < pSRB->SRBSGCount;
1512 * find last time which SG transfer be
1515 if (TempSRBXferredLength >=
1517 TempSRBXferredLength -=
1521 * update last time disconnected SG
1525 TempSRBXferredLength;
1526 /* residue data length */
1528 TempSRBXferredLength;
1529 /* residue data pointer */
1530 pSRB->SRBSGIndex = SGIndexTemp;
1538 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL);
1543 trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1547 * do prepare befor transfer when data out phase
1550 ioDir = XFERDATAOUT;
1551 trm_DataIO_transfer(pACB, pSRB, ioDir);
1555 trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1557 u_int8_t TempDMAstatus, SGIndexTemp;
1558 u_int16_t scsi_status;
1560 u_long TempSRBXferredLength,dLeftCounter = 0;
1562 scsi_status = *pscsi_status;
1563 if (!(pSRB->SRBState & SRB_XFERPAD)) {
1564 if (scsi_status & PARITYERROR)
1565 pSRB->SRBStatus |= PARITY_ERROR;
1566 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER);
1567 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) {
1568 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS);
1569 while (!(TempDMAstatus & DMAXFERCOMP))
1570 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS);
1571 pSRB->SRBTotalXferLength = 0;
1575 * when a transfer not yet complete
1576 * but be disconnected by uper layer
1577 * if transfer not yet complete
1578 * there were some data residue in SCSI FIFO or
1579 * SCSI transfer counter not empty
1581 if (pSRB->SRBTotalXferLength != dLeftCounter) {
1583 * data that had transferred length
1585 TempSRBXferredLength =
1586 pSRB->SRBTotalXferLength - dLeftCounter;
1588 * next time to be transferred length
1590 pSRB->SRBTotalXferLength = dLeftCounter;
1592 * parsing from last time disconnect SRBSGIndex
1594 pseg = pSRB->pSRBSGL + pSRB->SRBSGIndex;
1595 for (SGIndexTemp = pSRB->SRBSGIndex;
1596 SGIndexTemp < pSRB->SRBSGCount;
1599 * find last time which SG transfer be disconnect
1601 if (TempSRBXferredLength >= pseg->length)
1602 TempSRBXferredLength -= pseg->length;
1605 * update last time disconnected SG list
1607 pseg->length -= TempSRBXferredLength;
1608 /* residue data length */
1609 pseg->address += TempSRBXferredLength;
1610 /* residue data pointer */
1611 pSRB->SRBSGIndex = SGIndexTemp;
1622 trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1626 * do prepare befor transfer when data in phase
1630 trm_DataIO_transfer(pACB, pSRB, ioDir);
1634 trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir)
1639 pDCB = pSRB->pSRBDCB;
1640 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) {
1641 if (pSRB->SRBTotalXferLength != 0) {
1643 * load what physical address of Scatter/Gather list
1644 table want to be transfer
1646 TRM_DPRINTF(" SG->address=%8x \n",pSRB->pSRBSGL->address);
1647 TRM_DPRINTF(" SG->length=%8x \n",pSRB->pSRBSGL->length);
1648 TRM_DPRINTF(" pDCB->SyncPeriod=%x \n",pDCB->SyncPeriod);
1649 TRM_DPRINTF(" pSRB->pSRBSGL=%8x \n",(unsigned int)pSRB->pSRBSGL);
1650 TRM_DPRINTF(" pSRB->SRBSGPhyAddr=%8x \n",pSRB->SRBSGPhyAddr);
1651 TRM_DPRINTF(" pSRB->SRBSGIndex=%d \n",pSRB->SRBSGIndex);
1652 TRM_DPRINTF(" pSRB->SRBSGCount=%d \n",pSRB->SRBSGCount);
1653 TRM_DPRINTF(" pSRB->SRBTotalXferLength=%d \n",pSRB->SRBTotalXferLength);
1655 pSRB->SRBState = SRB_DATA_XFER;
1656 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR);
1658 (pSRB->SRBSGPhyAddr +
1659 ((u_long)pSRB->SRBSGIndex << 3)),
1660 TRMREG_DMA_XLOWADDR);
1662 * load how many bytes in the Scatter/Gather
1666 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3),
1669 * load total transfer length (24bits) max value
1672 trm_reg_write32(pSRB->SRBTotalXferLength,
1673 TRMREG_SCSI_COUNTER);
1674 /* Start DMA transfer */
1675 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND);
1676 /* Start SCSI transfer */
1677 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1678 /* it's important for atn stop */
1682 bval = (ioDir == XFERDATAOUT) ?
1683 SCMD_DMA_OUT : SCMD_DMA_IN;
1684 trm_reg_write8(bval, TRMREG_SCSI_COMMAND);
1687 if (pSRB->SRBSGCount) {
1688 pSRB->AdaptStatus = H_OVER_UNDER_RUN;
1689 pSRB->SRBStatus |= OVER_RUN;
1691 if (pDCB->SyncPeriod & WIDE_SYNC)
1692 trm_reg_write32(2,TRMREG_SCSI_COUNTER);
1694 trm_reg_write32(1,TRMREG_SCSI_COUNTER);
1695 if (ioDir == XFERDATAOUT)
1696 trm_reg_write16(0, TRMREG_SCSI_FIFO);
1698 trm_reg_read16(TRMREG_SCSI_FIFO);
1699 pSRB->SRBState |= SRB_XFERPAD;
1700 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1701 /* it's important for atn stop */
1705 bval = (ioDir == XFERDATAOUT) ?
1706 SCMD_FIFO_OUT : SCMD_FIFO_IN;
1707 trm_reg_write8(bval, TRMREG_SCSI_COMMAND);
1713 trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1716 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO);
1717 pSRB->SRBState = SRB_COMPLETED;
1718 *pscsi_status = PH_BUS_FREE;
1719 /*.. initial phase*/
1720 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1721 /* it's important for atn stop */
1725 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1731 trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1734 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) {
1735 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40))
1736 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL);
1737 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000))
1738 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL);
1740 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000))
1741 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL);
1742 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40))
1743 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL);
1745 pSRB->SRBState = SRB_STATUS;
1746 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1747 /* it's important for atn stop */
1751 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND);
1756 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors
1757 * stateV = (void *) trm_SCSI_phase0[phase]
1759 * extended message codes:
1764 * 00h MODIFY DATA POINTER
1765 * 01h SYNCHRONOUS DATA TRANSFER REQUEST
1766 * 03h WIDE DATA TRANSFER REQUEST
1767 * 04h - 7Fh Reserved
1768 * 80h - FFh Vendor specific
1773 trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1775 u_int8_t message_in_code,bIndex,message_in_tag_id;
1779 pDCB = pACB->pActiveDCB;
1781 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO);
1782 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) {
1783 if (message_in_code == MSG_DISCONNECT) {
1784 pSRB->SRBState = SRB_DISCONNECT;
1785 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1786 /* it's important for atn stop */
1787 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1791 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1793 } else if (message_in_code == MSG_SAVE_PTR) {
1794 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1795 /* it's important for atn stop */
1796 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1800 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1802 } else if ((message_in_code == MSG_EXTENDED) ||
1803 ((message_in_code >= MSG_SIMPLE_QTAG) &&
1804 (message_in_code <= MSG_ORDER_QTAG))) {
1805 pSRB->SRBState |= SRB_EXTEND_MSGIN;
1806 pSRB->MsgInBuf[0] = message_in_code;
1807 /* extended message (01h) */
1809 pSRB->pMsgPtr = &pSRB->MsgInBuf[1];
1810 /* extended message length (n) */
1811 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1812 /* it's important for atn stop */
1813 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1817 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1819 } else if (message_in_code == MSG_REJECT_) {
1820 /* Reject message */
1821 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) {
1822 /* do wide nego reject */
1823 pDCB = pSRB->pSRBDCB;
1824 pDCB->SyncMode |= WIDE_NEGO_DONE;
1825 pDCB->SyncMode &= ~(SYNC_NEGO_DONE |
1826 EN_ATN_STOP | WIDE_NEGO_ENABLE);
1827 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN);
1828 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE)
1829 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) {
1830 /* Set ATN, in case ATN was clear */
1831 pSRB->SRBState |= SRB_MSGOUT;
1834 TRMREG_SCSI_CONTROL);
1839 TRMREG_SCSI_CONTROL);
1841 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) {
1842 /* do sync nego reject */
1843 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL);
1844 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) {
1845 pDCB = pSRB->pSRBDCB;
1847 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE);
1848 pDCB->SyncPeriod = 0;
1849 pDCB->SyncOffset = 0;
1852 * program SCSI control register
1855 trm_reg_write8(pDCB->SyncPeriod,
1857 trm_reg_write8(pDCB->SyncOffset,
1858 TRMREG_SCSI_OFFSET);
1859 trm_SetXferRate(pACB,pSRB,pDCB);
1862 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1863 /* it's important for atn stop */
1864 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1868 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1870 } else if (message_in_code == MSG_IGNOREWIDE) {
1871 trm_reg_write32(1, TRMREG_SCSI_COUNTER);
1872 trm_reg_read8(TRMREG_SCSI_FIFO);
1873 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1874 /* it's important for atn stop */
1875 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1879 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1882 /* Restore data pointer message */
1883 /* Save data pointer message */
1884 /* Completion message */
1886 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1887 /* it's important for atn stop */
1888 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1892 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1897 * Parsing incomming extented messages
1899 *pSRB->pMsgPtr = message_in_code;
1902 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]);
1903 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]);
1904 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]);
1905 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]);
1906 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]);
1907 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG)
1908 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) {
1910 * is QUEUE tag message :
1913 * HEAD QUEUE TAG (20h)
1914 * ORDERED QUEUE TAG (21h)
1915 * SIMPLE QUEUE TAG (22h)
1917 * Queue tag (00h - FFh)
1919 if (pSRB->MsgCnt == 2) {
1921 message_in_tag_id = pSRB->MsgInBuf[1];
1922 pSRB = pDCB->pGoingSRB;
1923 pSRBTemp = pDCB->pGoingLastSRB;
1926 if (pSRB->TagNumber !=
1927 message_in_tag_id) {
1928 if (pSRB == pSRBTemp) {
1931 pSRB = pSRB->pNextSRB;
1935 if (pDCB->DCBFlag & ABORT_DEV_) {
1936 pSRB->SRBState = SRB_ABORT_SENT;
1937 trm_EnableMsgOutAbort1(
1940 if (!(pSRB->SRBState & SRB_DISCONNECT)) {
1941 TRM_DPRINTF("SRB not yet disconnect........ \n ");
1944 pDCB->pActiveSRB = pSRB;
1945 pSRB->SRBState = SRB_DATA_XFER;
1948 pSRB = &pACB->TmpSRB;
1949 pSRB->SRBState = SRB_UNEXPECT_RESEL;
1950 pDCB->pActiveSRB = pSRB;
1951 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG;
1952 trm_EnableMsgOutAbort2(
1957 *pscsi_status = PH_BUS_FREE;
1958 /* .. initial phase */
1959 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1960 /* it's important for atn stop */
1964 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1966 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) &&
1967 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) {
1969 * is Wide data xfer Extended message :
1970 * ======================================
1971 * WIDE DATA TRANSFER REQUEST
1972 * ======================================
1973 * byte 0 : Extended message (01h)
1974 * byte 1 : Extended message length (02h)
1975 * byte 2 : WIDE DATA TRANSFER code (03h)
1976 * byte 3 : Transfer width exponent
1978 pDCB = pSRB->pSRBDCB;
1979 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO);
1980 if ((pSRB->MsgInBuf[1] != 2)) {
1981 /* Length is wrong, reject it */
1983 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE);
1985 pSRB->MsgInBuf[0] = MSG_REJECT_;
1986 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL);
1987 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1988 /* it's important for atn stop */
1989 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1993 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1996 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) {
1997 /* Do wide negoniation */
1998 if (pSRB->MsgInBuf[3] > 2) {
2002 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE);
2004 pSRB->MsgInBuf[0] = MSG_REJECT_;
2005 trm_reg_write16(DO_SETATN,
2006 TRMREG_SCSI_CONTROL);
2007 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
2008 /* it's important for atn stop */
2009 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2013 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2016 if (pSRB->MsgInBuf[3] == 2) {
2017 pSRB->MsgInBuf[3] = 1;
2020 if (!(pDCB->SyncMode
2021 & WIDE_NEGO_DONE)) {
2023 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN);
2030 if (pSRB->MsgInBuf[3] != 0) {
2031 /* is Wide data xfer */
2034 pDCB->tinfo.current.width
2035 = MSG_EXT_WDTR_BUS_16_BIT;
2036 pDCB->tinfo.goal.width
2037 = MSG_EXT_WDTR_BUS_16_BIT;
2042 pSRB->MsgInBuf[3] = 0;
2043 pSRB->SRBState |= SRB_MSGOUT;
2044 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL);
2045 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
2046 /* it's important for atn stop */
2047 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2051 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2053 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) &&
2054 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) {
2056 * is 8bit transfer Extended message :
2057 * =================================
2058 * SYNCHRONOUS DATA TRANSFER REQUEST
2059 * =================================
2060 * byte 0 : Extended message (01h)
2061 * byte 1 : Extended message length (03)
2062 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h)
2063 * byte 3 : Transfer period factor
2064 * byte 4 : REQ/ACK offset
2066 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO);
2067 if ((pSRB->MsgInBuf[1] != 3) ||
2068 (pSRB->MsgInBuf[2] != 1)) {
2071 pSRB->MsgInBuf[0] = MSG_REJECT_;
2072 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL);
2073 *pscsi_status = PH_BUS_FREE;
2074 /* .. initial phase */
2075 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2076 /* it's important for atn stop */
2080 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2082 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) {
2084 pDCB = pSRB->pSRBDCB;
2085 /* disable sync & sync nego */
2087 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE);
2088 pDCB->SyncPeriod = 0;
2089 pDCB->SyncOffset = 0;
2090 pDCB->tinfo.goal.period = 0;
2091 pDCB->tinfo.goal.offset = 0;
2092 pDCB->tinfo.current.period = 0;
2093 pDCB->tinfo.current.offset = 0;
2094 pDCB->tinfo.current.width =
2095 MSG_EXT_WDTR_BUS_8_BIT;
2098 * program SCSI control register
2101 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC);
2102 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET);
2103 trm_SetXferRate(pACB,pSRB,pDCB);
2104 *pscsi_status = PH_BUS_FREE;
2105 /* .. initial phase */
2106 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2107 /* it's important for atn stop */
2111 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2115 pDCB = pSRB->pSRBDCB;
2117 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE;
2118 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3];
2119 /* Transfer period factor */
2120 pDCB->SyncOffset = pSRB->MsgInBuf[4];
2121 /* REQ/ACK offset */
2122 if (pACB->AdaptType == 1) {
2123 for(bIndex = 0; bIndex < 7; bIndex++) {
2124 if (pSRB->MsgInBuf[3] <=
2125 dc395u2x_clock_period[bIndex]) {
2126 pDCB->tinfo.goal.period =
2127 dc395u2x_tinfo_period[bIndex];
2128 pDCB->tinfo.current.period =
2129 dc395u2x_tinfo_period[bIndex];
2130 pDCB->tinfo.goal.offset =
2132 pDCB->tinfo.current.offset =
2134 pDCB->SyncPeriod |= (bIndex|LVDS_SYNC);
2139 for(bIndex = 0; bIndex < 7; bIndex++) {
2140 if (pSRB->MsgInBuf[3] <=
2141 dc395x_clock_period[bIndex]) {
2142 pDCB->tinfo.goal.period =
2143 dc395x_tinfo_period[bIndex];
2144 pDCB->tinfo.current.period =
2145 dc395x_tinfo_period[bIndex];
2146 pDCB->tinfo.goal.offset =
2148 pDCB->tinfo.current.offset =
2158 * program SCSI control register
2161 trm_reg_write8(pDCB->SyncPeriod,
2163 trm_reg_write8(pDCB->SyncOffset,
2164 TRMREG_SCSI_OFFSET);
2165 trm_SetXferRate(pACB,pSRB,pDCB);
2166 *pscsi_status=PH_BUS_FREE;/*.. initial phase*/
2167 trm_reg_write16(DO_DATALATCH,TRMREG_SCSI_CONTROL);/* it's important for atn stop*/
2171 trm_reg_write8(SCMD_MSGACCEPT,TRMREG_SCSI_COMMAND);
2175 *pscsi_status = PH_BUS_FREE;
2176 /* .. initial phase */
2177 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2178 /* it's important for atn stop */
2182 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2187 trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
2190 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL);
2191 trm_reg_write32(1,TRMREG_SCSI_COUNTER);
2192 if (!(pSRB->SRBState & SRB_MSGIN)) {
2193 pSRB->SRBState &= SRB_DISCONNECT;
2194 pSRB->SRBState |= SRB_MSGIN;
2196 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2197 /* it's important for atn stop*/
2201 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND);
2205 trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
2211 trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
2217 trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB)
2220 struct ccb_trans_settings neg;
2226 * set all lun device's period , offset
2228 TRM_DPRINTF("trm_SetXferRate\n");
2230 memset(&neg, 0, sizeof (neg));
2231 neg.xport_specific.spi.sync_period = pDCB->tinfo.goal.period;
2232 neg.xport_specific.spi.sync_offset = pDCB->tinfo.goal.offset;
2233 neg.xport_specific.spi.valid =
2234 CTS_SPI_VALID_SYNC_RATE | CTS_SPI_VALID_SYNC_OFFSET;
2235 xpt_setup_ccb(&neg.ccb_h, pccb->ccb_h.path, /* priority */1);
2236 xpt_async(AC_TRANSFER_NEG, pccb->ccb_h.path, &neg);
2237 if (!(pDCB->IdentifyMsg & 0x07)) {
2238 pDCBTemp = pACB->pLinkDCB;
2239 cnt = pACB->DeviceCnt;
2240 bval = pDCB->TargetID;
2241 for (i = 0; i < cnt; i++) {
2242 if (pDCBTemp->TargetID == bval) {
2243 pDCBTemp->SyncPeriod = pDCB->SyncPeriod;
2244 pDCBTemp->SyncOffset = pDCB->SyncOffset;
2245 pDCBTemp->SyncMode = pDCB->SyncMode;
2247 pDCBTemp = pDCBTemp->pNextDCB;
2260 * PH_DATA_OUT 0x00 Data out phase
2261 * PH_DATA_IN 0x01 Data in phase
2262 * PH_COMMAND 0x02 Command phase
2263 * PH_STATUS 0x03 Status phase
2264 * PH_BUS_FREE 0x04 Invalid phase used as bus free
2265 * PH_BUS_FREE 0x05 Invalid phase used as bus free
2266 * PH_MSG_OUT 0x06 Message out phase
2267 * PH_MSG_IN 0x07 Message in phase
2271 trm_Disconnect(PACB pACB)
2276 u_int target_id,target_lun;
2278 TRM_DPRINTF("trm_Disconnect...............\n ");
2280 pDCB = pACB->pActiveDCB;
2282 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n ");
2287 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT),
2288 TRMREG_SCSI_CONTROL);
2291 pSRB = pDCB->pActiveSRB;
2293 target_id = pSRB->pccb->ccb_h.target_id;
2294 target_lun = pSRB->pccb->ccb_h.target_lun;
2295 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB);
2296 pACB->pActiveDCB = 0;
2297 pSRB->ScsiPhase = PH_BUS_FREE;
2298 /* SCSI bus free Phase */
2299 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL);
2300 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) {
2302 trm_DoWaitingSRB(pACB);
2303 } else if (pSRB->SRBState & SRB_ABORT_SENT) {
2305 cnt = pDCB->GoingSRBCnt;
2306 pDCB->GoingSRBCnt = 0;
2307 pSRB = pDCB->pGoingSRB;
2308 for (i = 0; i < cnt; i++) {
2309 psrb = pSRB->pNextSRB;
2310 pSRB->pNextSRB = pACB->pFreeSRB;
2311 pACB->pFreeSRB = pSRB;
2314 pDCB->pGoingSRB = 0;
2315 trm_DoWaitingSRB(pACB);
2317 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) ||
2318 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) {
2319 /* Selection time out */
2320 if (!(pACB->scan_devices[target_id][target_lun]) &&
2321 pSRB->CmdBlock[0] != 0x00 && /* TEST UNIT READY */
2322 pSRB->CmdBlock[0] != INQUIRY) {
2323 pSRB->SRBState = SRB_READY;
2324 trm_RewaitSRB(pDCB, pSRB);
2326 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT;
2329 } else if (pSRB->SRBState & SRB_DISCONNECT) {
2333 trm_DoWaitingSRB(pACB);
2334 } else if (pSRB->SRBState & SRB_COMPLETED) {
2339 pDCB->pActiveSRB = 0;
2340 pSRB->SRBState = SRB_FREE;
2341 trm_SRBdone(pACB, pDCB, pSRB);
2348 trm_Reselect(PACB pACB)
2352 u_int16_t RselTarLunId;
2354 TRM_DPRINTF("trm_Reselect................. \n");
2355 pDCB = pACB->pActiveDCB;
2357 /* Arbitration lost but Reselection win */
2358 pSRB = pDCB->pActiveSRB;
2359 pSRB->SRBState = SRB_READY;
2360 trm_RewaitSRB(pDCB, pSRB);
2362 /* Read Reselected Target Id and LUN */
2363 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF;
2364 pDCB = pACB->pLinkDCB;
2365 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) {
2366 /* get pDCB of the reselect id */
2367 pDCB = pDCB->pNextDCB;
2370 pACB->pActiveDCB = pDCB;
2371 if (pDCB->SyncMode & EN_TAG_QUEUING) {
2372 pSRB = &pACB->TmpSRB;
2373 pDCB->pActiveSRB = pSRB;
2375 pSRB = pDCB->pActiveSRB;
2376 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) {
2380 pSRB = &pACB->TmpSRB;
2381 pSRB->SRBState = SRB_UNEXPECT_RESEL;
2382 pDCB->pActiveSRB = pSRB;
2383 trm_EnableMsgOutAbort1(pACB, pSRB);
2385 if (pDCB->DCBFlag & ABORT_DEV_) {
2386 pSRB->SRBState = SRB_ABORT_SENT;
2387 trm_EnableMsgOutAbort1(pACB, pSRB);
2389 pSRB->SRBState = SRB_DATA_XFER;
2392 pSRB->ScsiPhase = PH_BUS_FREE;
2393 /* SCSI bus free Phase */
2395 * Program HA ID, target ID, period and offset
2397 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID);
2399 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID);
2401 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC);
2403 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET);
2405 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2406 /* it's important for atn stop*/
2410 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2411 /* to rls the /ACK signal */
2415 trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB)
2418 u_int8_t bval, bval1,status;
2420 struct ccb_scsiio *pcsio;
2423 u_int target_id,target_lun;
2429 pcsio = &pccb->csio;
2430 target_id = pSRB->pccb->ccb_h.target_id;
2431 target_lun = pSRB->pccb->ccb_h.target_lun;
2432 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
2433 bus_dmasync_op_t op;
2434 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
2435 op = BUS_DMASYNC_POSTREAD;
2437 op = BUS_DMASYNC_POSTWRITE;
2438 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op);
2439 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap);
2446 status = pSRB->TargetStatus;
2447 pcsio->scsi_status=SCSI_STAT_GOOD;
2448 pccb->ccb_h.status = CAM_REQ_CMP;
2449 if (pSRB->SRBFlag & AUTO_REQSENSE) {
2451 * status of auto request sense
2453 pSRB->SRBFlag &= ~AUTO_REQSENSE;
2454 pSRB->AdaptStatus = 0;
2455 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND;
2457 if (status == SCSI_STATUS_CHECK_COND) {
2458 pccb->ccb_h.status = CAM_SEL_TIMEOUT;
2461 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0];
2462 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1];
2463 pSRB->SRBTotalXferLength = pSRB->Segment1[1];
2464 pSRB->pSRBSGL->address = pSRB->SgSenseTemp.address;
2465 pSRB->pSRBSGL->length = pSRB->SgSenseTemp.length;
2466 pcsio->scsi_status = SCSI_STATUS_CHECK_COND;
2467 bcopy(trm_get_sense_buf(pACB, pSRB), &pcsio->sense_data,
2469 pcsio->ccb_h.status = CAM_SCSI_STATUS_ERROR
2470 | CAM_AUTOSNS_VALID;
2477 if (status == SCSI_STATUS_CHECK_COND) {
2478 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) {
2479 TRM_DPRINTF("trm_RequestSense..................\n");
2480 trm_RequestSense(pACB, pDCB, pSRB);
2483 pcsio->scsi_status = SCSI_STATUS_CHECK_COND;
2484 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
2486 } else if (status == SCSI_STAT_QUEUEFULL) {
2487 bval = (u_int8_t) pDCB->GoingSRBCnt;
2489 pDCB->MaxActiveCommandCnt = bval;
2490 trm_RewaitSRB(pDCB, pSRB);
2491 pSRB->AdaptStatus = 0;
2492 pSRB->TargetStatus = 0;
2494 } else if (status == SCSI_STAT_SEL_TIMEOUT) {
2495 pSRB->AdaptStatus = H_SEL_TIMEOUT;
2496 pSRB->TargetStatus = 0;
2497 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT;
2498 pccb->ccb_h.status = CAM_SEL_TIMEOUT;
2499 } else if (status == SCSI_STAT_BUSY) {
2500 TRM_DPRINTF("trm: target busy at %s %d\n",
2501 __FILE__, __LINE__);
2502 pcsio->scsi_status = SCSI_STAT_BUSY;
2503 pccb->ccb_h.status = CAM_SCSI_BUSY;
2505 /* The device busy, try again later? */
2506 } else if (status == SCSI_STAT_RESCONFLICT) {
2507 TRM_DPRINTF("trm: target reserved at %s %d\n",
2508 __FILE__, __LINE__);
2509 pcsio->scsi_status = SCSI_STAT_RESCONFLICT;
2510 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/
2513 pSRB->AdaptStatus = 0;
2514 if (pSRB->RetryCnt) {
2516 pSRB->TargetStatus = 0;
2517 pSRB->SRBSGIndex = 0;
2518 if (trm_StartSCSI(pACB, pDCB, pSRB)) {
2520 * If trm_StartSCSI return 1 :
2521 * current interrupt status is interrupt
2523 * It's said that SCSI processor has more
2524 * one SRB need to do
2526 trm_RewaitSRB(pDCB, pSRB);
2530 TRM_DPRINTF("trm: driver stuffup at %s %d\n",
2531 __FILE__, __LINE__);
2532 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
2537 * process initiator status..........................
2538 * Adapter (initiator) status
2540 status = pSRB->AdaptStatus;
2541 if (status & H_OVER_UNDER_RUN) {
2542 pSRB->TargetStatus = 0;
2543 pccb->ccb_h.status = CAM_DATA_RUN_ERR;
2544 /* Illegal length (over/under run) */
2545 } else if (pSRB->SRBStatus & PARITY_ERROR) {
2546 TRM_DPRINTF("trm: driver stuffup %s %d\n",
2547 __FILE__, __LINE__);
2548 pDCB->tinfo.goal.period = 0;
2549 pDCB->tinfo.goal.offset = 0;
2550 /* Driver failed to perform operation */
2551 pccb->ccb_h.status = CAM_UNCOR_PARITY;
2554 pSRB->AdaptStatus = 0;
2555 pSRB->TargetStatus = 0;
2556 pccb->ccb_h.status = CAM_REQ_CMP;
2557 /* there is no error, (sense is invalid) */
2561 if (pACB->scan_devices[target_id][target_lun]) {
2563 * if SCSI command in "scan devices" duty
2565 if (pSRB->CmdBlock[0] == TEST_UNIT_READY)
2566 pACB->scan_devices[target_id][target_lun] = 0;
2567 /* SCSI command phase :test unit ready */
2568 else if (pSRB->CmdBlock[0] == INQUIRY) {
2570 * SCSI command phase :inquiry scsi device data
2571 * (type,capacity,manufacture....
2573 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT)
2575 ptr = (PSCSI_INQDATA) pcsio->data_ptr;
2577 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n",
2579 bval1 = ptr->DevType & SCSI_DEVTYPE;
2580 if (bval1 == SCSI_NODEV) {
2582 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n",
2586 pACB->scan_devices[target_id][target_lun] = 0;
2587 /* no device set scan device flag =0*/
2589 /* move the head of DCB to tempDCB*/
2590 pTempDCB=pACB->pLinkDCB;
2591 /* search current DCB for pass link */
2592 while (pTempDCB->pNextDCB != pDCB) {
2593 pTempDCB = pTempDCB->pNextDCB;
2596 * when the current DCB found than connect
2599 /* to the DCB tail that before current DCB */
2600 pTempDCB->pNextDCB = pDCB->pNextDCB;
2602 * if there was only one DCB ,connect his tail
2605 if (pACB->pLinkDCB == pDCB)
2606 pACB->pLinkDCB = pTempDCB->pNextDCB;
2607 if (pACB->pDCBRunRobin == pDCB)
2608 pACB->pDCBRunRobin = pTempDCB->pNextDCB;
2609 pDCB->DCBstatus &= ~DS_IN_QUEUE;
2611 if (pACB->DeviceCnt == 0) {
2612 pACB->pLinkDCB = NULL;
2613 pACB->pDCBRunRobin = NULL;
2619 for (j = 0; j < 28; j++) {
2620 TRM_DPRINTF("ptr=%2x ",
2621 ((u_int8_t *)ptr)[j]);
2624 pDCB->DevType = bval1;
2625 if (bval1 == SCSI_DASD ||
2626 bval1 == SCSI_OPTICAL) {
2627 if ((((ptr->Vers & 0x07) >= 2) ||
2628 ((ptr->RDF & 0x0F) == 2)) &&
2629 (ptr->Flags & SCSI_INQ_CMDQUEUE) &&
2630 (pDCB->DevMode & TAG_QUEUING_) &&
2631 (pDCB->DevMode & EN_DISCONNECT_)) {
2635 MaxActiveCommandCnt =
2639 pDCB->tinfo.disc_tag |=
2644 pDCB->tinfo.disc_tag &=
2650 /* pSRB->CmdBlock[0] == INQUIRY */
2652 /* pACB->scan_devices[target_id][target_lun] */
2655 /* ReleaseSRB(pDCB, pSRB); */
2656 if (pSRB == pDCB->pGoingSRB)
2657 pDCB->pGoingSRB = pSRB->pNextSRB;
2659 psrb = pDCB->pGoingSRB;
2660 while (psrb->pNextSRB != pSRB) {
2661 psrb = psrb->pNextSRB;
2663 psrb->pNextSRB = pSRB->pNextSRB;
2664 if (pSRB == pDCB->pGoingLastSRB) {
2665 pDCB->pGoingLastSRB = psrb;
2668 pSRB->pNextSRB = pACB->pFreeSRB;
2669 pACB->pFreeSRB = pSRB;
2670 pDCB->GoingSRBCnt--;
2671 trm_DoWaitingSRB(pACB);
2674 /* Notify cmd done */
2679 trm_DoingSRB_Done(PACB pACB)
2686 pDCB = pACB->pLinkDCB;
2691 cnt = pdcb->GoingSRBCnt;
2692 psrb = pdcb->pGoingSRB;
2693 for (i = 0; i < cnt; i++) {
2694 psrb2 = psrb->pNextSRB;
2696 pccb->ccb_h.status = CAM_SEL_TIMEOUT;
2697 /* ReleaseSRB(pDCB, pSRB); */
2698 psrb->pNextSRB = pACB->pFreeSRB;
2699 pACB->pFreeSRB = psrb;
2703 pdcb->GoingSRBCnt = 0;
2704 pdcb->pGoingSRB = NULL;
2705 pdcb = pdcb->pNextDCB;
2707 while (pdcb != pDCB);
2711 trm_ResetSCSIBus(PACB pACB)
2716 pACB->ACBFlag |= RESET_DEV;
2718 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL);
2719 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET));
2725 trm_ScsiRstDetect(PACB pACB)
2730 TRM_DPRINTF("trm_ScsiRstDetect \n");
2735 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL);
2737 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL);
2739 if (pACB->ACBFlag & RESET_DEV)
2740 pACB->ACBFlag |= RESET_DONE;
2742 pACB->ACBFlag |= RESET_DETECT;
2743 trm_ResetDevParam(pACB);
2744 /* trm_DoingSRB_Done(pACB); ???? */
2745 trm_RecoverSRB(pACB);
2746 pACB->pActiveDCB = NULL;
2748 trm_DoWaitingSRB(pACB);
2755 trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB)
2758 struct ccb_scsiio *pcsio;
2761 pcsio = &pccb->csio;
2763 pSRB->SRBFlag |= AUTO_REQSENSE;
2764 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0]));
2765 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4]));
2766 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) +
2768 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */
2770 /* $$$$$$ Status of initiator/target $$$$$$$$ */
2771 pSRB->AdaptStatus = 0;
2772 pSRB->TargetStatus = 0;
2773 /* $$$$$$ Status of initiator/target $$$$$$$$ */
2775 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data);
2776 pSRB->SgSenseTemp.address = pSRB->pSRBSGL->address;
2777 pSRB->SgSenseTemp.length = pSRB->pSRBSGL->length;
2778 pSRB->pSRBSGL->address = trm_get_sense_bufaddr(pACB, pSRB);
2779 pSRB->pSRBSGL->length = (u_long) sizeof(struct scsi_sense_data);
2780 pSRB->SRBSGCount = 1;
2781 pSRB->SRBSGIndex = 0;
2783 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003;
2784 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5;
2785 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len;
2786 pSRB->ScsiCmdLen = 6;
2788 if (trm_StartSCSI(pACB, pDCB, pSRB))
2790 * If trm_StartSCSI return 1 :
2791 * current interrupt status is interrupt disreenable
2792 * It's said that SCSI processor has more one SRB need to do
2794 trm_RewaitSRB(pDCB, pSRB);
2798 trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB)
2802 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL);
2806 trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB)
2809 pSRB->MsgOutBuf[0] = MSG_ABORT;
2810 trm_EnableMsgOutAbort2(pACB, pSRB);
2814 trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j)
2816 PNVRAMTYPE pEEpromBuf;
2817 u_int8_t bval,PeriodIndex;
2818 u_int target_id,target_lun;
2826 * Using the lun 0 device to init other DCB first, if the device
2827 * has been initialized.
2828 * I don't want init sync arguments one by one, it is the same.
2830 if (target_lun != 0 &&
2831 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE))
2832 bcopy(&pACB->DCBarray[target_id][0], pDCB,
2835 if (pACB->pLinkDCB == 0) {
2836 pACB->pLinkDCB = pDCB;
2838 * RunRobin impersonate the role
2839 * that let each device had good proportion
2840 * about SCSI command proceeding
2842 pACB->pDCBRunRobin = pDCB;
2843 pDCB->pNextDCB = pDCB;
2845 pTempDCB=pACB->pLinkDCB;
2846 /* search the last nod of DCB link */
2847 while (pTempDCB->pNextDCB != pACB->pLinkDCB)
2848 pTempDCB = pTempDCB->pNextDCB;
2849 /* connect current DCB with last DCB tail */
2850 pTempDCB->pNextDCB = pDCB;
2851 /* connect current DCB tail to this DCB Q head */
2852 pDCB->pNextDCB=pACB->pLinkDCB;
2857 pDCB->TargetID = target_id;
2858 pDCB->TargetLUN = target_lun;
2859 pDCB->pWaitingSRB = NULL;
2860 pDCB->pGoingSRB = NULL;
2861 pDCB->GoingSRBCnt = 0;
2862 pDCB->pActiveSRB = NULL;
2863 pDCB->MaxActiveCommandCnt = 1;
2865 pDCB->DCBstatus |= DS_IN_QUEUE;
2867 pEEpromBuf = &trm_eepromBuf[unit];
2868 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0;
2869 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg;
2872 * disconnect enable ?
2874 if (pDCB->DevMode & NTC_DO_DISCONNECT) {
2876 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ;
2879 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB);
2882 pDCB->IdentifyMsg = bval;
2883 if (target_lun != 0 &&
2884 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE))
2890 if (pDCB->DevMode & TAG_QUEUING_) {
2891 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ;
2893 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB);
2896 * wide nego ,sync nego enable ?
2898 pDCB->SyncPeriod = 0;
2899 pDCB->SyncOffset = 0;
2900 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07;
2901 if (pACB->AdaptType==1) {/* is U2? */
2902 pDCB->MaxNegoPeriod=dc395u2x_clock_period[ PeriodIndex ];
2903 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod;
2904 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 31 : 0;
2906 pDCB->MaxNegoPeriod=dc395x_clock_period[ PeriodIndex ];
2907 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod;
2908 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0;
2911 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) &&
2912 (pACB->Config & HCC_WIDE_CARD))
2913 pDCB->SyncMode |= WIDE_NEGO_ENABLE;
2914 /* enable wide nego */
2915 if (pDCB->DevMode & NTC_DO_SYNC_NEGO)
2916 pDCB->SyncMode |= SYNC_NEGO_ENABLE;
2917 /* enable sync nego */
2920 * Fill in tinfo structure.
2922 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ?
2923 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT;
2925 pDCB->tinfo.current.period = 0;
2926 pDCB->tinfo.current.offset = 0;
2927 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT;
2931 trm_srbmapSG(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2936 pSRB->SRBSGPhyAddr=segs->ds_addr;
2941 trm_destroySRB(PACB pACB)
2945 pSRB = pACB->pFreeSRB;
2947 if (pSRB->sg_dmamap) {
2948 bus_dmamap_unload(pACB->sg_dmat, pSRB->sg_dmamap);
2949 bus_dmamem_free(pACB->sg_dmat, pSRB->pSRBSGL,
2951 bus_dmamap_destroy(pACB->sg_dmat, pSRB->sg_dmamap);
2954 bus_dmamap_destroy(pACB->buffer_dmat, pSRB->dmamap);
2955 pSRB = pSRB->pNextSRB;
2960 trm_initSRB(PACB pACB)
2966 for (i = 0; i < TRM_MAX_SRB_CNT; i++) {
2967 pSRB = (PSRB)&pACB->pFreeSRB[i];
2969 if (bus_dmamem_alloc(pACB->sg_dmat, (void **)&pSRB->pSRBSGL,
2970 BUS_DMA_NOWAIT, &pSRB->sg_dmamap) !=0 ) {
2973 bus_dmamap_load(pACB->sg_dmat, pSRB->sg_dmamap, pSRB->pSRBSGL,
2974 TRM_MAX_SG_LISTENTRY * sizeof(SGentry),
2975 trm_srbmapSG, pSRB, /*flags*/0);
2976 if (i != TRM_MAX_SRB_CNT - 1) {
2980 pSRB->pNextSRB = &pACB->pFreeSRB[i+1];
2983 * load NULL to NextSRB of the last SRB
2985 pSRB->pNextSRB = NULL;
2987 pSRB->TagNumber = i;
2990 * Create the dmamap. This is no longer optional!
2992 if ((error = bus_dmamap_create(pACB->buffer_dmat, 0,
2993 &pSRB->dmamap)) != 0)
3004 trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit)
3006 PNVRAMTYPE pEEpromBuf;
3008 pEEpromBuf = &trm_eepromBuf[unit];
3011 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN)
3016 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n",
3017 pACB->max_id, pACB->max_lun);
3018 pACB->pLinkDCB = NULL;
3019 pACB->pDCBRunRobin = NULL;
3020 pACB->pActiveDCB = NULL;
3021 pACB->AdapterUnit = (u_int8_t)unit;
3022 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId;
3023 pACB->AdaptSCSILUN = 0;
3024 pACB->DeviceCnt = 0;
3025 pACB->AdaptType = adaptType;
3026 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag;
3032 NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB)
3034 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf;
3037 /* Enable SEEPROM */
3038 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM),
3039 TRMREG_GEN_CONTROL);
3043 NVRAM_trm_write_cmd(pACB, 0x04, 0xFF);
3044 trm_reg_write8(0, TRMREG_GEN_NVRAM);
3045 NVRAM_trm_wait_30us(pACB);
3046 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) {
3047 NVRAM_trm_set_data(pACB, bAddr, *bpEeprom);
3052 NVRAM_trm_write_cmd(pACB, 0x04, 0x00);
3053 trm_reg_write8(0 , TRMREG_GEN_NVRAM);
3054 NVRAM_trm_wait_30us(pACB);
3055 /* Disable SEEPROM */
3056 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM),
3057 TRMREG_GEN_CONTROL);
3062 NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData)
3067 * Send write command & address
3070 NVRAM_trm_write_cmd(pACB, 0x05, bAddr);
3074 for (i = 0; i < 8; i++, bData <<= 1) {
3075 bSendData = NVR_SELECT;
3077 /* Start from bit 7 */
3078 bSendData |= NVR_BITOUT;
3079 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM);
3080 NVRAM_trm_wait_30us(pACB);
3081 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM);
3082 NVRAM_trm_wait_30us(pACB);
3084 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM);
3085 NVRAM_trm_wait_30us(pACB);
3087 * Disable chip select
3089 trm_reg_write8(0 , TRMREG_GEN_NVRAM);
3090 NVRAM_trm_wait_30us(pACB);
3091 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM);
3092 NVRAM_trm_wait_30us(pACB);
3094 * Wait for write ready
3097 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM);
3098 NVRAM_trm_wait_30us(pACB);
3099 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM);
3100 NVRAM_trm_wait_30us(pACB);
3101 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) {
3106 * Disable chip select
3108 trm_reg_write8(0, TRMREG_GEN_NVRAM);
3113 NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB)
3115 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf;
3121 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM),
3122 TRMREG_GEN_CONTROL);
3123 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++)
3124 *bpEeprom = NVRAM_trm_get_data(pACB, bAddr);
3128 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM),
3129 TRMREG_GEN_CONTROL);
3134 NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr)
3137 u_int8_t bReadData, bData = 0;
3139 * Send read command & address
3142 NVRAM_trm_write_cmd(pACB, 0x06, bAddr);
3144 for (i = 0; i < 8; i++) {
3148 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM);
3149 NVRAM_trm_wait_30us(pACB);
3150 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM);
3152 * Get data bit while falling edge
3154 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM);
3156 if (bReadData & NVR_BITIN) {
3159 NVRAM_trm_wait_30us(pACB);
3162 * Disable chip select
3164 trm_reg_write8(0, TRMREG_GEN_NVRAM);
3169 NVRAM_trm_wait_30us(PACB pACB)
3172 /* ScsiPortStallExecution(30); wait 30 us */
3173 trm_reg_write8(5, TRMREG_GEN_TIMER);
3174 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT));
3179 NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr)
3184 for (i = 0; i < 3; i++, bCmd <<= 1) {
3186 * Program SB+OP code
3188 bSendData = NVR_SELECT;
3190 bSendData |= NVR_BITOUT;
3191 /* start from bit 2 */
3192 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM);
3193 NVRAM_trm_wait_30us(pACB);
3194 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM);
3195 NVRAM_trm_wait_30us(pACB);
3197 for (i = 0; i < 7; i++, bAddr <<= 1) {
3201 bSendData = NVR_SELECT;
3203 /* Start from bit 6 */
3204 bSendData |= NVR_BITOUT;
3205 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM);
3206 NVRAM_trm_wait_30us(pACB);
3207 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM);
3208 NVRAM_trm_wait_30us(pACB);
3210 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM);
3211 NVRAM_trm_wait_30us(pACB);
3215 trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB)
3217 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf;
3218 u_int16_t wAddr, wCheckSum;
3219 u_long dAddr, *dpEeprom;
3221 NVRAM_trm_read_all(pEEpromBuf,pACB);
3223 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf;
3224 wAddr < 64; wAddr++, wpEeprom++) {
3225 wCheckSum += *wpEeprom;
3227 if (wCheckSum != 0x1234) {
3229 * Checksum error, load default
3231 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM;
3232 pEEpromBuf->NvramSubVendorID[1] =
3233 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8);
3234 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040;
3235 pEEpromBuf->NvramSubSysID[1] =
3236 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8);
3237 pEEpromBuf->NvramSubClass = 0x00;
3238 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM;
3239 pEEpromBuf->NvramVendorID[1] =
3240 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8);
3241 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040;
3242 pEEpromBuf->NvramDeviceID[1] =
3243 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8);
3244 pEEpromBuf->NvramReserved = 0x00;
3246 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget;
3247 dAddr < 16; dAddr++, dpEeprom++) {
3248 *dpEeprom = 0x00000077;
3249 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */
3252 *dpEeprom++ = 0x04000F07;
3253 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */
3254 *dpEeprom++ = 0x00000015;
3255 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */
3256 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++)
3258 pEEpromBuf->NvramCheckSum = 0x00;
3259 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf;
3260 wAddr < 63; wAddr++, wpEeprom++)
3261 wCheckSum += *wpEeprom;
3262 *wpEeprom = 0x1234 - wCheckSum;
3263 NVRAM_trm_write_all(pEEpromBuf,pACB);
3268 trm_initAdapter(PACB pACB, u_int16_t unit)
3270 PNVRAMTYPE pEEpromBuf;
3274 pEEpromBuf = &trm_eepromBuf[unit];
3276 /* 250ms selection timeout */
3277 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT);
3278 /* Mask all the interrupt */
3279 trm_reg_write8(0x00, TRMREG_DMA_INTEN);
3280 trm_reg_write8(0x00, TRMREG_SCSI_INTEN);
3281 /* Reset SCSI module */
3282 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL);
3283 /* program configuration 0 */
3284 pACB->Config = HCC_AUTOTERM | HCC_PARITY;
3285 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI)
3286 pACB->Config |= HCC_WIDE_CARD;
3287 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET)
3288 pACB->Config |= HCC_SCSI_RESET;
3289 if (pACB->Config & HCC_PARITY)
3290 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK;
3292 bval = PHASELATCH | INITIATOR | BLOCKRST ;
3293 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0);
3294 /* program configuration 1 */
3295 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1);
3296 /* program Host ID */
3297 bval = pEEpromBuf->NvramScsiId;
3298 trm_reg_write8(bval, TRMREG_SCSI_HOSTID);
3299 /* set ansynchronous transfer */
3300 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET);
3301 /* Trun LED control off*/
3302 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F;
3303 trm_reg_write16(wval, TRMREG_GEN_CONTROL);
3305 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE;
3306 trm_reg_write16(wval, TRMREG_DMA_CONFIG);
3307 /* Clear pending interrupt status */
3308 trm_reg_read8(TRMREG_SCSI_INTSTATUS);
3309 /* Enable SCSI interrupt */
3310 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN);
3311 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN);
3316 trm_mapSRB(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3321 pACB->srb_physbase = segs->ds_addr;
3325 trm_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3329 baddr = (bus_addr_t *)arg;
3330 *baddr = segs->ds_addr;
3334 trm_init(u_int16_t unit, device_t dev)
3337 int rid = PCIR_BAR(0), i = 0, j = 0;
3338 u_int16_t adaptType = 0;
3340 pACB = (PACB) device_get_softc(dev);
3342 printf("trm%d: cannot allocate ACB !\n", unit);
3345 pACB->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
3347 if (pACB->iores == NULL) {
3348 printf("trm_init: bus_alloc_resource failed!\n");
3351 switch (pci_get_devid(dev)) {
3352 case PCI_DEVICEID_TRMS1040:
3355 case PCI_DEVICEID_TRMS2080:
3359 printf("trm_init %d: unknown adapter type!\n", unit);
3363 pACB->tag = rman_get_bustag(pACB->iores);
3364 pACB->bsh = rman_get_bushandle(pACB->iores);
3365 if (bus_dma_tag_create(
3366 /*parent_dmat*/ bus_get_dma_tag(dev),
3369 /*lowaddr*/ BUS_SPACE_MAXADDR,
3370 /*highaddr*/ BUS_SPACE_MAXADDR,
3373 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT,
3374 /*nsegments*/ BUS_SPACE_UNRESTRICTED,
3375 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
3379 /* dmat */ &pACB->parent_dmat) != 0)
3381 if (bus_dma_tag_create(
3382 /*parent_dmat*/ pACB->parent_dmat,
3385 /*lowaddr*/ BUS_SPACE_MAXADDR,
3386 /*highaddr*/ BUS_SPACE_MAXADDR,
3389 /*maxsize*/ MAXBSIZE,
3390 /*nsegments*/ TRM_NSEG,
3391 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE,
3392 /*flags*/ BUS_DMA_ALLOCNOW,
3393 /*lockfunc*/ busdma_lock_mutex,
3395 /* dmat */ &pACB->buffer_dmat) != 0)
3397 /* DMA tag for our ccb structures */
3398 if (bus_dma_tag_create(
3399 /*parent_dmat*/pACB->parent_dmat,
3402 /*lowaddr*/ BUS_SPACE_MAXADDR,
3403 /*highaddr*/ BUS_SPACE_MAXADDR,
3406 /*maxsize*/ TRM_MAX_SRB_CNT * sizeof(TRM_SRB),
3408 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE,
3410 /*lockfunc*/ busdma_lock_mutex,
3412 /*dmat*/ &pACB->srb_dmat) != 0) {
3413 printf("trm_init %d: bus_dma_tag_create SRB failure\n", unit);
3416 if (bus_dmamem_alloc(pACB->srb_dmat, (void **)&pACB->pFreeSRB,
3417 BUS_DMA_NOWAIT, &pACB->srb_dmamap) != 0) {
3418 printf("trm_init %d: bus_dmamem_alloc SRB failure\n", unit);
3421 bus_dmamap_load(pACB->srb_dmat, pACB->srb_dmamap, pACB->pFreeSRB,
3422 TRM_MAX_SRB_CNT * sizeof(TRM_SRB), trm_mapSRB, pACB,
3424 /* Create, allocate, and map DMA buffers for autosense data */
3425 if (bus_dma_tag_create(
3426 /*parent_dmat*/pACB->parent_dmat,
3429 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
3430 /*highaddr*/BUS_SPACE_MAXADDR,
3431 /*filter*/NULL, /*filterarg*/NULL,
3432 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT,
3434 /*maxsegsz*/TRM_MAXTRANSFER_SIZE,
3435 /*flags*/0, /*lockfunc*/busdma_lock_mutex,
3436 /*lockarg*/&Giant, &pACB->sense_dmat) != 0) {
3438 device_printf(dev, "cannot create sense buffer dmat\n");
3442 if (bus_dmamem_alloc(pACB->sense_dmat, (void **)&pACB->sense_buffers,
3443 BUS_DMA_NOWAIT, &pACB->sense_dmamap) != 0)
3446 bus_dmamap_load(pACB->sense_dmat, pACB->sense_dmamap,
3447 pACB->sense_buffers,
3448 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT,
3449 trm_dmamap_cb, &pACB->sense_busaddr, /*flags*/0);
3451 trm_check_eeprom(&trm_eepromBuf[unit],pACB);
3452 trm_initACB(pACB, adaptType, unit);
3453 for (i = 0; i < (pACB->max_id + 1); i++) {
3454 if (pACB->AdaptSCSIID == i)
3456 for(j = 0; j < (pACB->max_lun + 1); j++) {
3457 pACB->scan_devices[i][j] = 1;
3458 /* we assume we need to scan all devices */
3459 trm_initDCB(pACB, &pACB->DCBarray[i][j], unit, i, j);
3462 bzero(pACB->pFreeSRB, TRM_MAX_SRB_CNT * sizeof(TRM_SRB));
3463 if (bus_dma_tag_create(
3464 /*parent_dmat*/pACB->parent_dmat,
3467 /*lowaddr*/ BUS_SPACE_MAXADDR,
3468 /*highaddr*/ BUS_SPACE_MAXADDR,
3471 /*maxsize*/ TRM_MAX_SG_LISTENTRY * sizeof(SGentry),
3473 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE,
3475 /*lockfunc*/ busdma_lock_mutex,
3477 /*dmat*/ &pACB->sg_dmat) != 0)
3480 if (trm_initSRB(pACB)) {
3481 printf("trm_initSRB: error\n");
3484 if (trm_initAdapter(pACB, unit)) {
3485 printf("trm_initAdapter: initial ERROR\n");
3491 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0),
3493 if (pACB->sense_dmamap) {
3494 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap);
3495 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers,
3496 pACB->sense_dmamap);
3497 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap);
3499 if (pACB->sense_dmat)
3500 bus_dma_tag_destroy(pACB->sense_dmat);
3501 if (pACB->sg_dmat) {
3502 trm_destroySRB(pACB);
3503 bus_dma_tag_destroy(pACB->sg_dmat);
3505 if (pACB->srb_dmamap) {
3506 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap);
3507 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB,
3509 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap);
3512 bus_dma_tag_destroy(pACB->srb_dmat);
3513 if (pACB->buffer_dmat)
3514 bus_dma_tag_destroy(pACB->buffer_dmat);
3515 if (pACB->parent_dmat)
3516 bus_dma_tag_destroy(pACB->parent_dmat);
3521 trm_attach(device_t dev)
3523 struct cam_devq *device_Q;
3527 int unit = device_get_unit(dev);
3529 device_id = pci_get_devid(dev);
3531 * These cards do not allow memory mapped accesses
3533 if ((pACB = trm_init((u_int16_t) unit,
3535 printf("trm%d: trm_init error!\n",unit);
3538 /* After setting up the adapter, map our interrupt */
3540 * Now let the CAM generic SCSI layer find the SCSI devices on the bus
3541 * start queue to reset to the idle loop.
3542 * Create device queue of SIM(s)
3543 * (MAX_START_JOB - 1) : max_sim_transactions
3545 pACB->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3546 RF_SHAREABLE | RF_ACTIVE);
3547 if (pACB->irq == NULL ||
3548 bus_setup_intr(dev, pACB->irq,
3549 INTR_TYPE_CAM, NULL, trm_Interrupt, pACB, &pACB->ih)) {
3550 printf("trm%d: register Interrupt handler error!\n", unit);
3553 device_Q = cam_simq_alloc(TRM_MAX_START_JOB);
3554 if (device_Q == NULL){
3555 printf("trm%d: device_Q == NULL !\n",unit);
3559 * Now tell the generic SCSI layer
3561 * If this is the xpt layer creating a sim, then it's OK
3562 * to wait for an allocation.
3563 * XXX Should we pass in a flag to indicate that wait is OK?
3567 * SCSI Interface Modules
3568 * The sim driver creates a sim for each controller. The sim device
3569 * queue is separately created in order to allow resource sharing betwee
3570 * sims. For instance, a driver may create one sim for each channel of
3571 * a multi-channel controller and use the same queue for each channel.
3572 * In this way, the queue resources are shared across all the channels
3573 * of the multi-channel controller.
3574 * trm_action : sim_action_func
3575 * trm_poll : sim_poll_func
3576 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK
3577 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT
3579 * 1 : max_dev_transactions
3580 * MAX_TAGS : max_tagged_dev_transactions
3582 * *******Construct our first channel SIM entry
3584 pACB->psim = cam_sim_alloc(trm_action,
3591 TRM_MAX_TAGS_CMD_QUEUE,
3593 if (pACB->psim == NULL) {
3594 printf("trm%d: SIM allocate fault !\n",unit);
3595 cam_simq_free(device_Q); /* SIM allocate fault*/
3598 if (xpt_bus_register(pACB->psim, dev, 0) != CAM_SUCCESS) {
3599 printf("trm%d: xpt_bus_register fault !\n",unit);
3602 if (xpt_create_path(&pACB->ppath,
3604 cam_sim_path(pACB->psim),
3605 CAM_TARGET_WILDCARD,
3606 CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
3607 printf("trm%d: xpt_create_path fault !\n",unit);
3608 xpt_bus_deregister(cam_sim_path(pACB->psim));
3614 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0),
3616 if (pACB->sg_dmat) {
3617 trm_destroySRB(pACB);
3618 bus_dma_tag_destroy(pACB->sg_dmat);
3621 if (pACB->srb_dmamap) {
3622 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap);
3623 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB,
3625 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap);
3628 bus_dma_tag_destroy(pACB->srb_dmat);
3629 if (pACB->sense_dmamap) {
3630 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap);
3631 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers,
3632 pACB->sense_dmamap);
3633 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap);
3635 if (pACB->sense_dmat)
3636 bus_dma_tag_destroy(pACB->sense_dmat);
3637 if (pACB->buffer_dmat)
3638 bus_dma_tag_destroy(pACB->buffer_dmat);
3640 bus_teardown_intr(dev, pACB->irq, pACB->ih);
3642 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq);
3644 cam_sim_free(pACB->psim, TRUE);
3652 * trm_probe (device_t tag, pcidi_t type)
3656 trm_probe(device_t dev)
3658 switch (pci_get_devid(dev)) {
3659 case PCI_DEVICEID_TRMS1040:
3660 device_set_desc(dev,
3661 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter");
3662 return (BUS_PROBE_DEFAULT);
3663 case PCI_DEVICEID_TRMS2080:
3664 device_set_desc(dev,
3665 "Tekram DC395U2D/U2W Fast40 Wide SCSI Adapter");
3666 return (BUS_PROBE_DEFAULT);
3673 trm_detach(device_t dev)
3675 PACB pACB = device_get_softc(dev);
3677 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), pACB->iores);
3678 trm_destroySRB(pACB);
3679 bus_dma_tag_destroy(pACB->sg_dmat);
3680 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap);
3681 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB,
3683 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap);
3684 bus_dma_tag_destroy(pACB->srb_dmat);
3685 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap);
3686 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers,
3687 pACB->sense_dmamap);
3688 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap);
3689 bus_dma_tag_destroy(pACB->sense_dmat);
3690 bus_dma_tag_destroy(pACB->buffer_dmat);
3691 bus_teardown_intr(dev, pACB->irq, pACB->ih);
3692 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq);
3693 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL);
3694 xpt_free_path(pACB->ppath);
3695 xpt_bus_deregister(cam_sim_path(pACB->psim));
3696 cam_sim_free(pACB->psim, TRUE);
3699 static device_method_t trm_methods[] = {
3700 /* Device interface */
3701 DEVMETHOD(device_probe, trm_probe),
3702 DEVMETHOD(device_attach, trm_attach),
3703 DEVMETHOD(device_detach, trm_detach),
3707 static driver_t trm_driver = {
3708 "trm", trm_methods, sizeof(struct _ACB)
3711 static devclass_t trm_devclass;
3712 DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0);
3713 MODULE_DEPEND(trm, pci, 1, 1, 1);
3714 MODULE_DEPEND(trm, cam, 1, 1, 1);