2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #ifdef HAVE_KERNEL_OPTION_HEADERS
34 #include "opt_device_polling.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/sockio.h>
46 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
51 #include <net/if_var.h>
52 #include <net/if_arp.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
58 #include <netinet/in_systm.h>
59 #include <netinet/in.h>
60 #include <netinet/ip.h>
62 #include <machine/bus.h>
64 #include <dev/mii/mii.h>
65 #include <dev/mii/miivar.h>
67 #include <dev/tsec/if_tsec.h>
68 #include <dev/tsec/if_tsecreg.h>
70 static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag,
71 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr,
73 static void tsec_dma_ctl(struct tsec_softc *sc, int state);
74 static void tsec_encap(struct ifnet *ifp, struct tsec_softc *sc,
75 struct mbuf *m0, uint16_t fcb_flags, int *start_tx);
76 static void tsec_free_dma(struct tsec_softc *sc);
77 static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr);
78 static int tsec_ifmedia_upd(struct ifnet *ifp);
79 static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
80 static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map,
81 struct mbuf **mbufp, uint32_t *paddr);
82 static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs,
84 static void tsec_intrs_ctl(struct tsec_softc *sc, int state);
85 static void tsec_init(void *xsc);
86 static void tsec_init_locked(struct tsec_softc *sc);
87 static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
88 static void tsec_reset_mac(struct tsec_softc *sc);
89 static void tsec_setfilter(struct tsec_softc *sc);
90 static void tsec_set_mac_address(struct tsec_softc *sc);
91 static void tsec_start(struct ifnet *ifp);
92 static void tsec_start_locked(struct ifnet *ifp);
93 static void tsec_stop(struct tsec_softc *sc);
94 static void tsec_tick(void *arg);
95 static void tsec_watchdog(struct tsec_softc *sc);
96 static void tsec_add_sysctls(struct tsec_softc *sc);
97 static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS);
98 static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS);
99 static void tsec_set_rxic(struct tsec_softc *sc);
100 static void tsec_set_txic(struct tsec_softc *sc);
101 static int tsec_receive_intr_locked(struct tsec_softc *sc, int count);
102 static void tsec_transmit_intr_locked(struct tsec_softc *sc);
103 static void tsec_error_intr_locked(struct tsec_softc *sc, int count);
104 static void tsec_offload_setup(struct tsec_softc *sc);
105 static void tsec_offload_process_frame(struct tsec_softc *sc,
107 static void tsec_setup_multicast(struct tsec_softc *sc);
108 static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu);
110 devclass_t tsec_devclass;
111 DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0);
112 MODULE_DEPEND(tsec, ether, 1, 1, 1);
113 MODULE_DEPEND(tsec, miibus, 1, 1, 1);
115 struct mtx tsec_phy_mtx;
118 tsec_attach(struct tsec_softc *sc)
120 uint8_t hwaddr[ETHER_ADDR_LEN];
125 /* Initialize global (because potentially shared) MII lock */
126 if (!mtx_initialized(&tsec_phy_mtx))
127 mtx_init(&tsec_phy_mtx, "tsec mii", NULL, MTX_DEF);
129 /* Reset all TSEC counters */
130 TSEC_TX_RX_COUNTERS_INIT(sc);
132 /* Stop DMA engine if enabled by firmware */
138 /* Disable interrupts for now */
139 tsec_intrs_ctl(sc, 0);
141 /* Configure defaults for interrupts coalescing */
142 sc->rx_ic_time = 768;
143 sc->rx_ic_count = 16;
144 sc->tx_ic_time = 768;
145 sc->tx_ic_count = 16;
148 tsec_add_sysctls(sc);
150 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */
151 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag,
152 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC,
153 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX");
160 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */
161 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag,
162 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC,
163 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX");
169 /* Allocate a busdma tag for TX mbufs. */
170 error = bus_dma_tag_create(NULL, /* parent */
171 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
172 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
173 BUS_SPACE_MAXADDR, /* highaddr */
174 NULL, NULL, /* filtfunc, filtfuncarg */
175 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */
176 TSEC_TX_MAX_DMA_SEGS, /* nsegments */
177 MCLBYTES, 0, /* maxsegsz, flags */
178 NULL, NULL, /* lockfunc, lockfuncarg */
179 &sc->tsec_tx_mtag); /* dmat */
181 device_printf(sc->dev, "failed to allocate busdma tag "
187 /* Allocate a busdma tag for RX mbufs. */
188 error = bus_dma_tag_create(NULL, /* parent */
189 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
190 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
191 BUS_SPACE_MAXADDR, /* highaddr */
192 NULL, NULL, /* filtfunc, filtfuncarg */
193 MCLBYTES, /* maxsize */
195 MCLBYTES, 0, /* maxsegsz, flags */
196 NULL, NULL, /* lockfunc, lockfuncarg */
197 &sc->tsec_rx_mtag); /* dmat */
199 device_printf(sc->dev, "failed to allocate busdma tag "
205 /* Create TX busdma maps */
206 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
207 error = bus_dmamap_create(sc->tsec_tx_mtag, 0,
208 &sc->tx_bufmap[i].map);
210 device_printf(sc->dev, "failed to init TX ring\n");
214 sc->tx_bufmap[i].map_initialized = 1;
217 /* Create RX busdma maps and zero mbuf handlers */
218 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
219 error = bus_dmamap_create(sc->tsec_rx_mtag, 0,
220 &sc->rx_data[i].map);
222 device_printf(sc->dev, "failed to init RX ring\n");
226 sc->rx_data[i].mbuf = NULL;
229 /* Create mbufs for RX buffers */
230 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
231 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map,
232 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr);
234 device_printf(sc->dev, "can't load rx DMA map %d, "
235 "error = %d\n", i, error);
241 /* Create network interface for upper layers */
242 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER);
244 device_printf(sc->dev, "if_alloc() failed\n");
250 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
251 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
252 ifp->if_init = tsec_init;
253 ifp->if_start = tsec_start;
254 ifp->if_ioctl = tsec_ioctl;
256 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1);
257 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1;
258 IFQ_SET_READY(&ifp->if_snd);
260 ifp->if_capabilities = IFCAP_VLAN_MTU;
262 ifp->if_capabilities |= IFCAP_HWCSUM;
264 ifp->if_capenable = ifp->if_capabilities;
266 #ifdef DEVICE_POLLING
267 /* Advertise that polling is supported */
268 ifp->if_capabilities |= IFCAP_POLLING;
272 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd,
273 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY,
276 device_printf(sc->dev, "attaching PHYs failed\n");
282 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
284 /* Set MAC address */
285 tsec_get_hwaddr(sc, hwaddr);
286 ether_ifattach(ifp, hwaddr);
292 tsec_detach(struct tsec_softc *sc)
295 if (sc->tsec_ifp != NULL) {
296 #ifdef DEVICE_POLLING
297 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING)
298 ether_poll_deregister(sc->tsec_ifp);
301 /* Stop TSEC controller and free TX queue */
303 tsec_shutdown(sc->dev);
305 /* Detach network interface */
306 ether_ifdetach(sc->tsec_ifp);
307 if_free(sc->tsec_ifp);
311 /* Free DMA resources */
318 tsec_shutdown(device_t dev)
320 struct tsec_softc *sc;
322 sc = device_get_softc(dev);
324 TSEC_GLOBAL_LOCK(sc);
326 TSEC_GLOBAL_UNLOCK(sc);
331 tsec_suspend(device_t dev)
334 /* TODO not implemented! */
339 tsec_resume(device_t dev)
342 /* TODO not implemented! */
349 struct tsec_softc *sc = xsc;
351 TSEC_GLOBAL_LOCK(sc);
352 tsec_init_locked(sc);
353 TSEC_GLOBAL_UNLOCK(sc);
357 tsec_mii_wait(struct tsec_softc *sc, uint32_t flags)
362 * The status indicators are not set immediatly after a command.
363 * Discard the first value.
365 TSEC_PHY_READ(sc, TSEC_REG_MIIMIND);
367 timeout = TSEC_READ_RETRY;
368 while ((TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) & flags) && --timeout)
369 DELAY(TSEC_READ_DELAY);
371 return (timeout == 0);
376 tsec_init_locked(struct tsec_softc *sc)
378 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr;
379 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr;
380 struct ifnet *ifp = sc->tsec_ifp;
384 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
387 TSEC_GLOBAL_LOCK_ASSERT(sc);
391 * These steps are according to the MPC8555E PowerQUICCIII RM:
392 * 14.7 Initialization/Application Information
395 /* Step 1: soft reset MAC */
398 /* Step 2: Initialize MACCFG2 */
399 TSEC_WRITE(sc, TSEC_REG_MACCFG2,
400 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */
401 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */
402 TSEC_MACCFG2_GMII | /* I/F Mode bit */
403 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */
406 /* Step 3: Initialize ECNTRL
407 * While the documentation states that R100M is ignored if RPM is
408 * not set, it does seem to be needed to get the orange boxes to
409 * work (which have a Marvell 88E1111 PHY). Go figure.
413 * XXX kludge - use circumstancial evidence to program ECNTRL
414 * correctly. Ideally we need some board information to guide
417 i = TSEC_READ(sc, TSEC_REG_ID2);
419 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */
420 : TSEC_ECNTRL_R100M; /* Orange + CDS */
421 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val);
423 /* Step 4: Initialize MAC station address */
424 tsec_set_mac_address(sc);
427 * Step 5: Assign a Physical address to the TBI so as to not conflict
428 * with the external PHY physical address
430 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5);
434 /* Step 6: Reset the management interface */
435 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT);
437 /* Step 7: Setup the MII Mgmt clock speed */
438 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28);
440 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */
441 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY);
445 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n");
449 /* Step 9: Setup the MII Mgmt */
450 mii_mediachg(sc->tsec_mii);
452 /* Step 10: Clear IEVENT register */
453 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff);
455 /* Step 11: Enable interrupts */
456 #ifdef DEVICE_POLLING
458 * ...only if polling is not turned on. Disable interrupts explicitly
459 * if polling is enabled.
461 if (ifp->if_capenable & IFCAP_POLLING )
462 tsec_intrs_ctl(sc, 0);
464 #endif /* DEVICE_POLLING */
465 tsec_intrs_ctl(sc, 1);
467 /* Step 12: Initialize IADDRn */
468 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0);
469 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0);
470 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0);
471 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0);
472 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0);
473 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0);
474 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0);
475 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0);
477 /* Step 13: Initialize GADDRn */
478 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0);
479 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0);
480 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0);
481 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0);
482 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0);
483 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0);
484 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0);
485 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0);
487 /* Step 14: Initialize RCTRL */
488 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0);
490 /* Step 15: Initialize DMACTRL */
493 /* Step 16: Initialize FIFO_PAUSE_CTRL */
494 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN);
497 * Step 17: Initialize transmit/receive descriptor rings.
498 * Initialize TBASE and RBASE.
500 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr);
501 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr);
503 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
504 tx_desc[i].bufptr = 0;
505 tx_desc[i].length = 0;
506 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ?
509 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
510 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
512 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
513 rx_desc[i].bufptr = sc->rx_data[i].paddr;
514 rx_desc[i].length = 0;
515 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I |
516 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0);
518 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
519 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
521 /* Step 18: Initialize the maximum receive buffer length */
522 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES);
524 /* Step 19: Configure ethernet frame sizes */
525 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE);
526 tsec_set_mtu(sc, ifp->if_mtu);
528 /* Step 20: Enable Rx and RxBD sdata snooping */
529 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN);
530 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0);
532 /* Step 21: Reset collision counters in hardware */
533 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
534 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
535 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
536 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
537 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
539 /* Step 22: Mask all CAM interrupts */
540 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff);
541 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff);
543 /* Step 23: Enable Rx and Tx */
544 val = TSEC_READ(sc, TSEC_REG_MACCFG1);
545 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
546 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val);
548 /* Step 24: Reset TSEC counters for Tx and Rx rings */
549 TSEC_TX_RX_COUNTERS_INIT(sc);
551 /* Step 25: Setup TCP/IP Off-Load engine */
553 tsec_offload_setup(sc);
555 /* Step 26: Setup multicast filters */
556 tsec_setup_multicast(sc);
558 /* Step 27: Activate network interface */
559 ifp->if_drv_flags |= IFF_DRV_RUNNING;
560 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
561 sc->tsec_if_flags = ifp->if_flags;
562 sc->tsec_watchdog = 0;
564 /* Schedule watchdog timeout */
565 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
569 tsec_set_mac_address(struct tsec_softc *sc)
571 uint32_t macbuf[2] = { 0, 0 };
572 char *macbufp, *curmac;
575 TSEC_GLOBAL_LOCK_ASSERT(sc);
577 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)),
578 ("tsec_set_mac_address: (%d <= %zd", ETHER_ADDR_LEN,
581 macbufp = (char *)macbuf;
582 curmac = (char *)IF_LLADDR(sc->tsec_ifp);
584 /* Correct order of MAC address bytes */
585 for (i = 1; i <= ETHER_ADDR_LEN; i++)
586 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1];
588 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */
589 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]);
590 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]);
594 * DMA control function, if argument state is:
595 * 0 - DMA engine will be disabled
596 * 1 - DMA engine will be enabled
599 tsec_dma_ctl(struct tsec_softc *sc, int state)
602 uint32_t dma_flags, timeout;
606 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL);
610 /* Temporarily clear stop graceful stop bits. */
611 tsec_dma_ctl(sc, 1000);
614 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
618 /* Set write with response (WWR), wait (WOP) and snoop bits */
619 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN |
620 DMACTRL_WWR | DMACTRL_WOP);
622 /* Clear graceful stop bits */
623 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
626 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n",
630 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags);
634 /* Wait for DMA stop */
635 timeout = TSEC_READ_RETRY;
636 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) &
637 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC))))
638 DELAY(TSEC_READ_DELAY);
641 device_printf(dev, "tsec_dma_ctl(): timeout!\n");
644 /* Restart transmission function */
645 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
650 * Interrupts control function, if argument state is:
651 * 0 - all TSEC interrupts will be masked
652 * 1 - all TSEC interrupts will be unmasked
655 tsec_intrs_ctl(struct tsec_softc *sc, int state)
663 TSEC_WRITE(sc, TSEC_REG_IMASK, 0);
666 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN |
667 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN |
668 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN |
669 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN);
672 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n",
678 tsec_reset_mac(struct tsec_softc *sc)
680 uint32_t maccfg1_flags;
682 /* Set soft reset bit */
683 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
684 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET;
685 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
687 /* Clear soft reset bit */
688 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
689 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET;
690 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
694 tsec_watchdog(struct tsec_softc *sc)
698 TSEC_GLOBAL_LOCK_ASSERT(sc);
700 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0)
704 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
705 if_printf(ifp, "watchdog timeout\n");
708 tsec_init_locked(sc);
712 tsec_start(struct ifnet *ifp)
714 struct tsec_softc *sc = ifp->if_softc;
716 TSEC_TRANSMIT_LOCK(sc);
717 tsec_start_locked(ifp);
718 TSEC_TRANSMIT_UNLOCK(sc);
722 tsec_start_locked(struct ifnet *ifp)
724 struct tsec_softc *sc;
726 struct tsec_tx_fcb *tx_fcb;
734 TSEC_TRANSMIT_LOCK_ASSERT(sc);
736 if (sc->tsec_link == 0)
739 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
740 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
744 if (TSEC_FREE_TX_DESC(sc) < TSEC_TX_MAX_DMA_SEGS) {
745 /* No free descriptors */
746 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
750 /* Get packet from the queue */
751 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
755 /* Insert TCP/IP Off-load frame control block */
757 csum_flags = m0->m_pkthdr.csum_flags;
759 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT);
763 if (csum_flags & CSUM_IP)
764 fcb_flags |= TSEC_TX_FCB_IP4 |
767 if (csum_flags & CSUM_TCP)
768 fcb_flags |= TSEC_TX_FCB_TCP |
769 TSEC_TX_FCB_CSUM_TCP_UDP;
771 if (csum_flags & CSUM_UDP)
772 fcb_flags |= TSEC_TX_FCB_UDP |
773 TSEC_TX_FCB_CSUM_TCP_UDP;
775 tx_fcb = mtod(m0, struct tsec_tx_fcb *);
776 tx_fcb->flags = fcb_flags;
777 tx_fcb->l3_offset = ETHER_HDR_LEN;
778 tx_fcb->l4_offset = sizeof(struct ip);
781 tsec_encap(ifp, sc, m0, fcb_flags, &start_tx);
783 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
784 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
787 /* Enable transmitter and watchdog timer */
788 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
789 sc->tsec_watchdog = 5;
794 tsec_encap(struct ifnet *ifp, struct tsec_softc *sc, struct mbuf *m0,
795 uint16_t fcb_flags, int *start_tx)
797 bus_dma_segment_t segs[TSEC_TX_MAX_DMA_SEGS];
799 struct tsec_bufmap *tx_bufmap;
803 TSEC_TRANSMIT_LOCK_ASSERT(sc);
805 tx_idx = sc->tx_idx_head;
806 tx_bufmap = &sc->tx_bufmap[tx_idx];
808 /* Create mapping in DMA memory */
809 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, tx_bufmap->map, m0,
810 segs, &nsegs, BUS_DMA_NOWAIT);
811 if (error == EFBIG) {
812 /* Too many segments! Defrag and try again. */
813 struct mbuf *m = m_defrag(m0, M_NOWAIT);
820 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
821 tx_bufmap->map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
829 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map,
830 BUS_DMASYNC_PREWRITE);
831 tx_bufmap->mbuf = m0;
834 * Fill in the TX descriptors back to front so that READY bit in first
835 * descriptor is set last.
837 tx_idx = (tx_idx + (uint32_t)nsegs) & (TSEC_TX_NUM_DESC - 1);
838 sc->tx_idx_head = tx_idx;
839 flags = TSEC_TXBD_L | TSEC_TXBD_I | TSEC_TXBD_R | TSEC_TXBD_TC;
840 for (i = nsegs - 1; i >= 0; i--) {
841 struct tsec_desc *tx_desc;
843 tx_idx = (tx_idx - 1) & (TSEC_TX_NUM_DESC - 1);
844 tx_desc = &sc->tsec_tx_vaddr[tx_idx];
845 tx_desc->length = segs[i].ds_len;
846 tx_desc->bufptr = segs[i].ds_addr;
852 flags |= TSEC_TXBD_TOE;
860 * - transmit the CRC sequence after the last data byte
861 * - interrupt after the last buffer
863 tx_desc->flags = (tx_idx == (TSEC_TX_NUM_DESC - 1) ?
864 TSEC_TXBD_W : 0) | flags;
866 flags &= ~(TSEC_TXBD_L | TSEC_TXBD_I);
874 tsec_setfilter(struct tsec_softc *sc)
880 flags = TSEC_READ(sc, TSEC_REG_RCTRL);
882 /* Promiscuous mode */
883 if (ifp->if_flags & IFF_PROMISC)
884 flags |= TSEC_RCTRL_PROM;
886 flags &= ~TSEC_RCTRL_PROM;
888 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags);
891 #ifdef DEVICE_POLLING
892 static poll_handler_t tsec_poll;
895 tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
898 struct tsec_softc *sc = ifp->if_softc;
903 TSEC_GLOBAL_LOCK(sc);
904 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
905 TSEC_GLOBAL_UNLOCK(sc);
909 if (cmd == POLL_AND_CHECK_STATUS) {
910 tsec_error_intr_locked(sc, count);
912 /* Clear all events reported */
913 ie = TSEC_READ(sc, TSEC_REG_IEVENT);
914 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie);
917 tsec_transmit_intr_locked(sc);
919 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc);
921 rx_npkts = tsec_receive_intr_locked(sc, count);
923 TSEC_RECEIVE_UNLOCK(sc);
927 #endif /* DEVICE_POLLING */
930 tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
932 struct tsec_softc *sc = ifp->if_softc;
933 struct ifreq *ifr = (struct ifreq *)data;
938 TSEC_GLOBAL_LOCK(sc);
939 if (tsec_set_mtu(sc, ifr->ifr_mtu))
940 ifp->if_mtu = ifr->ifr_mtu;
943 TSEC_GLOBAL_UNLOCK(sc);
946 TSEC_GLOBAL_LOCK(sc);
947 if (ifp->if_flags & IFF_UP) {
948 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
949 if ((sc->tsec_if_flags ^ ifp->if_flags) &
953 if ((sc->tsec_if_flags ^ ifp->if_flags) &
955 tsec_setup_multicast(sc);
957 tsec_init_locked(sc);
958 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
961 sc->tsec_if_flags = ifp->if_flags;
962 TSEC_GLOBAL_UNLOCK(sc);
966 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
967 TSEC_GLOBAL_LOCK(sc);
968 tsec_setup_multicast(sc);
969 TSEC_GLOBAL_UNLOCK(sc);
973 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media,
977 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
978 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) {
979 TSEC_GLOBAL_LOCK(sc);
980 ifp->if_capenable &= ~IFCAP_HWCSUM;
981 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap;
982 tsec_offload_setup(sc);
983 TSEC_GLOBAL_UNLOCK(sc);
985 #ifdef DEVICE_POLLING
986 if (mask & IFCAP_POLLING) {
987 if (ifr->ifr_reqcap & IFCAP_POLLING) {
988 error = ether_poll_register(tsec_poll, ifp);
992 TSEC_GLOBAL_LOCK(sc);
993 /* Disable interrupts */
994 tsec_intrs_ctl(sc, 0);
995 ifp->if_capenable |= IFCAP_POLLING;
996 TSEC_GLOBAL_UNLOCK(sc);
998 error = ether_poll_deregister(ifp);
999 TSEC_GLOBAL_LOCK(sc);
1000 /* Enable interrupts */
1001 tsec_intrs_ctl(sc, 1);
1002 ifp->if_capenable &= ~IFCAP_POLLING;
1003 TSEC_GLOBAL_UNLOCK(sc);
1010 error = ether_ioctl(ifp, command, data);
1013 /* Flush buffers if not empty */
1014 if (ifp->if_flags & IFF_UP)
1020 tsec_ifmedia_upd(struct ifnet *ifp)
1022 struct tsec_softc *sc = ifp->if_softc;
1023 struct mii_data *mii;
1025 TSEC_TRANSMIT_LOCK(sc);
1030 TSEC_TRANSMIT_UNLOCK(sc);
1035 tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1037 struct tsec_softc *sc = ifp->if_softc;
1038 struct mii_data *mii;
1040 TSEC_TRANSMIT_LOCK(sc);
1045 ifmr->ifm_active = mii->mii_media_active;
1046 ifmr->ifm_status = mii->mii_media_status;
1048 TSEC_TRANSMIT_UNLOCK(sc);
1052 tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp,
1055 struct mbuf *new_mbuf;
1056 bus_dma_segment_t seg[1];
1059 KASSERT(mbufp != NULL, ("NULL mbuf pointer!"));
1061 new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES);
1062 if (new_mbuf == NULL)
1064 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size;
1067 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD);
1068 bus_dmamap_unload(tag, map);
1071 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs,
1073 KASSERT(nsegs == 1, ("Too many segments returned!"));
1074 if (nsegs != 1 || error)
1075 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error);
1079 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n",
1087 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0,
1088 ("Wrong alignment of RX buffer!"));
1090 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD);
1092 (*mbufp) = new_mbuf;
1093 (*paddr) = seg->ds_addr;
1098 tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1102 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1104 *paddr = segs->ds_addr;
1108 tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap,
1109 bus_size_t dsize, void **vaddr, void *raddr, const char *dname)
1113 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1114 error = bus_dma_tag_create(NULL, /* parent */
1115 PAGE_SIZE, 0, /* alignment, boundary */
1116 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1117 BUS_SPACE_MAXADDR, /* highaddr */
1118 NULL, NULL, /* filtfunc, filtfuncarg */
1119 dsize, 1, /* maxsize, nsegments */
1120 dsize, 0, /* maxsegsz, flags */
1121 NULL, NULL, /* lockfunc, lockfuncarg */
1125 device_printf(dev, "failed to allocate busdma %s tag\n",
1131 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1134 device_printf(dev, "failed to allocate %s DMA safe memory\n",
1136 bus_dma_tag_destroy(*dtag);
1141 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize,
1142 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT);
1144 device_printf(dev, "cannot get address of the %s "
1145 "descriptors\n", dname);
1146 bus_dmamem_free(*dtag, *vaddr, *dmap);
1147 bus_dma_tag_destroy(*dtag);
1156 tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr)
1162 /* Unmap descriptors from DMA memory */
1163 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD |
1164 BUS_DMASYNC_POSTWRITE);
1165 bus_dmamap_unload(dtag, dmap);
1167 /* Free descriptors memory */
1168 bus_dmamem_free(dtag, vaddr, dmap);
1170 /* Destroy descriptors tag */
1171 bus_dma_tag_destroy(dtag);
1175 tsec_free_dma(struct tsec_softc *sc)
1180 for (i = 0; i < TSEC_TX_NUM_DESC; i++)
1181 if (sc->tx_bufmap[i].map_initialized)
1182 bus_dmamap_destroy(sc->tsec_tx_mtag,
1183 sc->tx_bufmap[i].map);
1184 /* Destroy tag for TX mbufs */
1185 bus_dma_tag_destroy(sc->tsec_tx_mtag);
1187 /* Free RX mbufs and maps */
1188 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
1189 if (sc->rx_data[i].mbuf) {
1190 /* Unload buffer from DMA */
1191 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map,
1192 BUS_DMASYNC_POSTREAD);
1193 bus_dmamap_unload(sc->tsec_rx_mtag,
1194 sc->rx_data[i].map);
1197 m_freem(sc->rx_data[i].mbuf);
1199 /* Destroy map for this buffer */
1200 if (sc->rx_data[i].map != NULL)
1201 bus_dmamap_destroy(sc->tsec_rx_mtag,
1202 sc->rx_data[i].map);
1204 /* Destroy tag for RX mbufs */
1205 bus_dma_tag_destroy(sc->tsec_rx_mtag);
1207 /* Unload TX/RX descriptors */
1208 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1210 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1215 tsec_stop(struct tsec_softc *sc)
1220 TSEC_GLOBAL_LOCK_ASSERT(sc);
1224 /* Disable interface and watchdog timer */
1225 callout_stop(&sc->tsec_callout);
1226 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1227 sc->tsec_watchdog = 0;
1229 /* Disable all interrupts and stop DMA */
1230 tsec_intrs_ctl(sc, 0);
1231 tsec_dma_ctl(sc, 0);
1233 /* Remove pending data from TX queue */
1234 while (sc->tx_idx_tail != sc->tx_idx_head) {
1235 bus_dmamap_sync(sc->tsec_tx_mtag,
1236 sc->tx_bufmap[sc->tx_idx_tail].map,
1237 BUS_DMASYNC_POSTWRITE);
1238 bus_dmamap_unload(sc->tsec_tx_mtag,
1239 sc->tx_bufmap[sc->tx_idx_tail].map);
1240 m_freem(sc->tx_bufmap[sc->tx_idx_tail].mbuf);
1241 sc->tx_idx_tail = (sc->tx_idx_tail + 1)
1242 & (TSEC_TX_NUM_DESC - 1);
1245 /* Disable RX and TX */
1246 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1);
1247 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
1248 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval);
1253 tsec_tick(void *arg)
1255 struct tsec_softc *sc = arg;
1259 TSEC_GLOBAL_LOCK(sc);
1264 link = sc->tsec_link;
1266 mii_tick(sc->tsec_mii);
1268 if (link == 0 && sc->tsec_link == 1 &&
1269 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)))
1270 tsec_start_locked(ifp);
1272 /* Schedule another timeout one second from now. */
1273 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
1275 TSEC_GLOBAL_UNLOCK(sc);
1279 * This is the core RX routine. It replenishes mbufs in the descriptor and
1280 * sends data which have been dma'ed into host memory to upper layer.
1282 * Loops at most count times if count is > 0, or until done if count < 0.
1285 tsec_receive_intr_locked(struct tsec_softc *sc, int count)
1287 struct tsec_desc *rx_desc;
1289 struct rx_data_type *rx_data;
1295 TSEC_RECEIVE_LOCK_ASSERT(sc);
1298 rx_data = sc->rx_data;
1301 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1302 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1304 for (c = 0; ; c++) {
1305 if (count >= 0 && count-- == 0)
1308 rx_desc = TSEC_GET_CUR_RX_DESC(sc);
1309 flags = rx_desc->flags;
1311 /* Check if there is anything to receive */
1312 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) {
1314 * Avoid generating another interrupt
1316 if (flags & TSEC_RXBD_E)
1317 TSEC_WRITE(sc, TSEC_REG_IEVENT,
1318 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1320 * We didn't consume current descriptor and have to
1321 * return it to the queue
1323 TSEC_BACK_CUR_RX_DESC(sc);
1327 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO |
1328 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) {
1330 rx_desc->length = 0;
1331 rx_desc->flags = (rx_desc->flags &
1332 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I;
1334 if (sc->frame != NULL) {
1342 /* Ok... process frame */
1343 i = TSEC_GET_CUR_RX_DESC_CNT(sc);
1344 m = rx_data[i].mbuf;
1345 m->m_len = rx_desc->length;
1347 if (sc->frame != NULL) {
1348 if ((flags & TSEC_RXBD_L) != 0)
1349 m->m_len -= m_length(sc->frame, NULL);
1351 m->m_flags &= ~M_PKTHDR;
1352 m_cat(sc->frame, m);
1359 if ((flags & TSEC_RXBD_L) != 0) {
1364 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map,
1365 &rx_data[i].mbuf, &rx_data[i].paddr)) {
1366 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1368 * We ran out of mbufs; didn't consume current
1369 * descriptor and have to return it to the queue.
1371 TSEC_BACK_CUR_RX_DESC(sc);
1375 /* Attach new buffer to descriptor and clear flags */
1376 rx_desc->bufptr = rx_data[i].paddr;
1377 rx_desc->length = 0;
1378 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) |
1379 TSEC_RXBD_E | TSEC_RXBD_I;
1382 m->m_pkthdr.rcvif = ifp;
1385 m_adj(m, -ETHER_CRC_LEN);
1388 tsec_offload_process_frame(sc, m);
1390 TSEC_RECEIVE_UNLOCK(sc);
1391 (*ifp->if_input)(ifp, m);
1392 TSEC_RECEIVE_LOCK(sc);
1397 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1398 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1401 * Make sure TSEC receiver is not halted.
1403 * Various conditions can stop the TSEC receiver, but not all are
1404 * signaled and handled by error interrupt, so make sure the receiver
1405 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when
1406 * halted, and is harmless if already running.
1408 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT);
1413 tsec_receive_intr(void *arg)
1415 struct tsec_softc *sc = arg;
1417 TSEC_RECEIVE_LOCK(sc);
1419 #ifdef DEVICE_POLLING
1420 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1421 TSEC_RECEIVE_UNLOCK(sc);
1426 /* Confirm the interrupt was received by driver */
1427 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1428 tsec_receive_intr_locked(sc, -1);
1430 TSEC_RECEIVE_UNLOCK(sc);
1434 tsec_transmit_intr_locked(struct tsec_softc *sc)
1439 TSEC_TRANSMIT_LOCK_ASSERT(sc);
1443 /* Update collision statistics */
1444 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, TSEC_READ(sc, TSEC_REG_MON_TNCL));
1446 /* Reset collision counters in hardware */
1447 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
1448 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
1449 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
1450 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
1451 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
1453 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1454 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1456 tx_idx = sc->tx_idx_tail;
1457 while (tx_idx != sc->tx_idx_head) {
1458 struct tsec_desc *tx_desc;
1459 struct tsec_bufmap *tx_bufmap;
1461 tx_desc = &sc->tsec_tx_vaddr[tx_idx];
1462 if (tx_desc->flags & TSEC_TXBD_R) {
1466 tx_bufmap = &sc->tx_bufmap[tx_idx];
1467 tx_idx = (tx_idx + 1) & (TSEC_TX_NUM_DESC - 1);
1468 if (tx_bufmap->mbuf == NULL)
1472 * This is the last buf in this packet, so unmap and free it.
1474 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map,
1475 BUS_DMASYNC_POSTWRITE);
1476 bus_dmamap_unload(sc->tsec_tx_mtag, tx_bufmap->map);
1477 m_freem(tx_bufmap->mbuf);
1478 tx_bufmap->mbuf = NULL;
1480 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1482 sc->tx_idx_tail = tx_idx;
1483 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1484 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1486 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1487 tsec_start_locked(ifp);
1489 if (sc->tx_idx_tail == sc->tx_idx_head)
1490 sc->tsec_watchdog = 0;
1494 tsec_transmit_intr(void *arg)
1496 struct tsec_softc *sc = arg;
1498 TSEC_TRANSMIT_LOCK(sc);
1500 #ifdef DEVICE_POLLING
1501 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1502 TSEC_TRANSMIT_UNLOCK(sc);
1506 /* Confirm the interrupt was received by driver */
1507 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF);
1508 tsec_transmit_intr_locked(sc);
1510 TSEC_TRANSMIT_UNLOCK(sc);
1514 tsec_error_intr_locked(struct tsec_softc *sc, int count)
1519 TSEC_GLOBAL_LOCK_ASSERT(sc);
1523 eflags = TSEC_READ(sc, TSEC_REG_IEVENT);
1525 /* Clear events bits in hardware */
1526 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY |
1527 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT |
1528 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC |
1529 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN);
1531 /* Check transmitter errors */
1532 if (eflags & TSEC_IEVENT_TXE) {
1533 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1535 if (eflags & TSEC_IEVENT_LC)
1536 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1538 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
1541 /* Check for discarded frame due to a lack of buffers */
1542 if (eflags & TSEC_IEVENT_BSY) {
1543 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1546 if (ifp->if_flags & IFF_DEBUG)
1547 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n",
1550 if (eflags & TSEC_IEVENT_EBERR) {
1551 if_printf(ifp, "System bus error occurred during"
1552 "DMA transaction (flags: 0x%x)\n", eflags);
1553 tsec_init_locked(sc);
1556 if (eflags & TSEC_IEVENT_BABT)
1557 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1559 if (eflags & TSEC_IEVENT_BABR)
1560 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1564 tsec_error_intr(void *arg)
1566 struct tsec_softc *sc = arg;
1568 TSEC_GLOBAL_LOCK(sc);
1569 tsec_error_intr_locked(sc, -1);
1570 TSEC_GLOBAL_UNLOCK(sc);
1574 tsec_miibus_readreg(device_t dev, int phy, int reg)
1576 struct tsec_softc *sc;
1580 sc = device_get_softc(dev);
1583 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1584 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, 0);
1585 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
1587 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY);
1588 rv = TSEC_PHY_READ(sc, TSEC_REG_MIIMSTAT);
1592 device_printf(dev, "Timeout while reading from PHY!\n");
1598 tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1600 struct tsec_softc *sc;
1603 sc = device_get_softc(dev);
1606 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1607 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCON, value);
1608 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY);
1612 device_printf(dev, "Timeout while writing to PHY!\n");
1618 tsec_miibus_statchg(device_t dev)
1620 struct tsec_softc *sc;
1621 struct mii_data *mii;
1622 uint32_t ecntrl, id, tmp;
1625 sc = device_get_softc(dev);
1627 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0);
1629 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF;
1631 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
1632 tmp |= TSEC_MACCFG2_FULLDUPLEX;
1634 tmp &= ~TSEC_MACCFG2_FULLDUPLEX;
1636 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1639 tmp |= TSEC_MACCFG2_GMII;
1640 sc->tsec_link = link;
1644 tmp |= TSEC_MACCFG2_MII;
1645 sc->tsec_link = link;
1649 device_printf(dev, "No speed selected but link "
1655 device_printf(dev, "Unknown speed (%d), link %s!\n",
1656 IFM_SUBTYPE(mii->mii_media_active),
1657 ((link) ? "up" : "down"));
1660 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp);
1662 /* XXX kludge - use circumstantial evidence for reduced mode. */
1663 id = TSEC_READ(sc, TSEC_REG_ID2);
1665 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M;
1666 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0;
1667 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl);
1672 tsec_add_sysctls(struct tsec_softc *sc)
1674 struct sysctl_ctx_list *ctx;
1675 struct sysctl_oid_list *children;
1676 struct sysctl_oid *tree;
1678 ctx = device_get_sysctl_ctx(sc->dev);
1679 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
1680 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal",
1681 CTLFLAG_RD, 0, "TSEC Interrupts coalescing");
1682 children = SYSCTL_CHILDREN(tree);
1684 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time",
1685 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time,
1686 "I", "IC RX time threshold (0-65535)");
1687 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count",
1688 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count,
1689 "I", "IC RX frame count threshold (0-255)");
1691 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time",
1692 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time,
1693 "I", "IC TX time threshold (0-65535)");
1694 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count",
1695 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count,
1696 "I", "IC TX frame count threshold (0-255)");
1700 * With Interrupt Coalescing (IC) active, a transmit/receive frame
1701 * interrupt is raised either upon:
1703 * - threshold-defined period of time elapsed, or
1704 * - threshold-defined number of frames is received/transmitted,
1705 * whichever occurs first.
1707 * The following sysctls regulate IC behaviour (for TX/RX separately):
1709 * dev.tsec.<unit>.int_coal.rx_time
1710 * dev.tsec.<unit>.int_coal.rx_count
1711 * dev.tsec.<unit>.int_coal.tx_time
1712 * dev.tsec.<unit>.int_coal.tx_count
1716 * - 0 for either time or count disables IC on the given TX/RX path
1718 * - count: 1-255 (expresses frame count number; note that value of 1 is
1719 * effectively IC off)
1721 * - time: 1-65535 (value corresponds to a real time period and is
1722 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer
1723 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps,
1724 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the
1725 * TSEC reference manual.
1728 tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)
1732 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1734 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
1736 error = sysctl_handle_int(oidp, &time, 0, req);
1744 if (arg2 == TSEC_IC_RX) {
1745 sc->rx_ic_time = time;
1748 sc->tx_ic_time = time;
1757 tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)
1761 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1763 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count;
1765 error = sysctl_handle_int(oidp, &count, 0, req);
1773 if (arg2 == TSEC_IC_RX) {
1774 sc->rx_ic_count = count;
1777 sc->tx_ic_count = count;
1786 tsec_set_rxic(struct tsec_softc *sc)
1790 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0)
1794 rxic_val = 0x80000000;
1795 rxic_val |= (sc->rx_ic_count << 21);
1796 rxic_val |= sc->rx_ic_time;
1799 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val);
1803 tsec_set_txic(struct tsec_softc *sc)
1807 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0)
1811 txic_val = 0x80000000;
1812 txic_val |= (sc->tx_ic_count << 21);
1813 txic_val |= sc->tx_ic_time;
1816 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val);
1820 tsec_offload_setup(struct tsec_softc *sc)
1822 struct ifnet *ifp = sc->tsec_ifp;
1825 TSEC_GLOBAL_LOCK_ASSERT(sc);
1827 reg = TSEC_READ(sc, TSEC_REG_TCTRL);
1828 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN;
1830 if (ifp->if_capenable & IFCAP_TXCSUM)
1831 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES;
1833 ifp->if_hwassist = 0;
1835 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg);
1837 reg = TSEC_READ(sc, TSEC_REG_RCTRL);
1838 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP);
1839 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX;
1841 if (ifp->if_capenable & IFCAP_RXCSUM)
1842 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN |
1843 TSEC_RCTRL_PRSDEP_PARSE_L234;
1845 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg);
1850 tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m)
1852 struct tsec_rx_fcb rx_fcb;
1854 int protocol, flags;
1856 TSEC_RECEIVE_LOCK_ASSERT(sc);
1858 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb));
1859 flags = rx_fcb.flags;
1860 protocol = rx_fcb.protocol;
1862 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) {
1863 csum_flags |= CSUM_IP_CHECKED;
1865 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0)
1866 csum_flags |= CSUM_IP_VALID;
1869 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) &&
1870 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) &&
1871 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) {
1873 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1874 m->m_pkthdr.csum_data = 0xFFFF;
1877 m->m_pkthdr.csum_flags = csum_flags;
1879 if (flags & TSEC_RX_FCB_VLAN) {
1880 m->m_pkthdr.ether_vtag = rx_fcb.vlan;
1881 m->m_flags |= M_VLANTAG;
1884 m_adj(m, sizeof(struct tsec_rx_fcb));
1888 tsec_setup_multicast(struct tsec_softc *sc)
1890 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
1891 struct ifnet *ifp = sc->tsec_ifp;
1892 struct ifmultiaddr *ifma;
1896 TSEC_GLOBAL_LOCK_ASSERT(sc);
1898 if (ifp->if_flags & IFF_ALLMULTI) {
1899 for (i = 0; i < 8; i++)
1900 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF);
1905 if_maddr_rlock(ifp);
1906 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1908 if (ifma->ifma_addr->sa_family != AF_LINK)
1911 h = (ether_crc32_be(LLADDR((struct sockaddr_dl *)
1912 ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF;
1914 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F));
1916 if_maddr_runlock(ifp);
1918 for (i = 0; i < 8; i++)
1919 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]);
1923 tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu)
1926 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
1928 TSEC_GLOBAL_LOCK_ASSERT(sc);
1930 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) {
1931 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu);