2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
5 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #ifdef HAVE_KERNEL_OPTION_HEADERS
36 #include "opt_device_polling.h"
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/endian.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
51 #include <net/ethernet.h>
53 #include <net/if_var.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_types.h>
58 #include <net/if_vlan_var.h>
60 #include <netinet/in_systm.h>
61 #include <netinet/in.h>
62 #include <netinet/ip.h>
64 #include <machine/bus.h>
66 #include <dev/mii/mii.h>
67 #include <dev/mii/miivar.h>
69 #include <dev/tsec/if_tsec.h>
70 #include <dev/tsec/if_tsecreg.h>
72 static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag,
73 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr,
75 static void tsec_dma_ctl(struct tsec_softc *sc, int state);
76 static void tsec_encap(struct ifnet *ifp, struct tsec_softc *sc,
77 struct mbuf *m0, uint16_t fcb_flags, int *start_tx);
78 static void tsec_free_dma(struct tsec_softc *sc);
79 static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr);
80 static int tsec_ifmedia_upd(struct ifnet *ifp);
81 static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
82 static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map,
83 struct mbuf **mbufp, uint32_t *paddr);
84 static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs,
86 static void tsec_intrs_ctl(struct tsec_softc *sc, int state);
87 static void tsec_init(void *xsc);
88 static void tsec_init_locked(struct tsec_softc *sc);
89 static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
90 static void tsec_reset_mac(struct tsec_softc *sc);
91 static void tsec_setfilter(struct tsec_softc *sc);
92 static void tsec_set_mac_address(struct tsec_softc *sc);
93 static void tsec_start(struct ifnet *ifp);
94 static void tsec_start_locked(struct ifnet *ifp);
95 static void tsec_stop(struct tsec_softc *sc);
96 static void tsec_tick(void *arg);
97 static void tsec_watchdog(struct tsec_softc *sc);
98 static void tsec_add_sysctls(struct tsec_softc *sc);
99 static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS);
100 static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS);
101 static void tsec_set_rxic(struct tsec_softc *sc);
102 static void tsec_set_txic(struct tsec_softc *sc);
103 static int tsec_receive_intr_locked(struct tsec_softc *sc, int count);
104 static void tsec_transmit_intr_locked(struct tsec_softc *sc);
105 static void tsec_error_intr_locked(struct tsec_softc *sc, int count);
106 static void tsec_offload_setup(struct tsec_softc *sc);
107 static void tsec_offload_process_frame(struct tsec_softc *sc,
109 static void tsec_setup_multicast(struct tsec_softc *sc);
110 static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu);
112 devclass_t tsec_devclass;
113 DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0);
114 MODULE_DEPEND(tsec, ether, 1, 1, 1);
115 MODULE_DEPEND(tsec, miibus, 1, 1, 1);
117 struct mtx tsec_phy_mtx;
120 tsec_attach(struct tsec_softc *sc)
122 uint8_t hwaddr[ETHER_ADDR_LEN];
127 /* Initialize global (because potentially shared) MII lock */
128 if (!mtx_initialized(&tsec_phy_mtx))
129 mtx_init(&tsec_phy_mtx, "tsec mii", NULL, MTX_DEF);
131 /* Reset all TSEC counters */
132 TSEC_TX_RX_COUNTERS_INIT(sc);
134 /* Stop DMA engine if enabled by firmware */
140 /* Disable interrupts for now */
141 tsec_intrs_ctl(sc, 0);
143 /* Configure defaults for interrupts coalescing */
144 sc->rx_ic_time = 768;
145 sc->rx_ic_count = 16;
146 sc->tx_ic_time = 768;
147 sc->tx_ic_count = 16;
150 tsec_add_sysctls(sc);
152 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */
153 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag,
154 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC,
155 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX");
162 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */
163 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag,
164 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC,
165 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX");
171 /* Allocate a busdma tag for TX mbufs. */
172 error = bus_dma_tag_create(NULL, /* parent */
173 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
174 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
175 BUS_SPACE_MAXADDR, /* highaddr */
176 NULL, NULL, /* filtfunc, filtfuncarg */
177 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */
178 TSEC_TX_MAX_DMA_SEGS, /* nsegments */
179 MCLBYTES, 0, /* maxsegsz, flags */
180 NULL, NULL, /* lockfunc, lockfuncarg */
181 &sc->tsec_tx_mtag); /* dmat */
183 device_printf(sc->dev, "failed to allocate busdma tag "
189 /* Allocate a busdma tag for RX mbufs. */
190 error = bus_dma_tag_create(NULL, /* parent */
191 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
192 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
193 BUS_SPACE_MAXADDR, /* highaddr */
194 NULL, NULL, /* filtfunc, filtfuncarg */
195 MCLBYTES, /* maxsize */
197 MCLBYTES, 0, /* maxsegsz, flags */
198 NULL, NULL, /* lockfunc, lockfuncarg */
199 &sc->tsec_rx_mtag); /* dmat */
201 device_printf(sc->dev, "failed to allocate busdma tag "
207 /* Create TX busdma maps */
208 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
209 error = bus_dmamap_create(sc->tsec_tx_mtag, 0,
210 &sc->tx_bufmap[i].map);
212 device_printf(sc->dev, "failed to init TX ring\n");
216 sc->tx_bufmap[i].map_initialized = 1;
219 /* Create RX busdma maps and zero mbuf handlers */
220 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
221 error = bus_dmamap_create(sc->tsec_rx_mtag, 0,
222 &sc->rx_data[i].map);
224 device_printf(sc->dev, "failed to init RX ring\n");
228 sc->rx_data[i].mbuf = NULL;
231 /* Create mbufs for RX buffers */
232 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
233 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map,
234 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr);
236 device_printf(sc->dev, "can't load rx DMA map %d, "
237 "error = %d\n", i, error);
243 /* Create network interface for upper layers */
244 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER);
246 device_printf(sc->dev, "if_alloc() failed\n");
252 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
253 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
254 ifp->if_init = tsec_init;
255 ifp->if_start = tsec_start;
256 ifp->if_ioctl = tsec_ioctl;
258 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1);
259 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1;
260 IFQ_SET_READY(&ifp->if_snd);
262 ifp->if_capabilities = IFCAP_VLAN_MTU;
264 ifp->if_capabilities |= IFCAP_HWCSUM;
266 ifp->if_capenable = ifp->if_capabilities;
268 #ifdef DEVICE_POLLING
269 /* Advertise that polling is supported */
270 ifp->if_capabilities |= IFCAP_POLLING;
274 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd,
275 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY,
278 device_printf(sc->dev, "attaching PHYs failed\n");
284 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
286 /* Set MAC address */
287 tsec_get_hwaddr(sc, hwaddr);
288 ether_ifattach(ifp, hwaddr);
294 tsec_detach(struct tsec_softc *sc)
297 if (sc->tsec_ifp != NULL) {
298 #ifdef DEVICE_POLLING
299 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING)
300 ether_poll_deregister(sc->tsec_ifp);
303 /* Stop TSEC controller and free TX queue */
305 tsec_shutdown(sc->dev);
307 /* Detach network interface */
308 ether_ifdetach(sc->tsec_ifp);
309 if_free(sc->tsec_ifp);
313 /* Free DMA resources */
320 tsec_shutdown(device_t dev)
322 struct tsec_softc *sc;
324 sc = device_get_softc(dev);
326 TSEC_GLOBAL_LOCK(sc);
328 TSEC_GLOBAL_UNLOCK(sc);
333 tsec_suspend(device_t dev)
336 /* TODO not implemented! */
341 tsec_resume(device_t dev)
344 /* TODO not implemented! */
351 struct tsec_softc *sc = xsc;
353 TSEC_GLOBAL_LOCK(sc);
354 tsec_init_locked(sc);
355 TSEC_GLOBAL_UNLOCK(sc);
359 tsec_mii_wait(struct tsec_softc *sc, uint32_t flags)
364 * The status indicators are not set immediatly after a command.
365 * Discard the first value.
367 TSEC_PHY_READ(sc, TSEC_REG_MIIMIND);
369 timeout = TSEC_READ_RETRY;
370 while ((TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) & flags) && --timeout)
371 DELAY(TSEC_READ_DELAY);
373 return (timeout == 0);
378 tsec_init_locked(struct tsec_softc *sc)
380 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr;
381 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr;
382 struct ifnet *ifp = sc->tsec_ifp;
386 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
389 TSEC_GLOBAL_LOCK_ASSERT(sc);
393 * These steps are according to the MPC8555E PowerQUICCIII RM:
394 * 14.7 Initialization/Application Information
397 /* Step 1: soft reset MAC */
400 /* Step 2: Initialize MACCFG2 */
401 TSEC_WRITE(sc, TSEC_REG_MACCFG2,
402 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */
403 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */
404 TSEC_MACCFG2_GMII | /* I/F Mode bit */
405 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */
408 /* Step 3: Initialize ECNTRL
409 * While the documentation states that R100M is ignored if RPM is
410 * not set, it does seem to be needed to get the orange boxes to
411 * work (which have a Marvell 88E1111 PHY). Go figure.
415 * XXX kludge - use circumstancial evidence to program ECNTRL
416 * correctly. Ideally we need some board information to guide
419 i = TSEC_READ(sc, TSEC_REG_ID2);
421 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */
422 : TSEC_ECNTRL_R100M; /* Orange + CDS */
423 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val);
425 /* Step 4: Initialize MAC station address */
426 tsec_set_mac_address(sc);
429 * Step 5: Assign a Physical address to the TBI so as to not conflict
430 * with the external PHY physical address
432 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5);
436 /* Step 6: Reset the management interface */
437 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT);
439 /* Step 7: Setup the MII Mgmt clock speed */
440 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28);
442 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */
443 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY);
447 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n");
451 /* Step 9: Setup the MII Mgmt */
452 mii_mediachg(sc->tsec_mii);
454 /* Step 10: Clear IEVENT register */
455 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff);
457 /* Step 11: Enable interrupts */
458 #ifdef DEVICE_POLLING
460 * ...only if polling is not turned on. Disable interrupts explicitly
461 * if polling is enabled.
463 if (ifp->if_capenable & IFCAP_POLLING )
464 tsec_intrs_ctl(sc, 0);
466 #endif /* DEVICE_POLLING */
467 tsec_intrs_ctl(sc, 1);
469 /* Step 12: Initialize IADDRn */
470 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0);
471 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0);
472 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0);
473 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0);
474 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0);
475 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0);
476 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0);
477 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0);
479 /* Step 13: Initialize GADDRn */
480 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0);
481 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0);
482 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0);
483 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0);
484 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0);
485 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0);
486 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0);
487 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0);
489 /* Step 14: Initialize RCTRL */
490 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0);
492 /* Step 15: Initialize DMACTRL */
495 /* Step 16: Initialize FIFO_PAUSE_CTRL */
496 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN);
499 * Step 17: Initialize transmit/receive descriptor rings.
500 * Initialize TBASE and RBASE.
502 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr);
503 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr);
505 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
506 tx_desc[i].bufptr = 0;
507 tx_desc[i].length = 0;
508 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ?
511 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
512 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
514 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
515 rx_desc[i].bufptr = sc->rx_data[i].paddr;
516 rx_desc[i].length = 0;
517 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I |
518 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0);
520 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
521 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
523 /* Step 18: Initialize the maximum receive buffer length */
524 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES);
526 /* Step 19: Configure ethernet frame sizes */
527 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE);
528 tsec_set_mtu(sc, ifp->if_mtu);
530 /* Step 20: Enable Rx and RxBD sdata snooping */
531 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN);
532 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0);
534 /* Step 21: Reset collision counters in hardware */
535 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
536 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
537 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
538 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
539 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
541 /* Step 22: Mask all CAM interrupts */
542 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff);
543 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff);
545 /* Step 23: Enable Rx and Tx */
546 val = TSEC_READ(sc, TSEC_REG_MACCFG1);
547 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
548 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val);
550 /* Step 24: Reset TSEC counters for Tx and Rx rings */
551 TSEC_TX_RX_COUNTERS_INIT(sc);
553 /* Step 25: Setup TCP/IP Off-Load engine */
555 tsec_offload_setup(sc);
557 /* Step 26: Setup multicast filters */
558 tsec_setup_multicast(sc);
560 /* Step 27: Activate network interface */
561 ifp->if_drv_flags |= IFF_DRV_RUNNING;
562 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
563 sc->tsec_if_flags = ifp->if_flags;
564 sc->tsec_watchdog = 0;
566 /* Schedule watchdog timeout */
567 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
571 tsec_set_mac_address(struct tsec_softc *sc)
573 uint32_t macbuf[2] = { 0, 0 };
574 char *macbufp, *curmac;
577 TSEC_GLOBAL_LOCK_ASSERT(sc);
579 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)),
580 ("tsec_set_mac_address: (%d <= %zd", ETHER_ADDR_LEN,
583 macbufp = (char *)macbuf;
584 curmac = (char *)IF_LLADDR(sc->tsec_ifp);
586 /* Correct order of MAC address bytes */
587 for (i = 1; i <= ETHER_ADDR_LEN; i++)
588 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1];
590 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */
591 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]);
592 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]);
596 * DMA control function, if argument state is:
597 * 0 - DMA engine will be disabled
598 * 1 - DMA engine will be enabled
601 tsec_dma_ctl(struct tsec_softc *sc, int state)
604 uint32_t dma_flags, timeout;
608 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL);
612 /* Temporarily clear stop graceful stop bits. */
613 tsec_dma_ctl(sc, 1000);
616 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
620 /* Set write with response (WWR), wait (WOP) and snoop bits */
621 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN |
622 DMACTRL_WWR | DMACTRL_WOP);
624 /* Clear graceful stop bits */
625 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
628 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n",
632 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags);
636 /* Wait for DMA stop */
637 timeout = TSEC_READ_RETRY;
638 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) &
639 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC))))
640 DELAY(TSEC_READ_DELAY);
643 device_printf(dev, "tsec_dma_ctl(): timeout!\n");
646 /* Restart transmission function */
647 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
652 * Interrupts control function, if argument state is:
653 * 0 - all TSEC interrupts will be masked
654 * 1 - all TSEC interrupts will be unmasked
657 tsec_intrs_ctl(struct tsec_softc *sc, int state)
665 TSEC_WRITE(sc, TSEC_REG_IMASK, 0);
668 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN |
669 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN |
670 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN |
671 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN);
674 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n",
680 tsec_reset_mac(struct tsec_softc *sc)
682 uint32_t maccfg1_flags;
684 /* Set soft reset bit */
685 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
686 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET;
687 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
689 /* Clear soft reset bit */
690 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
691 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET;
692 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
696 tsec_watchdog(struct tsec_softc *sc)
700 TSEC_GLOBAL_LOCK_ASSERT(sc);
702 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0)
706 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
707 if_printf(ifp, "watchdog timeout\n");
710 tsec_init_locked(sc);
714 tsec_start(struct ifnet *ifp)
716 struct tsec_softc *sc = ifp->if_softc;
718 TSEC_TRANSMIT_LOCK(sc);
719 tsec_start_locked(ifp);
720 TSEC_TRANSMIT_UNLOCK(sc);
724 tsec_start_locked(struct ifnet *ifp)
726 struct tsec_softc *sc;
728 struct tsec_tx_fcb *tx_fcb;
736 TSEC_TRANSMIT_LOCK_ASSERT(sc);
738 if (sc->tsec_link == 0)
741 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
742 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
746 if (TSEC_FREE_TX_DESC(sc) < TSEC_TX_MAX_DMA_SEGS) {
747 /* No free descriptors */
748 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
752 /* Get packet from the queue */
753 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
757 /* Insert TCP/IP Off-load frame control block */
759 csum_flags = m0->m_pkthdr.csum_flags;
761 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT);
765 if (csum_flags & CSUM_IP)
766 fcb_flags |= TSEC_TX_FCB_IP4 |
769 if (csum_flags & CSUM_TCP)
770 fcb_flags |= TSEC_TX_FCB_TCP |
771 TSEC_TX_FCB_CSUM_TCP_UDP;
773 if (csum_flags & CSUM_UDP)
774 fcb_flags |= TSEC_TX_FCB_UDP |
775 TSEC_TX_FCB_CSUM_TCP_UDP;
777 tx_fcb = mtod(m0, struct tsec_tx_fcb *);
778 tx_fcb->flags = fcb_flags;
779 tx_fcb->l3_offset = ETHER_HDR_LEN;
780 tx_fcb->l4_offset = sizeof(struct ip);
783 tsec_encap(ifp, sc, m0, fcb_flags, &start_tx);
785 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
786 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
789 /* Enable transmitter and watchdog timer */
790 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
791 sc->tsec_watchdog = 5;
796 tsec_encap(struct ifnet *ifp, struct tsec_softc *sc, struct mbuf *m0,
797 uint16_t fcb_flags, int *start_tx)
799 bus_dma_segment_t segs[TSEC_TX_MAX_DMA_SEGS];
801 struct tsec_bufmap *tx_bufmap;
805 TSEC_TRANSMIT_LOCK_ASSERT(sc);
807 tx_idx = sc->tx_idx_head;
808 tx_bufmap = &sc->tx_bufmap[tx_idx];
810 /* Create mapping in DMA memory */
811 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, tx_bufmap->map, m0,
812 segs, &nsegs, BUS_DMA_NOWAIT);
813 if (error == EFBIG) {
814 /* Too many segments! Defrag and try again. */
815 struct mbuf *m = m_defrag(m0, M_NOWAIT);
822 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
823 tx_bufmap->map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
831 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map,
832 BUS_DMASYNC_PREWRITE);
833 tx_bufmap->mbuf = m0;
836 * Fill in the TX descriptors back to front so that READY bit in first
837 * descriptor is set last.
839 tx_idx = (tx_idx + (uint32_t)nsegs) & (TSEC_TX_NUM_DESC - 1);
840 sc->tx_idx_head = tx_idx;
841 flags = TSEC_TXBD_L | TSEC_TXBD_I | TSEC_TXBD_R | TSEC_TXBD_TC;
842 for (i = nsegs - 1; i >= 0; i--) {
843 struct tsec_desc *tx_desc;
845 tx_idx = (tx_idx - 1) & (TSEC_TX_NUM_DESC - 1);
846 tx_desc = &sc->tsec_tx_vaddr[tx_idx];
847 tx_desc->length = segs[i].ds_len;
848 tx_desc->bufptr = segs[i].ds_addr;
854 flags |= TSEC_TXBD_TOE;
862 * - transmit the CRC sequence after the last data byte
863 * - interrupt after the last buffer
865 tx_desc->flags = (tx_idx == (TSEC_TX_NUM_DESC - 1) ?
866 TSEC_TXBD_W : 0) | flags;
868 flags &= ~(TSEC_TXBD_L | TSEC_TXBD_I);
876 tsec_setfilter(struct tsec_softc *sc)
882 flags = TSEC_READ(sc, TSEC_REG_RCTRL);
884 /* Promiscuous mode */
885 if (ifp->if_flags & IFF_PROMISC)
886 flags |= TSEC_RCTRL_PROM;
888 flags &= ~TSEC_RCTRL_PROM;
890 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags);
893 #ifdef DEVICE_POLLING
894 static poll_handler_t tsec_poll;
897 tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
900 struct tsec_softc *sc = ifp->if_softc;
905 TSEC_GLOBAL_LOCK(sc);
906 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
907 TSEC_GLOBAL_UNLOCK(sc);
911 if (cmd == POLL_AND_CHECK_STATUS) {
912 tsec_error_intr_locked(sc, count);
914 /* Clear all events reported */
915 ie = TSEC_READ(sc, TSEC_REG_IEVENT);
916 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie);
919 tsec_transmit_intr_locked(sc);
921 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc);
923 rx_npkts = tsec_receive_intr_locked(sc, count);
925 TSEC_RECEIVE_UNLOCK(sc);
929 #endif /* DEVICE_POLLING */
932 tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
934 struct tsec_softc *sc = ifp->if_softc;
935 struct ifreq *ifr = (struct ifreq *)data;
940 TSEC_GLOBAL_LOCK(sc);
941 if (tsec_set_mtu(sc, ifr->ifr_mtu))
942 ifp->if_mtu = ifr->ifr_mtu;
945 TSEC_GLOBAL_UNLOCK(sc);
948 TSEC_GLOBAL_LOCK(sc);
949 if (ifp->if_flags & IFF_UP) {
950 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
951 if ((sc->tsec_if_flags ^ ifp->if_flags) &
955 if ((sc->tsec_if_flags ^ ifp->if_flags) &
957 tsec_setup_multicast(sc);
959 tsec_init_locked(sc);
960 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
963 sc->tsec_if_flags = ifp->if_flags;
964 TSEC_GLOBAL_UNLOCK(sc);
968 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
969 TSEC_GLOBAL_LOCK(sc);
970 tsec_setup_multicast(sc);
971 TSEC_GLOBAL_UNLOCK(sc);
975 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media,
979 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
980 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) {
981 TSEC_GLOBAL_LOCK(sc);
982 ifp->if_capenable &= ~IFCAP_HWCSUM;
983 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap;
984 tsec_offload_setup(sc);
985 TSEC_GLOBAL_UNLOCK(sc);
987 #ifdef DEVICE_POLLING
988 if (mask & IFCAP_POLLING) {
989 if (ifr->ifr_reqcap & IFCAP_POLLING) {
990 error = ether_poll_register(tsec_poll, ifp);
994 TSEC_GLOBAL_LOCK(sc);
995 /* Disable interrupts */
996 tsec_intrs_ctl(sc, 0);
997 ifp->if_capenable |= IFCAP_POLLING;
998 TSEC_GLOBAL_UNLOCK(sc);
1000 error = ether_poll_deregister(ifp);
1001 TSEC_GLOBAL_LOCK(sc);
1002 /* Enable interrupts */
1003 tsec_intrs_ctl(sc, 1);
1004 ifp->if_capenable &= ~IFCAP_POLLING;
1005 TSEC_GLOBAL_UNLOCK(sc);
1012 error = ether_ioctl(ifp, command, data);
1015 /* Flush buffers if not empty */
1016 if (ifp->if_flags & IFF_UP)
1022 tsec_ifmedia_upd(struct ifnet *ifp)
1024 struct tsec_softc *sc = ifp->if_softc;
1025 struct mii_data *mii;
1027 TSEC_TRANSMIT_LOCK(sc);
1032 TSEC_TRANSMIT_UNLOCK(sc);
1037 tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1039 struct tsec_softc *sc = ifp->if_softc;
1040 struct mii_data *mii;
1042 TSEC_TRANSMIT_LOCK(sc);
1047 ifmr->ifm_active = mii->mii_media_active;
1048 ifmr->ifm_status = mii->mii_media_status;
1050 TSEC_TRANSMIT_UNLOCK(sc);
1054 tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp,
1057 struct mbuf *new_mbuf;
1058 bus_dma_segment_t seg[1];
1061 KASSERT(mbufp != NULL, ("NULL mbuf pointer!"));
1063 new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES);
1064 if (new_mbuf == NULL)
1066 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size;
1069 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD);
1070 bus_dmamap_unload(tag, map);
1073 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs,
1075 KASSERT(nsegs == 1, ("Too many segments returned!"));
1076 if (nsegs != 1 || error)
1077 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error);
1081 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n",
1089 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0,
1090 ("Wrong alignment of RX buffer!"));
1092 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD);
1094 (*mbufp) = new_mbuf;
1095 (*paddr) = seg->ds_addr;
1100 tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1104 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1106 *paddr = segs->ds_addr;
1110 tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap,
1111 bus_size_t dsize, void **vaddr, void *raddr, const char *dname)
1115 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1116 error = bus_dma_tag_create(NULL, /* parent */
1117 PAGE_SIZE, 0, /* alignment, boundary */
1118 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1119 BUS_SPACE_MAXADDR, /* highaddr */
1120 NULL, NULL, /* filtfunc, filtfuncarg */
1121 dsize, 1, /* maxsize, nsegments */
1122 dsize, 0, /* maxsegsz, flags */
1123 NULL, NULL, /* lockfunc, lockfuncarg */
1127 device_printf(dev, "failed to allocate busdma %s tag\n",
1133 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1136 device_printf(dev, "failed to allocate %s DMA safe memory\n",
1138 bus_dma_tag_destroy(*dtag);
1143 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize,
1144 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT);
1146 device_printf(dev, "cannot get address of the %s "
1147 "descriptors\n", dname);
1148 bus_dmamem_free(*dtag, *vaddr, *dmap);
1149 bus_dma_tag_destroy(*dtag);
1158 tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr)
1164 /* Unmap descriptors from DMA memory */
1165 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD |
1166 BUS_DMASYNC_POSTWRITE);
1167 bus_dmamap_unload(dtag, dmap);
1169 /* Free descriptors memory */
1170 bus_dmamem_free(dtag, vaddr, dmap);
1172 /* Destroy descriptors tag */
1173 bus_dma_tag_destroy(dtag);
1177 tsec_free_dma(struct tsec_softc *sc)
1182 for (i = 0; i < TSEC_TX_NUM_DESC; i++)
1183 if (sc->tx_bufmap[i].map_initialized)
1184 bus_dmamap_destroy(sc->tsec_tx_mtag,
1185 sc->tx_bufmap[i].map);
1186 /* Destroy tag for TX mbufs */
1187 bus_dma_tag_destroy(sc->tsec_tx_mtag);
1189 /* Free RX mbufs and maps */
1190 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
1191 if (sc->rx_data[i].mbuf) {
1192 /* Unload buffer from DMA */
1193 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map,
1194 BUS_DMASYNC_POSTREAD);
1195 bus_dmamap_unload(sc->tsec_rx_mtag,
1196 sc->rx_data[i].map);
1199 m_freem(sc->rx_data[i].mbuf);
1201 /* Destroy map for this buffer */
1202 if (sc->rx_data[i].map != NULL)
1203 bus_dmamap_destroy(sc->tsec_rx_mtag,
1204 sc->rx_data[i].map);
1206 /* Destroy tag for RX mbufs */
1207 bus_dma_tag_destroy(sc->tsec_rx_mtag);
1209 /* Unload TX/RX descriptors */
1210 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1212 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1217 tsec_stop(struct tsec_softc *sc)
1222 TSEC_GLOBAL_LOCK_ASSERT(sc);
1226 /* Disable interface and watchdog timer */
1227 callout_stop(&sc->tsec_callout);
1228 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1229 sc->tsec_watchdog = 0;
1231 /* Disable all interrupts and stop DMA */
1232 tsec_intrs_ctl(sc, 0);
1233 tsec_dma_ctl(sc, 0);
1235 /* Remove pending data from TX queue */
1236 while (sc->tx_idx_tail != sc->tx_idx_head) {
1237 bus_dmamap_sync(sc->tsec_tx_mtag,
1238 sc->tx_bufmap[sc->tx_idx_tail].map,
1239 BUS_DMASYNC_POSTWRITE);
1240 bus_dmamap_unload(sc->tsec_tx_mtag,
1241 sc->tx_bufmap[sc->tx_idx_tail].map);
1242 m_freem(sc->tx_bufmap[sc->tx_idx_tail].mbuf);
1243 sc->tx_idx_tail = (sc->tx_idx_tail + 1)
1244 & (TSEC_TX_NUM_DESC - 1);
1247 /* Disable RX and TX */
1248 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1);
1249 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
1250 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval);
1255 tsec_tick(void *arg)
1257 struct tsec_softc *sc = arg;
1261 TSEC_GLOBAL_LOCK(sc);
1266 link = sc->tsec_link;
1268 mii_tick(sc->tsec_mii);
1270 if (link == 0 && sc->tsec_link == 1 &&
1271 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)))
1272 tsec_start_locked(ifp);
1274 /* Schedule another timeout one second from now. */
1275 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
1277 TSEC_GLOBAL_UNLOCK(sc);
1281 * This is the core RX routine. It replenishes mbufs in the descriptor and
1282 * sends data which have been dma'ed into host memory to upper layer.
1284 * Loops at most count times if count is > 0, or until done if count < 0.
1287 tsec_receive_intr_locked(struct tsec_softc *sc, int count)
1289 struct tsec_desc *rx_desc;
1291 struct rx_data_type *rx_data;
1297 TSEC_RECEIVE_LOCK_ASSERT(sc);
1300 rx_data = sc->rx_data;
1303 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1304 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1306 for (c = 0; ; c++) {
1307 if (count >= 0 && count-- == 0)
1310 rx_desc = TSEC_GET_CUR_RX_DESC(sc);
1311 flags = rx_desc->flags;
1313 /* Check if there is anything to receive */
1314 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) {
1316 * Avoid generating another interrupt
1318 if (flags & TSEC_RXBD_E)
1319 TSEC_WRITE(sc, TSEC_REG_IEVENT,
1320 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1322 * We didn't consume current descriptor and have to
1323 * return it to the queue
1325 TSEC_BACK_CUR_RX_DESC(sc);
1329 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO |
1330 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) {
1332 rx_desc->length = 0;
1333 rx_desc->flags = (rx_desc->flags &
1334 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I;
1336 if (sc->frame != NULL) {
1344 /* Ok... process frame */
1345 i = TSEC_GET_CUR_RX_DESC_CNT(sc);
1346 m = rx_data[i].mbuf;
1347 m->m_len = rx_desc->length;
1349 if (sc->frame != NULL) {
1350 if ((flags & TSEC_RXBD_L) != 0)
1351 m->m_len -= m_length(sc->frame, NULL);
1353 m->m_flags &= ~M_PKTHDR;
1354 m_cat(sc->frame, m);
1361 if ((flags & TSEC_RXBD_L) != 0) {
1366 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map,
1367 &rx_data[i].mbuf, &rx_data[i].paddr)) {
1368 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1370 * We ran out of mbufs; didn't consume current
1371 * descriptor and have to return it to the queue.
1373 TSEC_BACK_CUR_RX_DESC(sc);
1377 /* Attach new buffer to descriptor and clear flags */
1378 rx_desc->bufptr = rx_data[i].paddr;
1379 rx_desc->length = 0;
1380 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) |
1381 TSEC_RXBD_E | TSEC_RXBD_I;
1384 m->m_pkthdr.rcvif = ifp;
1387 m_adj(m, -ETHER_CRC_LEN);
1390 tsec_offload_process_frame(sc, m);
1392 TSEC_RECEIVE_UNLOCK(sc);
1393 (*ifp->if_input)(ifp, m);
1394 TSEC_RECEIVE_LOCK(sc);
1399 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1400 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1403 * Make sure TSEC receiver is not halted.
1405 * Various conditions can stop the TSEC receiver, but not all are
1406 * signaled and handled by error interrupt, so make sure the receiver
1407 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when
1408 * halted, and is harmless if already running.
1410 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT);
1415 tsec_receive_intr(void *arg)
1417 struct tsec_softc *sc = arg;
1419 TSEC_RECEIVE_LOCK(sc);
1421 #ifdef DEVICE_POLLING
1422 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1423 TSEC_RECEIVE_UNLOCK(sc);
1428 /* Confirm the interrupt was received by driver */
1429 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1430 tsec_receive_intr_locked(sc, -1);
1432 TSEC_RECEIVE_UNLOCK(sc);
1436 tsec_transmit_intr_locked(struct tsec_softc *sc)
1441 TSEC_TRANSMIT_LOCK_ASSERT(sc);
1445 /* Update collision statistics */
1446 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, TSEC_READ(sc, TSEC_REG_MON_TNCL));
1448 /* Reset collision counters in hardware */
1449 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
1450 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
1451 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
1452 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
1453 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
1455 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1456 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1458 tx_idx = sc->tx_idx_tail;
1459 while (tx_idx != sc->tx_idx_head) {
1460 struct tsec_desc *tx_desc;
1461 struct tsec_bufmap *tx_bufmap;
1463 tx_desc = &sc->tsec_tx_vaddr[tx_idx];
1464 if (tx_desc->flags & TSEC_TXBD_R) {
1468 tx_bufmap = &sc->tx_bufmap[tx_idx];
1469 tx_idx = (tx_idx + 1) & (TSEC_TX_NUM_DESC - 1);
1470 if (tx_bufmap->mbuf == NULL)
1474 * This is the last buf in this packet, so unmap and free it.
1476 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map,
1477 BUS_DMASYNC_POSTWRITE);
1478 bus_dmamap_unload(sc->tsec_tx_mtag, tx_bufmap->map);
1479 m_freem(tx_bufmap->mbuf);
1480 tx_bufmap->mbuf = NULL;
1482 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1484 sc->tx_idx_tail = tx_idx;
1485 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1486 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1488 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1489 tsec_start_locked(ifp);
1491 if (sc->tx_idx_tail == sc->tx_idx_head)
1492 sc->tsec_watchdog = 0;
1496 tsec_transmit_intr(void *arg)
1498 struct tsec_softc *sc = arg;
1500 TSEC_TRANSMIT_LOCK(sc);
1502 #ifdef DEVICE_POLLING
1503 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1504 TSEC_TRANSMIT_UNLOCK(sc);
1508 /* Confirm the interrupt was received by driver */
1509 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF);
1510 tsec_transmit_intr_locked(sc);
1512 TSEC_TRANSMIT_UNLOCK(sc);
1516 tsec_error_intr_locked(struct tsec_softc *sc, int count)
1521 TSEC_GLOBAL_LOCK_ASSERT(sc);
1525 eflags = TSEC_READ(sc, TSEC_REG_IEVENT);
1527 /* Clear events bits in hardware */
1528 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY |
1529 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT |
1530 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC |
1531 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN);
1533 /* Check transmitter errors */
1534 if (eflags & TSEC_IEVENT_TXE) {
1535 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1537 if (eflags & TSEC_IEVENT_LC)
1538 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1540 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
1543 /* Check for discarded frame due to a lack of buffers */
1544 if (eflags & TSEC_IEVENT_BSY) {
1545 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1548 if (ifp->if_flags & IFF_DEBUG)
1549 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n",
1552 if (eflags & TSEC_IEVENT_EBERR) {
1553 if_printf(ifp, "System bus error occurred during"
1554 "DMA transaction (flags: 0x%x)\n", eflags);
1555 tsec_init_locked(sc);
1558 if (eflags & TSEC_IEVENT_BABT)
1559 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1561 if (eflags & TSEC_IEVENT_BABR)
1562 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1566 tsec_error_intr(void *arg)
1568 struct tsec_softc *sc = arg;
1570 TSEC_GLOBAL_LOCK(sc);
1571 tsec_error_intr_locked(sc, -1);
1572 TSEC_GLOBAL_UNLOCK(sc);
1576 tsec_miibus_readreg(device_t dev, int phy, int reg)
1578 struct tsec_softc *sc;
1582 sc = device_get_softc(dev);
1585 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1586 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, 0);
1587 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
1589 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY);
1590 rv = TSEC_PHY_READ(sc, TSEC_REG_MIIMSTAT);
1594 device_printf(dev, "Timeout while reading from PHY!\n");
1600 tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1602 struct tsec_softc *sc;
1605 sc = device_get_softc(dev);
1608 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1609 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCON, value);
1610 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY);
1614 device_printf(dev, "Timeout while writing to PHY!\n");
1620 tsec_miibus_statchg(device_t dev)
1622 struct tsec_softc *sc;
1623 struct mii_data *mii;
1624 uint32_t ecntrl, id, tmp;
1627 sc = device_get_softc(dev);
1629 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0);
1631 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF;
1633 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
1634 tmp |= TSEC_MACCFG2_FULLDUPLEX;
1636 tmp &= ~TSEC_MACCFG2_FULLDUPLEX;
1638 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1641 tmp |= TSEC_MACCFG2_GMII;
1642 sc->tsec_link = link;
1646 tmp |= TSEC_MACCFG2_MII;
1647 sc->tsec_link = link;
1651 device_printf(dev, "No speed selected but link "
1657 device_printf(dev, "Unknown speed (%d), link %s!\n",
1658 IFM_SUBTYPE(mii->mii_media_active),
1659 ((link) ? "up" : "down"));
1662 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp);
1664 /* XXX kludge - use circumstantial evidence for reduced mode. */
1665 id = TSEC_READ(sc, TSEC_REG_ID2);
1667 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M;
1668 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0;
1669 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl);
1674 tsec_add_sysctls(struct tsec_softc *sc)
1676 struct sysctl_ctx_list *ctx;
1677 struct sysctl_oid_list *children;
1678 struct sysctl_oid *tree;
1680 ctx = device_get_sysctl_ctx(sc->dev);
1681 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
1682 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal",
1683 CTLFLAG_RD, 0, "TSEC Interrupts coalescing");
1684 children = SYSCTL_CHILDREN(tree);
1686 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time",
1687 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time,
1688 "I", "IC RX time threshold (0-65535)");
1689 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count",
1690 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count,
1691 "I", "IC RX frame count threshold (0-255)");
1693 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time",
1694 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time,
1695 "I", "IC TX time threshold (0-65535)");
1696 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count",
1697 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count,
1698 "I", "IC TX frame count threshold (0-255)");
1702 * With Interrupt Coalescing (IC) active, a transmit/receive frame
1703 * interrupt is raised either upon:
1705 * - threshold-defined period of time elapsed, or
1706 * - threshold-defined number of frames is received/transmitted,
1707 * whichever occurs first.
1709 * The following sysctls regulate IC behaviour (for TX/RX separately):
1711 * dev.tsec.<unit>.int_coal.rx_time
1712 * dev.tsec.<unit>.int_coal.rx_count
1713 * dev.tsec.<unit>.int_coal.tx_time
1714 * dev.tsec.<unit>.int_coal.tx_count
1718 * - 0 for either time or count disables IC on the given TX/RX path
1720 * - count: 1-255 (expresses frame count number; note that value of 1 is
1721 * effectively IC off)
1723 * - time: 1-65535 (value corresponds to a real time period and is
1724 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer
1725 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps,
1726 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the
1727 * TSEC reference manual.
1730 tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)
1734 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1736 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
1738 error = sysctl_handle_int(oidp, &time, 0, req);
1746 if (arg2 == TSEC_IC_RX) {
1747 sc->rx_ic_time = time;
1750 sc->tx_ic_time = time;
1759 tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)
1763 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1765 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count;
1767 error = sysctl_handle_int(oidp, &count, 0, req);
1775 if (arg2 == TSEC_IC_RX) {
1776 sc->rx_ic_count = count;
1779 sc->tx_ic_count = count;
1788 tsec_set_rxic(struct tsec_softc *sc)
1792 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0)
1796 rxic_val = 0x80000000;
1797 rxic_val |= (sc->rx_ic_count << 21);
1798 rxic_val |= sc->rx_ic_time;
1801 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val);
1805 tsec_set_txic(struct tsec_softc *sc)
1809 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0)
1813 txic_val = 0x80000000;
1814 txic_val |= (sc->tx_ic_count << 21);
1815 txic_val |= sc->tx_ic_time;
1818 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val);
1822 tsec_offload_setup(struct tsec_softc *sc)
1824 struct ifnet *ifp = sc->tsec_ifp;
1827 TSEC_GLOBAL_LOCK_ASSERT(sc);
1829 reg = TSEC_READ(sc, TSEC_REG_TCTRL);
1830 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN;
1832 if (ifp->if_capenable & IFCAP_TXCSUM)
1833 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES;
1835 ifp->if_hwassist = 0;
1837 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg);
1839 reg = TSEC_READ(sc, TSEC_REG_RCTRL);
1840 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP);
1841 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX;
1843 if (ifp->if_capenable & IFCAP_RXCSUM)
1844 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN |
1845 TSEC_RCTRL_PRSDEP_PARSE_L234;
1847 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg);
1852 tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m)
1854 struct tsec_rx_fcb rx_fcb;
1856 int protocol, flags;
1858 TSEC_RECEIVE_LOCK_ASSERT(sc);
1860 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb));
1861 flags = rx_fcb.flags;
1862 protocol = rx_fcb.protocol;
1864 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) {
1865 csum_flags |= CSUM_IP_CHECKED;
1867 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0)
1868 csum_flags |= CSUM_IP_VALID;
1871 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) &&
1872 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) &&
1873 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) {
1875 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1876 m->m_pkthdr.csum_data = 0xFFFF;
1879 m->m_pkthdr.csum_flags = csum_flags;
1881 if (flags & TSEC_RX_FCB_VLAN) {
1882 m->m_pkthdr.ether_vtag = rx_fcb.vlan;
1883 m->m_flags |= M_VLANTAG;
1886 m_adj(m, sizeof(struct tsec_rx_fcb));
1890 tsec_setup_multicast(struct tsec_softc *sc)
1892 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
1893 struct ifnet *ifp = sc->tsec_ifp;
1894 struct ifmultiaddr *ifma;
1898 TSEC_GLOBAL_LOCK_ASSERT(sc);
1900 if (ifp->if_flags & IFF_ALLMULTI) {
1901 for (i = 0; i < 8; i++)
1902 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF);
1907 if_maddr_rlock(ifp);
1908 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1910 if (ifma->ifma_addr->sa_family != AF_LINK)
1913 h = (ether_crc32_be(LLADDR((struct sockaddr_dl *)
1914 ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF;
1916 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F));
1918 if_maddr_runlock(ifp);
1920 for (i = 0; i < 8; i++)
1921 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]);
1925 tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu)
1928 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
1930 TSEC_GLOBAL_LOCK_ASSERT(sc);
1932 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) {
1933 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu);